config.ini revision 10636:9ac724889705
1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=System 13children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain 17eventq_index=0 18init_param=0 19kernel= 20kernel_addr_check=true 21load_addr_mask=1099511627775 22load_offset=0 23mem_mode=timing 24mem_ranges= 25memories=system.physmem 26num_work_ids=16 27readfile= 28symbolfile= 29work_begin_ckpt_count=0 30work_begin_cpu_id_exit=-1 31work_begin_exit_count=0 32work_cpus_ckpt_count=0 33work_end_ckpt_count=0 34work_end_exit_count=0 35work_item_id=-1 36system_port=system.membus.slave[0] 37 38[system.clk_domain] 39type=SrcClockDomain 40clock=1000 41domain_id=-1 42eventq_index=0 43init_perf_level=0 44voltage_domain=system.voltage_domain 45 46[system.cpu] 47type=DerivO3CPU 48children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload 49LFSTSize=1024 50LQEntries=16 51LSQCheckLoads=true 52LSQDepCheckShift=0 53SQEntries=16 54SSITSize=1024 55activity=0 56backComSize=5 57branchPred=system.cpu.branchPred 58cachePorts=200 59checker=Null 60clk_domain=system.cpu_clk_domain 61commitToDecodeDelay=1 62commitToFetchDelay=1 63commitToIEWDelay=1 64commitToRenameDelay=1 65commitWidth=8 66cpu_id=0 67decodeToFetchDelay=1 68decodeToRenameDelay=2 69decodeWidth=3 70dispatchWidth=6 71do_checkpoint_insts=true 72do_quiesce=true 73do_statistics_insts=true 74dstage2_mmu=system.cpu.dstage2_mmu 75dtb=system.cpu.dtb 76eventq_index=0 77fetchBufferSize=16 78fetchQueueSize=32 79fetchToDecodeDelay=3 80fetchTrapLatency=1 81fetchWidth=3 82forwardComSize=5 83fuPool=system.cpu.fuPool 84function_trace=false 85function_trace_start=0 86iewToCommitDelay=1 87iewToDecodeDelay=1 88iewToFetchDelay=1 89iewToRenameDelay=1 90interrupts=system.cpu.interrupts 91isa=system.cpu.isa 92issueToExecuteDelay=1 93issueWidth=8 94istage2_mmu=system.cpu.istage2_mmu 95itb=system.cpu.itb 96max_insts_all_threads=0 97max_insts_any_thread=0 98max_loads_all_threads=0 99max_loads_any_thread=0 100needsTSO=false 101numIQEntries=32 102numPhysCCRegs=640 103numPhysFloatRegs=192 104numPhysIntRegs=128 105numROBEntries=40 106numRobs=1 107numThreads=1 108profile=0 109progress_interval=0 110renameToDecodeDelay=1 111renameToFetchDelay=1 112renameToIEWDelay=1 113renameToROBDelay=1 114renameWidth=3 115simpoint_start_insts= 116smtCommitPolicy=RoundRobin 117smtFetchPolicy=SingleThread 118smtIQPolicy=Partitioned 119smtIQThreshold=100 120smtLSQPolicy=Partitioned 121smtLSQThreshold=100 122smtNumFetchingThreads=1 123smtROBPolicy=Partitioned 124smtROBThreshold=100 125socket_id=0 126squashWidth=8 127store_set_clear_period=250000 128switched_out=false 129system=system 130tracer=system.cpu.tracer 131trapLatency=13 132wbWidth=8 133workload=system.cpu.workload 134dcache_port=system.cpu.dcache.cpu_side 135icache_port=system.cpu.icache.cpu_side 136 137[system.cpu.branchPred] 138type=BranchPredictor 139BTBEntries=2048 140BTBTagSize=18 141RASSize=16 142choiceCtrBits=2 143choicePredictorSize=8192 144eventq_index=0 145globalCtrBits=2 146globalPredictorSize=8192 147instShiftAmt=2 148localCtrBits=2 149localHistoryTableSize=2048 150localPredictorSize=2048 151numThreads=1 152predType=bi-mode 153 154[system.cpu.dcache] 155type=BaseCache 156children=tags 157addr_ranges=0:18446744073709551615 158assoc=2 159clk_domain=system.cpu_clk_domain 160demand_mshr_reserve=1 161eventq_index=0 162forward_snoops=true 163hit_latency=2 164is_top_level=true 165max_miss_count=0 166mshrs=6 167prefetch_on_access=false 168prefetcher=Null 169response_latency=2 170sequential_access=false 171size=32768 172system=system 173tags=system.cpu.dcache.tags 174tgts_per_mshr=8 175two_queue=false 176write_buffers=16 177cpu_side=system.cpu.dcache_port 178mem_side=system.cpu.toL2Bus.slave[1] 179 180[system.cpu.dcache.tags] 181type=LRU 182assoc=2 183block_size=64 184clk_domain=system.cpu_clk_domain 185eventq_index=0 186hit_latency=2 187sequential_access=false 188size=32768 189 190[system.cpu.dstage2_mmu] 191type=ArmStage2MMU 192children=stage2_tlb 193eventq_index=0 194stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb 195tlb=system.cpu.dtb 196 197[system.cpu.dstage2_mmu.stage2_tlb] 198type=ArmTLB 199children=walker 200eventq_index=0 201is_stage2=true 202size=32 203walker=system.cpu.dstage2_mmu.stage2_tlb.walker 204 205[system.cpu.dstage2_mmu.stage2_tlb.walker] 206type=ArmTableWalker 207clk_domain=system.cpu_clk_domain 208eventq_index=0 209is_stage2=true 210num_squash_per_cycle=2 211sys=system 212port=system.cpu.toL2Bus.slave[5] 213 214[system.cpu.dtb] 215type=ArmTLB 216children=walker 217eventq_index=0 218is_stage2=false 219size=64 220walker=system.cpu.dtb.walker 221 222[system.cpu.dtb.walker] 223type=ArmTableWalker 224clk_domain=system.cpu_clk_domain 225eventq_index=0 226is_stage2=false 227num_squash_per_cycle=2 228sys=system 229port=system.cpu.toL2Bus.slave[3] 230 231[system.cpu.fuPool] 232type=FUPool 233children=FUList0 FUList1 FUList2 FUList3 FUList4 234FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 235eventq_index=0 236 237[system.cpu.fuPool.FUList0] 238type=FUDesc 239children=opList 240count=2 241eventq_index=0 242opList=system.cpu.fuPool.FUList0.opList 243 244[system.cpu.fuPool.FUList0.opList] 245type=OpDesc 246eventq_index=0 247issueLat=1 248opClass=IntAlu 249opLat=1 250 251[system.cpu.fuPool.FUList1] 252type=FUDesc 253children=opList0 opList1 opList2 254count=1 255eventq_index=0 256opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 system.cpu.fuPool.FUList1.opList2 257 258[system.cpu.fuPool.FUList1.opList0] 259type=OpDesc 260eventq_index=0 261issueLat=1 262opClass=IntMult 263opLat=3 264 265[system.cpu.fuPool.FUList1.opList1] 266type=OpDesc 267eventq_index=0 268issueLat=12 269opClass=IntDiv 270opLat=12 271 272[system.cpu.fuPool.FUList1.opList2] 273type=OpDesc 274eventq_index=0 275issueLat=1 276opClass=IprAccess 277opLat=3 278 279[system.cpu.fuPool.FUList2] 280type=FUDesc 281children=opList 282count=1 283eventq_index=0 284opList=system.cpu.fuPool.FUList2.opList 285 286[system.cpu.fuPool.FUList2.opList] 287type=OpDesc 288eventq_index=0 289issueLat=1 290opClass=MemRead 291opLat=2 292 293[system.cpu.fuPool.FUList3] 294type=FUDesc 295children=opList 296count=1 297eventq_index=0 298opList=system.cpu.fuPool.FUList3.opList 299 300[system.cpu.fuPool.FUList3.opList] 301type=OpDesc 302eventq_index=0 303issueLat=1 304opClass=MemWrite 305opLat=2 306 307[system.cpu.fuPool.FUList4] 308type=FUDesc 309children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25 310count=2 311eventq_index=0 312opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 system.cpu.fuPool.FUList4.opList02 system.cpu.fuPool.FUList4.opList03 system.cpu.fuPool.FUList4.opList04 system.cpu.fuPool.FUList4.opList05 system.cpu.fuPool.FUList4.opList06 system.cpu.fuPool.FUList4.opList07 system.cpu.fuPool.FUList4.opList08 system.cpu.fuPool.FUList4.opList09 system.cpu.fuPool.FUList4.opList10 system.cpu.fuPool.FUList4.opList11 system.cpu.fuPool.FUList4.opList12 system.cpu.fuPool.FUList4.opList13 system.cpu.fuPool.FUList4.opList14 system.cpu.fuPool.FUList4.opList15 system.cpu.fuPool.FUList4.opList16 system.cpu.fuPool.FUList4.opList17 system.cpu.fuPool.FUList4.opList18 system.cpu.fuPool.FUList4.opList19 system.cpu.fuPool.FUList4.opList20 system.cpu.fuPool.FUList4.opList21 system.cpu.fuPool.FUList4.opList22 system.cpu.fuPool.FUList4.opList23 system.cpu.fuPool.FUList4.opList24 system.cpu.fuPool.FUList4.opList25 313 314[system.cpu.fuPool.FUList4.opList00] 315type=OpDesc 316eventq_index=0 317issueLat=1 318opClass=SimdAdd 319opLat=4 320 321[system.cpu.fuPool.FUList4.opList01] 322type=OpDesc 323eventq_index=0 324issueLat=1 325opClass=SimdAddAcc 326opLat=4 327 328[system.cpu.fuPool.FUList4.opList02] 329type=OpDesc 330eventq_index=0 331issueLat=1 332opClass=SimdAlu 333opLat=4 334 335[system.cpu.fuPool.FUList4.opList03] 336type=OpDesc 337eventq_index=0 338issueLat=1 339opClass=SimdCmp 340opLat=4 341 342[system.cpu.fuPool.FUList4.opList04] 343type=OpDesc 344eventq_index=0 345issueLat=1 346opClass=SimdCvt 347opLat=3 348 349[system.cpu.fuPool.FUList4.opList05] 350type=OpDesc 351eventq_index=0 352issueLat=1 353opClass=SimdMisc 354opLat=3 355 356[system.cpu.fuPool.FUList4.opList06] 357type=OpDesc 358eventq_index=0 359issueLat=1 360opClass=SimdMult 361opLat=5 362 363[system.cpu.fuPool.FUList4.opList07] 364type=OpDesc 365eventq_index=0 366issueLat=1 367opClass=SimdMultAcc 368opLat=5 369 370[system.cpu.fuPool.FUList4.opList08] 371type=OpDesc 372eventq_index=0 373issueLat=1 374opClass=SimdShift 375opLat=3 376 377[system.cpu.fuPool.FUList4.opList09] 378type=OpDesc 379eventq_index=0 380issueLat=1 381opClass=SimdShiftAcc 382opLat=3 383 384[system.cpu.fuPool.FUList4.opList10] 385type=OpDesc 386eventq_index=0 387issueLat=1 388opClass=SimdSqrt 389opLat=9 390 391[system.cpu.fuPool.FUList4.opList11] 392type=OpDesc 393eventq_index=0 394issueLat=1 395opClass=SimdFloatAdd 396opLat=5 397 398[system.cpu.fuPool.FUList4.opList12] 399type=OpDesc 400eventq_index=0 401issueLat=1 402opClass=SimdFloatAlu 403opLat=5 404 405[system.cpu.fuPool.FUList4.opList13] 406type=OpDesc 407eventq_index=0 408issueLat=1 409opClass=SimdFloatCmp 410opLat=3 411 412[system.cpu.fuPool.FUList4.opList14] 413type=OpDesc 414eventq_index=0 415issueLat=1 416opClass=SimdFloatCvt 417opLat=3 418 419[system.cpu.fuPool.FUList4.opList15] 420type=OpDesc 421eventq_index=0 422issueLat=1 423opClass=SimdFloatDiv 424opLat=3 425 426[system.cpu.fuPool.FUList4.opList16] 427type=OpDesc 428eventq_index=0 429issueLat=1 430opClass=SimdFloatMisc 431opLat=3 432 433[system.cpu.fuPool.FUList4.opList17] 434type=OpDesc 435eventq_index=0 436issueLat=1 437opClass=SimdFloatMult 438opLat=3 439 440[system.cpu.fuPool.FUList4.opList18] 441type=OpDesc 442eventq_index=0 443issueLat=1 444opClass=SimdFloatMultAcc 445opLat=1 446 447[system.cpu.fuPool.FUList4.opList19] 448type=OpDesc 449eventq_index=0 450issueLat=1 451opClass=SimdFloatSqrt 452opLat=9 453 454[system.cpu.fuPool.FUList4.opList20] 455type=OpDesc 456eventq_index=0 457issueLat=1 458opClass=FloatAdd 459opLat=5 460 461[system.cpu.fuPool.FUList4.opList21] 462type=OpDesc 463eventq_index=0 464issueLat=1 465opClass=FloatCmp 466opLat=5 467 468[system.cpu.fuPool.FUList4.opList22] 469type=OpDesc 470eventq_index=0 471issueLat=1 472opClass=FloatCvt 473opLat=5 474 475[system.cpu.fuPool.FUList4.opList23] 476type=OpDesc 477eventq_index=0 478issueLat=9 479opClass=FloatDiv 480opLat=9 481 482[system.cpu.fuPool.FUList4.opList24] 483type=OpDesc 484eventq_index=0 485issueLat=33 486opClass=FloatSqrt 487opLat=33 488 489[system.cpu.fuPool.FUList4.opList25] 490type=OpDesc 491eventq_index=0 492issueLat=1 493opClass=FloatMult 494opLat=4 495 496[system.cpu.icache] 497type=BaseCache 498children=tags 499addr_ranges=0:18446744073709551615 500assoc=2 501clk_domain=system.cpu_clk_domain 502demand_mshr_reserve=1 503eventq_index=0 504forward_snoops=true 505hit_latency=1 506is_top_level=true 507max_miss_count=0 508mshrs=2 509prefetch_on_access=false 510prefetcher=Null 511response_latency=1 512sequential_access=false 513size=32768 514system=system 515tags=system.cpu.icache.tags 516tgts_per_mshr=8 517two_queue=false 518write_buffers=8 519cpu_side=system.cpu.icache_port 520mem_side=system.cpu.toL2Bus.slave[0] 521 522[system.cpu.icache.tags] 523type=LRU 524assoc=2 525block_size=64 526clk_domain=system.cpu_clk_domain 527eventq_index=0 528hit_latency=1 529sequential_access=false 530size=32768 531 532[system.cpu.interrupts] 533type=ArmInterrupts 534eventq_index=0 535 536[system.cpu.isa] 537type=ArmISA 538eventq_index=0 539fpsid=1090793632 540id_aa64afr0_el1=0 541id_aa64afr1_el1=0 542id_aa64dfr0_el1=1052678 543id_aa64dfr1_el1=0 544id_aa64isar0_el1=0 545id_aa64isar1_el1=0 546id_aa64mmfr0_el1=15728642 547id_aa64mmfr1_el1=0 548id_aa64pfr0_el1=17 549id_aa64pfr1_el1=0 550id_isar0=34607377 551id_isar1=34677009 552id_isar2=555950401 553id_isar3=17899825 554id_isar4=268501314 555id_isar5=0 556id_mmfr0=270536963 557id_mmfr1=0 558id_mmfr2=19070976 559id_mmfr3=34611729 560id_pfr0=49 561id_pfr1=4113 562midr=1091551472 563pmu=Null 564system=system 565 566[system.cpu.istage2_mmu] 567type=ArmStage2MMU 568children=stage2_tlb 569eventq_index=0 570stage2_tlb=system.cpu.istage2_mmu.stage2_tlb 571tlb=system.cpu.itb 572 573[system.cpu.istage2_mmu.stage2_tlb] 574type=ArmTLB 575children=walker 576eventq_index=0 577is_stage2=true 578size=32 579walker=system.cpu.istage2_mmu.stage2_tlb.walker 580 581[system.cpu.istage2_mmu.stage2_tlb.walker] 582type=ArmTableWalker 583clk_domain=system.cpu_clk_domain 584eventq_index=0 585is_stage2=true 586num_squash_per_cycle=2 587sys=system 588port=system.cpu.toL2Bus.slave[4] 589 590[system.cpu.itb] 591type=ArmTLB 592children=walker 593eventq_index=0 594is_stage2=false 595size=64 596walker=system.cpu.itb.walker 597 598[system.cpu.itb.walker] 599type=ArmTableWalker 600clk_domain=system.cpu_clk_domain 601eventq_index=0 602is_stage2=false 603num_squash_per_cycle=2 604sys=system 605port=system.cpu.toL2Bus.slave[2] 606 607[system.cpu.l2cache] 608type=BaseCache 609children=prefetcher tags 610addr_ranges=0:18446744073709551615 611assoc=16 612clk_domain=system.cpu_clk_domain 613demand_mshr_reserve=1 614eventq_index=0 615forward_snoops=true 616hit_latency=12 617is_top_level=false 618max_miss_count=0 619mshrs=16 620prefetch_on_access=true 621prefetcher=system.cpu.l2cache.prefetcher 622response_latency=12 623sequential_access=false 624size=1048576 625system=system 626tags=system.cpu.l2cache.tags 627tgts_per_mshr=8 628two_queue=false 629write_buffers=8 630cpu_side=system.cpu.toL2Bus.master[0] 631mem_side=system.membus.slave[1] 632 633[system.cpu.l2cache.prefetcher] 634type=StridePrefetcher 635cache_snoop=false 636clk_domain=system.cpu_clk_domain 637degree=8 638eventq_index=0 639latency=1 640max_conf=7 641min_conf=0 642on_data=true 643on_inst=true 644on_miss=false 645on_read=true 646on_write=true 647queue_filter=true 648queue_size=32 649queue_squash=true 650start_conf=4 651sys=system 652table_assoc=4 653table_sets=16 654tag_prefetch=true 655thresh_conf=4 656use_master_id=true 657 658[system.cpu.l2cache.tags] 659type=RandomRepl 660assoc=16 661block_size=64 662clk_domain=system.cpu_clk_domain 663eventq_index=0 664hit_latency=12 665sequential_access=false 666size=1048576 667 668[system.cpu.toL2Bus] 669type=CoherentXBar 670clk_domain=system.cpu_clk_domain 671eventq_index=0 672header_cycles=1 673snoop_filter=Null 674system=system 675use_default_range=false 676width=32 677master=system.cpu.l2cache.cpu_side 678slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port 679 680[system.cpu.tracer] 681type=ExeTracer 682eventq_index=0 683 684[system.cpu.workload] 685type=LiveProcess 686cmd=vortex lendian.raw 687cwd=build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing 688drivers= 689egid=100 690env= 691errout=cerr 692euid=100 693eventq_index=0 694executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/vortex 695gid=100 696input=cin 697kvmInSE=false 698max_stack_size=67108864 699output=cout 700pid=100 701ppid=99 702simpoint=0 703system=system 704uid=100 705useArchPT=false 706 707[system.cpu_clk_domain] 708type=SrcClockDomain 709clock=500 710domain_id=-1 711eventq_index=0 712init_perf_level=0 713voltage_domain=system.voltage_domain 714 715[system.dvfs_handler] 716type=DVFSHandler 717domains= 718enable=false 719eventq_index=0 720sys_clk_domain=system.clk_domain 721transition_latency=100000000 722 723[system.membus] 724type=CoherentXBar 725clk_domain=system.clk_domain 726eventq_index=0 727header_cycles=1 728snoop_filter=Null 729system=system 730use_default_range=false 731width=8 732master=system.physmem.port 733slave=system.system_port system.cpu.l2cache.mem_side 734 735[system.physmem] 736type=DRAMCtrl 737IDD0=0.075000 738IDD02=0.000000 739IDD2N=0.050000 740IDD2N2=0.000000 741IDD2P0=0.000000 742IDD2P02=0.000000 743IDD2P1=0.000000 744IDD2P12=0.000000 745IDD3N=0.057000 746IDD3N2=0.000000 747IDD3P0=0.000000 748IDD3P02=0.000000 749IDD3P1=0.000000 750IDD3P12=0.000000 751IDD4R=0.187000 752IDD4R2=0.000000 753IDD4W=0.165000 754IDD4W2=0.000000 755IDD5=0.220000 756IDD52=0.000000 757IDD6=0.000000 758IDD62=0.000000 759VDD=1.500000 760VDD2=0.000000 761activation_limit=4 762addr_mapping=RoRaBaChCo 763bank_groups_per_rank=0 764banks_per_rank=8 765burst_length=8 766channels=1 767clk_domain=system.clk_domain 768conf_table_reported=true 769device_bus_width=8 770device_rowbuffer_size=1024 771device_size=536870912 772devices_per_rank=8 773dll=true 774eventq_index=0 775in_addr_map=true 776max_accesses_per_row=16 777mem_sched_policy=frfcfs 778min_writes_per_switch=16 779null=false 780page_policy=open_adaptive 781range=0:134217727 782ranks_per_channel=2 783read_buffer_size=32 784static_backend_latency=10000 785static_frontend_latency=10000 786tBURST=5000 787tCCD_L=0 788tCK=1250 789tCL=13750 790tCS=2500 791tRAS=35000 792tRCD=13750 793tREFI=7800000 794tRFC=260000 795tRP=13750 796tRRD=6000 797tRRD_L=0 798tRTP=7500 799tRTW=2500 800tWR=15000 801tWTR=7500 802tXAW=30000 803tXP=0 804tXPDLL=0 805tXS=0 806tXSDLL=0 807write_buffer_size=64 808write_high_thresh_perc=85 809write_low_thresh_perc=50 810port=system.membus.master[0] 811 812[system.voltage_domain] 813type=VoltageDomain 814eventq_index=0 815voltage=1.000000 816 817