config.ini revision 10036:80e84beef3bb
1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=System 13children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain 17eventq_index=0 18init_param=0 19kernel= 20load_addr_mask=1099511627775 21mem_mode=timing 22mem_ranges= 23memories=system.physmem 24num_work_ids=16 25readfile= 26symbolfile= 27work_begin_ckpt_count=0 28work_begin_cpu_id_exit=-1 29work_begin_exit_count=0 30work_cpus_ckpt_count=0 31work_end_ckpt_count=0 32work_end_exit_count=0 33work_item_id=-1 34system_port=system.membus.slave[0] 35 36[system.clk_domain] 37type=SrcClockDomain 38clock=1000 39eventq_index=0 40voltage_domain=system.voltage_domain 41 42[system.cpu] 43type=DerivO3CPU 44children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload 45LFSTSize=1024 46LQEntries=32 47LSQCheckLoads=true 48LSQDepCheckShift=4 49SQEntries=32 50SSITSize=1024 51activity=0 52backComSize=5 53branchPred=system.cpu.branchPred 54cachePorts=200 55checker=Null 56clk_domain=system.cpu_clk_domain 57commitToDecodeDelay=1 58commitToFetchDelay=1 59commitToIEWDelay=1 60commitToRenameDelay=1 61commitWidth=8 62cpu_id=0 63decodeToFetchDelay=1 64decodeToRenameDelay=1 65decodeWidth=8 66dispatchWidth=8 67do_checkpoint_insts=true 68do_quiesce=true 69do_statistics_insts=true 70dtb=system.cpu.dtb 71eventq_index=0 72fetchBufferSize=64 73fetchToDecodeDelay=1 74fetchTrapLatency=1 75fetchWidth=8 76forwardComSize=5 77fuPool=system.cpu.fuPool 78function_trace=false 79function_trace_start=0 80iewToCommitDelay=1 81iewToDecodeDelay=1 82iewToFetchDelay=1 83iewToRenameDelay=1 84interrupts=system.cpu.interrupts 85isa=system.cpu.isa 86issueToExecuteDelay=1 87issueWidth=8 88itb=system.cpu.itb 89max_insts_all_threads=0 90max_insts_any_thread=0 91max_loads_all_threads=0 92max_loads_any_thread=0 93needsTSO=false 94numIQEntries=64 95numPhysCCRegs=0 96numPhysFloatRegs=256 97numPhysIntRegs=256 98numROBEntries=192 99numRobs=1 100numThreads=1 101profile=0 102progress_interval=0 103renameToDecodeDelay=1 104renameToFetchDelay=1 105renameToIEWDelay=2 106renameToROBDelay=1 107renameWidth=8 108simpoint_start_insts= 109smtCommitPolicy=RoundRobin 110smtFetchPolicy=SingleThread 111smtIQPolicy=Partitioned 112smtIQThreshold=100 113smtLSQPolicy=Partitioned 114smtLSQThreshold=100 115smtNumFetchingThreads=1 116smtROBPolicy=Partitioned 117smtROBThreshold=100 118squashWidth=8 119store_set_clear_period=250000 120switched_out=false 121system=system 122tracer=system.cpu.tracer 123trapLatency=13 124wbDepth=1 125wbWidth=8 126workload=system.cpu.workload 127dcache_port=system.cpu.dcache.cpu_side 128icache_port=system.cpu.icache.cpu_side 129 130[system.cpu.branchPred] 131type=BranchPredictor 132BTBEntries=4096 133BTBTagSize=16 134RASSize=16 135choiceCtrBits=2 136choicePredictorSize=8192 137eventq_index=0 138globalCtrBits=2 139globalPredictorSize=8192 140instShiftAmt=2 141localCtrBits=2 142localHistoryTableSize=2048 143localPredictorSize=2048 144numThreads=1 145predType=tournament 146 147[system.cpu.dcache] 148type=BaseCache 149children=tags 150addr_ranges=0:18446744073709551615 151assoc=2 152clk_domain=system.cpu_clk_domain 153eventq_index=0 154forward_snoops=true 155hit_latency=2 156is_top_level=true 157max_miss_count=0 158mshrs=4 159prefetch_on_access=false 160prefetcher=Null 161response_latency=2 162sequential_access=false 163size=262144 164system=system 165tags=system.cpu.dcache.tags 166tgts_per_mshr=20 167two_queue=false 168write_buffers=8 169cpu_side=system.cpu.dcache_port 170mem_side=system.cpu.toL2Bus.slave[1] 171 172[system.cpu.dcache.tags] 173type=LRU 174assoc=2 175block_size=64 176clk_domain=system.cpu_clk_domain 177eventq_index=0 178hit_latency=2 179sequential_access=false 180size=262144 181 182[system.cpu.dtb] 183type=ArmTLB 184children=walker 185eventq_index=0 186size=64 187walker=system.cpu.dtb.walker 188 189[system.cpu.dtb.walker] 190type=ArmTableWalker 191clk_domain=system.cpu_clk_domain 192eventq_index=0 193num_squash_per_cycle=2 194sys=system 195port=system.cpu.toL2Bus.slave[3] 196 197[system.cpu.fuPool] 198type=FUPool 199children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 200FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 201eventq_index=0 202 203[system.cpu.fuPool.FUList0] 204type=FUDesc 205children=opList 206count=6 207eventq_index=0 208opList=system.cpu.fuPool.FUList0.opList 209 210[system.cpu.fuPool.FUList0.opList] 211type=OpDesc 212eventq_index=0 213issueLat=1 214opClass=IntAlu 215opLat=1 216 217[system.cpu.fuPool.FUList1] 218type=FUDesc 219children=opList0 opList1 220count=2 221eventq_index=0 222opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 223 224[system.cpu.fuPool.FUList1.opList0] 225type=OpDesc 226eventq_index=0 227issueLat=1 228opClass=IntMult 229opLat=3 230 231[system.cpu.fuPool.FUList1.opList1] 232type=OpDesc 233eventq_index=0 234issueLat=19 235opClass=IntDiv 236opLat=20 237 238[system.cpu.fuPool.FUList2] 239type=FUDesc 240children=opList0 opList1 opList2 241count=4 242eventq_index=0 243opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 244 245[system.cpu.fuPool.FUList2.opList0] 246type=OpDesc 247eventq_index=0 248issueLat=1 249opClass=FloatAdd 250opLat=2 251 252[system.cpu.fuPool.FUList2.opList1] 253type=OpDesc 254eventq_index=0 255issueLat=1 256opClass=FloatCmp 257opLat=2 258 259[system.cpu.fuPool.FUList2.opList2] 260type=OpDesc 261eventq_index=0 262issueLat=1 263opClass=FloatCvt 264opLat=2 265 266[system.cpu.fuPool.FUList3] 267type=FUDesc 268children=opList0 opList1 opList2 269count=2 270eventq_index=0 271opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 272 273[system.cpu.fuPool.FUList3.opList0] 274type=OpDesc 275eventq_index=0 276issueLat=1 277opClass=FloatMult 278opLat=4 279 280[system.cpu.fuPool.FUList3.opList1] 281type=OpDesc 282eventq_index=0 283issueLat=12 284opClass=FloatDiv 285opLat=12 286 287[system.cpu.fuPool.FUList3.opList2] 288type=OpDesc 289eventq_index=0 290issueLat=24 291opClass=FloatSqrt 292opLat=24 293 294[system.cpu.fuPool.FUList4] 295type=FUDesc 296children=opList 297count=0 298eventq_index=0 299opList=system.cpu.fuPool.FUList4.opList 300 301[system.cpu.fuPool.FUList4.opList] 302type=OpDesc 303eventq_index=0 304issueLat=1 305opClass=MemRead 306opLat=1 307 308[system.cpu.fuPool.FUList5] 309type=FUDesc 310children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 311count=4 312eventq_index=0 313opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 314 315[system.cpu.fuPool.FUList5.opList00] 316type=OpDesc 317eventq_index=0 318issueLat=1 319opClass=SimdAdd 320opLat=1 321 322[system.cpu.fuPool.FUList5.opList01] 323type=OpDesc 324eventq_index=0 325issueLat=1 326opClass=SimdAddAcc 327opLat=1 328 329[system.cpu.fuPool.FUList5.opList02] 330type=OpDesc 331eventq_index=0 332issueLat=1 333opClass=SimdAlu 334opLat=1 335 336[system.cpu.fuPool.FUList5.opList03] 337type=OpDesc 338eventq_index=0 339issueLat=1 340opClass=SimdCmp 341opLat=1 342 343[system.cpu.fuPool.FUList5.opList04] 344type=OpDesc 345eventq_index=0 346issueLat=1 347opClass=SimdCvt 348opLat=1 349 350[system.cpu.fuPool.FUList5.opList05] 351type=OpDesc 352eventq_index=0 353issueLat=1 354opClass=SimdMisc 355opLat=1 356 357[system.cpu.fuPool.FUList5.opList06] 358type=OpDesc 359eventq_index=0 360issueLat=1 361opClass=SimdMult 362opLat=1 363 364[system.cpu.fuPool.FUList5.opList07] 365type=OpDesc 366eventq_index=0 367issueLat=1 368opClass=SimdMultAcc 369opLat=1 370 371[system.cpu.fuPool.FUList5.opList08] 372type=OpDesc 373eventq_index=0 374issueLat=1 375opClass=SimdShift 376opLat=1 377 378[system.cpu.fuPool.FUList5.opList09] 379type=OpDesc 380eventq_index=0 381issueLat=1 382opClass=SimdShiftAcc 383opLat=1 384 385[system.cpu.fuPool.FUList5.opList10] 386type=OpDesc 387eventq_index=0 388issueLat=1 389opClass=SimdSqrt 390opLat=1 391 392[system.cpu.fuPool.FUList5.opList11] 393type=OpDesc 394eventq_index=0 395issueLat=1 396opClass=SimdFloatAdd 397opLat=1 398 399[system.cpu.fuPool.FUList5.opList12] 400type=OpDesc 401eventq_index=0 402issueLat=1 403opClass=SimdFloatAlu 404opLat=1 405 406[system.cpu.fuPool.FUList5.opList13] 407type=OpDesc 408eventq_index=0 409issueLat=1 410opClass=SimdFloatCmp 411opLat=1 412 413[system.cpu.fuPool.FUList5.opList14] 414type=OpDesc 415eventq_index=0 416issueLat=1 417opClass=SimdFloatCvt 418opLat=1 419 420[system.cpu.fuPool.FUList5.opList15] 421type=OpDesc 422eventq_index=0 423issueLat=1 424opClass=SimdFloatDiv 425opLat=1 426 427[system.cpu.fuPool.FUList5.opList16] 428type=OpDesc 429eventq_index=0 430issueLat=1 431opClass=SimdFloatMisc 432opLat=1 433 434[system.cpu.fuPool.FUList5.opList17] 435type=OpDesc 436eventq_index=0 437issueLat=1 438opClass=SimdFloatMult 439opLat=1 440 441[system.cpu.fuPool.FUList5.opList18] 442type=OpDesc 443eventq_index=0 444issueLat=1 445opClass=SimdFloatMultAcc 446opLat=1 447 448[system.cpu.fuPool.FUList5.opList19] 449type=OpDesc 450eventq_index=0 451issueLat=1 452opClass=SimdFloatSqrt 453opLat=1 454 455[system.cpu.fuPool.FUList6] 456type=FUDesc 457children=opList 458count=0 459eventq_index=0 460opList=system.cpu.fuPool.FUList6.opList 461 462[system.cpu.fuPool.FUList6.opList] 463type=OpDesc 464eventq_index=0 465issueLat=1 466opClass=MemWrite 467opLat=1 468 469[system.cpu.fuPool.FUList7] 470type=FUDesc 471children=opList0 opList1 472count=4 473eventq_index=0 474opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 475 476[system.cpu.fuPool.FUList7.opList0] 477type=OpDesc 478eventq_index=0 479issueLat=1 480opClass=MemRead 481opLat=1 482 483[system.cpu.fuPool.FUList7.opList1] 484type=OpDesc 485eventq_index=0 486issueLat=1 487opClass=MemWrite 488opLat=1 489 490[system.cpu.fuPool.FUList8] 491type=FUDesc 492children=opList 493count=1 494eventq_index=0 495opList=system.cpu.fuPool.FUList8.opList 496 497[system.cpu.fuPool.FUList8.opList] 498type=OpDesc 499eventq_index=0 500issueLat=3 501opClass=IprAccess 502opLat=3 503 504[system.cpu.icache] 505type=BaseCache 506children=tags 507addr_ranges=0:18446744073709551615 508assoc=2 509clk_domain=system.cpu_clk_domain 510eventq_index=0 511forward_snoops=true 512hit_latency=2 513is_top_level=true 514max_miss_count=0 515mshrs=4 516prefetch_on_access=false 517prefetcher=Null 518response_latency=2 519sequential_access=false 520size=131072 521system=system 522tags=system.cpu.icache.tags 523tgts_per_mshr=20 524two_queue=false 525write_buffers=8 526cpu_side=system.cpu.icache_port 527mem_side=system.cpu.toL2Bus.slave[0] 528 529[system.cpu.icache.tags] 530type=LRU 531assoc=2 532block_size=64 533clk_domain=system.cpu_clk_domain 534eventq_index=0 535hit_latency=2 536sequential_access=false 537size=131072 538 539[system.cpu.interrupts] 540type=ArmInterrupts 541eventq_index=0 542 543[system.cpu.isa] 544type=ArmISA 545eventq_index=0 546fpsid=1090793632 547id_isar0=34607377 548id_isar1=34677009 549id_isar2=555950401 550id_isar3=17899825 551id_isar4=268501314 552id_isar5=0 553id_mmfr0=3 554id_mmfr1=0 555id_mmfr2=19070976 556id_mmfr3=4027589137 557id_pfr0=49 558id_pfr1=1 559midr=890224640 560 561[system.cpu.itb] 562type=ArmTLB 563children=walker 564eventq_index=0 565size=64 566walker=system.cpu.itb.walker 567 568[system.cpu.itb.walker] 569type=ArmTableWalker 570clk_domain=system.cpu_clk_domain 571eventq_index=0 572num_squash_per_cycle=2 573sys=system 574port=system.cpu.toL2Bus.slave[2] 575 576[system.cpu.l2cache] 577type=BaseCache 578children=tags 579addr_ranges=0:18446744073709551615 580assoc=8 581clk_domain=system.cpu_clk_domain 582eventq_index=0 583forward_snoops=true 584hit_latency=20 585is_top_level=false 586max_miss_count=0 587mshrs=20 588prefetch_on_access=false 589prefetcher=Null 590response_latency=20 591sequential_access=false 592size=2097152 593system=system 594tags=system.cpu.l2cache.tags 595tgts_per_mshr=12 596two_queue=false 597write_buffers=8 598cpu_side=system.cpu.toL2Bus.master[0] 599mem_side=system.membus.slave[1] 600 601[system.cpu.l2cache.tags] 602type=LRU 603assoc=8 604block_size=64 605clk_domain=system.cpu_clk_domain 606eventq_index=0 607hit_latency=20 608sequential_access=false 609size=2097152 610 611[system.cpu.toL2Bus] 612type=CoherentBus 613clk_domain=system.cpu_clk_domain 614eventq_index=0 615header_cycles=1 616system=system 617use_default_range=false 618width=32 619master=system.cpu.l2cache.cpu_side 620slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port 621 622[system.cpu.tracer] 623type=ExeTracer 624eventq_index=0 625 626[system.cpu.workload] 627type=LiveProcess 628cmd=vortex lendian.raw 629cwd=build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing 630egid=100 631env= 632errout=cerr 633euid=100 634eventq_index=0 635executable=/dist/cpu2000/binaries/arm/linux/vortex 636gid=100 637input=cin 638max_stack_size=67108864 639output=cout 640pid=100 641ppid=99 642simpoint=0 643system=system 644uid=100 645 646[system.cpu_clk_domain] 647type=SrcClockDomain 648clock=500 649eventq_index=0 650voltage_domain=system.voltage_domain 651 652[system.membus] 653type=CoherentBus 654clk_domain=system.clk_domain 655eventq_index=0 656header_cycles=1 657system=system 658use_default_range=false 659width=8 660master=system.physmem.port 661slave=system.system_port system.cpu.l2cache.mem_side 662 663[system.physmem] 664type=SimpleDRAM 665activation_limit=4 666addr_mapping=RaBaChCo 667banks_per_rank=8 668burst_length=8 669channels=1 670clk_domain=system.clk_domain 671conf_table_reported=true 672device_bus_width=8 673device_rowbuffer_size=1024 674devices_per_rank=8 675eventq_index=0 676in_addr_map=true 677mem_sched_policy=frfcfs 678null=false 679page_policy=open 680range=0:134217727 681ranks_per_channel=2 682read_buffer_size=32 683static_backend_latency=10000 684static_frontend_latency=10000 685tBURST=5000 686tCL=13750 687tRAS=35000 688tRCD=13750 689tREFI=7800000 690tRFC=300000 691tRP=13750 692tRRD=6250 693tWTR=7500 694tXAW=40000 695write_buffer_size=32 696write_high_thresh_perc=70 697write_low_thresh_perc=0 698port=system.membus.master[0] 699 700[system.voltage_domain] 701type=VoltageDomain 702eventq_index=0 703voltage=1.000000 704 705