stats.txt revision 10852:5b58b4cccfd7
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.057148 # Number of seconds simulated 4sim_ticks 57147901500 # Number of ticks simulated 5final_tick 57147901500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 198372 # Simulator instruction rate (inst/s) 8host_op_rate 253689 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 159860838 # Simulator tick rate (ticks/s) 10host_mem_usage 323444 # Number of bytes of host memory used 11host_seconds 357.49 # Real time elapsed on the host 12sim_insts 70915128 # Number of instructions simulated 13sim_ops 90690084 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 324160 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 7923136 # Number of bytes read from this memory 18system.physmem.bytes_read::total 8247296 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 324160 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 324160 # Number of instructions bytes read from this memory 21system.physmem.bytes_written::writebacks 5372800 # Number of bytes written to this memory 22system.physmem.bytes_written::total 5372800 # Number of bytes written to this memory 23system.physmem.num_reads::cpu.inst 5065 # Number of read requests responded to by this memory 24system.physmem.num_reads::cpu.data 123799 # Number of read requests responded to by this memory 25system.physmem.num_reads::total 128864 # Number of read requests responded to by this memory 26system.physmem.num_writes::writebacks 83950 # Number of write requests responded to by this memory 27system.physmem.num_writes::total 83950 # Number of write requests responded to by this memory 28system.physmem.bw_read::cpu.inst 5672299 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::cpu.data 138642641 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::total 144314940 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_inst_read::cpu.inst 5672299 # Instruction read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::total 5672299 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_write::writebacks 94015701 # Write bandwidth from this memory (bytes/s) 34system.physmem.bw_write::total 94015701 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_total::writebacks 94015701 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::cpu.inst 5672299 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.data 138642641 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::total 238330641 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.readReqs 128864 # Number of read requests accepted 40system.physmem.writeReqs 83950 # Number of write requests accepted 41system.physmem.readBursts 128864 # Number of DRAM read bursts, including those serviced by the write queue 42system.physmem.writeBursts 83950 # Number of DRAM write bursts, including those merged in the write queue 43system.physmem.bytesReadDRAM 8246976 # Total number of bytes read from DRAM 44system.physmem.bytesReadWrQ 320 # Total number of bytes read from write queue 45system.physmem.bytesWritten 5370816 # Total number of bytes written to DRAM 46system.physmem.bytesReadSys 8247296 # Total read bytes from the system interface side 47system.physmem.bytesWrittenSys 5372800 # Total written bytes from the system interface side 48system.physmem.servicedByWrQ 5 # Number of DRAM read bursts serviced by the write queue 49system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 50system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 51system.physmem.perBankRdBursts::0 8158 # Per bank write bursts 52system.physmem.perBankRdBursts::1 8375 # Per bank write bursts 53system.physmem.perBankRdBursts::2 8229 # Per bank write bursts 54system.physmem.perBankRdBursts::3 8170 # Per bank write bursts 55system.physmem.perBankRdBursts::4 8317 # Per bank write bursts 56system.physmem.perBankRdBursts::5 8450 # Per bank write bursts 57system.physmem.perBankRdBursts::6 8089 # Per bank write bursts 58system.physmem.perBankRdBursts::7 7970 # Per bank write bursts 59system.physmem.perBankRdBursts::8 8070 # Per bank write bursts 60system.physmem.perBankRdBursts::9 7639 # Per bank write bursts 61system.physmem.perBankRdBursts::10 7818 # Per bank write bursts 62system.physmem.perBankRdBursts::11 7830 # Per bank write bursts 63system.physmem.perBankRdBursts::12 7882 # Per bank write bursts 64system.physmem.perBankRdBursts::13 7879 # Per bank write bursts 65system.physmem.perBankRdBursts::14 7978 # Per bank write bursts 66system.physmem.perBankRdBursts::15 8005 # Per bank write bursts 67system.physmem.perBankWrBursts::0 5181 # Per bank write bursts 68system.physmem.perBankWrBursts::1 5374 # Per bank write bursts 69system.physmem.perBankWrBursts::2 5285 # Per bank write bursts 70system.physmem.perBankWrBursts::3 5155 # Per bank write bursts 71system.physmem.perBankWrBursts::4 5266 # Per bank write bursts 72system.physmem.perBankWrBursts::5 5517 # Per bank write bursts 73system.physmem.perBankWrBursts::6 5197 # Per bank write bursts 74system.physmem.perBankWrBursts::7 5049 # Per bank write bursts 75system.physmem.perBankWrBursts::8 5033 # Per bank write bursts 76system.physmem.perBankWrBursts::9 5087 # Per bank write bursts 77system.physmem.perBankWrBursts::10 5251 # Per bank write bursts 78system.physmem.perBankWrBursts::11 5143 # Per bank write bursts 79system.physmem.perBankWrBursts::12 5343 # Per bank write bursts 80system.physmem.perBankWrBursts::13 5363 # Per bank write bursts 81system.physmem.perBankWrBursts::14 5451 # Per bank write bursts 82system.physmem.perBankWrBursts::15 5224 # Per bank write bursts 83system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 84system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 85system.physmem.totGap 57147867000 # Total gap between requests 86system.physmem.readPktSize::0 0 # Read request sizes (log2) 87system.physmem.readPktSize::1 0 # Read request sizes (log2) 88system.physmem.readPktSize::2 0 # Read request sizes (log2) 89system.physmem.readPktSize::3 0 # Read request sizes (log2) 90system.physmem.readPktSize::4 0 # Read request sizes (log2) 91system.physmem.readPktSize::5 0 # Read request sizes (log2) 92system.physmem.readPktSize::6 128864 # Read request sizes (log2) 93system.physmem.writePktSize::0 0 # Write request sizes (log2) 94system.physmem.writePktSize::1 0 # Write request sizes (log2) 95system.physmem.writePktSize::2 0 # Write request sizes (log2) 96system.physmem.writePktSize::3 0 # Write request sizes (log2) 97system.physmem.writePktSize::4 0 # Write request sizes (log2) 98system.physmem.writePktSize::5 0 # Write request sizes (log2) 99system.physmem.writePktSize::6 83950 # Write request sizes (log2) 100system.physmem.rdQLenPdf::0 116734 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::1 12104 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::2 21 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 132system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 133system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 134system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::15 616 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::16 627 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::17 4050 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::18 5040 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::19 5146 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::20 5176 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::21 5178 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::22 5169 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::23 5182 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::24 5197 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::25 5188 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::26 5213 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::27 5385 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::28 5264 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::29 5293 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::30 5718 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::31 5316 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::32 5164 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::33 10 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::34 2 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::35 1 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 196system.physmem.bytesPerActivate::samples 38410 # Bytes accessed per row activation 197system.physmem.bytesPerActivate::mean 354.471023 # Bytes accessed per row activation 198system.physmem.bytesPerActivate::gmean 215.710692 # Bytes accessed per row activation 199system.physmem.bytesPerActivate::stdev 335.512328 # Bytes accessed per row activation 200system.physmem.bytesPerActivate::0-127 12078 31.44% 31.44% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::128-255 8121 21.14% 52.59% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::256-383 4196 10.92% 63.51% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::384-511 2833 7.38% 70.89% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::512-639 2487 6.47% 77.36% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::640-767 1687 4.39% 81.75% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::768-895 1308 3.41% 85.16% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::896-1023 1147 2.99% 88.15% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::1024-1151 4553 11.85% 100.00% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::total 38410 # Bytes accessed per row activation 210system.physmem.rdPerTurnAround::samples 5157 # Reads before turning the bus around for writes 211system.physmem.rdPerTurnAround::mean 24.969750 # Reads before turning the bus around for writes 212system.physmem.rdPerTurnAround::stdev 360.703721 # Reads before turning the bus around for writes 213system.physmem.rdPerTurnAround::0-1023 5155 99.96% 99.96% # Reads before turning the bus around for writes 214system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes 215system.physmem.rdPerTurnAround::25600-26623 1 0.02% 100.00% # Reads before turning the bus around for writes 216system.physmem.rdPerTurnAround::total 5157 # Reads before turning the bus around for writes 217system.physmem.wrPerTurnAround::samples 5157 # Writes before turning the bus around for reads 218system.physmem.wrPerTurnAround::mean 16.272833 # Writes before turning the bus around for reads 219system.physmem.wrPerTurnAround::gmean 16.256213 # Writes before turning the bus around for reads 220system.physmem.wrPerTurnAround::stdev 0.766988 # Writes before turning the bus around for reads 221system.physmem.wrPerTurnAround::16 4532 87.88% 87.88% # Writes before turning the bus around for reads 222system.physmem.wrPerTurnAround::17 8 0.16% 88.04% # Writes before turning the bus around for reads 223system.physmem.wrPerTurnAround::18 487 9.44% 97.48% # Writes before turning the bus around for reads 224system.physmem.wrPerTurnAround::19 109 2.11% 99.59% # Writes before turning the bus around for reads 225system.physmem.wrPerTurnAround::20 13 0.25% 99.84% # Writes before turning the bus around for reads 226system.physmem.wrPerTurnAround::21 4 0.08% 99.92% # Writes before turning the bus around for reads 227system.physmem.wrPerTurnAround::22 3 0.06% 99.98% # Writes before turning the bus around for reads 228system.physmem.wrPerTurnAround::24 1 0.02% 100.00% # Writes before turning the bus around for reads 229system.physmem.wrPerTurnAround::total 5157 # Writes before turning the bus around for reads 230system.physmem.totQLat 1657207000 # Total ticks spent queuing 231system.physmem.totMemAccLat 4073313250 # Total ticks spent from burst creation until serviced by the DRAM 232system.physmem.totBusLat 644295000 # Total ticks spent in databus transfers 233system.physmem.avgQLat 12860.62 # Average queueing delay per DRAM burst 234system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 235system.physmem.avgMemAccLat 31610.62 # Average memory access latency per DRAM burst 236system.physmem.avgRdBW 144.31 # Average DRAM read bandwidth in MiByte/s 237system.physmem.avgWrBW 93.98 # Average achieved write bandwidth in MiByte/s 238system.physmem.avgRdBWSys 144.31 # Average system read bandwidth in MiByte/s 239system.physmem.avgWrBWSys 94.02 # Average system write bandwidth in MiByte/s 240system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 241system.physmem.busUtil 1.86 # Data bus utilization in percentage 242system.physmem.busUtilRead 1.13 # Data bus utilization in percentage for reads 243system.physmem.busUtilWrite 0.73 # Data bus utilization in percentage for writes 244system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing 245system.physmem.avgWrQLen 23.46 # Average write queue length when enqueuing 246system.physmem.readRowHits 112198 # Number of row buffer hits during reads 247system.physmem.writeRowHits 62160 # Number of row buffer hits during writes 248system.physmem.readRowHitRate 87.07 # Row buffer hit rate for reads 249system.physmem.writeRowHitRate 74.04 # Row buffer hit rate for writes 250system.physmem.avgGap 268534.34 # Average gap between requests 251system.physmem.pageHitRate 81.93 # Row buffer hit rate, read and write combined 252system.physmem_0.actEnergy 150580080 # Energy for activate commands per rank (pJ) 253system.physmem_0.preEnergy 82161750 # Energy for precharge commands per rank (pJ) 254system.physmem_0.readEnergy 512592600 # Energy for read commands per rank (pJ) 255system.physmem_0.writeEnergy 272315520 # Energy for write commands per rank (pJ) 256system.physmem_0.refreshEnergy 3732321840 # Energy for refresh commands per rank (pJ) 257system.physmem_0.actBackEnergy 11751586830 # Energy for active background per rank (pJ) 258system.physmem_0.preBackEnergy 23977725000 # Energy for precharge background per rank (pJ) 259system.physmem_0.totalEnergy 40479283620 # Total energy per rank (pJ) 260system.physmem_0.averagePower 708.378781 # Core power per rank (mW) 261system.physmem_0.memoryStateTime::IDLE 39762160500 # Time in different power states 262system.physmem_0.memoryStateTime::REF 1908140000 # Time in different power states 263system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 264system.physmem_0.memoryStateTime::ACT 15473270000 # Time in different power states 265system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 266system.physmem_1.actEnergy 139769280 # Energy for activate commands per rank (pJ) 267system.physmem_1.preEnergy 76263000 # Energy for precharge commands per rank (pJ) 268system.physmem_1.readEnergy 492016200 # Energy for read commands per rank (pJ) 269system.physmem_1.writeEnergy 271479600 # Energy for write commands per rank (pJ) 270system.physmem_1.refreshEnergy 3732321840 # Energy for refresh commands per rank (pJ) 271system.physmem_1.actBackEnergy 11244014370 # Energy for active background per rank (pJ) 272system.physmem_1.preBackEnergy 24422958750 # Energy for precharge background per rank (pJ) 273system.physmem_1.totalEnergy 40378823040 # Total energy per rank (pJ) 274system.physmem_1.averagePower 706.620851 # Core power per rank (mW) 275system.physmem_1.memoryStateTime::IDLE 40500942500 # Time in different power states 276system.physmem_1.memoryStateTime::REF 1908140000 # Time in different power states 277system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 278system.physmem_1.memoryStateTime::ACT 14734649500 # Time in different power states 279system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 280system.cpu.branchPred.lookups 14823153 # Number of BP lookups 281system.cpu.branchPred.condPredicted 9921447 # Number of conditional branches predicted 282system.cpu.branchPred.condIncorrect 393425 # Number of conditional branches incorrect 283system.cpu.branchPred.BTBLookups 9508830 # Number of BTB lookups 284system.cpu.branchPred.BTBHits 6745421 # Number of BTB hits 285system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 286system.cpu.branchPred.BTBHitPct 70.938496 # BTB Hit Percentage 287system.cpu.branchPred.usedRAS 1716328 # Number of times the RAS was used to get a target. 288system.cpu.branchPred.RASInCorrect 3 # Number of incorrect RAS predictions. 289system.cpu_clk_domain.clock 500 # Clock period in ticks 290system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 291system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 292system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 293system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 294system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 295system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 296system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 297system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 298system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 299system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 300system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 301system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 302system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 303system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 304system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 305system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 306system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 307system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 308system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 309system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 310system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 311system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 312system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 313system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 314system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 315system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 316system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 317system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 318system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 319system.cpu.dtb.walker.walks 0 # Table walker walks requested 320system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 321system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 322system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 323system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 324system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 325system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 326system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 327system.cpu.dtb.inst_hits 0 # ITB inst hits 328system.cpu.dtb.inst_misses 0 # ITB inst misses 329system.cpu.dtb.read_hits 0 # DTB read hits 330system.cpu.dtb.read_misses 0 # DTB read misses 331system.cpu.dtb.write_hits 0 # DTB write hits 332system.cpu.dtb.write_misses 0 # DTB write misses 333system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 334system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 335system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 336system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 337system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 338system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 339system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 340system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 341system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 342system.cpu.dtb.read_accesses 0 # DTB read accesses 343system.cpu.dtb.write_accesses 0 # DTB write accesses 344system.cpu.dtb.inst_accesses 0 # ITB inst accesses 345system.cpu.dtb.hits 0 # DTB hits 346system.cpu.dtb.misses 0 # DTB misses 347system.cpu.dtb.accesses 0 # DTB accesses 348system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 349system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 350system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 351system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 352system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 353system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 354system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 355system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 356system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 357system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 358system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 359system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 360system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 361system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 362system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 363system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 364system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 365system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 366system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 367system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 368system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 369system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 370system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 371system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 372system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 373system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 374system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 375system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 376system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 377system.cpu.itb.walker.walks 0 # Table walker walks requested 378system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 379system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 380system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 381system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 382system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 383system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 384system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 385system.cpu.itb.inst_hits 0 # ITB inst hits 386system.cpu.itb.inst_misses 0 # ITB inst misses 387system.cpu.itb.read_hits 0 # DTB read hits 388system.cpu.itb.read_misses 0 # DTB read misses 389system.cpu.itb.write_hits 0 # DTB write hits 390system.cpu.itb.write_misses 0 # DTB write misses 391system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 392system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 393system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 394system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 395system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 396system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 397system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 398system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 399system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 400system.cpu.itb.read_accesses 0 # DTB read accesses 401system.cpu.itb.write_accesses 0 # DTB write accesses 402system.cpu.itb.inst_accesses 0 # ITB inst accesses 403system.cpu.itb.hits 0 # DTB hits 404system.cpu.itb.misses 0 # DTB misses 405system.cpu.itb.accesses 0 # DTB accesses 406system.cpu.workload.num_syscalls 1946 # Number of system calls 407system.cpu.numCycles 114295803 # number of cpu cycles simulated 408system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 409system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 410system.cpu.committedInsts 70915128 # Number of instructions committed 411system.cpu.committedOps 90690084 # Number of ops (including micro ops) committed 412system.cpu.discardedOps 1165738 # Number of ops (including micro ops) which were discarded before commit 413system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching 414system.cpu.cpi 1.611727 # CPI: cycles per instruction 415system.cpu.ipc 0.620453 # IPC: instructions per cycle 416system.cpu.tickCycles 95732462 # Number of cycles that the object actually ticked 417system.cpu.idleCycles 18563341 # Total number of cycles that the object has spent stopped 418system.cpu.dcache.tags.replacements 156421 # number of replacements 419system.cpu.dcache.tags.tagsinuse 4067.059654 # Cycle average of tags in use 420system.cpu.dcache.tags.total_refs 42628242 # Total number of references to valid blocks. 421system.cpu.dcache.tags.sampled_refs 160517 # Sample count of references to valid blocks. 422system.cpu.dcache.tags.avg_refs 265.568395 # Average number of references to valid blocks. 423system.cpu.dcache.tags.warmup_cycle 829804250 # Cycle when the warmup percentage was hit. 424system.cpu.dcache.tags.occ_blocks::cpu.data 4067.059654 # Average occupied blocks per requestor 425system.cpu.dcache.tags.occ_percent::cpu.data 0.992934 # Average percentage of cache occupancy 426system.cpu.dcache.tags.occ_percent::total 0.992934 # Average percentage of cache occupancy 427system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 428system.cpu.dcache.tags.age_task_id_blocks_1024::0 45 # Occupied blocks per task id 429system.cpu.dcache.tags.age_task_id_blocks_1024::1 1142 # Occupied blocks per task id 430system.cpu.dcache.tags.age_task_id_blocks_1024::2 2909 # Occupied blocks per task id 431system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 432system.cpu.dcache.tags.tag_accesses 86023319 # Number of tag accesses 433system.cpu.dcache.tags.data_accesses 86023319 # Number of data accesses 434system.cpu.dcache.ReadReq_hits::cpu.data 22869697 # number of ReadReq hits 435system.cpu.dcache.ReadReq_hits::total 22869697 # number of ReadReq hits 436system.cpu.dcache.WriteReq_hits::cpu.data 19642191 # number of WriteReq hits 437system.cpu.dcache.WriteReq_hits::total 19642191 # number of WriteReq hits 438system.cpu.dcache.SoftPFReq_hits::cpu.data 84516 # number of SoftPFReq hits 439system.cpu.dcache.SoftPFReq_hits::total 84516 # number of SoftPFReq hits 440system.cpu.dcache.LoadLockedReq_hits::cpu.data 15919 # number of LoadLockedReq hits 441system.cpu.dcache.LoadLockedReq_hits::total 15919 # number of LoadLockedReq hits 442system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits 443system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits 444system.cpu.dcache.demand_hits::cpu.data 42511888 # number of demand (read+write) hits 445system.cpu.dcache.demand_hits::total 42511888 # number of demand (read+write) hits 446system.cpu.dcache.overall_hits::cpu.data 42596404 # number of overall hits 447system.cpu.dcache.overall_hits::total 42596404 # number of overall hits 448system.cpu.dcache.ReadReq_misses::cpu.data 51738 # number of ReadReq misses 449system.cpu.dcache.ReadReq_misses::total 51738 # number of ReadReq misses 450system.cpu.dcache.WriteReq_misses::cpu.data 207710 # number of WriteReq misses 451system.cpu.dcache.WriteReq_misses::total 207710 # number of WriteReq misses 452system.cpu.dcache.SoftPFReq_misses::cpu.data 43711 # number of SoftPFReq misses 453system.cpu.dcache.SoftPFReq_misses::total 43711 # number of SoftPFReq misses 454system.cpu.dcache.demand_misses::cpu.data 259448 # number of demand (read+write) misses 455system.cpu.dcache.demand_misses::total 259448 # number of demand (read+write) misses 456system.cpu.dcache.overall_misses::cpu.data 303159 # number of overall misses 457system.cpu.dcache.overall_misses::total 303159 # number of overall misses 458system.cpu.dcache.ReadReq_miss_latency::cpu.data 1479377187 # number of ReadReq miss cycles 459system.cpu.dcache.ReadReq_miss_latency::total 1479377187 # number of ReadReq miss cycles 460system.cpu.dcache.WriteReq_miss_latency::cpu.data 16921529000 # number of WriteReq miss cycles 461system.cpu.dcache.WriteReq_miss_latency::total 16921529000 # number of WriteReq miss cycles 462system.cpu.dcache.demand_miss_latency::cpu.data 18400906187 # number of demand (read+write) miss cycles 463system.cpu.dcache.demand_miss_latency::total 18400906187 # number of demand (read+write) miss cycles 464system.cpu.dcache.overall_miss_latency::cpu.data 18400906187 # number of overall miss cycles 465system.cpu.dcache.overall_miss_latency::total 18400906187 # number of overall miss cycles 466system.cpu.dcache.ReadReq_accesses::cpu.data 22921435 # number of ReadReq accesses(hits+misses) 467system.cpu.dcache.ReadReq_accesses::total 22921435 # number of ReadReq accesses(hits+misses) 468system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) 469system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) 470system.cpu.dcache.SoftPFReq_accesses::cpu.data 128227 # number of SoftPFReq accesses(hits+misses) 471system.cpu.dcache.SoftPFReq_accesses::total 128227 # number of SoftPFReq accesses(hits+misses) 472system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15919 # number of LoadLockedReq accesses(hits+misses) 473system.cpu.dcache.LoadLockedReq_accesses::total 15919 # number of LoadLockedReq accesses(hits+misses) 474system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) 475system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) 476system.cpu.dcache.demand_accesses::cpu.data 42771336 # number of demand (read+write) accesses 477system.cpu.dcache.demand_accesses::total 42771336 # number of demand (read+write) accesses 478system.cpu.dcache.overall_accesses::cpu.data 42899563 # number of overall (read+write) accesses 479system.cpu.dcache.overall_accesses::total 42899563 # number of overall (read+write) accesses 480system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002257 # miss rate for ReadReq accesses 481system.cpu.dcache.ReadReq_miss_rate::total 0.002257 # miss rate for ReadReq accesses 482system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010464 # miss rate for WriteReq accesses 483system.cpu.dcache.WriteReq_miss_rate::total 0.010464 # miss rate for WriteReq accesses 484system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.340888 # miss rate for SoftPFReq accesses 485system.cpu.dcache.SoftPFReq_miss_rate::total 0.340888 # miss rate for SoftPFReq accesses 486system.cpu.dcache.demand_miss_rate::cpu.data 0.006066 # miss rate for demand accesses 487system.cpu.dcache.demand_miss_rate::total 0.006066 # miss rate for demand accesses 488system.cpu.dcache.overall_miss_rate::cpu.data 0.007067 # miss rate for overall accesses 489system.cpu.dcache.overall_miss_rate::total 0.007067 # miss rate for overall accesses 490system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28593.629189 # average ReadReq miss latency 491system.cpu.dcache.ReadReq_avg_miss_latency::total 28593.629189 # average ReadReq miss latency 492system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 81467.088729 # average WriteReq miss latency 493system.cpu.dcache.WriteReq_avg_miss_latency::total 81467.088729 # average WriteReq miss latency 494system.cpu.dcache.demand_avg_miss_latency::cpu.data 70923.291708 # average overall miss latency 495system.cpu.dcache.demand_avg_miss_latency::total 70923.291708 # average overall miss latency 496system.cpu.dcache.overall_avg_miss_latency::cpu.data 60697.212311 # average overall miss latency 497system.cpu.dcache.overall_avg_miss_latency::total 60697.212311 # average overall miss latency 498system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 499system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 500system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 501system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 502system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 503system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 504system.cpu.dcache.fast_writes 0 # number of fast writes performed 505system.cpu.dcache.cache_copies 0 # number of cache copies performed 506system.cpu.dcache.writebacks::writebacks 128425 # number of writebacks 507system.cpu.dcache.writebacks::total 128425 # number of writebacks 508system.cpu.dcache.ReadReq_mshr_hits::cpu.data 22255 # number of ReadReq MSHR hits 509system.cpu.dcache.ReadReq_mshr_hits::total 22255 # number of ReadReq MSHR hits 510system.cpu.dcache.WriteReq_mshr_hits::cpu.data 100680 # number of WriteReq MSHR hits 511system.cpu.dcache.WriteReq_mshr_hits::total 100680 # number of WriteReq MSHR hits 512system.cpu.dcache.demand_mshr_hits::cpu.data 122935 # number of demand (read+write) MSHR hits 513system.cpu.dcache.demand_mshr_hits::total 122935 # number of demand (read+write) MSHR hits 514system.cpu.dcache.overall_mshr_hits::cpu.data 122935 # number of overall MSHR hits 515system.cpu.dcache.overall_mshr_hits::total 122935 # number of overall MSHR hits 516system.cpu.dcache.ReadReq_mshr_misses::cpu.data 29483 # number of ReadReq MSHR misses 517system.cpu.dcache.ReadReq_mshr_misses::total 29483 # number of ReadReq MSHR misses 518system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107030 # number of WriteReq MSHR misses 519system.cpu.dcache.WriteReq_mshr_misses::total 107030 # number of WriteReq MSHR misses 520system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 24004 # number of SoftPFReq MSHR misses 521system.cpu.dcache.SoftPFReq_mshr_misses::total 24004 # number of SoftPFReq MSHR misses 522system.cpu.dcache.demand_mshr_misses::cpu.data 136513 # number of demand (read+write) MSHR misses 523system.cpu.dcache.demand_mshr_misses::total 136513 # number of demand (read+write) MSHR misses 524system.cpu.dcache.overall_mshr_misses::cpu.data 160517 # number of overall MSHR misses 525system.cpu.dcache.overall_mshr_misses::total 160517 # number of overall MSHR misses 526system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 559151063 # number of ReadReq MSHR miss cycles 527system.cpu.dcache.ReadReq_mshr_miss_latency::total 559151063 # number of ReadReq MSHR miss cycles 528system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8446390250 # number of WriteReq MSHR miss cycles 529system.cpu.dcache.WriteReq_mshr_miss_latency::total 8446390250 # number of WriteReq MSHR miss cycles 530system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1684744250 # number of SoftPFReq MSHR miss cycles 531system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1684744250 # number of SoftPFReq MSHR miss cycles 532system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9005541313 # number of demand (read+write) MSHR miss cycles 533system.cpu.dcache.demand_mshr_miss_latency::total 9005541313 # number of demand (read+write) MSHR miss cycles 534system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10690285563 # number of overall MSHR miss cycles 535system.cpu.dcache.overall_mshr_miss_latency::total 10690285563 # number of overall MSHR miss cycles 536system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001286 # mshr miss rate for ReadReq accesses 537system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001286 # mshr miss rate for ReadReq accesses 538system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005392 # mshr miss rate for WriteReq accesses 539system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005392 # mshr miss rate for WriteReq accesses 540system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.187199 # mshr miss rate for SoftPFReq accesses 541system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.187199 # mshr miss rate for SoftPFReq accesses 542system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003192 # mshr miss rate for demand accesses 543system.cpu.dcache.demand_mshr_miss_rate::total 0.003192 # mshr miss rate for demand accesses 544system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003742 # mshr miss rate for overall accesses 545system.cpu.dcache.overall_mshr_miss_rate::total 0.003742 # mshr miss rate for overall accesses 546system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18965.202422 # average ReadReq mshr miss latency 547system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18965.202422 # average ReadReq mshr miss latency 548system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78916.100626 # average WriteReq mshr miss latency 549system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78916.100626 # average WriteReq mshr miss latency 550system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 70185.979420 # average SoftPFReq mshr miss latency 551system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 70185.979420 # average SoftPFReq mshr miss latency 552system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 65968.378931 # average overall mshr miss latency 553system.cpu.dcache.demand_avg_mshr_miss_latency::total 65968.378931 # average overall mshr miss latency 554system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66599.086471 # average overall mshr miss latency 555system.cpu.dcache.overall_avg_mshr_miss_latency::total 66599.086471 # average overall mshr miss latency 556system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 557system.cpu.icache.tags.replacements 42924 # number of replacements 558system.cpu.icache.tags.tagsinuse 1852.595671 # Cycle average of tags in use 559system.cpu.icache.tags.total_refs 24987535 # Total number of references to valid blocks. 560system.cpu.icache.tags.sampled_refs 44966 # Sample count of references to valid blocks. 561system.cpu.icache.tags.avg_refs 555.698417 # Average number of references to valid blocks. 562system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 563system.cpu.icache.tags.occ_blocks::cpu.inst 1852.595671 # Average occupied blocks per requestor 564system.cpu.icache.tags.occ_percent::cpu.inst 0.904588 # Average percentage of cache occupancy 565system.cpu.icache.tags.occ_percent::total 0.904588 # Average percentage of cache occupancy 566system.cpu.icache.tags.occ_task_id_blocks::1024 2042 # Occupied blocks per task id 567system.cpu.icache.tags.age_task_id_blocks_1024::0 82 # Occupied blocks per task id 568system.cpu.icache.tags.age_task_id_blocks_1024::1 39 # Occupied blocks per task id 569system.cpu.icache.tags.age_task_id_blocks_1024::3 915 # Occupied blocks per task id 570system.cpu.icache.tags.age_task_id_blocks_1024::4 1006 # Occupied blocks per task id 571system.cpu.icache.tags.occ_task_id_percent::1024 0.997070 # Percentage of cache occupancy per task id 572system.cpu.icache.tags.tag_accesses 50109970 # Number of tag accesses 573system.cpu.icache.tags.data_accesses 50109970 # Number of data accesses 574system.cpu.icache.ReadReq_hits::cpu.inst 24987535 # number of ReadReq hits 575system.cpu.icache.ReadReq_hits::total 24987535 # number of ReadReq hits 576system.cpu.icache.demand_hits::cpu.inst 24987535 # number of demand (read+write) hits 577system.cpu.icache.demand_hits::total 24987535 # number of demand (read+write) hits 578system.cpu.icache.overall_hits::cpu.inst 24987535 # number of overall hits 579system.cpu.icache.overall_hits::total 24987535 # number of overall hits 580system.cpu.icache.ReadReq_misses::cpu.inst 44967 # number of ReadReq misses 581system.cpu.icache.ReadReq_misses::total 44967 # number of ReadReq misses 582system.cpu.icache.demand_misses::cpu.inst 44967 # number of demand (read+write) misses 583system.cpu.icache.demand_misses::total 44967 # number of demand (read+write) misses 584system.cpu.icache.overall_misses::cpu.inst 44967 # number of overall misses 585system.cpu.icache.overall_misses::total 44967 # number of overall misses 586system.cpu.icache.ReadReq_miss_latency::cpu.inst 940451988 # number of ReadReq miss cycles 587system.cpu.icache.ReadReq_miss_latency::total 940451988 # number of ReadReq miss cycles 588system.cpu.icache.demand_miss_latency::cpu.inst 940451988 # number of demand (read+write) miss cycles 589system.cpu.icache.demand_miss_latency::total 940451988 # number of demand (read+write) miss cycles 590system.cpu.icache.overall_miss_latency::cpu.inst 940451988 # number of overall miss cycles 591system.cpu.icache.overall_miss_latency::total 940451988 # number of overall miss cycles 592system.cpu.icache.ReadReq_accesses::cpu.inst 25032502 # number of ReadReq accesses(hits+misses) 593system.cpu.icache.ReadReq_accesses::total 25032502 # number of ReadReq accesses(hits+misses) 594system.cpu.icache.demand_accesses::cpu.inst 25032502 # number of demand (read+write) accesses 595system.cpu.icache.demand_accesses::total 25032502 # number of demand (read+write) accesses 596system.cpu.icache.overall_accesses::cpu.inst 25032502 # number of overall (read+write) accesses 597system.cpu.icache.overall_accesses::total 25032502 # number of overall (read+write) accesses 598system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001796 # miss rate for ReadReq accesses 599system.cpu.icache.ReadReq_miss_rate::total 0.001796 # miss rate for ReadReq accesses 600system.cpu.icache.demand_miss_rate::cpu.inst 0.001796 # miss rate for demand accesses 601system.cpu.icache.demand_miss_rate::total 0.001796 # miss rate for demand accesses 602system.cpu.icache.overall_miss_rate::cpu.inst 0.001796 # miss rate for overall accesses 603system.cpu.icache.overall_miss_rate::total 0.001796 # miss rate for overall accesses 604system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20914.270198 # average ReadReq miss latency 605system.cpu.icache.ReadReq_avg_miss_latency::total 20914.270198 # average ReadReq miss latency 606system.cpu.icache.demand_avg_miss_latency::cpu.inst 20914.270198 # average overall miss latency 607system.cpu.icache.demand_avg_miss_latency::total 20914.270198 # average overall miss latency 608system.cpu.icache.overall_avg_miss_latency::cpu.inst 20914.270198 # average overall miss latency 609system.cpu.icache.overall_avg_miss_latency::total 20914.270198 # average overall miss latency 610system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 611system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 612system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 613system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 614system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 615system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 616system.cpu.icache.fast_writes 0 # number of fast writes performed 617system.cpu.icache.cache_copies 0 # number of cache copies performed 618system.cpu.icache.ReadReq_mshr_misses::cpu.inst 44967 # number of ReadReq MSHR misses 619system.cpu.icache.ReadReq_mshr_misses::total 44967 # number of ReadReq MSHR misses 620system.cpu.icache.demand_mshr_misses::cpu.inst 44967 # number of demand (read+write) MSHR misses 621system.cpu.icache.demand_mshr_misses::total 44967 # number of demand (read+write) MSHR misses 622system.cpu.icache.overall_mshr_misses::cpu.inst 44967 # number of overall MSHR misses 623system.cpu.icache.overall_mshr_misses::total 44967 # number of overall MSHR misses 624system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 871086012 # number of ReadReq MSHR miss cycles 625system.cpu.icache.ReadReq_mshr_miss_latency::total 871086012 # number of ReadReq MSHR miss cycles 626system.cpu.icache.demand_mshr_miss_latency::cpu.inst 871086012 # number of demand (read+write) MSHR miss cycles 627system.cpu.icache.demand_mshr_miss_latency::total 871086012 # number of demand (read+write) MSHR miss cycles 628system.cpu.icache.overall_mshr_miss_latency::cpu.inst 871086012 # number of overall MSHR miss cycles 629system.cpu.icache.overall_mshr_miss_latency::total 871086012 # number of overall MSHR miss cycles 630system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001796 # mshr miss rate for ReadReq accesses 631system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001796 # mshr miss rate for ReadReq accesses 632system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001796 # mshr miss rate for demand accesses 633system.cpu.icache.demand_mshr_miss_rate::total 0.001796 # mshr miss rate for demand accesses 634system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001796 # mshr miss rate for overall accesses 635system.cpu.icache.overall_mshr_miss_rate::total 0.001796 # mshr miss rate for overall accesses 636system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19371.672827 # average ReadReq mshr miss latency 637system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19371.672827 # average ReadReq mshr miss latency 638system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19371.672827 # average overall mshr miss latency 639system.cpu.icache.demand_avg_mshr_miss_latency::total 19371.672827 # average overall mshr miss latency 640system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19371.672827 # average overall mshr miss latency 641system.cpu.icache.overall_avg_mshr_miss_latency::total 19371.672827 # average overall mshr miss latency 642system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 643system.cpu.l2cache.tags.replacements 95727 # number of replacements 644system.cpu.l2cache.tags.tagsinuse 29852.290925 # Cycle average of tags in use 645system.cpu.l2cache.tags.total_refs 99928 # Total number of references to valid blocks. 646system.cpu.l2cache.tags.sampled_refs 126845 # Sample count of references to valid blocks. 647system.cpu.l2cache.tags.avg_refs 0.787796 # Average number of references to valid blocks. 648system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 649system.cpu.l2cache.tags.occ_blocks::writebacks 26729.758607 # Average occupied blocks per requestor 650system.cpu.l2cache.tags.occ_blocks::cpu.inst 1556.401717 # Average occupied blocks per requestor 651system.cpu.l2cache.tags.occ_blocks::cpu.data 1566.130601 # Average occupied blocks per requestor 652system.cpu.l2cache.tags.occ_percent::writebacks 0.815727 # Average percentage of cache occupancy 653system.cpu.l2cache.tags.occ_percent::cpu.inst 0.047498 # Average percentage of cache occupancy 654system.cpu.l2cache.tags.occ_percent::cpu.data 0.047795 # Average percentage of cache occupancy 655system.cpu.l2cache.tags.occ_percent::total 0.911020 # Average percentage of cache occupancy 656system.cpu.l2cache.tags.occ_task_id_blocks::1024 31118 # Occupied blocks per task id 657system.cpu.l2cache.tags.age_task_id_blocks_1024::0 120 # Occupied blocks per task id 658system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1811 # Occupied blocks per task id 659system.cpu.l2cache.tags.age_task_id_blocks_1024::2 12771 # Occupied blocks per task id 660system.cpu.l2cache.tags.age_task_id_blocks_1024::3 15840 # Occupied blocks per task id 661system.cpu.l2cache.tags.age_task_id_blocks_1024::4 576 # Occupied blocks per task id 662system.cpu.l2cache.tags.occ_task_id_percent::1024 0.949646 # Percentage of cache occupancy per task id 663system.cpu.l2cache.tags.tag_accesses 2905147 # Number of tag accesses 664system.cpu.l2cache.tags.data_accesses 2905147 # Number of data accesses 665system.cpu.l2cache.ReadReq_hits::cpu.inst 39890 # number of ReadReq hits 666system.cpu.l2cache.ReadReq_hits::cpu.data 31903 # number of ReadReq hits 667system.cpu.l2cache.ReadReq_hits::total 71793 # number of ReadReq hits 668system.cpu.l2cache.Writeback_hits::writebacks 128425 # number of Writeback hits 669system.cpu.l2cache.Writeback_hits::total 128425 # number of Writeback hits 670system.cpu.l2cache.ReadExReq_hits::cpu.data 4752 # number of ReadExReq hits 671system.cpu.l2cache.ReadExReq_hits::total 4752 # number of ReadExReq hits 672system.cpu.l2cache.demand_hits::cpu.inst 39890 # number of demand (read+write) hits 673system.cpu.l2cache.demand_hits::cpu.data 36655 # number of demand (read+write) hits 674system.cpu.l2cache.demand_hits::total 76545 # number of demand (read+write) hits 675system.cpu.l2cache.overall_hits::cpu.inst 39890 # number of overall hits 676system.cpu.l2cache.overall_hits::cpu.data 36655 # number of overall hits 677system.cpu.l2cache.overall_hits::total 76545 # number of overall hits 678system.cpu.l2cache.ReadReq_misses::cpu.inst 5077 # number of ReadReq misses 679system.cpu.l2cache.ReadReq_misses::cpu.data 21584 # number of ReadReq misses 680system.cpu.l2cache.ReadReq_misses::total 26661 # number of ReadReq misses 681system.cpu.l2cache.ReadExReq_misses::cpu.data 102278 # number of ReadExReq misses 682system.cpu.l2cache.ReadExReq_misses::total 102278 # number of ReadExReq misses 683system.cpu.l2cache.demand_misses::cpu.inst 5077 # number of demand (read+write) misses 684system.cpu.l2cache.demand_misses::cpu.data 123862 # number of demand (read+write) misses 685system.cpu.l2cache.demand_misses::total 128939 # number of demand (read+write) misses 686system.cpu.l2cache.overall_misses::cpu.inst 5077 # number of overall misses 687system.cpu.l2cache.overall_misses::cpu.data 123862 # number of overall misses 688system.cpu.l2cache.overall_misses::total 128939 # number of overall misses 689system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 407245000 # number of ReadReq miss cycles 690system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1855059250 # number of ReadReq miss cycles 691system.cpu.l2cache.ReadReq_miss_latency::total 2262304250 # number of ReadReq miss cycles 692system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8289427250 # number of ReadExReq miss cycles 693system.cpu.l2cache.ReadExReq_miss_latency::total 8289427250 # number of ReadExReq miss cycles 694system.cpu.l2cache.demand_miss_latency::cpu.inst 407245000 # number of demand (read+write) miss cycles 695system.cpu.l2cache.demand_miss_latency::cpu.data 10144486500 # number of demand (read+write) miss cycles 696system.cpu.l2cache.demand_miss_latency::total 10551731500 # number of demand (read+write) miss cycles 697system.cpu.l2cache.overall_miss_latency::cpu.inst 407245000 # number of overall miss cycles 698system.cpu.l2cache.overall_miss_latency::cpu.data 10144486500 # number of overall miss cycles 699system.cpu.l2cache.overall_miss_latency::total 10551731500 # number of overall miss cycles 700system.cpu.l2cache.ReadReq_accesses::cpu.inst 44967 # number of ReadReq accesses(hits+misses) 701system.cpu.l2cache.ReadReq_accesses::cpu.data 53487 # number of ReadReq accesses(hits+misses) 702system.cpu.l2cache.ReadReq_accesses::total 98454 # number of ReadReq accesses(hits+misses) 703system.cpu.l2cache.Writeback_accesses::writebacks 128425 # number of Writeback accesses(hits+misses) 704system.cpu.l2cache.Writeback_accesses::total 128425 # number of Writeback accesses(hits+misses) 705system.cpu.l2cache.ReadExReq_accesses::cpu.data 107030 # number of ReadExReq accesses(hits+misses) 706system.cpu.l2cache.ReadExReq_accesses::total 107030 # number of ReadExReq accesses(hits+misses) 707system.cpu.l2cache.demand_accesses::cpu.inst 44967 # number of demand (read+write) accesses 708system.cpu.l2cache.demand_accesses::cpu.data 160517 # number of demand (read+write) accesses 709system.cpu.l2cache.demand_accesses::total 205484 # number of demand (read+write) accesses 710system.cpu.l2cache.overall_accesses::cpu.inst 44967 # number of overall (read+write) accesses 711system.cpu.l2cache.overall_accesses::cpu.data 160517 # number of overall (read+write) accesses 712system.cpu.l2cache.overall_accesses::total 205484 # number of overall (read+write) accesses 713system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.112905 # miss rate for ReadReq accesses 714system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.403537 # miss rate for ReadReq accesses 715system.cpu.l2cache.ReadReq_miss_rate::total 0.270797 # miss rate for ReadReq accesses 716system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.955601 # miss rate for ReadExReq accesses 717system.cpu.l2cache.ReadExReq_miss_rate::total 0.955601 # miss rate for ReadExReq accesses 718system.cpu.l2cache.demand_miss_rate::cpu.inst 0.112905 # miss rate for demand accesses 719system.cpu.l2cache.demand_miss_rate::cpu.data 0.771644 # miss rate for demand accesses 720system.cpu.l2cache.demand_miss_rate::total 0.627489 # miss rate for demand accesses 721system.cpu.l2cache.overall_miss_rate::cpu.inst 0.112905 # miss rate for overall accesses 722system.cpu.l2cache.overall_miss_rate::cpu.data 0.771644 # miss rate for overall accesses 723system.cpu.l2cache.overall_miss_rate::total 0.627489 # miss rate for overall accesses 724system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 80213.708883 # average ReadReq miss latency 725system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 85946.036416 # average ReadReq miss latency 726system.cpu.l2cache.ReadReq_avg_miss_latency::total 84854.440944 # average ReadReq miss latency 727system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81047.999081 # average ReadExReq miss latency 728system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81047.999081 # average ReadExReq miss latency 729system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80213.708883 # average overall miss latency 730system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81901.523470 # average overall miss latency 731system.cpu.l2cache.demand_avg_miss_latency::total 81835.065419 # average overall miss latency 732system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80213.708883 # average overall miss latency 733system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81901.523470 # average overall miss latency 734system.cpu.l2cache.overall_avg_miss_latency::total 81835.065419 # average overall miss latency 735system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 736system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 737system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 738system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 739system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 740system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 741system.cpu.l2cache.fast_writes 0 # number of fast writes performed 742system.cpu.l2cache.cache_copies 0 # number of cache copies performed 743system.cpu.l2cache.writebacks::writebacks 83950 # number of writebacks 744system.cpu.l2cache.writebacks::total 83950 # number of writebacks 745system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 11 # number of ReadReq MSHR hits 746system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 63 # number of ReadReq MSHR hits 747system.cpu.l2cache.ReadReq_mshr_hits::total 74 # number of ReadReq MSHR hits 748system.cpu.l2cache.demand_mshr_hits::cpu.inst 11 # number of demand (read+write) MSHR hits 749system.cpu.l2cache.demand_mshr_hits::cpu.data 63 # number of demand (read+write) MSHR hits 750system.cpu.l2cache.demand_mshr_hits::total 74 # number of demand (read+write) MSHR hits 751system.cpu.l2cache.overall_mshr_hits::cpu.inst 11 # number of overall MSHR hits 752system.cpu.l2cache.overall_mshr_hits::cpu.data 63 # number of overall MSHR hits 753system.cpu.l2cache.overall_mshr_hits::total 74 # number of overall MSHR hits 754system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 5066 # number of ReadReq MSHR misses 755system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 21521 # number of ReadReq MSHR misses 756system.cpu.l2cache.ReadReq_mshr_misses::total 26587 # number of ReadReq MSHR misses 757system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102278 # number of ReadExReq MSHR misses 758system.cpu.l2cache.ReadExReq_mshr_misses::total 102278 # number of ReadExReq MSHR misses 759system.cpu.l2cache.demand_mshr_misses::cpu.inst 5066 # number of demand (read+write) MSHR misses 760system.cpu.l2cache.demand_mshr_misses::cpu.data 123799 # number of demand (read+write) MSHR misses 761system.cpu.l2cache.demand_mshr_misses::total 128865 # number of demand (read+write) MSHR misses 762system.cpu.l2cache.overall_mshr_misses::cpu.inst 5066 # number of overall MSHR misses 763system.cpu.l2cache.overall_mshr_misses::cpu.data 123799 # number of overall MSHR misses 764system.cpu.l2cache.overall_mshr_misses::total 128865 # number of overall MSHR misses 765system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 342787750 # number of ReadReq MSHR miss cycles 766system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1580541000 # number of ReadReq MSHR miss cycles 767system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1923328750 # number of ReadReq MSHR miss cycles 768system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7010820250 # number of ReadExReq MSHR miss cycles 769system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7010820250 # number of ReadExReq MSHR miss cycles 770system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 342787750 # number of demand (read+write) MSHR miss cycles 771system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8591361250 # number of demand (read+write) MSHR miss cycles 772system.cpu.l2cache.demand_mshr_miss_latency::total 8934149000 # number of demand (read+write) MSHR miss cycles 773system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 342787750 # number of overall MSHR miss cycles 774system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8591361250 # number of overall MSHR miss cycles 775system.cpu.l2cache.overall_mshr_miss_latency::total 8934149000 # number of overall MSHR miss cycles 776system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.112660 # mshr miss rate for ReadReq accesses 777system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.402359 # mshr miss rate for ReadReq accesses 778system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.270045 # mshr miss rate for ReadReq accesses 779system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955601 # mshr miss rate for ReadExReq accesses 780system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955601 # mshr miss rate for ReadExReq accesses 781system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.112660 # mshr miss rate for demand accesses 782system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.771252 # mshr miss rate for demand accesses 783system.cpu.l2cache.demand_mshr_miss_rate::total 0.627129 # mshr miss rate for demand accesses 784system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.112660 # mshr miss rate for overall accesses 785system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.771252 # mshr miss rate for overall accesses 786system.cpu.l2cache.overall_mshr_miss_rate::total 0.627129 # mshr miss rate for overall accesses 787system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67664.380182 # average ReadReq mshr miss latency 788system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 73441.801032 # average ReadReq mshr miss latency 789system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 72340.946703 # average ReadReq mshr miss latency 790system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68546.708481 # average ReadExReq mshr miss latency 791system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68546.708481 # average ReadExReq mshr miss latency 792system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67664.380182 # average overall mshr miss latency 793system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69397.662744 # average overall mshr miss latency 794system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69329.523144 # average overall mshr miss latency 795system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67664.380182 # average overall mshr miss latency 796system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69397.662744 # average overall mshr miss latency 797system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69329.523144 # average overall mshr miss latency 798system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 799system.cpu.toL2Bus.trans_dist::ReadReq 98454 # Transaction distribution 800system.cpu.toL2Bus.trans_dist::ReadResp 98453 # Transaction distribution 801system.cpu.toL2Bus.trans_dist::Writeback 128425 # Transaction distribution 802system.cpu.toL2Bus.trans_dist::ReadExReq 107030 # Transaction distribution 803system.cpu.toL2Bus.trans_dist::ReadExResp 107030 # Transaction distribution 804system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 89933 # Packet count per connected master and slave (bytes) 805system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 449459 # Packet count per connected master and slave (bytes) 806system.cpu.toL2Bus.pkt_count::total 539392 # Packet count per connected master and slave (bytes) 807system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2877824 # Cumulative packet size per connected master and slave (bytes) 808system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18492288 # Cumulative packet size per connected master and slave (bytes) 809system.cpu.toL2Bus.pkt_size::total 21370112 # Cumulative packet size per connected master and slave (bytes) 810system.cpu.toL2Bus.snoops 0 # Total snoops (count) 811system.cpu.toL2Bus.snoop_fanout::samples 333909 # Request fanout histogram 812system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram 813system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram 814system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 815system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 816system.cpu.toL2Bus.snoop_fanout::1 333909 100.00% 100.00% # Request fanout histogram 817system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 818system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 819system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 820system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 821system.cpu.toL2Bus.snoop_fanout::total 333909 # Request fanout histogram 822system.cpu.toL2Bus.reqLayer0.occupancy 295379500 # Layer occupancy (ticks) 823system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%) 824system.cpu.toL2Bus.respLayer0.occupancy 68407488 # Layer occupancy (ticks) 825system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 826system.cpu.toL2Bus.respLayer1.occupancy 268248937 # Layer occupancy (ticks) 827system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) 828system.membus.trans_dist::ReadReq 26586 # Transaction distribution 829system.membus.trans_dist::ReadResp 26586 # Transaction distribution 830system.membus.trans_dist::Writeback 83950 # Transaction distribution 831system.membus.trans_dist::ReadExReq 102278 # Transaction distribution 832system.membus.trans_dist::ReadExResp 102278 # Transaction distribution 833system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 341678 # Packet count per connected master and slave (bytes) 834system.membus.pkt_count::total 341678 # Packet count per connected master and slave (bytes) 835system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13620096 # Cumulative packet size per connected master and slave (bytes) 836system.membus.pkt_size::total 13620096 # Cumulative packet size per connected master and slave (bytes) 837system.membus.snoops 0 # Total snoops (count) 838system.membus.snoop_fanout::samples 212814 # Request fanout histogram 839system.membus.snoop_fanout::mean 0 # Request fanout histogram 840system.membus.snoop_fanout::stdev 0 # Request fanout histogram 841system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 842system.membus.snoop_fanout::0 212814 100.00% 100.00% # Request fanout histogram 843system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 844system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 845system.membus.snoop_fanout::min_value 0 # Request fanout histogram 846system.membus.snoop_fanout::max_value 0 # Request fanout histogram 847system.membus.snoop_fanout::total 212814 # Request fanout histogram 848system.membus.reqLayer0.occupancy 578378500 # Layer occupancy (ticks) 849system.membus.reqLayer0.utilization 1.0 # Layer utilization (%) 850system.membus.respLayer1.occupancy 680081000 # Layer occupancy (ticks) 851system.membus.respLayer1.utilization 1.2 # Layer utilization (%) 852 853---------- End Simulation Statistics ---------- 854