stats.txt revision 9797:9cd5f91e7a79
14434Ssaidi@eecs.umich.edu 24434Ssaidi@eecs.umich.edu---------- Begin Simulation Statistics ---------- 34434Ssaidi@eecs.umich.edusim_seconds 2.326119 # Number of seconds simulated 44434Ssaidi@eecs.umich.edusim_ticks 2326118592000 # Number of ticks simulated 54434Ssaidi@eecs.umich.edufinal_tick 2326118592000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 64434Ssaidi@eecs.umich.edusim_freq 1000000000000 # Frequency of simulated ticks 74434Ssaidi@eecs.umich.eduhost_inst_rate 575384 # Simulator instruction rate (inst/s) 84434Ssaidi@eecs.umich.eduhost_op_rate 780549 # Simulator op (including micro ops) rate (op/s) 94434Ssaidi@eecs.umich.eduhost_tick_rate 968736790 # Simulator tick rate (ticks/s) 104434Ssaidi@eecs.umich.eduhost_mem_usage 250996 # Number of bytes of host memory used 114434Ssaidi@eecs.umich.eduhost_seconds 2401.19 # Real time elapsed on the host 124434Ssaidi@eecs.umich.edusim_insts 1381604339 # Number of instructions simulated 134434Ssaidi@eecs.umich.edusim_ops 1874244941 # Number of ops (including micro ops) simulated 144434Ssaidi@eecs.umich.edusystem.physmem.bytes_read::cpu.inst 113472 # Number of bytes read from this memory 154434Ssaidi@eecs.umich.edusystem.physmem.bytes_read::cpu.data 30232512 # Number of bytes read from this memory 164434Ssaidi@eecs.umich.edusystem.physmem.bytes_read::total 30345984 # Number of bytes read from this memory 174434Ssaidi@eecs.umich.edusystem.physmem.bytes_inst_read::cpu.inst 113472 # Number of instructions bytes read from this memory 184434Ssaidi@eecs.umich.edusystem.physmem.bytes_inst_read::total 113472 # Number of instructions bytes read from this memory 194434Ssaidi@eecs.umich.edusystem.physmem.bytes_written::writebacks 4230336 # Number of bytes written to this memory 204434Ssaidi@eecs.umich.edusystem.physmem.bytes_written::total 4230336 # Number of bytes written to this memory 214434Ssaidi@eecs.umich.edusystem.physmem.num_reads::cpu.inst 1773 # Number of read requests responded to by this memory 224434Ssaidi@eecs.umich.edusystem.physmem.num_reads::cpu.data 472383 # Number of read requests responded to by this memory 234434Ssaidi@eecs.umich.edusystem.physmem.num_reads::total 474156 # Number of read requests responded to by this memory 244434Ssaidi@eecs.umich.edusystem.physmem.num_writes::writebacks 66099 # Number of write requests responded to by this memory 254434Ssaidi@eecs.umich.edusystem.physmem.num_writes::total 66099 # Number of write requests responded to by this memory 264434Ssaidi@eecs.umich.edusystem.physmem.bw_read::cpu.inst 48782 # Total read bandwidth from this memory (bytes/s) 274434Ssaidi@eecs.umich.edusystem.physmem.bw_read::cpu.data 12996978 # Total read bandwidth from this memory (bytes/s) 284434Ssaidi@eecs.umich.edusystem.physmem.bw_read::total 13045760 # Total read bandwidth from this memory (bytes/s) 294434Ssaidi@eecs.umich.edusystem.physmem.bw_inst_read::cpu.inst 48782 # Instruction read bandwidth from this memory (bytes/s) 304434Ssaidi@eecs.umich.edusystem.physmem.bw_inst_read::total 48782 # Instruction read bandwidth from this memory (bytes/s) 314434Ssaidi@eecs.umich.edusystem.physmem.bw_write::writebacks 1818624 # Write bandwidth from this memory (bytes/s) 324434Ssaidi@eecs.umich.edusystem.physmem.bw_write::total 1818624 # Write bandwidth from this memory (bytes/s) 334434Ssaidi@eecs.umich.edusystem.physmem.bw_total::writebacks 1818624 # Total bandwidth to/from this memory (bytes/s) 344434Ssaidi@eecs.umich.edusystem.physmem.bw_total::cpu.inst 48782 # Total bandwidth to/from this memory (bytes/s) 354434Ssaidi@eecs.umich.edusystem.physmem.bw_total::cpu.data 12996978 # Total bandwidth to/from this memory (bytes/s) 364434Ssaidi@eecs.umich.edusystem.physmem.bw_total::total 14864384 # Total bandwidth to/from this memory (bytes/s) 374434Ssaidi@eecs.umich.edusystem.membus.throughput 14864384 # Throughput (bytes/s) 388706Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadReq 408063 # Transaction distribution 397678Sgblack@eecs.umich.edusystem.membus.trans_dist::ReadResp 408063 # Transaction distribution 404434Ssaidi@eecs.umich.edusystem.membus.trans_dist::Writeback 66099 # Transaction distribution 414434Ssaidi@eecs.umich.edusystem.membus.trans_dist::ReadExReq 66093 # Transaction distribution 424434Ssaidi@eecs.umich.edusystem.membus.trans_dist::ReadExResp 66093 # Transaction distribution 434434Ssaidi@eecs.umich.edusystem.membus.pkt_count_system.cpu.l2cache.mem_side 1014411 # Packet count per connected master and slave (bytes) 444434Ssaidi@eecs.umich.edusystem.membus.pkt_count 1014411 # Packet count per connected master and slave (bytes) 454434Ssaidi@eecs.umich.edusystem.membus.tot_pkt_size_system.cpu.l2cache.mem_side 34576320 # Cumulative packet size per connected master and slave (bytes) 468852Sandreas.hansson@arm.comsystem.membus.tot_pkt_size 34576320 # Cumulative packet size per connected master and slave (bytes) 474434Ssaidi@eecs.umich.edusystem.membus.data_through_bus 34576320 # Total data (bytes) 484434Ssaidi@eecs.umich.edusystem.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 496227Snate@binkert.orgsystem.membus.reqLayer0.occupancy 1069047000 # Layer occupancy (ticks) 508737Skoansin.tan@gmail.comsystem.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 518852Sandreas.hansson@arm.comsystem.membus.respLayer1.occupancy 4267404000 # Layer occupancy (ticks) 524434Ssaidi@eecs.umich.edusystem.membus.respLayer1.utilization 0.2 # Layer utilization (%) 538852Sandreas.hansson@arm.comsystem.cpu.dtb.inst_hits 0 # ITB inst hits 544434Ssaidi@eecs.umich.edusystem.cpu.dtb.inst_misses 0 # ITB inst misses 554434Ssaidi@eecs.umich.edusystem.cpu.dtb.read_hits 0 # DTB read hits 564434Ssaidi@eecs.umich.edusystem.cpu.dtb.read_misses 0 # DTB read misses 574434Ssaidi@eecs.umich.edusystem.cpu.dtb.write_hits 0 # DTB write hits 584434Ssaidi@eecs.umich.edusystem.cpu.dtb.write_misses 0 # DTB write misses 594434Ssaidi@eecs.umich.edusystem.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 608852Sandreas.hansson@arm.comsystem.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 614434Ssaidi@eecs.umich.edusystem.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 624434Ssaidi@eecs.umich.edusystem.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 634434Ssaidi@eecs.umich.edusystem.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 64system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 65system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 66system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 67system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 68system.cpu.dtb.read_accesses 0 # DTB read accesses 69system.cpu.dtb.write_accesses 0 # DTB write accesses 70system.cpu.dtb.inst_accesses 0 # ITB inst accesses 71system.cpu.dtb.hits 0 # DTB hits 72system.cpu.dtb.misses 0 # DTB misses 73system.cpu.dtb.accesses 0 # DTB accesses 74system.cpu.itb.inst_hits 0 # ITB inst hits 75system.cpu.itb.inst_misses 0 # ITB inst misses 76system.cpu.itb.read_hits 0 # DTB read hits 77system.cpu.itb.read_misses 0 # DTB read misses 78system.cpu.itb.write_hits 0 # DTB write hits 79system.cpu.itb.write_misses 0 # DTB write misses 80system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 81system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 82system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 83system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 84system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 85system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 86system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 87system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 88system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 89system.cpu.itb.read_accesses 0 # DTB read accesses 90system.cpu.itb.write_accesses 0 # DTB write accesses 91system.cpu.itb.inst_accesses 0 # ITB inst accesses 92system.cpu.itb.hits 0 # DTB hits 93system.cpu.itb.misses 0 # DTB misses 94system.cpu.itb.accesses 0 # DTB accesses 95system.cpu.workload.num_syscalls 1411 # Number of system calls 96system.cpu.numCycles 4652237184 # number of cpu cycles simulated 97system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 98system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 99system.cpu.committedInsts 1381604339 # Number of instructions committed 100system.cpu.committedOps 1874244941 # Number of ops (including micro ops) committed 101system.cpu.num_int_alu_accesses 1653698868 # Number of integer alu accesses 102system.cpu.num_fp_alu_accesses 52289415 # Number of float alu accesses 103system.cpu.num_func_calls 80372855 # number of times a function call or return occured 104system.cpu.num_conditional_control_insts 230619738 # number of instructions that are conditional controls 105system.cpu.num_int_insts 1653698868 # number of integer instructions 106system.cpu.num_fp_insts 52289415 # number of float instructions 107system.cpu.num_int_register_reads 10466679913 # number of times the integer registers were read 108system.cpu.num_int_register_writes 1874331393 # number of times the integer registers were written 109system.cpu.num_fp_register_reads 60540850 # number of times the floating registers were read 110system.cpu.num_fp_register_writes 46777010 # number of times the floating registers were written 111system.cpu.num_mem_refs 908382479 # number of memory refs 112system.cpu.num_load_insts 631387181 # Number of load instructions 113system.cpu.num_store_insts 276995298 # Number of store instructions 114system.cpu.num_idle_cycles 0 # Number of idle cycles 115system.cpu.num_busy_cycles 4652237184 # Number of busy cycles 116system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles 117system.cpu.idle_fraction 0 # Percentage of idle cycles 118system.cpu.icache.tags.replacements 18364 # number of replacements 119system.cpu.icache.tags.tagsinuse 1392.317060 # Cycle average of tags in use 120system.cpu.icache.tags.total_refs 1390251699 # Total number of references to valid blocks. 121system.cpu.icache.tags.sampled_refs 19803 # Sample count of references to valid blocks. 122system.cpu.icache.tags.avg_refs 70204.095289 # Average number of references to valid blocks. 123system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 124system.cpu.icache.tags.occ_blocks::cpu.inst 1392.317060 # Average occupied blocks per requestor 125system.cpu.icache.tags.occ_percent::cpu.inst 0.679842 # Average percentage of cache occupancy 126system.cpu.icache.tags.occ_percent::total 0.679842 # Average percentage of cache occupancy 127system.cpu.icache.ReadReq_hits::cpu.inst 1390251699 # number of ReadReq hits 128system.cpu.icache.ReadReq_hits::total 1390251699 # number of ReadReq hits 129system.cpu.icache.demand_hits::cpu.inst 1390251699 # number of demand (read+write) hits 130system.cpu.icache.demand_hits::total 1390251699 # number of demand (read+write) hits 131system.cpu.icache.overall_hits::cpu.inst 1390251699 # number of overall hits 132system.cpu.icache.overall_hits::total 1390251699 # number of overall hits 133system.cpu.icache.ReadReq_misses::cpu.inst 19803 # number of ReadReq misses 134system.cpu.icache.ReadReq_misses::total 19803 # number of ReadReq misses 135system.cpu.icache.demand_misses::cpu.inst 19803 # number of demand (read+write) misses 136system.cpu.icache.demand_misses::total 19803 # number of demand (read+write) misses 137system.cpu.icache.overall_misses::cpu.inst 19803 # number of overall misses 138system.cpu.icache.overall_misses::total 19803 # number of overall misses 139system.cpu.icache.ReadReq_miss_latency::cpu.inst 331911000 # number of ReadReq miss cycles 140system.cpu.icache.ReadReq_miss_latency::total 331911000 # number of ReadReq miss cycles 141system.cpu.icache.demand_miss_latency::cpu.inst 331911000 # number of demand (read+write) miss cycles 142system.cpu.icache.demand_miss_latency::total 331911000 # number of demand (read+write) miss cycles 143system.cpu.icache.overall_miss_latency::cpu.inst 331911000 # number of overall miss cycles 144system.cpu.icache.overall_miss_latency::total 331911000 # number of overall miss cycles 145system.cpu.icache.ReadReq_accesses::cpu.inst 1390271502 # number of ReadReq accesses(hits+misses) 146system.cpu.icache.ReadReq_accesses::total 1390271502 # number of ReadReq accesses(hits+misses) 147system.cpu.icache.demand_accesses::cpu.inst 1390271502 # number of demand (read+write) accesses 148system.cpu.icache.demand_accesses::total 1390271502 # number of demand (read+write) accesses 149system.cpu.icache.overall_accesses::cpu.inst 1390271502 # number of overall (read+write) accesses 150system.cpu.icache.overall_accesses::total 1390271502 # number of overall (read+write) accesses 151system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000014 # miss rate for ReadReq accesses 152system.cpu.icache.ReadReq_miss_rate::total 0.000014 # miss rate for ReadReq accesses 153system.cpu.icache.demand_miss_rate::cpu.inst 0.000014 # miss rate for demand accesses 154system.cpu.icache.demand_miss_rate::total 0.000014 # miss rate for demand accesses 155system.cpu.icache.overall_miss_rate::cpu.inst 0.000014 # miss rate for overall accesses 156system.cpu.icache.overall_miss_rate::total 0.000014 # miss rate for overall accesses 157system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16760.642327 # average ReadReq miss latency 158system.cpu.icache.ReadReq_avg_miss_latency::total 16760.642327 # average ReadReq miss latency 159system.cpu.icache.demand_avg_miss_latency::cpu.inst 16760.642327 # average overall miss latency 160system.cpu.icache.demand_avg_miss_latency::total 16760.642327 # average overall miss latency 161system.cpu.icache.overall_avg_miss_latency::cpu.inst 16760.642327 # average overall miss latency 162system.cpu.icache.overall_avg_miss_latency::total 16760.642327 # average overall miss latency 163system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 164system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 165system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 166system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 167system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 168system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 169system.cpu.icache.fast_writes 0 # number of fast writes performed 170system.cpu.icache.cache_copies 0 # number of cache copies performed 171system.cpu.icache.ReadReq_mshr_misses::cpu.inst 19803 # number of ReadReq MSHR misses 172system.cpu.icache.ReadReq_mshr_misses::total 19803 # number of ReadReq MSHR misses 173system.cpu.icache.demand_mshr_misses::cpu.inst 19803 # number of demand (read+write) MSHR misses 174system.cpu.icache.demand_mshr_misses::total 19803 # number of demand (read+write) MSHR misses 175system.cpu.icache.overall_mshr_misses::cpu.inst 19803 # number of overall MSHR misses 176system.cpu.icache.overall_mshr_misses::total 19803 # number of overall MSHR misses 177system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 292305000 # number of ReadReq MSHR miss cycles 178system.cpu.icache.ReadReq_mshr_miss_latency::total 292305000 # number of ReadReq MSHR miss cycles 179system.cpu.icache.demand_mshr_miss_latency::cpu.inst 292305000 # number of demand (read+write) MSHR miss cycles 180system.cpu.icache.demand_mshr_miss_latency::total 292305000 # number of demand (read+write) MSHR miss cycles 181system.cpu.icache.overall_mshr_miss_latency::cpu.inst 292305000 # number of overall MSHR miss cycles 182system.cpu.icache.overall_mshr_miss_latency::total 292305000 # number of overall MSHR miss cycles 183system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000014 # mshr miss rate for ReadReq accesses 184system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000014 # mshr miss rate for ReadReq accesses 185system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000014 # mshr miss rate for demand accesses 186system.cpu.icache.demand_mshr_miss_rate::total 0.000014 # mshr miss rate for demand accesses 187system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000014 # mshr miss rate for overall accesses 188system.cpu.icache.overall_mshr_miss_rate::total 0.000014 # mshr miss rate for overall accesses 189system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14760.642327 # average ReadReq mshr miss latency 190system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14760.642327 # average ReadReq mshr miss latency 191system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14760.642327 # average overall mshr miss latency 192system.cpu.icache.demand_avg_mshr_miss_latency::total 14760.642327 # average overall mshr miss latency 193system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14760.642327 # average overall mshr miss latency 194system.cpu.icache.overall_avg_mshr_miss_latency::total 14760.642327 # average overall mshr miss latency 195system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 196system.cpu.l2cache.tags.replacements 441378 # number of replacements 197system.cpu.l2cache.tags.tagsinuse 32692.891822 # Cycle average of tags in use 198system.cpu.l2cache.tags.total_refs 1102614 # Total number of references to valid blocks. 199system.cpu.l2cache.tags.sampled_refs 474121 # Sample count of references to valid blocks. 200system.cpu.l2cache.tags.avg_refs 2.325596 # Average number of references to valid blocks. 201system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 202system.cpu.l2cache.tags.occ_blocks::writebacks 1298.141733 # Average occupied blocks per requestor 203system.cpu.l2cache.tags.occ_blocks::cpu.inst 30.233408 # Average occupied blocks per requestor 204system.cpu.l2cache.tags.occ_blocks::cpu.data 31364.516681 # Average occupied blocks per requestor 205system.cpu.l2cache.tags.occ_percent::writebacks 0.039616 # Average percentage of cache occupancy 206system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000923 # Average percentage of cache occupancy 207system.cpu.l2cache.tags.occ_percent::cpu.data 0.957169 # Average percentage of cache occupancy 208system.cpu.l2cache.tags.occ_percent::total 0.997708 # Average percentage of cache occupancy 209system.cpu.l2cache.ReadReq_hits::cpu.inst 18030 # number of ReadReq hits 210system.cpu.l2cache.ReadReq_hits::cpu.data 1054583 # number of ReadReq hits 211system.cpu.l2cache.ReadReq_hits::total 1072613 # number of ReadReq hits 212system.cpu.l2cache.Writeback_hits::writebacks 96257 # number of Writeback hits 213system.cpu.l2cache.Writeback_hits::total 96257 # number of Writeback hits 214system.cpu.l2cache.ReadExReq_hits::cpu.data 6687 # number of ReadExReq hits 215system.cpu.l2cache.ReadExReq_hits::total 6687 # number of ReadExReq hits 216system.cpu.l2cache.demand_hits::cpu.inst 18030 # number of demand (read+write) hits 217system.cpu.l2cache.demand_hits::cpu.data 1061270 # number of demand (read+write) hits 218system.cpu.l2cache.demand_hits::total 1079300 # number of demand (read+write) hits 219system.cpu.l2cache.overall_hits::cpu.inst 18030 # number of overall hits 220system.cpu.l2cache.overall_hits::cpu.data 1061270 # number of overall hits 221system.cpu.l2cache.overall_hits::total 1079300 # number of overall hits 222system.cpu.l2cache.ReadReq_misses::cpu.inst 1773 # number of ReadReq misses 223system.cpu.l2cache.ReadReq_misses::cpu.data 406290 # number of ReadReq misses 224system.cpu.l2cache.ReadReq_misses::total 408063 # number of ReadReq misses 225system.cpu.l2cache.ReadExReq_misses::cpu.data 66093 # number of ReadExReq misses 226system.cpu.l2cache.ReadExReq_misses::total 66093 # number of ReadExReq misses 227system.cpu.l2cache.demand_misses::cpu.inst 1773 # number of demand (read+write) misses 228system.cpu.l2cache.demand_misses::cpu.data 472383 # number of demand (read+write) misses 229system.cpu.l2cache.demand_misses::total 474156 # number of demand (read+write) misses 230system.cpu.l2cache.overall_misses::cpu.inst 1773 # number of overall misses 231system.cpu.l2cache.overall_misses::cpu.data 472383 # number of overall misses 232system.cpu.l2cache.overall_misses::total 474156 # number of overall misses 233system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 92202000 # number of ReadReq miss cycles 234system.cpu.l2cache.ReadReq_miss_latency::cpu.data 21127080000 # number of ReadReq miss cycles 235system.cpu.l2cache.ReadReq_miss_latency::total 21219282000 # number of ReadReq miss cycles 236system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3436836000 # number of ReadExReq miss cycles 237system.cpu.l2cache.ReadExReq_miss_latency::total 3436836000 # number of ReadExReq miss cycles 238system.cpu.l2cache.demand_miss_latency::cpu.inst 92202000 # number of demand (read+write) miss cycles 239system.cpu.l2cache.demand_miss_latency::cpu.data 24563916000 # number of demand (read+write) miss cycles 240system.cpu.l2cache.demand_miss_latency::total 24656118000 # number of demand (read+write) miss cycles 241system.cpu.l2cache.overall_miss_latency::cpu.inst 92202000 # number of overall miss cycles 242system.cpu.l2cache.overall_miss_latency::cpu.data 24563916000 # number of overall miss cycles 243system.cpu.l2cache.overall_miss_latency::total 24656118000 # number of overall miss cycles 244system.cpu.l2cache.ReadReq_accesses::cpu.inst 19803 # number of ReadReq accesses(hits+misses) 245system.cpu.l2cache.ReadReq_accesses::cpu.data 1460873 # number of ReadReq accesses(hits+misses) 246system.cpu.l2cache.ReadReq_accesses::total 1480676 # number of ReadReq accesses(hits+misses) 247system.cpu.l2cache.Writeback_accesses::writebacks 96257 # number of Writeback accesses(hits+misses) 248system.cpu.l2cache.Writeback_accesses::total 96257 # number of Writeback accesses(hits+misses) 249system.cpu.l2cache.ReadExReq_accesses::cpu.data 72780 # number of ReadExReq accesses(hits+misses) 250system.cpu.l2cache.ReadExReq_accesses::total 72780 # number of ReadExReq accesses(hits+misses) 251system.cpu.l2cache.demand_accesses::cpu.inst 19803 # number of demand (read+write) accesses 252system.cpu.l2cache.demand_accesses::cpu.data 1533653 # number of demand (read+write) accesses 253system.cpu.l2cache.demand_accesses::total 1553456 # number of demand (read+write) accesses 254system.cpu.l2cache.overall_accesses::cpu.inst 19803 # number of overall (read+write) accesses 255system.cpu.l2cache.overall_accesses::cpu.data 1533653 # number of overall (read+write) accesses 256system.cpu.l2cache.overall_accesses::total 1553456 # number of overall (read+write) accesses 257system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.089532 # miss rate for ReadReq accesses 258system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.278115 # miss rate for ReadReq accesses 259system.cpu.l2cache.ReadReq_miss_rate::total 0.275592 # miss rate for ReadReq accesses 260system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.908120 # miss rate for ReadExReq accesses 261system.cpu.l2cache.ReadExReq_miss_rate::total 0.908120 # miss rate for ReadExReq accesses 262system.cpu.l2cache.demand_miss_rate::cpu.inst 0.089532 # miss rate for demand accesses 263system.cpu.l2cache.demand_miss_rate::cpu.data 0.308012 # miss rate for demand accesses 264system.cpu.l2cache.demand_miss_rate::total 0.305227 # miss rate for demand accesses 265system.cpu.l2cache.overall_miss_rate::cpu.inst 0.089532 # miss rate for overall accesses 266system.cpu.l2cache.overall_miss_rate::cpu.data 0.308012 # miss rate for overall accesses 267system.cpu.l2cache.overall_miss_rate::total 0.305227 # miss rate for overall accesses 268system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52003.384095 # average ReadReq miss latency 269system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency 270system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000.014704 # average ReadReq miss latency 271system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency 272system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency 273system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52003.384095 # average overall miss latency 274system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency 275system.cpu.l2cache.demand_avg_miss_latency::total 52000.012654 # average overall miss latency 276system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52003.384095 # average overall miss latency 277system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency 278system.cpu.l2cache.overall_avg_miss_latency::total 52000.012654 # average overall miss latency 279system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 280system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 281system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 282system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 283system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 284system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 285system.cpu.l2cache.fast_writes 0 # number of fast writes performed 286system.cpu.l2cache.cache_copies 0 # number of cache copies performed 287system.cpu.l2cache.writebacks::writebacks 66099 # number of writebacks 288system.cpu.l2cache.writebacks::total 66099 # number of writebacks 289system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1773 # number of ReadReq MSHR misses 290system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 406290 # number of ReadReq MSHR misses 291system.cpu.l2cache.ReadReq_mshr_misses::total 408063 # number of ReadReq MSHR misses 292system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66093 # number of ReadExReq MSHR misses 293system.cpu.l2cache.ReadExReq_mshr_misses::total 66093 # number of ReadExReq MSHR misses 294system.cpu.l2cache.demand_mshr_misses::cpu.inst 1773 # number of demand (read+write) MSHR misses 295system.cpu.l2cache.demand_mshr_misses::cpu.data 472383 # number of demand (read+write) MSHR misses 296system.cpu.l2cache.demand_mshr_misses::total 474156 # number of demand (read+write) MSHR misses 297system.cpu.l2cache.overall_mshr_misses::cpu.inst 1773 # number of overall MSHR misses 298system.cpu.l2cache.overall_mshr_misses::cpu.data 472383 # number of overall MSHR misses 299system.cpu.l2cache.overall_mshr_misses::total 474156 # number of overall MSHR misses 300system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 70926000 # number of ReadReq MSHR miss cycles 301system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 16251600000 # number of ReadReq MSHR miss cycles 302system.cpu.l2cache.ReadReq_mshr_miss_latency::total 16322526000 # number of ReadReq MSHR miss cycles 303system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2643720000 # number of ReadExReq MSHR miss cycles 304system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2643720000 # number of ReadExReq MSHR miss cycles 305system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 70926000 # number of demand (read+write) MSHR miss cycles 306system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 18895320000 # number of demand (read+write) MSHR miss cycles 307system.cpu.l2cache.demand_mshr_miss_latency::total 18966246000 # number of demand (read+write) MSHR miss cycles 308system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 70926000 # number of overall MSHR miss cycles 309system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 18895320000 # number of overall MSHR miss cycles 310system.cpu.l2cache.overall_mshr_miss_latency::total 18966246000 # number of overall MSHR miss cycles 311system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.089532 # mshr miss rate for ReadReq accesses 312system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.278115 # mshr miss rate for ReadReq accesses 313system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.275592 # mshr miss rate for ReadReq accesses 314system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.908120 # mshr miss rate for ReadExReq accesses 315system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.908120 # mshr miss rate for ReadExReq accesses 316system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.089532 # mshr miss rate for demand accesses 317system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.308012 # mshr miss rate for demand accesses 318system.cpu.l2cache.demand_mshr_miss_rate::total 0.305227 # mshr miss rate for demand accesses 319system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.089532 # mshr miss rate for overall accesses 320system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.308012 # mshr miss rate for overall accesses 321system.cpu.l2cache.overall_mshr_miss_rate::total 0.305227 # mshr miss rate for overall accesses 322system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40003.384095 # average ReadReq mshr miss latency 323system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency 324system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000.014704 # average ReadReq mshr miss latency 325system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency 326system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency 327system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40003.384095 # average overall mshr miss latency 328system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency 329system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000.012654 # average overall mshr miss latency 330system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40003.384095 # average overall mshr miss latency 331system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency 332system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.012654 # average overall mshr miss latency 333system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 334system.cpu.dcache.tags.replacements 1529557 # number of replacements 335system.cpu.dcache.tags.tagsinuse 4094.947189 # Cycle average of tags in use 336system.cpu.dcache.tags.total_refs 895757408 # Total number of references to valid blocks. 337system.cpu.dcache.tags.sampled_refs 1533653 # Sample count of references to valid blocks. 338system.cpu.dcache.tags.avg_refs 584.067848 # Average number of references to valid blocks. 339system.cpu.dcache.tags.warmup_cycle 991199000 # Cycle when the warmup percentage was hit. 340system.cpu.dcache.tags.occ_blocks::cpu.data 4094.947189 # Average occupied blocks per requestor 341system.cpu.dcache.tags.occ_percent::cpu.data 0.999743 # Average percentage of cache occupancy 342system.cpu.dcache.tags.occ_percent::total 0.999743 # Average percentage of cache occupancy 343system.cpu.dcache.ReadReq_hits::cpu.data 618874540 # number of ReadReq hits 344system.cpu.dcache.ReadReq_hits::total 618874540 # number of ReadReq hits 345system.cpu.dcache.WriteReq_hits::cpu.data 276862898 # number of WriteReq hits 346system.cpu.dcache.WriteReq_hits::total 276862898 # number of WriteReq hits 347system.cpu.dcache.LoadLockedReq_hits::cpu.data 9985 # number of LoadLockedReq hits 348system.cpu.dcache.LoadLockedReq_hits::total 9985 # number of LoadLockedReq hits 349system.cpu.dcache.StoreCondReq_hits::cpu.data 9985 # number of StoreCondReq hits 350system.cpu.dcache.StoreCondReq_hits::total 9985 # number of StoreCondReq hits 351system.cpu.dcache.demand_hits::cpu.data 895737438 # number of demand (read+write) hits 352system.cpu.dcache.demand_hits::total 895737438 # number of demand (read+write) hits 353system.cpu.dcache.overall_hits::cpu.data 895737438 # number of overall hits 354system.cpu.dcache.overall_hits::total 895737438 # number of overall hits 355system.cpu.dcache.ReadReq_misses::cpu.data 1460873 # number of ReadReq misses 356system.cpu.dcache.ReadReq_misses::total 1460873 # number of ReadReq misses 357system.cpu.dcache.WriteReq_misses::cpu.data 72780 # number of WriteReq misses 358system.cpu.dcache.WriteReq_misses::total 72780 # number of WriteReq misses 359system.cpu.dcache.demand_misses::cpu.data 1533653 # number of demand (read+write) misses 360system.cpu.dcache.demand_misses::total 1533653 # number of demand (read+write) misses 361system.cpu.dcache.overall_misses::cpu.data 1533653 # number of overall misses 362system.cpu.dcache.overall_misses::total 1533653 # number of overall misses 363system.cpu.dcache.ReadReq_miss_latency::cpu.data 36055529000 # number of ReadReq miss cycles 364system.cpu.dcache.ReadReq_miss_latency::total 36055529000 # number of ReadReq miss cycles 365system.cpu.dcache.WriteReq_miss_latency::cpu.data 3722046000 # number of WriteReq miss cycles 366system.cpu.dcache.WriteReq_miss_latency::total 3722046000 # number of WriteReq miss cycles 367system.cpu.dcache.demand_miss_latency::cpu.data 39777575000 # number of demand (read+write) miss cycles 368system.cpu.dcache.demand_miss_latency::total 39777575000 # number of demand (read+write) miss cycles 369system.cpu.dcache.overall_miss_latency::cpu.data 39777575000 # number of overall miss cycles 370system.cpu.dcache.overall_miss_latency::total 39777575000 # number of overall miss cycles 371system.cpu.dcache.ReadReq_accesses::cpu.data 620335413 # number of ReadReq accesses(hits+misses) 372system.cpu.dcache.ReadReq_accesses::total 620335413 # number of ReadReq accesses(hits+misses) 373system.cpu.dcache.WriteReq_accesses::cpu.data 276935678 # number of WriteReq accesses(hits+misses) 374system.cpu.dcache.WriteReq_accesses::total 276935678 # number of WriteReq accesses(hits+misses) 375system.cpu.dcache.LoadLockedReq_accesses::cpu.data 9985 # number of LoadLockedReq accesses(hits+misses) 376system.cpu.dcache.LoadLockedReq_accesses::total 9985 # number of LoadLockedReq accesses(hits+misses) 377system.cpu.dcache.StoreCondReq_accesses::cpu.data 9985 # number of StoreCondReq accesses(hits+misses) 378system.cpu.dcache.StoreCondReq_accesses::total 9985 # number of StoreCondReq accesses(hits+misses) 379system.cpu.dcache.demand_accesses::cpu.data 897271091 # number of demand (read+write) accesses 380system.cpu.dcache.demand_accesses::total 897271091 # number of demand (read+write) accesses 381system.cpu.dcache.overall_accesses::cpu.data 897271091 # number of overall (read+write) accesses 382system.cpu.dcache.overall_accesses::total 897271091 # number of overall (read+write) accesses 383system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002355 # miss rate for ReadReq accesses 384system.cpu.dcache.ReadReq_miss_rate::total 0.002355 # miss rate for ReadReq accesses 385system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000263 # miss rate for WriteReq accesses 386system.cpu.dcache.WriteReq_miss_rate::total 0.000263 # miss rate for WriteReq accesses 387system.cpu.dcache.demand_miss_rate::cpu.data 0.001709 # miss rate for demand accesses 388system.cpu.dcache.demand_miss_rate::total 0.001709 # miss rate for demand accesses 389system.cpu.dcache.overall_miss_rate::cpu.data 0.001709 # miss rate for overall accesses 390system.cpu.dcache.overall_miss_rate::total 0.001709 # miss rate for overall accesses 391system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24680.810036 # average ReadReq miss latency 392system.cpu.dcache.ReadReq_avg_miss_latency::total 24680.810036 # average ReadReq miss latency 393system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 51141.055235 # average WriteReq miss latency 394system.cpu.dcache.WriteReq_avg_miss_latency::total 51141.055235 # average WriteReq miss latency 395system.cpu.dcache.demand_avg_miss_latency::cpu.data 25936.489545 # average overall miss latency 396system.cpu.dcache.demand_avg_miss_latency::total 25936.489545 # average overall miss latency 397system.cpu.dcache.overall_avg_miss_latency::cpu.data 25936.489545 # average overall miss latency 398system.cpu.dcache.overall_avg_miss_latency::total 25936.489545 # average overall miss latency 399system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 400system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 401system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 402system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 403system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 404system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 405system.cpu.dcache.fast_writes 0 # number of fast writes performed 406system.cpu.dcache.cache_copies 0 # number of cache copies performed 407system.cpu.dcache.writebacks::writebacks 96257 # number of writebacks 408system.cpu.dcache.writebacks::total 96257 # number of writebacks 409system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1460873 # number of ReadReq MSHR misses 410system.cpu.dcache.ReadReq_mshr_misses::total 1460873 # number of ReadReq MSHR misses 411system.cpu.dcache.WriteReq_mshr_misses::cpu.data 72780 # number of WriteReq MSHR misses 412system.cpu.dcache.WriteReq_mshr_misses::total 72780 # number of WriteReq MSHR misses 413system.cpu.dcache.demand_mshr_misses::cpu.data 1533653 # number of demand (read+write) MSHR misses 414system.cpu.dcache.demand_mshr_misses::total 1533653 # number of demand (read+write) MSHR misses 415system.cpu.dcache.overall_mshr_misses::cpu.data 1533653 # number of overall MSHR misses 416system.cpu.dcache.overall_mshr_misses::total 1533653 # number of overall MSHR misses 417system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33133783000 # number of ReadReq MSHR miss cycles 418system.cpu.dcache.ReadReq_mshr_miss_latency::total 33133783000 # number of ReadReq MSHR miss cycles 419system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3576486000 # number of WriteReq MSHR miss cycles 420system.cpu.dcache.WriteReq_mshr_miss_latency::total 3576486000 # number of WriteReq MSHR miss cycles 421system.cpu.dcache.demand_mshr_miss_latency::cpu.data 36710269000 # number of demand (read+write) MSHR miss cycles 422system.cpu.dcache.demand_mshr_miss_latency::total 36710269000 # number of demand (read+write) MSHR miss cycles 423system.cpu.dcache.overall_mshr_miss_latency::cpu.data 36710269000 # number of overall MSHR miss cycles 424system.cpu.dcache.overall_mshr_miss_latency::total 36710269000 # number of overall MSHR miss cycles 425system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002355 # mshr miss rate for ReadReq accesses 426system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002355 # mshr miss rate for ReadReq accesses 427system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000263 # mshr miss rate for WriteReq accesses 428system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000263 # mshr miss rate for WriteReq accesses 429system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001709 # mshr miss rate for demand accesses 430system.cpu.dcache.demand_mshr_miss_rate::total 0.001709 # mshr miss rate for demand accesses 431system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001709 # mshr miss rate for overall accesses 432system.cpu.dcache.overall_mshr_miss_rate::total 0.001709 # mshr miss rate for overall accesses 433system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22680.810036 # average ReadReq mshr miss latency 434system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22680.810036 # average ReadReq mshr miss latency 435system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49141.055235 # average WriteReq mshr miss latency 436system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49141.055235 # average WriteReq mshr miss latency 437system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23936.489545 # average overall mshr miss latency 438system.cpu.dcache.demand_avg_mshr_miss_latency::total 23936.489545 # average overall mshr miss latency 439system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23936.489545 # average overall mshr miss latency 440system.cpu.dcache.overall_avg_mshr_miss_latency::total 23936.489545 # average overall mshr miss latency 441system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 442system.cpu.toL2Bus.throughput 45389617 # Throughput (bytes/s) 443system.cpu.toL2Bus.trans_dist::ReadReq 1480676 # Transaction distribution 444system.cpu.toL2Bus.trans_dist::ReadResp 1480676 # Transaction distribution 445system.cpu.toL2Bus.trans_dist::Writeback 96257 # Transaction distribution 446system.cpu.toL2Bus.trans_dist::ReadExReq 72780 # Transaction distribution 447system.cpu.toL2Bus.trans_dist::ReadExResp 72780 # Transaction distribution 448system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 39606 # Packet count per connected master and slave (bytes) 449system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 3163563 # Packet count per connected master and slave (bytes) 450system.cpu.toL2Bus.pkt_count 3203169 # Packet count per connected master and slave (bytes) 451system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 1267392 # Cumulative packet size per connected master and slave (bytes) 452system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 104314240 # Cumulative packet size per connected master and slave (bytes) 453system.cpu.toL2Bus.tot_pkt_size 105581632 # Cumulative packet size per connected master and slave (bytes) 454system.cpu.toL2Bus.data_through_bus 105581632 # Total data (bytes) 455system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) 456system.cpu.toL2Bus.reqLayer0.occupancy 921113500 # Layer occupancy (ticks) 457system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 458system.cpu.toL2Bus.respLayer0.occupancy 29704500 # Layer occupancy (ticks) 459system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 460system.cpu.toL2Bus.respLayer1.occupancy 2300479500 # Layer occupancy (ticks) 461system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) 462 463---------- End Simulation Statistics ---------- 464