stats.txt revision 11515:c48c7cc5a522
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.045756 # Number of seconds simulated 4sim_ticks 1045756396500 # Number of ticks simulated 5final_tick 1045756396500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 1156934 # Simulator instruction rate (inst/s) 8host_op_rate 1421363 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1892295085 # Simulator tick rate (ticks/s) 10host_mem_usage 319640 # Number of bytes of host memory used 11host_seconds 552.64 # Real time elapsed on the host 12sim_insts 639366787 # Number of instructions simulated 13sim_ops 785501035 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 112576 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 18470976 # Number of bytes read from this memory 18system.physmem.bytes_read::total 18583552 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 112576 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 112576 # Number of instructions bytes read from this memory 21system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory 22system.physmem.bytes_written::total 4230272 # Number of bytes written to this memory 23system.physmem.num_reads::cpu.inst 1759 # Number of read requests responded to by this memory 24system.physmem.num_reads::cpu.data 288609 # Number of read requests responded to by this memory 25system.physmem.num_reads::total 290368 # Number of read requests responded to by this memory 26system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory 27system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory 28system.physmem.bw_read::cpu.inst 107650 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::cpu.data 17662790 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::total 17770441 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_inst_read::cpu.inst 107650 # Instruction read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::total 107650 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_write::writebacks 4045179 # Write bandwidth from this memory (bytes/s) 34system.physmem.bw_write::total 4045179 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_total::writebacks 4045179 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::cpu.inst 107650 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.data 17662790 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::total 21815620 # Total bandwidth to/from this memory (bytes/s) 39system.cpu_clk_domain.clock 500 # Clock period in ticks 40system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 41system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 42system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 43system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 44system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 45system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 46system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 47system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 48system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 49system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 50system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 51system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 52system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 53system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 54system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 55system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 56system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 57system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 58system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 59system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 60system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 61system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 62system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 63system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 64system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 65system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 66system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 67system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 68system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 69system.cpu.dtb.walker.walks 0 # Table walker walks requested 70system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 71system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 72system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 73system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 74system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 75system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 76system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 77system.cpu.dtb.inst_hits 0 # ITB inst hits 78system.cpu.dtb.inst_misses 0 # ITB inst misses 79system.cpu.dtb.read_hits 0 # DTB read hits 80system.cpu.dtb.read_misses 0 # DTB read misses 81system.cpu.dtb.write_hits 0 # DTB write hits 82system.cpu.dtb.write_misses 0 # DTB write misses 83system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 84system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 85system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 86system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 87system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 88system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 89system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 90system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 91system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 92system.cpu.dtb.read_accesses 0 # DTB read accesses 93system.cpu.dtb.write_accesses 0 # DTB write accesses 94system.cpu.dtb.inst_accesses 0 # ITB inst accesses 95system.cpu.dtb.hits 0 # DTB hits 96system.cpu.dtb.misses 0 # DTB misses 97system.cpu.dtb.accesses 0 # DTB accesses 98system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 99system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 100system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 101system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 102system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 103system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 104system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 105system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 106system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 107system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 108system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 109system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 110system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 111system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 112system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 113system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 114system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 115system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 116system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 117system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 118system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 119system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 120system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 121system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 122system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 123system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 124system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 125system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 126system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 127system.cpu.itb.walker.walks 0 # Table walker walks requested 128system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 129system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 130system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 131system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 132system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 133system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 134system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 135system.cpu.itb.inst_hits 0 # ITB inst hits 136system.cpu.itb.inst_misses 0 # ITB inst misses 137system.cpu.itb.read_hits 0 # DTB read hits 138system.cpu.itb.read_misses 0 # DTB read misses 139system.cpu.itb.write_hits 0 # DTB write hits 140system.cpu.itb.write_misses 0 # DTB write misses 141system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 142system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 143system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 144system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 145system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 146system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 147system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 148system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 149system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 150system.cpu.itb.read_accesses 0 # DTB read accesses 151system.cpu.itb.write_accesses 0 # DTB write accesses 152system.cpu.itb.inst_accesses 0 # ITB inst accesses 153system.cpu.itb.hits 0 # DTB hits 154system.cpu.itb.misses 0 # DTB misses 155system.cpu.itb.accesses 0 # DTB accesses 156system.cpu.workload.num_syscalls 673 # Number of system calls 157system.cpu.numCycles 2091512793 # number of cpu cycles simulated 158system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 159system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 160system.cpu.committedInsts 639366787 # Number of instructions committed 161system.cpu.committedOps 785501035 # Number of ops (including micro ops) committed 162system.cpu.num_int_alu_accesses 682251400 # Number of integer alu accesses 163system.cpu.num_fp_alu_accesses 24239771 # Number of float alu accesses 164system.cpu.num_func_calls 37261296 # number of times a function call or return occured 165system.cpu.num_conditional_control_insts 91575866 # number of instructions that are conditional controls 166system.cpu.num_int_insts 682251400 # number of integer instructions 167system.cpu.num_fp_insts 24239771 # number of float instructions 168system.cpu.num_int_register_reads 1272307653 # number of times the integer registers were read 169system.cpu.num_int_register_writes 468423268 # number of times the integer registers were written 170system.cpu.num_fp_register_reads 28064643 # number of times the floating registers were read 171system.cpu.num_fp_register_writes 21684311 # number of times the floating registers were written 172system.cpu.num_cc_register_reads 3116296060 # number of times the CC registers were read 173system.cpu.num_cc_register_writes 351919006 # number of times the CC registers were written 174system.cpu.num_mem_refs 381221435 # number of memory refs 175system.cpu.num_load_insts 252240938 # Number of load instructions 176system.cpu.num_store_insts 128980497 # Number of store instructions 177system.cpu.num_idle_cycles 0.002000 # Number of idle cycles 178system.cpu.num_busy_cycles 2091512792.998000 # Number of busy cycles 179system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles 180system.cpu.idle_fraction 0.000000 # Percentage of idle cycles 181system.cpu.Branches 137364860 # Number of branches fetched 182system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction 183system.cpu.op_class::IntAlu 385757467 48.91% 48.91% # Class of executed instruction 184system.cpu.op_class::IntMult 5173441 0.66% 49.56% # Class of executed instruction 185system.cpu.op_class::IntDiv 0 0.00% 49.56% # Class of executed instruction 186system.cpu.op_class::FloatAdd 0 0.00% 49.56% # Class of executed instruction 187system.cpu.op_class::FloatCmp 0 0.00% 49.56% # Class of executed instruction 188system.cpu.op_class::FloatCvt 0 0.00% 49.56% # Class of executed instruction 189system.cpu.op_class::FloatMult 0 0.00% 49.56% # Class of executed instruction 190system.cpu.op_class::FloatDiv 0 0.00% 49.56% # Class of executed instruction 191system.cpu.op_class::FloatSqrt 0 0.00% 49.56% # Class of executed instruction 192system.cpu.op_class::SimdAdd 0 0.00% 49.56% # Class of executed instruction 193system.cpu.op_class::SimdAddAcc 0 0.00% 49.56% # Class of executed instruction 194system.cpu.op_class::SimdAlu 0 0.00% 49.56% # Class of executed instruction 195system.cpu.op_class::SimdCmp 0 0.00% 49.56% # Class of executed instruction 196system.cpu.op_class::SimdCvt 0 0.00% 49.56% # Class of executed instruction 197system.cpu.op_class::SimdMisc 0 0.00% 49.56% # Class of executed instruction 198system.cpu.op_class::SimdMult 0 0.00% 49.56% # Class of executed instruction 199system.cpu.op_class::SimdMultAcc 0 0.00% 49.56% # Class of executed instruction 200system.cpu.op_class::SimdShift 0 0.00% 49.56% # Class of executed instruction 201system.cpu.op_class::SimdShiftAcc 0 0.00% 49.56% # Class of executed instruction 202system.cpu.op_class::SimdSqrt 0 0.00% 49.56% # Class of executed instruction 203system.cpu.op_class::SimdFloatAdd 637528 0.08% 49.65% # Class of executed instruction 204system.cpu.op_class::SimdFloatAlu 0 0.00% 49.65% # Class of executed instruction 205system.cpu.op_class::SimdFloatCmp 3187668 0.40% 50.05% # Class of executed instruction 206system.cpu.op_class::SimdFloatCvt 2550131 0.32% 50.37% # Class of executed instruction 207system.cpu.op_class::SimdFloatDiv 0 0.00% 50.37% # Class of executed instruction 208system.cpu.op_class::SimdFloatMisc 10203074 1.29% 51.67% # Class of executed instruction 209system.cpu.op_class::SimdFloatMult 0 0.00% 51.67% # Class of executed instruction 210system.cpu.op_class::SimdFloatMultAcc 0 0.00% 51.67% # Class of executed instruction 211system.cpu.op_class::SimdFloatSqrt 0 0.00% 51.67% # Class of executed instruction 212system.cpu.op_class::MemRead 252240938 31.98% 83.65% # Class of executed instruction 213system.cpu.op_class::MemWrite 128980497 16.35% 100.00% # Class of executed instruction 214system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 215system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 216system.cpu.op_class::total 788730744 # Class of executed instruction 217system.cpu.dcache.tags.replacements 778046 # number of replacements 218system.cpu.dcache.tags.tagsinuse 4093.549761 # Cycle average of tags in use 219system.cpu.dcache.tags.total_refs 378510311 # Total number of references to valid blocks. 220system.cpu.dcache.tags.sampled_refs 782142 # Sample count of references to valid blocks. 221system.cpu.dcache.tags.avg_refs 483.940654 # Average number of references to valid blocks. 222system.cpu.dcache.tags.warmup_cycle 1041808500 # Cycle when the warmup percentage was hit. 223system.cpu.dcache.tags.occ_blocks::cpu.data 4093.549761 # Average occupied blocks per requestor 224system.cpu.dcache.tags.occ_percent::cpu.data 0.999402 # Average percentage of cache occupancy 225system.cpu.dcache.tags.occ_percent::total 0.999402 # Average percentage of cache occupancy 226system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 227system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id 228system.cpu.dcache.tags.age_task_id_blocks_1024::1 122 # Occupied blocks per task id 229system.cpu.dcache.tags.age_task_id_blocks_1024::2 591 # Occupied blocks per task id 230system.cpu.dcache.tags.age_task_id_blocks_1024::3 1037 # Occupied blocks per task id 231system.cpu.dcache.tags.age_task_id_blocks_1024::4 2319 # Occupied blocks per task id 232system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 233system.cpu.dcache.tags.tag_accesses 759367050 # Number of tag accesses 234system.cpu.dcache.tags.data_accesses 759367050 # Number of data accesses 235system.cpu.dcache.ReadReq_hits::cpu.data 249613198 # number of ReadReq hits 236system.cpu.dcache.ReadReq_hits::total 249613198 # number of ReadReq hits 237system.cpu.dcache.WriteReq_hits::cpu.data 128882154 # number of WriteReq hits 238system.cpu.dcache.WriteReq_hits::total 128882154 # number of WriteReq hits 239system.cpu.dcache.SoftPFReq_hits::cpu.data 3481 # number of SoftPFReq hits 240system.cpu.dcache.SoftPFReq_hits::total 3481 # number of SoftPFReq hits 241system.cpu.dcache.LoadLockedReq_hits::cpu.data 5739 # number of LoadLockedReq hits 242system.cpu.dcache.LoadLockedReq_hits::total 5739 # number of LoadLockedReq hits 243system.cpu.dcache.StoreCondReq_hits::cpu.data 5739 # number of StoreCondReq hits 244system.cpu.dcache.StoreCondReq_hits::total 5739 # number of StoreCondReq hits 245system.cpu.dcache.demand_hits::cpu.data 378495352 # number of demand (read+write) hits 246system.cpu.dcache.demand_hits::total 378495352 # number of demand (read+write) hits 247system.cpu.dcache.overall_hits::cpu.data 378498833 # number of overall hits 248system.cpu.dcache.overall_hits::total 378498833 # number of overall hits 249system.cpu.dcache.ReadReq_misses::cpu.data 712681 # number of ReadReq misses 250system.cpu.dcache.ReadReq_misses::total 712681 # number of ReadReq misses 251system.cpu.dcache.WriteReq_misses::cpu.data 69323 # number of WriteReq misses 252system.cpu.dcache.WriteReq_misses::total 69323 # number of WriteReq misses 253system.cpu.dcache.SoftPFReq_misses::cpu.data 139 # number of SoftPFReq misses 254system.cpu.dcache.SoftPFReq_misses::total 139 # number of SoftPFReq misses 255system.cpu.dcache.demand_misses::cpu.data 782004 # number of demand (read+write) misses 256system.cpu.dcache.demand_misses::total 782004 # number of demand (read+write) misses 257system.cpu.dcache.overall_misses::cpu.data 782143 # number of overall misses 258system.cpu.dcache.overall_misses::total 782143 # number of overall misses 259system.cpu.dcache.ReadReq_miss_latency::cpu.data 20169396000 # number of ReadReq miss cycles 260system.cpu.dcache.ReadReq_miss_latency::total 20169396000 # number of ReadReq miss cycles 261system.cpu.dcache.WriteReq_miss_latency::cpu.data 4139811500 # number of WriteReq miss cycles 262system.cpu.dcache.WriteReq_miss_latency::total 4139811500 # number of WriteReq miss cycles 263system.cpu.dcache.demand_miss_latency::cpu.data 24309207500 # number of demand (read+write) miss cycles 264system.cpu.dcache.demand_miss_latency::total 24309207500 # number of demand (read+write) miss cycles 265system.cpu.dcache.overall_miss_latency::cpu.data 24309207500 # number of overall miss cycles 266system.cpu.dcache.overall_miss_latency::total 24309207500 # number of overall miss cycles 267system.cpu.dcache.ReadReq_accesses::cpu.data 250325879 # number of ReadReq accesses(hits+misses) 268system.cpu.dcache.ReadReq_accesses::total 250325879 # number of ReadReq accesses(hits+misses) 269system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses) 270system.cpu.dcache.WriteReq_accesses::total 128951477 # number of WriteReq accesses(hits+misses) 271system.cpu.dcache.SoftPFReq_accesses::cpu.data 3620 # number of SoftPFReq accesses(hits+misses) 272system.cpu.dcache.SoftPFReq_accesses::total 3620 # number of SoftPFReq accesses(hits+misses) 273system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5739 # number of LoadLockedReq accesses(hits+misses) 274system.cpu.dcache.LoadLockedReq_accesses::total 5739 # number of LoadLockedReq accesses(hits+misses) 275system.cpu.dcache.StoreCondReq_accesses::cpu.data 5739 # number of StoreCondReq accesses(hits+misses) 276system.cpu.dcache.StoreCondReq_accesses::total 5739 # number of StoreCondReq accesses(hits+misses) 277system.cpu.dcache.demand_accesses::cpu.data 379277356 # number of demand (read+write) accesses 278system.cpu.dcache.demand_accesses::total 379277356 # number of demand (read+write) accesses 279system.cpu.dcache.overall_accesses::cpu.data 379280976 # number of overall (read+write) accesses 280system.cpu.dcache.overall_accesses::total 379280976 # number of overall (read+write) accesses 281system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002847 # miss rate for ReadReq accesses 282system.cpu.dcache.ReadReq_miss_rate::total 0.002847 # miss rate for ReadReq accesses 283system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000538 # miss rate for WriteReq accesses 284system.cpu.dcache.WriteReq_miss_rate::total 0.000538 # miss rate for WriteReq accesses 285system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.038398 # miss rate for SoftPFReq accesses 286system.cpu.dcache.SoftPFReq_miss_rate::total 0.038398 # miss rate for SoftPFReq accesses 287system.cpu.dcache.demand_miss_rate::cpu.data 0.002062 # miss rate for demand accesses 288system.cpu.dcache.demand_miss_rate::total 0.002062 # miss rate for demand accesses 289system.cpu.dcache.overall_miss_rate::cpu.data 0.002062 # miss rate for overall accesses 290system.cpu.dcache.overall_miss_rate::total 0.002062 # miss rate for overall accesses 291system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28300.734831 # average ReadReq miss latency 292system.cpu.dcache.ReadReq_avg_miss_latency::total 28300.734831 # average ReadReq miss latency 293system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59717.719949 # average WriteReq miss latency 294system.cpu.dcache.WriteReq_avg_miss_latency::total 59717.719949 # average WriteReq miss latency 295system.cpu.dcache.demand_avg_miss_latency::cpu.data 31085.784088 # average overall miss latency 296system.cpu.dcache.demand_avg_miss_latency::total 31085.784088 # average overall miss latency 297system.cpu.dcache.overall_avg_miss_latency::cpu.data 31080.259620 # average overall miss latency 298system.cpu.dcache.overall_avg_miss_latency::total 31080.259620 # average overall miss latency 299system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 300system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 301system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 302system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 303system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 304system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 305system.cpu.dcache.writebacks::writebacks 88995 # number of writebacks 306system.cpu.dcache.writebacks::total 88995 # number of writebacks 307system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits 308system.cpu.dcache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits 309system.cpu.dcache.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits 310system.cpu.dcache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits 311system.cpu.dcache.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits 312system.cpu.dcache.overall_mshr_hits::total 1 # number of overall MSHR hits 313system.cpu.dcache.ReadReq_mshr_misses::cpu.data 712680 # number of ReadReq MSHR misses 314system.cpu.dcache.ReadReq_mshr_misses::total 712680 # number of ReadReq MSHR misses 315system.cpu.dcache.WriteReq_mshr_misses::cpu.data 69323 # number of WriteReq MSHR misses 316system.cpu.dcache.WriteReq_mshr_misses::total 69323 # number of WriteReq MSHR misses 317system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 139 # number of SoftPFReq MSHR misses 318system.cpu.dcache.SoftPFReq_mshr_misses::total 139 # number of SoftPFReq MSHR misses 319system.cpu.dcache.demand_mshr_misses::cpu.data 782003 # number of demand (read+write) MSHR misses 320system.cpu.dcache.demand_mshr_misses::total 782003 # number of demand (read+write) MSHR misses 321system.cpu.dcache.overall_mshr_misses::cpu.data 782142 # number of overall MSHR misses 322system.cpu.dcache.overall_mshr_misses::total 782142 # number of overall MSHR misses 323system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 19456669000 # number of ReadReq MSHR miss cycles 324system.cpu.dcache.ReadReq_mshr_miss_latency::total 19456669000 # number of ReadReq MSHR miss cycles 325system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4070488500 # number of WriteReq MSHR miss cycles 326system.cpu.dcache.WriteReq_mshr_miss_latency::total 4070488500 # number of WriteReq MSHR miss cycles 327system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1766000 # number of SoftPFReq MSHR miss cycles 328system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1766000 # number of SoftPFReq MSHR miss cycles 329system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23527157500 # number of demand (read+write) MSHR miss cycles 330system.cpu.dcache.demand_mshr_miss_latency::total 23527157500 # number of demand (read+write) MSHR miss cycles 331system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23528923500 # number of overall MSHR miss cycles 332system.cpu.dcache.overall_mshr_miss_latency::total 23528923500 # number of overall MSHR miss cycles 333system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002847 # mshr miss rate for ReadReq accesses 334system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002847 # mshr miss rate for ReadReq accesses 335system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000538 # mshr miss rate for WriteReq accesses 336system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000538 # mshr miss rate for WriteReq accesses 337system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.038398 # mshr miss rate for SoftPFReq accesses 338system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.038398 # mshr miss rate for SoftPFReq accesses 339system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002062 # mshr miss rate for demand accesses 340system.cpu.dcache.demand_mshr_miss_rate::total 0.002062 # mshr miss rate for demand accesses 341system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002062 # mshr miss rate for overall accesses 342system.cpu.dcache.overall_mshr_miss_rate::total 0.002062 # mshr miss rate for overall accesses 343system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27300.708593 # average ReadReq mshr miss latency 344system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27300.708593 # average ReadReq mshr miss latency 345system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 58717.719949 # average WriteReq mshr miss latency 346system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 58717.719949 # average WriteReq mshr miss latency 347system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12705.035971 # average SoftPFReq mshr miss latency 348system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12705.035971 # average SoftPFReq mshr miss latency 349system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30085.763737 # average overall mshr miss latency 350system.cpu.dcache.demand_avg_mshr_miss_latency::total 30085.763737 # average overall mshr miss latency 351system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30082.674885 # average overall mshr miss latency 352system.cpu.dcache.overall_avg_mshr_miss_latency::total 30082.674885 # average overall mshr miss latency 353system.cpu.icache.tags.replacements 8769 # number of replacements 354system.cpu.icache.tags.tagsinuse 1391.385132 # Cycle average of tags in use 355system.cpu.icache.tags.total_refs 643367692 # Total number of references to valid blocks. 356system.cpu.icache.tags.sampled_refs 10208 # Sample count of references to valid blocks. 357system.cpu.icache.tags.avg_refs 63025.831897 # Average number of references to valid blocks. 358system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 359system.cpu.icache.tags.occ_blocks::cpu.inst 1391.385132 # Average occupied blocks per requestor 360system.cpu.icache.tags.occ_percent::cpu.inst 0.679387 # Average percentage of cache occupancy 361system.cpu.icache.tags.occ_percent::total 0.679387 # Average percentage of cache occupancy 362system.cpu.icache.tags.occ_task_id_blocks::1024 1439 # Occupied blocks per task id 363system.cpu.icache.tags.age_task_id_blocks_1024::0 43 # Occupied blocks per task id 364system.cpu.icache.tags.age_task_id_blocks_1024::1 57 # Occupied blocks per task id 365system.cpu.icache.tags.age_task_id_blocks_1024::4 1339 # Occupied blocks per task id 366system.cpu.icache.tags.occ_task_id_percent::1024 0.702637 # Percentage of cache occupancy per task id 367system.cpu.icache.tags.tag_accesses 1286766008 # Number of tag accesses 368system.cpu.icache.tags.data_accesses 1286766008 # Number of data accesses 369system.cpu.icache.ReadReq_hits::cpu.inst 643367692 # number of ReadReq hits 370system.cpu.icache.ReadReq_hits::total 643367692 # number of ReadReq hits 371system.cpu.icache.demand_hits::cpu.inst 643367692 # number of demand (read+write) hits 372system.cpu.icache.demand_hits::total 643367692 # number of demand (read+write) hits 373system.cpu.icache.overall_hits::cpu.inst 643367692 # number of overall hits 374system.cpu.icache.overall_hits::total 643367692 # number of overall hits 375system.cpu.icache.ReadReq_misses::cpu.inst 10208 # number of ReadReq misses 376system.cpu.icache.ReadReq_misses::total 10208 # number of ReadReq misses 377system.cpu.icache.demand_misses::cpu.inst 10208 # number of demand (read+write) misses 378system.cpu.icache.demand_misses::total 10208 # number of demand (read+write) misses 379system.cpu.icache.overall_misses::cpu.inst 10208 # number of overall misses 380system.cpu.icache.overall_misses::total 10208 # number of overall misses 381system.cpu.icache.ReadReq_miss_latency::cpu.inst 219076500 # number of ReadReq miss cycles 382system.cpu.icache.ReadReq_miss_latency::total 219076500 # number of ReadReq miss cycles 383system.cpu.icache.demand_miss_latency::cpu.inst 219076500 # number of demand (read+write) miss cycles 384system.cpu.icache.demand_miss_latency::total 219076500 # number of demand (read+write) miss cycles 385system.cpu.icache.overall_miss_latency::cpu.inst 219076500 # number of overall miss cycles 386system.cpu.icache.overall_miss_latency::total 219076500 # number of overall miss cycles 387system.cpu.icache.ReadReq_accesses::cpu.inst 643377900 # number of ReadReq accesses(hits+misses) 388system.cpu.icache.ReadReq_accesses::total 643377900 # number of ReadReq accesses(hits+misses) 389system.cpu.icache.demand_accesses::cpu.inst 643377900 # number of demand (read+write) accesses 390system.cpu.icache.demand_accesses::total 643377900 # number of demand (read+write) accesses 391system.cpu.icache.overall_accesses::cpu.inst 643377900 # number of overall (read+write) accesses 392system.cpu.icache.overall_accesses::total 643377900 # number of overall (read+write) accesses 393system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000016 # miss rate for ReadReq accesses 394system.cpu.icache.ReadReq_miss_rate::total 0.000016 # miss rate for ReadReq accesses 395system.cpu.icache.demand_miss_rate::cpu.inst 0.000016 # miss rate for demand accesses 396system.cpu.icache.demand_miss_rate::total 0.000016 # miss rate for demand accesses 397system.cpu.icache.overall_miss_rate::cpu.inst 0.000016 # miss rate for overall accesses 398system.cpu.icache.overall_miss_rate::total 0.000016 # miss rate for overall accesses 399system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21461.255878 # average ReadReq miss latency 400system.cpu.icache.ReadReq_avg_miss_latency::total 21461.255878 # average ReadReq miss latency 401system.cpu.icache.demand_avg_miss_latency::cpu.inst 21461.255878 # average overall miss latency 402system.cpu.icache.demand_avg_miss_latency::total 21461.255878 # average overall miss latency 403system.cpu.icache.overall_avg_miss_latency::cpu.inst 21461.255878 # average overall miss latency 404system.cpu.icache.overall_avg_miss_latency::total 21461.255878 # average overall miss latency 405system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 406system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 407system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 408system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 409system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 410system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 411system.cpu.icache.writebacks::writebacks 8769 # number of writebacks 412system.cpu.icache.writebacks::total 8769 # number of writebacks 413system.cpu.icache.ReadReq_mshr_misses::cpu.inst 10208 # number of ReadReq MSHR misses 414system.cpu.icache.ReadReq_mshr_misses::total 10208 # number of ReadReq MSHR misses 415system.cpu.icache.demand_mshr_misses::cpu.inst 10208 # number of demand (read+write) MSHR misses 416system.cpu.icache.demand_mshr_misses::total 10208 # number of demand (read+write) MSHR misses 417system.cpu.icache.overall_mshr_misses::cpu.inst 10208 # number of overall MSHR misses 418system.cpu.icache.overall_mshr_misses::total 10208 # number of overall MSHR misses 419system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 208868500 # number of ReadReq MSHR miss cycles 420system.cpu.icache.ReadReq_mshr_miss_latency::total 208868500 # number of ReadReq MSHR miss cycles 421system.cpu.icache.demand_mshr_miss_latency::cpu.inst 208868500 # number of demand (read+write) MSHR miss cycles 422system.cpu.icache.demand_mshr_miss_latency::total 208868500 # number of demand (read+write) MSHR miss cycles 423system.cpu.icache.overall_mshr_miss_latency::cpu.inst 208868500 # number of overall MSHR miss cycles 424system.cpu.icache.overall_mshr_miss_latency::total 208868500 # number of overall MSHR miss cycles 425system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for ReadReq accesses 426system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000016 # mshr miss rate for ReadReq accesses 427system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for demand accesses 428system.cpu.icache.demand_mshr_miss_rate::total 0.000016 # mshr miss rate for demand accesses 429system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for overall accesses 430system.cpu.icache.overall_mshr_miss_rate::total 0.000016 # mshr miss rate for overall accesses 431system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20461.255878 # average ReadReq mshr miss latency 432system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20461.255878 # average ReadReq mshr miss latency 433system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20461.255878 # average overall mshr miss latency 434system.cpu.icache.demand_avg_mshr_miss_latency::total 20461.255878 # average overall mshr miss latency 435system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20461.255878 # average overall mshr miss latency 436system.cpu.icache.overall_avg_mshr_miss_latency::total 20461.255878 # average overall mshr miss latency 437system.cpu.l2cache.tags.replacements 257772 # number of replacements 438system.cpu.l2cache.tags.tagsinuse 32622.591915 # Cycle average of tags in use 439system.cpu.l2cache.tags.total_refs 1218050 # Total number of references to valid blocks. 440system.cpu.l2cache.tags.sampled_refs 290515 # Sample count of references to valid blocks. 441system.cpu.l2cache.tags.avg_refs 4.192727 # Average number of references to valid blocks. 442system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 443system.cpu.l2cache.tags.occ_blocks::writebacks 2525.639317 # Average occupied blocks per requestor 444system.cpu.l2cache.tags.occ_blocks::cpu.inst 45.833351 # Average occupied blocks per requestor 445system.cpu.l2cache.tags.occ_blocks::cpu.data 30051.119247 # Average occupied blocks per requestor 446system.cpu.l2cache.tags.occ_percent::writebacks 0.077076 # Average percentage of cache occupancy 447system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001399 # Average percentage of cache occupancy 448system.cpu.l2cache.tags.occ_percent::cpu.data 0.917087 # Average percentage of cache occupancy 449system.cpu.l2cache.tags.occ_percent::total 0.995562 # Average percentage of cache occupancy 450system.cpu.l2cache.tags.occ_task_id_blocks::1024 32743 # Occupied blocks per task id 451system.cpu.l2cache.tags.age_task_id_blocks_1024::0 89 # Occupied blocks per task id 452system.cpu.l2cache.tags.age_task_id_blocks_1024::1 143 # Occupied blocks per task id 453system.cpu.l2cache.tags.age_task_id_blocks_1024::2 148 # Occupied blocks per task id 454system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1440 # Occupied blocks per task id 455system.cpu.l2cache.tags.age_task_id_blocks_1024::4 30923 # Occupied blocks per task id 456system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999237 # Percentage of cache occupancy per task id 457system.cpu.l2cache.tags.tag_accesses 12984278 # Number of tag accesses 458system.cpu.l2cache.tags.data_accesses 12984278 # Number of data accesses 459system.cpu.l2cache.WritebackDirty_hits::writebacks 88995 # number of WritebackDirty hits 460system.cpu.l2cache.WritebackDirty_hits::total 88995 # number of WritebackDirty hits 461system.cpu.l2cache.WritebackClean_hits::writebacks 8752 # number of WritebackClean hits 462system.cpu.l2cache.WritebackClean_hits::total 8752 # number of WritebackClean hits 463system.cpu.l2cache.ReadExReq_hits::cpu.data 3230 # number of ReadExReq hits 464system.cpu.l2cache.ReadExReq_hits::total 3230 # number of ReadExReq hits 465system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 8449 # number of ReadCleanReq hits 466system.cpu.l2cache.ReadCleanReq_hits::total 8449 # number of ReadCleanReq hits 467system.cpu.l2cache.ReadSharedReq_hits::cpu.data 490303 # number of ReadSharedReq hits 468system.cpu.l2cache.ReadSharedReq_hits::total 490303 # number of ReadSharedReq hits 469system.cpu.l2cache.demand_hits::cpu.inst 8449 # number of demand (read+write) hits 470system.cpu.l2cache.demand_hits::cpu.data 493533 # number of demand (read+write) hits 471system.cpu.l2cache.demand_hits::total 501982 # number of demand (read+write) hits 472system.cpu.l2cache.overall_hits::cpu.inst 8449 # number of overall hits 473system.cpu.l2cache.overall_hits::cpu.data 493533 # number of overall hits 474system.cpu.l2cache.overall_hits::total 501982 # number of overall hits 475system.cpu.l2cache.ReadExReq_misses::cpu.data 66093 # number of ReadExReq misses 476system.cpu.l2cache.ReadExReq_misses::total 66093 # number of ReadExReq misses 477system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 1759 # number of ReadCleanReq misses 478system.cpu.l2cache.ReadCleanReq_misses::total 1759 # number of ReadCleanReq misses 479system.cpu.l2cache.ReadSharedReq_misses::cpu.data 222516 # number of ReadSharedReq misses 480system.cpu.l2cache.ReadSharedReq_misses::total 222516 # number of ReadSharedReq misses 481system.cpu.l2cache.demand_misses::cpu.inst 1759 # number of demand (read+write) misses 482system.cpu.l2cache.demand_misses::cpu.data 288609 # number of demand (read+write) misses 483system.cpu.l2cache.demand_misses::total 290368 # number of demand (read+write) misses 484system.cpu.l2cache.overall_misses::cpu.inst 1759 # number of overall misses 485system.cpu.l2cache.overall_misses::cpu.data 288609 # number of overall misses 486system.cpu.l2cache.overall_misses::total 290368 # number of overall misses 487system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3932586500 # number of ReadExReq miss cycles 488system.cpu.l2cache.ReadExReq_miss_latency::total 3932586500 # number of ReadExReq miss cycles 489system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 104759500 # number of ReadCleanReq miss cycles 490system.cpu.l2cache.ReadCleanReq_miss_latency::total 104759500 # number of ReadCleanReq miss cycles 491system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 13239976500 # number of ReadSharedReq miss cycles 492system.cpu.l2cache.ReadSharedReq_miss_latency::total 13239976500 # number of ReadSharedReq miss cycles 493system.cpu.l2cache.demand_miss_latency::cpu.inst 104759500 # number of demand (read+write) miss cycles 494system.cpu.l2cache.demand_miss_latency::cpu.data 17172563000 # number of demand (read+write) miss cycles 495system.cpu.l2cache.demand_miss_latency::total 17277322500 # number of demand (read+write) miss cycles 496system.cpu.l2cache.overall_miss_latency::cpu.inst 104759500 # number of overall miss cycles 497system.cpu.l2cache.overall_miss_latency::cpu.data 17172563000 # number of overall miss cycles 498system.cpu.l2cache.overall_miss_latency::total 17277322500 # number of overall miss cycles 499system.cpu.l2cache.WritebackDirty_accesses::writebacks 88995 # number of WritebackDirty accesses(hits+misses) 500system.cpu.l2cache.WritebackDirty_accesses::total 88995 # number of WritebackDirty accesses(hits+misses) 501system.cpu.l2cache.WritebackClean_accesses::writebacks 8752 # number of WritebackClean accesses(hits+misses) 502system.cpu.l2cache.WritebackClean_accesses::total 8752 # number of WritebackClean accesses(hits+misses) 503system.cpu.l2cache.ReadExReq_accesses::cpu.data 69323 # number of ReadExReq accesses(hits+misses) 504system.cpu.l2cache.ReadExReq_accesses::total 69323 # number of ReadExReq accesses(hits+misses) 505system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 10208 # number of ReadCleanReq accesses(hits+misses) 506system.cpu.l2cache.ReadCleanReq_accesses::total 10208 # number of ReadCleanReq accesses(hits+misses) 507system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 712819 # number of ReadSharedReq accesses(hits+misses) 508system.cpu.l2cache.ReadSharedReq_accesses::total 712819 # number of ReadSharedReq accesses(hits+misses) 509system.cpu.l2cache.demand_accesses::cpu.inst 10208 # number of demand (read+write) accesses 510system.cpu.l2cache.demand_accesses::cpu.data 782142 # number of demand (read+write) accesses 511system.cpu.l2cache.demand_accesses::total 792350 # number of demand (read+write) accesses 512system.cpu.l2cache.overall_accesses::cpu.inst 10208 # number of overall (read+write) accesses 513system.cpu.l2cache.overall_accesses::cpu.data 782142 # number of overall (read+write) accesses 514system.cpu.l2cache.overall_accesses::total 792350 # number of overall (read+write) accesses 515system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.953407 # miss rate for ReadExReq accesses 516system.cpu.l2cache.ReadExReq_miss_rate::total 0.953407 # miss rate for ReadExReq accesses 517system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.172316 # miss rate for ReadCleanReq accesses 518system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.172316 # miss rate for ReadCleanReq accesses 519system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.312163 # miss rate for ReadSharedReq accesses 520system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.312163 # miss rate for ReadSharedReq accesses 521system.cpu.l2cache.demand_miss_rate::cpu.inst 0.172316 # miss rate for demand accesses 522system.cpu.l2cache.demand_miss_rate::cpu.data 0.368998 # miss rate for demand accesses 523system.cpu.l2cache.demand_miss_rate::total 0.366464 # miss rate for demand accesses 524system.cpu.l2cache.overall_miss_rate::cpu.inst 0.172316 # miss rate for overall accesses 525system.cpu.l2cache.overall_miss_rate::cpu.data 0.368998 # miss rate for overall accesses 526system.cpu.l2cache.overall_miss_rate::total 0.366464 # miss rate for overall accesses 527system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500.801900 # average ReadExReq miss latency 528system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500.801900 # average ReadExReq miss latency 529system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59556.281978 # average ReadCleanReq miss latency 530system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59556.281978 # average ReadCleanReq miss latency 531system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59501.233619 # average ReadSharedReq miss latency 532system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59501.233619 # average ReadSharedReq miss latency 533system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59556.281978 # average overall miss latency 534system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59501.134753 # average overall miss latency 535system.cpu.l2cache.demand_avg_miss_latency::total 59501.468826 # average overall miss latency 536system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59556.281978 # average overall miss latency 537system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59501.134753 # average overall miss latency 538system.cpu.l2cache.overall_avg_miss_latency::total 59501.468826 # average overall miss latency 539system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 540system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 541system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 542system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 543system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 544system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 545system.cpu.l2cache.writebacks::writebacks 66098 # number of writebacks 546system.cpu.l2cache.writebacks::total 66098 # number of writebacks 547system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66093 # number of ReadExReq MSHR misses 548system.cpu.l2cache.ReadExReq_mshr_misses::total 66093 # number of ReadExReq MSHR misses 549system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1759 # number of ReadCleanReq MSHR misses 550system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1759 # number of ReadCleanReq MSHR misses 551system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 222516 # number of ReadSharedReq MSHR misses 552system.cpu.l2cache.ReadSharedReq_mshr_misses::total 222516 # number of ReadSharedReq MSHR misses 553system.cpu.l2cache.demand_mshr_misses::cpu.inst 1759 # number of demand (read+write) MSHR misses 554system.cpu.l2cache.demand_mshr_misses::cpu.data 288609 # number of demand (read+write) MSHR misses 555system.cpu.l2cache.demand_mshr_misses::total 290368 # number of demand (read+write) MSHR misses 556system.cpu.l2cache.overall_mshr_misses::cpu.inst 1759 # number of overall MSHR misses 557system.cpu.l2cache.overall_mshr_misses::cpu.data 288609 # number of overall MSHR misses 558system.cpu.l2cache.overall_mshr_misses::total 290368 # number of overall MSHR misses 559system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3271656500 # number of ReadExReq MSHR miss cycles 560system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3271656500 # number of ReadExReq MSHR miss cycles 561system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 87169500 # number of ReadCleanReq MSHR miss cycles 562system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 87169500 # number of ReadCleanReq MSHR miss cycles 563system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 11014816500 # number of ReadSharedReq MSHR miss cycles 564system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 11014816500 # number of ReadSharedReq MSHR miss cycles 565system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 87169500 # number of demand (read+write) MSHR miss cycles 566system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 14286473000 # number of demand (read+write) MSHR miss cycles 567system.cpu.l2cache.demand_mshr_miss_latency::total 14373642500 # number of demand (read+write) MSHR miss cycles 568system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 87169500 # number of overall MSHR miss cycles 569system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 14286473000 # number of overall MSHR miss cycles 570system.cpu.l2cache.overall_mshr_miss_latency::total 14373642500 # number of overall MSHR miss cycles 571system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.953407 # mshr miss rate for ReadExReq accesses 572system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.953407 # mshr miss rate for ReadExReq accesses 573system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.172316 # mshr miss rate for ReadCleanReq accesses 574system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.172316 # mshr miss rate for ReadCleanReq accesses 575system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312163 # mshr miss rate for ReadSharedReq accesses 576system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312163 # mshr miss rate for ReadSharedReq accesses 577system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.172316 # mshr miss rate for demand accesses 578system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.368998 # mshr miss rate for demand accesses 579system.cpu.l2cache.demand_mshr_miss_rate::total 0.366464 # mshr miss rate for demand accesses 580system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.172316 # mshr miss rate for overall accesses 581system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.368998 # mshr miss rate for overall accesses 582system.cpu.l2cache.overall_mshr_miss_rate::total 0.366464 # mshr miss rate for overall accesses 583system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500.801900 # average ReadExReq mshr miss latency 584system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500.801900 # average ReadExReq mshr miss latency 585system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49556.281978 # average ReadCleanReq mshr miss latency 586system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49556.281978 # average ReadCleanReq mshr miss latency 587system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49501.233619 # average ReadSharedReq mshr miss latency 588system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49501.233619 # average ReadSharedReq mshr miss latency 589system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49556.281978 # average overall mshr miss latency 590system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49501.134753 # average overall mshr miss latency 591system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49501.468826 # average overall mshr miss latency 592system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49556.281978 # average overall mshr miss latency 593system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49501.134753 # average overall mshr miss latency 594system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49501.468826 # average overall mshr miss latency 595system.cpu.toL2Bus.snoop_filter.tot_requests 1579165 # Total number of requests made to the snoop filter. 596system.cpu.toL2Bus.snoop_filter.hit_single_requests 786845 # Number of requests hitting in the snoop filter with a single holder of the requested data. 597system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1110 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 598system.cpu.toL2Bus.snoop_filter.tot_snoops 1580 # Total number of snoops made to the snoop filter. 599system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1573 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 600system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 7 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 601system.cpu.toL2Bus.trans_dist::ReadResp 723027 # Transaction distribution 602system.cpu.toL2Bus.trans_dist::WritebackDirty 155093 # Transaction distribution 603system.cpu.toL2Bus.trans_dist::WritebackClean 8769 # Transaction distribution 604system.cpu.toL2Bus.trans_dist::CleanEvict 880725 # Transaction distribution 605system.cpu.toL2Bus.trans_dist::ReadExReq 69323 # Transaction distribution 606system.cpu.toL2Bus.trans_dist::ReadExResp 69323 # Transaction distribution 607system.cpu.toL2Bus.trans_dist::ReadCleanReq 10208 # Transaction distribution 608system.cpu.toL2Bus.trans_dist::ReadSharedReq 712819 # Transaction distribution 609system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 29185 # Packet count per connected master and slave (bytes) 610system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2342330 # Packet count per connected master and slave (bytes) 611system.cpu.toL2Bus.pkt_count::total 2371515 # Packet count per connected master and slave (bytes) 612system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1214528 # Cumulative packet size per connected master and slave (bytes) 613system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55752768 # Cumulative packet size per connected master and slave (bytes) 614system.cpu.toL2Bus.pkt_size::total 56967296 # Cumulative packet size per connected master and slave (bytes) 615system.cpu.toL2Bus.snoops 257772 # Total snoops (count) 616system.cpu.toL2Bus.snoop_fanout::samples 1050122 # Request fanout histogram 617system.cpu.toL2Bus.snoop_fanout::mean 0.002597 # Request fanout histogram 618system.cpu.toL2Bus.snoop_fanout::stdev 0.051024 # Request fanout histogram 619system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 620system.cpu.toL2Bus.snoop_fanout::0 1047402 99.74% 99.74% # Request fanout histogram 621system.cpu.toL2Bus.snoop_fanout::1 2713 0.26% 100.00% # Request fanout histogram 622system.cpu.toL2Bus.snoop_fanout::2 7 0.00% 100.00% # Request fanout histogram 623system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 624system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 625system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 626system.cpu.toL2Bus.snoop_fanout::total 1050122 # Request fanout histogram 627system.cpu.toL2Bus.reqLayer0.occupancy 887346500 # Layer occupancy (ticks) 628system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 629system.cpu.toL2Bus.respLayer0.occupancy 15312000 # Layer occupancy (ticks) 630system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 631system.cpu.toL2Bus.respLayer1.occupancy 1173213000 # Layer occupancy (ticks) 632system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) 633system.membus.trans_dist::ReadResp 224275 # Transaction distribution 634system.membus.trans_dist::WritebackDirty 66098 # Transaction distribution 635system.membus.trans_dist::CleanEvict 190094 # Transaction distribution 636system.membus.trans_dist::ReadExReq 66093 # Transaction distribution 637system.membus.trans_dist::ReadExResp 66093 # Transaction distribution 638system.membus.trans_dist::ReadSharedReq 224275 # Transaction distribution 639system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 836928 # Packet count per connected master and slave (bytes) 640system.membus.pkt_count::total 836928 # Packet count per connected master and slave (bytes) 641system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22813824 # Cumulative packet size per connected master and slave (bytes) 642system.membus.pkt_size::total 22813824 # Cumulative packet size per connected master and slave (bytes) 643system.membus.snoops 0 # Total snoops (count) 644system.membus.snoop_fanout::samples 546561 # Request fanout histogram 645system.membus.snoop_fanout::mean 0 # Request fanout histogram 646system.membus.snoop_fanout::stdev 0 # Request fanout histogram 647system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 648system.membus.snoop_fanout::0 546561 100.00% 100.00% # Request fanout histogram 649system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 650system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 651system.membus.snoop_fanout::min_value 0 # Request fanout histogram 652system.membus.snoop_fanout::max_value 0 # Request fanout histogram 653system.membus.snoop_fanout::total 546561 # Request fanout histogram 654system.membus.reqLayer0.occupancy 811325000 # Layer occupancy (ticks) 655system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) 656system.membus.respLayer1.occupancy 1451840000 # Layer occupancy (ticks) 657system.membus.respLayer1.utilization 0.1 # Layer utilization (%) 658 659---------- End Simulation Statistics ---------- 660