stats.txt revision 10036:80e84beef3bb
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.326119 # Number of seconds simulated 4sim_ticks 2326118592000 # Number of ticks simulated 5final_tick 2326118592000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 968971 # Simulator instruction rate (inst/s) 8host_op_rate 1314478 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1631393565 # Simulator tick rate (ticks/s) 10host_mem_usage 255816 # Number of bytes of host memory used 11host_seconds 1425.85 # Real time elapsed on the host 12sim_insts 1381604339 # Number of instructions simulated 13sim_ops 1874244941 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 113472 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 30232512 # Number of bytes read from this memory 18system.physmem.bytes_read::total 30345984 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 113472 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 113472 # Number of instructions bytes read from this memory 21system.physmem.bytes_written::writebacks 4230336 # Number of bytes written to this memory 22system.physmem.bytes_written::total 4230336 # Number of bytes written to this memory 23system.physmem.num_reads::cpu.inst 1773 # Number of read requests responded to by this memory 24system.physmem.num_reads::cpu.data 472383 # Number of read requests responded to by this memory 25system.physmem.num_reads::total 474156 # Number of read requests responded to by this memory 26system.physmem.num_writes::writebacks 66099 # Number of write requests responded to by this memory 27system.physmem.num_writes::total 66099 # Number of write requests responded to by this memory 28system.physmem.bw_read::cpu.inst 48782 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::cpu.data 12996978 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::total 13045760 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_inst_read::cpu.inst 48782 # Instruction read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::total 48782 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_write::writebacks 1818624 # Write bandwidth from this memory (bytes/s) 34system.physmem.bw_write::total 1818624 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_total::writebacks 1818624 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::cpu.inst 48782 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.data 12996978 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::total 14864384 # Total bandwidth to/from this memory (bytes/s) 39system.membus.throughput 14864384 # Throughput (bytes/s) 40system.membus.trans_dist::ReadReq 408063 # Transaction distribution 41system.membus.trans_dist::ReadResp 408063 # Transaction distribution 42system.membus.trans_dist::Writeback 66099 # Transaction distribution 43system.membus.trans_dist::ReadExReq 66093 # Transaction distribution 44system.membus.trans_dist::ReadExResp 66093 # Transaction distribution 45system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1014411 # Packet count per connected master and slave (bytes) 46system.membus.pkt_count::total 1014411 # Packet count per connected master and slave (bytes) 47system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 34576320 # Cumulative packet size per connected master and slave (bytes) 48system.membus.tot_pkt_size::total 34576320 # Cumulative packet size per connected master and slave (bytes) 49system.membus.data_through_bus 34576320 # Total data (bytes) 50system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 51system.membus.reqLayer0.occupancy 1069047000 # Layer occupancy (ticks) 52system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 53system.membus.respLayer1.occupancy 4267404000 # Layer occupancy (ticks) 54system.membus.respLayer1.utilization 0.2 # Layer utilization (%) 55system.cpu_clk_domain.clock 500 # Clock period in ticks 56system.cpu.dtb.inst_hits 0 # ITB inst hits 57system.cpu.dtb.inst_misses 0 # ITB inst misses 58system.cpu.dtb.read_hits 0 # DTB read hits 59system.cpu.dtb.read_misses 0 # DTB read misses 60system.cpu.dtb.write_hits 0 # DTB write hits 61system.cpu.dtb.write_misses 0 # DTB write misses 62system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 63system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 64system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 65system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 66system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 67system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 68system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 69system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 70system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 71system.cpu.dtb.read_accesses 0 # DTB read accesses 72system.cpu.dtb.write_accesses 0 # DTB write accesses 73system.cpu.dtb.inst_accesses 0 # ITB inst accesses 74system.cpu.dtb.hits 0 # DTB hits 75system.cpu.dtb.misses 0 # DTB misses 76system.cpu.dtb.accesses 0 # DTB accesses 77system.cpu.itb.inst_hits 0 # ITB inst hits 78system.cpu.itb.inst_misses 0 # ITB inst misses 79system.cpu.itb.read_hits 0 # DTB read hits 80system.cpu.itb.read_misses 0 # DTB read misses 81system.cpu.itb.write_hits 0 # DTB write hits 82system.cpu.itb.write_misses 0 # DTB write misses 83system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 84system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 85system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 86system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 87system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 88system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 89system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 90system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 91system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 92system.cpu.itb.read_accesses 0 # DTB read accesses 93system.cpu.itb.write_accesses 0 # DTB write accesses 94system.cpu.itb.inst_accesses 0 # ITB inst accesses 95system.cpu.itb.hits 0 # DTB hits 96system.cpu.itb.misses 0 # DTB misses 97system.cpu.itb.accesses 0 # DTB accesses 98system.cpu.workload.num_syscalls 1411 # Number of system calls 99system.cpu.numCycles 4652237184 # number of cpu cycles simulated 100system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 101system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 102system.cpu.committedInsts 1381604339 # Number of instructions committed 103system.cpu.committedOps 1874244941 # Number of ops (including micro ops) committed 104system.cpu.num_int_alu_accesses 1653698868 # Number of integer alu accesses 105system.cpu.num_fp_alu_accesses 52289415 # Number of float alu accesses 106system.cpu.num_func_calls 80372855 # number of times a function call or return occured 107system.cpu.num_conditional_control_insts 230619738 # number of instructions that are conditional controls 108system.cpu.num_int_insts 1653698868 # number of integer instructions 109system.cpu.num_fp_insts 52289415 # number of float instructions 110system.cpu.num_int_register_reads 10466679913 # number of times the integer registers were read 111system.cpu.num_int_register_writes 1874331393 # number of times the integer registers were written 112system.cpu.num_fp_register_reads 60540850 # number of times the floating registers were read 113system.cpu.num_fp_register_writes 46777010 # number of times the floating registers were written 114system.cpu.num_mem_refs 908382479 # number of memory refs 115system.cpu.num_load_insts 631387181 # Number of load instructions 116system.cpu.num_store_insts 276995298 # Number of store instructions 117system.cpu.num_idle_cycles 0 # Number of idle cycles 118system.cpu.num_busy_cycles 4652237184 # Number of busy cycles 119system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles 120system.cpu.idle_fraction 0 # Percentage of idle cycles 121system.cpu.icache.tags.replacements 18364 # number of replacements 122system.cpu.icache.tags.tagsinuse 1392.317060 # Cycle average of tags in use 123system.cpu.icache.tags.total_refs 1390251699 # Total number of references to valid blocks. 124system.cpu.icache.tags.sampled_refs 19803 # Sample count of references to valid blocks. 125system.cpu.icache.tags.avg_refs 70204.095289 # Average number of references to valid blocks. 126system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 127system.cpu.icache.tags.occ_blocks::cpu.inst 1392.317060 # Average occupied blocks per requestor 128system.cpu.icache.tags.occ_percent::cpu.inst 0.679842 # Average percentage of cache occupancy 129system.cpu.icache.tags.occ_percent::total 0.679842 # Average percentage of cache occupancy 130system.cpu.icache.tags.occ_task_id_blocks::1024 1439 # Occupied blocks per task id 131system.cpu.icache.tags.age_task_id_blocks_1024::0 43 # Occupied blocks per task id 132system.cpu.icache.tags.age_task_id_blocks_1024::1 57 # Occupied blocks per task id 133system.cpu.icache.tags.age_task_id_blocks_1024::4 1339 # Occupied blocks per task id 134system.cpu.icache.tags.occ_task_id_percent::1024 0.702637 # Percentage of cache occupancy per task id 135system.cpu.icache.tags.tag_accesses 2780562807 # Number of tag accesses 136system.cpu.icache.tags.data_accesses 2780562807 # Number of data accesses 137system.cpu.icache.ReadReq_hits::cpu.inst 1390251699 # number of ReadReq hits 138system.cpu.icache.ReadReq_hits::total 1390251699 # number of ReadReq hits 139system.cpu.icache.demand_hits::cpu.inst 1390251699 # number of demand (read+write) hits 140system.cpu.icache.demand_hits::total 1390251699 # number of demand (read+write) hits 141system.cpu.icache.overall_hits::cpu.inst 1390251699 # number of overall hits 142system.cpu.icache.overall_hits::total 1390251699 # number of overall hits 143system.cpu.icache.ReadReq_misses::cpu.inst 19803 # number of ReadReq misses 144system.cpu.icache.ReadReq_misses::total 19803 # number of ReadReq misses 145system.cpu.icache.demand_misses::cpu.inst 19803 # number of demand (read+write) misses 146system.cpu.icache.demand_misses::total 19803 # number of demand (read+write) misses 147system.cpu.icache.overall_misses::cpu.inst 19803 # number of overall misses 148system.cpu.icache.overall_misses::total 19803 # number of overall misses 149system.cpu.icache.ReadReq_miss_latency::cpu.inst 331911000 # number of ReadReq miss cycles 150system.cpu.icache.ReadReq_miss_latency::total 331911000 # number of ReadReq miss cycles 151system.cpu.icache.demand_miss_latency::cpu.inst 331911000 # number of demand (read+write) miss cycles 152system.cpu.icache.demand_miss_latency::total 331911000 # number of demand (read+write) miss cycles 153system.cpu.icache.overall_miss_latency::cpu.inst 331911000 # number of overall miss cycles 154system.cpu.icache.overall_miss_latency::total 331911000 # number of overall miss cycles 155system.cpu.icache.ReadReq_accesses::cpu.inst 1390271502 # number of ReadReq accesses(hits+misses) 156system.cpu.icache.ReadReq_accesses::total 1390271502 # number of ReadReq accesses(hits+misses) 157system.cpu.icache.demand_accesses::cpu.inst 1390271502 # number of demand (read+write) accesses 158system.cpu.icache.demand_accesses::total 1390271502 # number of demand (read+write) accesses 159system.cpu.icache.overall_accesses::cpu.inst 1390271502 # number of overall (read+write) accesses 160system.cpu.icache.overall_accesses::total 1390271502 # number of overall (read+write) accesses 161system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000014 # miss rate for ReadReq accesses 162system.cpu.icache.ReadReq_miss_rate::total 0.000014 # miss rate for ReadReq accesses 163system.cpu.icache.demand_miss_rate::cpu.inst 0.000014 # miss rate for demand accesses 164system.cpu.icache.demand_miss_rate::total 0.000014 # miss rate for demand accesses 165system.cpu.icache.overall_miss_rate::cpu.inst 0.000014 # miss rate for overall accesses 166system.cpu.icache.overall_miss_rate::total 0.000014 # miss rate for overall accesses 167system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16760.642327 # average ReadReq miss latency 168system.cpu.icache.ReadReq_avg_miss_latency::total 16760.642327 # average ReadReq miss latency 169system.cpu.icache.demand_avg_miss_latency::cpu.inst 16760.642327 # average overall miss latency 170system.cpu.icache.demand_avg_miss_latency::total 16760.642327 # average overall miss latency 171system.cpu.icache.overall_avg_miss_latency::cpu.inst 16760.642327 # average overall miss latency 172system.cpu.icache.overall_avg_miss_latency::total 16760.642327 # average overall miss latency 173system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 174system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 175system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 176system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 177system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 178system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 179system.cpu.icache.fast_writes 0 # number of fast writes performed 180system.cpu.icache.cache_copies 0 # number of cache copies performed 181system.cpu.icache.ReadReq_mshr_misses::cpu.inst 19803 # number of ReadReq MSHR misses 182system.cpu.icache.ReadReq_mshr_misses::total 19803 # number of ReadReq MSHR misses 183system.cpu.icache.demand_mshr_misses::cpu.inst 19803 # number of demand (read+write) MSHR misses 184system.cpu.icache.demand_mshr_misses::total 19803 # number of demand (read+write) MSHR misses 185system.cpu.icache.overall_mshr_misses::cpu.inst 19803 # number of overall MSHR misses 186system.cpu.icache.overall_mshr_misses::total 19803 # number of overall MSHR misses 187system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 292305000 # number of ReadReq MSHR miss cycles 188system.cpu.icache.ReadReq_mshr_miss_latency::total 292305000 # number of ReadReq MSHR miss cycles 189system.cpu.icache.demand_mshr_miss_latency::cpu.inst 292305000 # number of demand (read+write) MSHR miss cycles 190system.cpu.icache.demand_mshr_miss_latency::total 292305000 # number of demand (read+write) MSHR miss cycles 191system.cpu.icache.overall_mshr_miss_latency::cpu.inst 292305000 # number of overall MSHR miss cycles 192system.cpu.icache.overall_mshr_miss_latency::total 292305000 # number of overall MSHR miss cycles 193system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000014 # mshr miss rate for ReadReq accesses 194system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000014 # mshr miss rate for ReadReq accesses 195system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000014 # mshr miss rate for demand accesses 196system.cpu.icache.demand_mshr_miss_rate::total 0.000014 # mshr miss rate for demand accesses 197system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000014 # mshr miss rate for overall accesses 198system.cpu.icache.overall_mshr_miss_rate::total 0.000014 # mshr miss rate for overall accesses 199system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14760.642327 # average ReadReq mshr miss latency 200system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14760.642327 # average ReadReq mshr miss latency 201system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14760.642327 # average overall mshr miss latency 202system.cpu.icache.demand_avg_mshr_miss_latency::total 14760.642327 # average overall mshr miss latency 203system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14760.642327 # average overall mshr miss latency 204system.cpu.icache.overall_avg_mshr_miss_latency::total 14760.642327 # average overall mshr miss latency 205system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 206system.cpu.l2cache.tags.replacements 441378 # number of replacements 207system.cpu.l2cache.tags.tagsinuse 32692.891822 # Cycle average of tags in use 208system.cpu.l2cache.tags.total_refs 1102614 # Total number of references to valid blocks. 209system.cpu.l2cache.tags.sampled_refs 474121 # Sample count of references to valid blocks. 210system.cpu.l2cache.tags.avg_refs 2.325596 # Average number of references to valid blocks. 211system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 212system.cpu.l2cache.tags.occ_blocks::writebacks 1298.141733 # Average occupied blocks per requestor 213system.cpu.l2cache.tags.occ_blocks::cpu.inst 30.233408 # Average occupied blocks per requestor 214system.cpu.l2cache.tags.occ_blocks::cpu.data 31364.516681 # Average occupied blocks per requestor 215system.cpu.l2cache.tags.occ_percent::writebacks 0.039616 # Average percentage of cache occupancy 216system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000923 # Average percentage of cache occupancy 217system.cpu.l2cache.tags.occ_percent::cpu.data 0.957169 # Average percentage of cache occupancy 218system.cpu.l2cache.tags.occ_percent::total 0.997708 # Average percentage of cache occupancy 219system.cpu.l2cache.tags.occ_task_id_blocks::1024 32743 # Occupied blocks per task id 220system.cpu.l2cache.tags.age_task_id_blocks_1024::0 68 # Occupied blocks per task id 221system.cpu.l2cache.tags.age_task_id_blocks_1024::1 120 # Occupied blocks per task id 222system.cpu.l2cache.tags.age_task_id_blocks_1024::2 144 # Occupied blocks per task id 223system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1387 # Occupied blocks per task id 224system.cpu.l2cache.tags.age_task_id_blocks_1024::4 31024 # Occupied blocks per task id 225system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999237 # Percentage of cache occupancy per task id 226system.cpu.l2cache.tags.tag_accesses 13744605 # Number of tag accesses 227system.cpu.l2cache.tags.data_accesses 13744605 # Number of data accesses 228system.cpu.l2cache.ReadReq_hits::cpu.inst 18030 # number of ReadReq hits 229system.cpu.l2cache.ReadReq_hits::cpu.data 1054583 # number of ReadReq hits 230system.cpu.l2cache.ReadReq_hits::total 1072613 # number of ReadReq hits 231system.cpu.l2cache.Writeback_hits::writebacks 96257 # number of Writeback hits 232system.cpu.l2cache.Writeback_hits::total 96257 # number of Writeback hits 233system.cpu.l2cache.ReadExReq_hits::cpu.data 6687 # number of ReadExReq hits 234system.cpu.l2cache.ReadExReq_hits::total 6687 # number of ReadExReq hits 235system.cpu.l2cache.demand_hits::cpu.inst 18030 # number of demand (read+write) hits 236system.cpu.l2cache.demand_hits::cpu.data 1061270 # number of demand (read+write) hits 237system.cpu.l2cache.demand_hits::total 1079300 # number of demand (read+write) hits 238system.cpu.l2cache.overall_hits::cpu.inst 18030 # number of overall hits 239system.cpu.l2cache.overall_hits::cpu.data 1061270 # number of overall hits 240system.cpu.l2cache.overall_hits::total 1079300 # number of overall hits 241system.cpu.l2cache.ReadReq_misses::cpu.inst 1773 # number of ReadReq misses 242system.cpu.l2cache.ReadReq_misses::cpu.data 406290 # number of ReadReq misses 243system.cpu.l2cache.ReadReq_misses::total 408063 # number of ReadReq misses 244system.cpu.l2cache.ReadExReq_misses::cpu.data 66093 # number of ReadExReq misses 245system.cpu.l2cache.ReadExReq_misses::total 66093 # number of ReadExReq misses 246system.cpu.l2cache.demand_misses::cpu.inst 1773 # number of demand (read+write) misses 247system.cpu.l2cache.demand_misses::cpu.data 472383 # number of demand (read+write) misses 248system.cpu.l2cache.demand_misses::total 474156 # number of demand (read+write) misses 249system.cpu.l2cache.overall_misses::cpu.inst 1773 # number of overall misses 250system.cpu.l2cache.overall_misses::cpu.data 472383 # number of overall misses 251system.cpu.l2cache.overall_misses::total 474156 # number of overall misses 252system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 92202000 # number of ReadReq miss cycles 253system.cpu.l2cache.ReadReq_miss_latency::cpu.data 21127080000 # number of ReadReq miss cycles 254system.cpu.l2cache.ReadReq_miss_latency::total 21219282000 # number of ReadReq miss cycles 255system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3436836000 # number of ReadExReq miss cycles 256system.cpu.l2cache.ReadExReq_miss_latency::total 3436836000 # number of ReadExReq miss cycles 257system.cpu.l2cache.demand_miss_latency::cpu.inst 92202000 # number of demand (read+write) miss cycles 258system.cpu.l2cache.demand_miss_latency::cpu.data 24563916000 # number of demand (read+write) miss cycles 259system.cpu.l2cache.demand_miss_latency::total 24656118000 # number of demand (read+write) miss cycles 260system.cpu.l2cache.overall_miss_latency::cpu.inst 92202000 # number of overall miss cycles 261system.cpu.l2cache.overall_miss_latency::cpu.data 24563916000 # number of overall miss cycles 262system.cpu.l2cache.overall_miss_latency::total 24656118000 # number of overall miss cycles 263system.cpu.l2cache.ReadReq_accesses::cpu.inst 19803 # number of ReadReq accesses(hits+misses) 264system.cpu.l2cache.ReadReq_accesses::cpu.data 1460873 # number of ReadReq accesses(hits+misses) 265system.cpu.l2cache.ReadReq_accesses::total 1480676 # number of ReadReq accesses(hits+misses) 266system.cpu.l2cache.Writeback_accesses::writebacks 96257 # number of Writeback accesses(hits+misses) 267system.cpu.l2cache.Writeback_accesses::total 96257 # number of Writeback accesses(hits+misses) 268system.cpu.l2cache.ReadExReq_accesses::cpu.data 72780 # number of ReadExReq accesses(hits+misses) 269system.cpu.l2cache.ReadExReq_accesses::total 72780 # number of ReadExReq accesses(hits+misses) 270system.cpu.l2cache.demand_accesses::cpu.inst 19803 # number of demand (read+write) accesses 271system.cpu.l2cache.demand_accesses::cpu.data 1533653 # number of demand (read+write) accesses 272system.cpu.l2cache.demand_accesses::total 1553456 # number of demand (read+write) accesses 273system.cpu.l2cache.overall_accesses::cpu.inst 19803 # number of overall (read+write) accesses 274system.cpu.l2cache.overall_accesses::cpu.data 1533653 # number of overall (read+write) accesses 275system.cpu.l2cache.overall_accesses::total 1553456 # number of overall (read+write) accesses 276system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.089532 # miss rate for ReadReq accesses 277system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.278115 # miss rate for ReadReq accesses 278system.cpu.l2cache.ReadReq_miss_rate::total 0.275592 # miss rate for ReadReq accesses 279system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.908120 # miss rate for ReadExReq accesses 280system.cpu.l2cache.ReadExReq_miss_rate::total 0.908120 # miss rate for ReadExReq accesses 281system.cpu.l2cache.demand_miss_rate::cpu.inst 0.089532 # miss rate for demand accesses 282system.cpu.l2cache.demand_miss_rate::cpu.data 0.308012 # miss rate for demand accesses 283system.cpu.l2cache.demand_miss_rate::total 0.305227 # miss rate for demand accesses 284system.cpu.l2cache.overall_miss_rate::cpu.inst 0.089532 # miss rate for overall accesses 285system.cpu.l2cache.overall_miss_rate::cpu.data 0.308012 # miss rate for overall accesses 286system.cpu.l2cache.overall_miss_rate::total 0.305227 # miss rate for overall accesses 287system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52003.384095 # average ReadReq miss latency 288system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency 289system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000.014704 # average ReadReq miss latency 290system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency 291system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency 292system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52003.384095 # average overall miss latency 293system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency 294system.cpu.l2cache.demand_avg_miss_latency::total 52000.012654 # average overall miss latency 295system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52003.384095 # average overall miss latency 296system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency 297system.cpu.l2cache.overall_avg_miss_latency::total 52000.012654 # average overall miss latency 298system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 299system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 300system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 301system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 302system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 303system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 304system.cpu.l2cache.fast_writes 0 # number of fast writes performed 305system.cpu.l2cache.cache_copies 0 # number of cache copies performed 306system.cpu.l2cache.writebacks::writebacks 66099 # number of writebacks 307system.cpu.l2cache.writebacks::total 66099 # number of writebacks 308system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1773 # number of ReadReq MSHR misses 309system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 406290 # number of ReadReq MSHR misses 310system.cpu.l2cache.ReadReq_mshr_misses::total 408063 # number of ReadReq MSHR misses 311system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66093 # number of ReadExReq MSHR misses 312system.cpu.l2cache.ReadExReq_mshr_misses::total 66093 # number of ReadExReq MSHR misses 313system.cpu.l2cache.demand_mshr_misses::cpu.inst 1773 # number of demand (read+write) MSHR misses 314system.cpu.l2cache.demand_mshr_misses::cpu.data 472383 # number of demand (read+write) MSHR misses 315system.cpu.l2cache.demand_mshr_misses::total 474156 # number of demand (read+write) MSHR misses 316system.cpu.l2cache.overall_mshr_misses::cpu.inst 1773 # number of overall MSHR misses 317system.cpu.l2cache.overall_mshr_misses::cpu.data 472383 # number of overall MSHR misses 318system.cpu.l2cache.overall_mshr_misses::total 474156 # number of overall MSHR misses 319system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 70926000 # number of ReadReq MSHR miss cycles 320system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 16251600000 # number of ReadReq MSHR miss cycles 321system.cpu.l2cache.ReadReq_mshr_miss_latency::total 16322526000 # number of ReadReq MSHR miss cycles 322system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2643720000 # number of ReadExReq MSHR miss cycles 323system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2643720000 # number of ReadExReq MSHR miss cycles 324system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 70926000 # number of demand (read+write) MSHR miss cycles 325system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 18895320000 # number of demand (read+write) MSHR miss cycles 326system.cpu.l2cache.demand_mshr_miss_latency::total 18966246000 # number of demand (read+write) MSHR miss cycles 327system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 70926000 # number of overall MSHR miss cycles 328system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 18895320000 # number of overall MSHR miss cycles 329system.cpu.l2cache.overall_mshr_miss_latency::total 18966246000 # number of overall MSHR miss cycles 330system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.089532 # mshr miss rate for ReadReq accesses 331system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.278115 # mshr miss rate for ReadReq accesses 332system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.275592 # mshr miss rate for ReadReq accesses 333system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.908120 # mshr miss rate for ReadExReq accesses 334system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.908120 # mshr miss rate for ReadExReq accesses 335system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.089532 # mshr miss rate for demand accesses 336system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.308012 # mshr miss rate for demand accesses 337system.cpu.l2cache.demand_mshr_miss_rate::total 0.305227 # mshr miss rate for demand accesses 338system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.089532 # mshr miss rate for overall accesses 339system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.308012 # mshr miss rate for overall accesses 340system.cpu.l2cache.overall_mshr_miss_rate::total 0.305227 # mshr miss rate for overall accesses 341system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40003.384095 # average ReadReq mshr miss latency 342system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency 343system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000.014704 # average ReadReq mshr miss latency 344system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency 345system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency 346system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40003.384095 # average overall mshr miss latency 347system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency 348system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000.012654 # average overall mshr miss latency 349system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40003.384095 # average overall mshr miss latency 350system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency 351system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.012654 # average overall mshr miss latency 352system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 353system.cpu.dcache.tags.replacements 1529557 # number of replacements 354system.cpu.dcache.tags.tagsinuse 4094.947189 # Cycle average of tags in use 355system.cpu.dcache.tags.total_refs 895757408 # Total number of references to valid blocks. 356system.cpu.dcache.tags.sampled_refs 1533653 # Sample count of references to valid blocks. 357system.cpu.dcache.tags.avg_refs 584.067848 # Average number of references to valid blocks. 358system.cpu.dcache.tags.warmup_cycle 991199000 # Cycle when the warmup percentage was hit. 359system.cpu.dcache.tags.occ_blocks::cpu.data 4094.947189 # Average occupied blocks per requestor 360system.cpu.dcache.tags.occ_percent::cpu.data 0.999743 # Average percentage of cache occupancy 361system.cpu.dcache.tags.occ_percent::total 0.999743 # Average percentage of cache occupancy 362system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 363system.cpu.dcache.tags.age_task_id_blocks_1024::0 29 # Occupied blocks per task id 364system.cpu.dcache.tags.age_task_id_blocks_1024::1 118 # Occupied blocks per task id 365system.cpu.dcache.tags.age_task_id_blocks_1024::2 568 # Occupied blocks per task id 366system.cpu.dcache.tags.age_task_id_blocks_1024::3 1040 # Occupied blocks per task id 367system.cpu.dcache.tags.age_task_id_blocks_1024::4 2341 # Occupied blocks per task id 368system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 369system.cpu.dcache.tags.tag_accesses 1796115775 # Number of tag accesses 370system.cpu.dcache.tags.data_accesses 1796115775 # Number of data accesses 371system.cpu.dcache.ReadReq_hits::cpu.data 618874540 # number of ReadReq hits 372system.cpu.dcache.ReadReq_hits::total 618874540 # number of ReadReq hits 373system.cpu.dcache.WriteReq_hits::cpu.data 276862898 # number of WriteReq hits 374system.cpu.dcache.WriteReq_hits::total 276862898 # number of WriteReq hits 375system.cpu.dcache.LoadLockedReq_hits::cpu.data 9985 # number of LoadLockedReq hits 376system.cpu.dcache.LoadLockedReq_hits::total 9985 # number of LoadLockedReq hits 377system.cpu.dcache.StoreCondReq_hits::cpu.data 9985 # number of StoreCondReq hits 378system.cpu.dcache.StoreCondReq_hits::total 9985 # number of StoreCondReq hits 379system.cpu.dcache.demand_hits::cpu.data 895737438 # number of demand (read+write) hits 380system.cpu.dcache.demand_hits::total 895737438 # number of demand (read+write) hits 381system.cpu.dcache.overall_hits::cpu.data 895737438 # number of overall hits 382system.cpu.dcache.overall_hits::total 895737438 # number of overall hits 383system.cpu.dcache.ReadReq_misses::cpu.data 1460873 # number of ReadReq misses 384system.cpu.dcache.ReadReq_misses::total 1460873 # number of ReadReq misses 385system.cpu.dcache.WriteReq_misses::cpu.data 72780 # number of WriteReq misses 386system.cpu.dcache.WriteReq_misses::total 72780 # number of WriteReq misses 387system.cpu.dcache.demand_misses::cpu.data 1533653 # number of demand (read+write) misses 388system.cpu.dcache.demand_misses::total 1533653 # number of demand (read+write) misses 389system.cpu.dcache.overall_misses::cpu.data 1533653 # number of overall misses 390system.cpu.dcache.overall_misses::total 1533653 # number of overall misses 391system.cpu.dcache.ReadReq_miss_latency::cpu.data 36055529000 # number of ReadReq miss cycles 392system.cpu.dcache.ReadReq_miss_latency::total 36055529000 # number of ReadReq miss cycles 393system.cpu.dcache.WriteReq_miss_latency::cpu.data 3722046000 # number of WriteReq miss cycles 394system.cpu.dcache.WriteReq_miss_latency::total 3722046000 # number of WriteReq miss cycles 395system.cpu.dcache.demand_miss_latency::cpu.data 39777575000 # number of demand (read+write) miss cycles 396system.cpu.dcache.demand_miss_latency::total 39777575000 # number of demand (read+write) miss cycles 397system.cpu.dcache.overall_miss_latency::cpu.data 39777575000 # number of overall miss cycles 398system.cpu.dcache.overall_miss_latency::total 39777575000 # number of overall miss cycles 399system.cpu.dcache.ReadReq_accesses::cpu.data 620335413 # number of ReadReq accesses(hits+misses) 400system.cpu.dcache.ReadReq_accesses::total 620335413 # number of ReadReq accesses(hits+misses) 401system.cpu.dcache.WriteReq_accesses::cpu.data 276935678 # number of WriteReq accesses(hits+misses) 402system.cpu.dcache.WriteReq_accesses::total 276935678 # number of WriteReq accesses(hits+misses) 403system.cpu.dcache.LoadLockedReq_accesses::cpu.data 9985 # number of LoadLockedReq accesses(hits+misses) 404system.cpu.dcache.LoadLockedReq_accesses::total 9985 # number of LoadLockedReq accesses(hits+misses) 405system.cpu.dcache.StoreCondReq_accesses::cpu.data 9985 # number of StoreCondReq accesses(hits+misses) 406system.cpu.dcache.StoreCondReq_accesses::total 9985 # number of StoreCondReq accesses(hits+misses) 407system.cpu.dcache.demand_accesses::cpu.data 897271091 # number of demand (read+write) accesses 408system.cpu.dcache.demand_accesses::total 897271091 # number of demand (read+write) accesses 409system.cpu.dcache.overall_accesses::cpu.data 897271091 # number of overall (read+write) accesses 410system.cpu.dcache.overall_accesses::total 897271091 # number of overall (read+write) accesses 411system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002355 # miss rate for ReadReq accesses 412system.cpu.dcache.ReadReq_miss_rate::total 0.002355 # miss rate for ReadReq accesses 413system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000263 # miss rate for WriteReq accesses 414system.cpu.dcache.WriteReq_miss_rate::total 0.000263 # miss rate for WriteReq accesses 415system.cpu.dcache.demand_miss_rate::cpu.data 0.001709 # miss rate for demand accesses 416system.cpu.dcache.demand_miss_rate::total 0.001709 # miss rate for demand accesses 417system.cpu.dcache.overall_miss_rate::cpu.data 0.001709 # miss rate for overall accesses 418system.cpu.dcache.overall_miss_rate::total 0.001709 # miss rate for overall accesses 419system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24680.810036 # average ReadReq miss latency 420system.cpu.dcache.ReadReq_avg_miss_latency::total 24680.810036 # average ReadReq miss latency 421system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 51141.055235 # average WriteReq miss latency 422system.cpu.dcache.WriteReq_avg_miss_latency::total 51141.055235 # average WriteReq miss latency 423system.cpu.dcache.demand_avg_miss_latency::cpu.data 25936.489545 # average overall miss latency 424system.cpu.dcache.demand_avg_miss_latency::total 25936.489545 # average overall miss latency 425system.cpu.dcache.overall_avg_miss_latency::cpu.data 25936.489545 # average overall miss latency 426system.cpu.dcache.overall_avg_miss_latency::total 25936.489545 # average overall miss latency 427system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 428system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 429system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 430system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 431system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 432system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 433system.cpu.dcache.fast_writes 0 # number of fast writes performed 434system.cpu.dcache.cache_copies 0 # number of cache copies performed 435system.cpu.dcache.writebacks::writebacks 96257 # number of writebacks 436system.cpu.dcache.writebacks::total 96257 # number of writebacks 437system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1460873 # number of ReadReq MSHR misses 438system.cpu.dcache.ReadReq_mshr_misses::total 1460873 # number of ReadReq MSHR misses 439system.cpu.dcache.WriteReq_mshr_misses::cpu.data 72780 # number of WriteReq MSHR misses 440system.cpu.dcache.WriteReq_mshr_misses::total 72780 # number of WriteReq MSHR misses 441system.cpu.dcache.demand_mshr_misses::cpu.data 1533653 # number of demand (read+write) MSHR misses 442system.cpu.dcache.demand_mshr_misses::total 1533653 # number of demand (read+write) MSHR misses 443system.cpu.dcache.overall_mshr_misses::cpu.data 1533653 # number of overall MSHR misses 444system.cpu.dcache.overall_mshr_misses::total 1533653 # number of overall MSHR misses 445system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33133783000 # number of ReadReq MSHR miss cycles 446system.cpu.dcache.ReadReq_mshr_miss_latency::total 33133783000 # number of ReadReq MSHR miss cycles 447system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3576486000 # number of WriteReq MSHR miss cycles 448system.cpu.dcache.WriteReq_mshr_miss_latency::total 3576486000 # number of WriteReq MSHR miss cycles 449system.cpu.dcache.demand_mshr_miss_latency::cpu.data 36710269000 # number of demand (read+write) MSHR miss cycles 450system.cpu.dcache.demand_mshr_miss_latency::total 36710269000 # number of demand (read+write) MSHR miss cycles 451system.cpu.dcache.overall_mshr_miss_latency::cpu.data 36710269000 # number of overall MSHR miss cycles 452system.cpu.dcache.overall_mshr_miss_latency::total 36710269000 # number of overall MSHR miss cycles 453system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002355 # mshr miss rate for ReadReq accesses 454system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002355 # mshr miss rate for ReadReq accesses 455system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000263 # mshr miss rate for WriteReq accesses 456system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000263 # mshr miss rate for WriteReq accesses 457system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001709 # mshr miss rate for demand accesses 458system.cpu.dcache.demand_mshr_miss_rate::total 0.001709 # mshr miss rate for demand accesses 459system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001709 # mshr miss rate for overall accesses 460system.cpu.dcache.overall_mshr_miss_rate::total 0.001709 # mshr miss rate for overall accesses 461system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22680.810036 # average ReadReq mshr miss latency 462system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22680.810036 # average ReadReq mshr miss latency 463system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49141.055235 # average WriteReq mshr miss latency 464system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49141.055235 # average WriteReq mshr miss latency 465system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23936.489545 # average overall mshr miss latency 466system.cpu.dcache.demand_avg_mshr_miss_latency::total 23936.489545 # average overall mshr miss latency 467system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23936.489545 # average overall mshr miss latency 468system.cpu.dcache.overall_avg_mshr_miss_latency::total 23936.489545 # average overall mshr miss latency 469system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 470system.cpu.toL2Bus.throughput 45389617 # Throughput (bytes/s) 471system.cpu.toL2Bus.trans_dist::ReadReq 1480676 # Transaction distribution 472system.cpu.toL2Bus.trans_dist::ReadResp 1480676 # Transaction distribution 473system.cpu.toL2Bus.trans_dist::Writeback 96257 # Transaction distribution 474system.cpu.toL2Bus.trans_dist::ReadExReq 72780 # Transaction distribution 475system.cpu.toL2Bus.trans_dist::ReadExResp 72780 # Transaction distribution 476system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 39606 # Packet count per connected master and slave (bytes) 477system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3163563 # Packet count per connected master and slave (bytes) 478system.cpu.toL2Bus.pkt_count::total 3203169 # Packet count per connected master and slave (bytes) 479system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1267392 # Cumulative packet size per connected master and slave (bytes) 480system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 104314240 # Cumulative packet size per connected master and slave (bytes) 481system.cpu.toL2Bus.tot_pkt_size::total 105581632 # Cumulative packet size per connected master and slave (bytes) 482system.cpu.toL2Bus.data_through_bus 105581632 # Total data (bytes) 483system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) 484system.cpu.toL2Bus.reqLayer0.occupancy 921113500 # Layer occupancy (ticks) 485system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 486system.cpu.toL2Bus.respLayer0.occupancy 29704500 # Layer occupancy (ticks) 487system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 488system.cpu.toL2Bus.respLayer1.occupancy 2300479500 # Layer occupancy (ticks) 489system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) 490 491---------- End Simulation Statistics ---------- 492