stats.txt revision 9285:9901180cd573
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.659244 # Number of seconds simulated 4sim_ticks 659244465000 # Number of ticks simulated 5final_tick 659244465000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 88407 # Simulator instruction rate (inst/s) 8host_op_rate 120399 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 42099861 # Simulator tick rate (ticks/s) 10host_mem_usage 243836 # Number of bytes of host memory used 11host_seconds 15659.07 # Real time elapsed on the host 12sim_insts 1384375635 # Number of instructions simulated 13sim_ops 1885330387 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 199616 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 94515200 # Number of bytes read from this memory 16system.physmem.bytes_read::total 94714816 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 199616 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 199616 # Number of instructions bytes read from this memory 19system.physmem.bytes_written::writebacks 4230336 # Number of bytes written to this memory 20system.physmem.bytes_written::total 4230336 # Number of bytes written to this memory 21system.physmem.num_reads::cpu.inst 3119 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 1476800 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 1479919 # Number of read requests responded to by this memory 24system.physmem.num_writes::writebacks 66099 # Number of write requests responded to by this memory 25system.physmem.num_writes::total 66099 # Number of write requests responded to by this memory 26system.physmem.bw_read::cpu.inst 302795 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::cpu.data 143368970 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_read::total 143671765 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::cpu.inst 302795 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_inst_read::total 302795 # Instruction read bandwidth from this memory (bytes/s) 31system.physmem.bw_write::writebacks 6416946 # Write bandwidth from this memory (bytes/s) 32system.physmem.bw_write::total 6416946 # Write bandwidth from this memory (bytes/s) 33system.physmem.bw_total::writebacks 6416946 # Total bandwidth to/from this memory (bytes/s) 34system.physmem.bw_total::cpu.inst 302795 # Total bandwidth to/from this memory (bytes/s) 35system.physmem.bw_total::cpu.data 143368970 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::total 150088711 # Total bandwidth to/from this memory (bytes/s) 37system.cpu.dtb.inst_hits 0 # ITB inst hits 38system.cpu.dtb.inst_misses 0 # ITB inst misses 39system.cpu.dtb.read_hits 0 # DTB read hits 40system.cpu.dtb.read_misses 0 # DTB read misses 41system.cpu.dtb.write_hits 0 # DTB write hits 42system.cpu.dtb.write_misses 0 # DTB write misses 43system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 44system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 45system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 46system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 47system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 48system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 49system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 50system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 51system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 52system.cpu.dtb.read_accesses 0 # DTB read accesses 53system.cpu.dtb.write_accesses 0 # DTB write accesses 54system.cpu.dtb.inst_accesses 0 # ITB inst accesses 55system.cpu.dtb.hits 0 # DTB hits 56system.cpu.dtb.misses 0 # DTB misses 57system.cpu.dtb.accesses 0 # DTB accesses 58system.cpu.itb.inst_hits 0 # ITB inst hits 59system.cpu.itb.inst_misses 0 # ITB inst misses 60system.cpu.itb.read_hits 0 # DTB read hits 61system.cpu.itb.read_misses 0 # DTB read misses 62system.cpu.itb.write_hits 0 # DTB write hits 63system.cpu.itb.write_misses 0 # DTB write misses 64system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 65system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 66system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 67system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 68system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 69system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 70system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 71system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 72system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 73system.cpu.itb.read_accesses 0 # DTB read accesses 74system.cpu.itb.write_accesses 0 # DTB write accesses 75system.cpu.itb.inst_accesses 0 # ITB inst accesses 76system.cpu.itb.hits 0 # DTB hits 77system.cpu.itb.misses 0 # DTB misses 78system.cpu.itb.accesses 0 # DTB accesses 79system.cpu.workload.num_syscalls 1411 # Number of system calls 80system.cpu.numCycles 1318488931 # number of cpu cycles simulated 81system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 82system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 83system.cpu.BPredUnit.lookups 461326092 # Number of BP lookups 84system.cpu.BPredUnit.condPredicted 364071075 # Number of conditional branches predicted 85system.cpu.BPredUnit.condIncorrect 34100101 # Number of conditional branches incorrect 86system.cpu.BPredUnit.BTBLookups 298580925 # Number of BTB lookups 87system.cpu.BPredUnit.BTBHits 245422956 # Number of BTB hits 88system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 89system.cpu.BPredUnit.usedRAS 54976315 # Number of times the RAS was used to get a target. 90system.cpu.BPredUnit.RASInCorrect 2806988 # Number of incorrect RAS predictions. 91system.cpu.fetch.icacheStallCycles 381926912 # Number of cycles fetch is stalled on an Icache miss 92system.cpu.fetch.Insts 2354617227 # Number of instructions fetch has processed 93system.cpu.fetch.Branches 461326092 # Number of branches that fetch encountered 94system.cpu.fetch.predictedBranches 300399271 # Number of branches that fetch has predicted taken 95system.cpu.fetch.Cycles 631966560 # Number of cycles fetch has run and was not squashing or blocked 96system.cpu.fetch.SquashCycles 174781634 # Number of cycles fetch has spent squashing 97system.cpu.fetch.BlockedCycles 133381872 # Number of cycles fetch has spent blocked 98system.cpu.fetch.MiscStallCycles 1547 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 99system.cpu.fetch.PendingTrapStallCycles 26290 # Number of stall cycles due to pending traps 100system.cpu.fetch.CacheLines 359560180 # Number of cache lines fetched 101system.cpu.fetch.IcacheSquashes 11891763 # Number of outstanding Icache misses that were squashed 102system.cpu.fetch.rateDist::samples 1287933807 # Number of instructions fetched each cycle (Total) 103system.cpu.fetch.rateDist::mean 2.529860 # Number of instructions fetched each cycle (Total) 104system.cpu.fetch.rateDist::stdev 3.156146 # Number of instructions fetched each cycle (Total) 105system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 106system.cpu.fetch.rateDist::0 656012764 50.94% 50.94% # Number of instructions fetched each cycle (Total) 107system.cpu.fetch.rateDist::1 47127862 3.66% 54.59% # Number of instructions fetched each cycle (Total) 108system.cpu.fetch.rateDist::2 105351348 8.18% 62.77% # Number of instructions fetched each cycle (Total) 109system.cpu.fetch.rateDist::3 60429666 4.69% 67.47% # Number of instructions fetched each cycle (Total) 110system.cpu.fetch.rateDist::4 75027065 5.83% 73.29% # Number of instructions fetched each cycle (Total) 111system.cpu.fetch.rateDist::5 45419751 3.53% 76.82% # Number of instructions fetched each cycle (Total) 112system.cpu.fetch.rateDist::6 32157937 2.50% 79.32% # Number of instructions fetched each cycle (Total) 113system.cpu.fetch.rateDist::7 32241388 2.50% 81.82% # Number of instructions fetched each cycle (Total) 114system.cpu.fetch.rateDist::8 234166026 18.18% 100.00% # Number of instructions fetched each cycle (Total) 115system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 116system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 117system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 118system.cpu.fetch.rateDist::total 1287933807 # Number of instructions fetched each cycle (Total) 119system.cpu.fetch.branchRate 0.349890 # Number of branch fetches per cycle 120system.cpu.fetch.rate 1.785845 # Number of inst fetches per cycle 121system.cpu.decode.IdleCycles 433461682 # Number of cycles decode is idle 122system.cpu.decode.BlockedCycles 105761116 # Number of cycles decode is blocked 123system.cpu.decode.RunCycles 591844441 # Number of cycles decode is running 124system.cpu.decode.UnblockCycles 16248270 # Number of cycles decode is unblocking 125system.cpu.decode.SquashCycles 140618298 # Number of cycles decode is squashing 126system.cpu.decode.BranchResolved 52072887 # Number of times decode resolved a branch 127system.cpu.decode.BranchMispred 12605 # Number of times decode detected a branch misprediction 128system.cpu.decode.DecodedInsts 3150187282 # Number of instructions handled by decode 129system.cpu.decode.SquashedInsts 23939 # Number of squashed instructions handled by decode 130system.cpu.rename.SquashCycles 140618298 # Number of cycles rename is squashing 131system.cpu.rename.IdleCycles 469309271 # Number of cycles rename is idle 132system.cpu.rename.BlockCycles 39277977 # Number of cycles rename is blocking 133system.cpu.rename.serializeStallCycles 483250 # count of cycles rename stalled for serializing inst 134system.cpu.rename.RunCycles 570159229 # Number of cycles rename is running 135system.cpu.rename.UnblockCycles 68085782 # Number of cycles rename is unblocking 136system.cpu.rename.RenamedInsts 3069262221 # Number of instructions processed by rename 137system.cpu.rename.ROBFullEvents 155 # Number of times rename has blocked due to ROB full 138system.cpu.rename.IQFullEvents 4380621 # Number of times rename has blocked due to IQ full 139system.cpu.rename.LSQFullEvents 54394099 # Number of times rename has blocked due to LSQ full 140system.cpu.rename.FullRegisterEvents 1922 # Number of times there has been no free registers 141system.cpu.rename.RenamedOperands 3038163295 # Number of destination operands rename has renamed 142system.cpu.rename.RenameLookups 14611934802 # Number of register rename lookups that rename has made 143system.cpu.rename.int_rename_lookups 13977694721 # Number of integer rename lookups 144system.cpu.rename.fp_rename_lookups 634240081 # Number of floating rename lookups 145system.cpu.rename.CommittedMaps 1993148162 # Number of HB maps that are committed 146system.cpu.rename.UndoneMaps 1045015133 # Number of HB maps that are undone due to squashing 147system.cpu.rename.serializingInsts 27322 # count of serializing insts renamed 148system.cpu.rename.tempSerializingInsts 23140 # count of temporary serializing insts renamed 149system.cpu.rename.skidInsts 179514029 # count of insts added to the skid buffer 150system.cpu.memDep0.insertedLoads 982659180 # Number of loads inserted to the mem dependence unit. 151system.cpu.memDep0.insertedStores 514844433 # Number of stores inserted to the mem dependence unit. 152system.cpu.memDep0.conflictingLoads 35819898 # Number of conflicting loads. 153system.cpu.memDep0.conflictingStores 36120464 # Number of conflicting stores. 154system.cpu.iq.iqInstsAdded 2890303698 # Number of instructions added to the IQ (excludes non-spec) 155system.cpu.iq.iqNonSpecInstsAdded 33130 # Number of non-speculative instructions added to the IQ 156system.cpu.iq.iqInstsIssued 2506565055 # Number of instructions issued 157system.cpu.iq.iqSquashedInstsIssued 17234382 # Number of squashed instructions issued 158system.cpu.iq.iqSquashedInstsExamined 992532581 # Number of squashed instructions iterated over during squash; mainly for profiling 159system.cpu.iq.iqSquashedOperandsExamined 2476785189 # Number of squashed operands that are examined and possibly removed from graph 160system.cpu.iq.iqSquashedNonSpecRemoved 10737 # Number of squashed non-spec instructions that were removed 161system.cpu.iq.issued_per_cycle::samples 1287933807 # Number of insts issued each cycle 162system.cpu.iq.issued_per_cycle::mean 1.946191 # Number of insts issued each cycle 163system.cpu.iq.issued_per_cycle::stdev 1.883330 # Number of insts issued each cycle 164system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 165system.cpu.iq.issued_per_cycle::0 425460645 33.03% 33.03% # Number of insts issued each cycle 166system.cpu.iq.issued_per_cycle::1 193710960 15.04% 48.07% # Number of insts issued each cycle 167system.cpu.iq.issued_per_cycle::2 207680071 16.13% 64.20% # Number of insts issued each cycle 168system.cpu.iq.issued_per_cycle::3 174651445 13.56% 77.76% # Number of insts issued each cycle 169system.cpu.iq.issued_per_cycle::4 137124890 10.65% 88.41% # Number of insts issued each cycle 170system.cpu.iq.issued_per_cycle::5 94993427 7.38% 95.78% # Number of insts issued each cycle 171system.cpu.iq.issued_per_cycle::6 35869114 2.79% 98.57% # Number of insts issued each cycle 172system.cpu.iq.issued_per_cycle::7 12687801 0.99% 99.55% # Number of insts issued each cycle 173system.cpu.iq.issued_per_cycle::8 5755454 0.45% 100.00% # Number of insts issued each cycle 174system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 175system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 176system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 177system.cpu.iq.issued_per_cycle::total 1287933807 # Number of insts issued each cycle 178system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 179system.cpu.iq.fu_full::IntAlu 692420 0.75% 0.75% # attempts to use FU when none available 180system.cpu.iq.fu_full::IntMult 24115 0.03% 0.78% # attempts to use FU when none available 181system.cpu.iq.fu_full::IntDiv 0 0.00% 0.78% # attempts to use FU when none available 182system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.78% # attempts to use FU when none available 183system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.78% # attempts to use FU when none available 184system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.78% # attempts to use FU when none available 185system.cpu.iq.fu_full::FloatMult 0 0.00% 0.78% # attempts to use FU when none available 186system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.78% # attempts to use FU when none available 187system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.78% # attempts to use FU when none available 188system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.78% # attempts to use FU when none available 189system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.78% # attempts to use FU when none available 190system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.78% # attempts to use FU when none available 191system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.78% # attempts to use FU when none available 192system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.78% # attempts to use FU when none available 193system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.78% # attempts to use FU when none available 194system.cpu.iq.fu_full::SimdMult 0 0.00% 0.78% # attempts to use FU when none available 195system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.78% # attempts to use FU when none available 196system.cpu.iq.fu_full::SimdShift 0 0.00% 0.78% # attempts to use FU when none available 197system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.78% # attempts to use FU when none available 198system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.78% # attempts to use FU when none available 199system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.78% # attempts to use FU when none available 200system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.78% # attempts to use FU when none available 201system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.78% # attempts to use FU when none available 202system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.78% # attempts to use FU when none available 203system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.78% # attempts to use FU when none available 204system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.78% # attempts to use FU when none available 205system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.78% # attempts to use FU when none available 206system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.78% # attempts to use FU when none available 207system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.78% # attempts to use FU when none available 208system.cpu.iq.fu_full::MemRead 56113360 61.04% 61.82% # attempts to use FU when none available 209system.cpu.iq.fu_full::MemWrite 35101326 38.18% 100.00% # attempts to use FU when none available 210system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 211system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 212system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 213system.cpu.iq.FU_type_0::IntAlu 1147061112 45.76% 45.76% # Type of FU issued 214system.cpu.iq.FU_type_0::IntMult 11228333 0.45% 46.21% # Type of FU issued 215system.cpu.iq.FU_type_0::IntDiv 0 0.00% 46.21% # Type of FU issued 216system.cpu.iq.FU_type_0::FloatAdd 1 0.00% 46.21% # Type of FU issued 217system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 46.21% # Type of FU issued 218system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 46.21% # Type of FU issued 219system.cpu.iq.FU_type_0::FloatMult 0 0.00% 46.21% # Type of FU issued 220system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 46.21% # Type of FU issued 221system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 46.21% # Type of FU issued 222system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 46.21% # Type of FU issued 223system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 46.21% # Type of FU issued 224system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 46.21% # Type of FU issued 225system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 46.21% # Type of FU issued 226system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 46.21% # Type of FU issued 227system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 46.21% # Type of FU issued 228system.cpu.iq.FU_type_0::SimdMult 0 0.00% 46.21% # Type of FU issued 229system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 46.21% # Type of FU issued 230system.cpu.iq.FU_type_0::SimdShift 0 0.00% 46.21% # Type of FU issued 231system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 46.21% # Type of FU issued 232system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 46.21% # Type of FU issued 233system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.05% 46.27% # Type of FU issued 234system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 46.27% # Type of FU issued 235system.cpu.iq.FU_type_0::SimdFloatCmp 6876483 0.27% 46.54% # Type of FU issued 236system.cpu.iq.FU_type_0::SimdFloatCvt 5512765 0.22% 46.76% # Type of FU issued 237system.cpu.iq.FU_type_0::SimdFloatDiv 16 0.00% 46.76% # Type of FU issued 238system.cpu.iq.FU_type_0::SimdFloatMisc 23755231 0.95% 47.71% # Type of FU issued 239system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.71% # Type of FU issued 240system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.71% # Type of FU issued 241system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.71% # Type of FU issued 242system.cpu.iq.FU_type_0::MemRead 846734490 33.78% 81.49% # Type of FU issued 243system.cpu.iq.FU_type_0::MemWrite 464021335 18.51% 100.00% # Type of FU issued 244system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 245system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 246system.cpu.iq.FU_type_0::total 2506565055 # Type of FU issued 247system.cpu.iq.rate 1.901089 # Inst issue rate 248system.cpu.iq.fu_busy_cnt 91931221 # FU busy when requested 249system.cpu.iq.fu_busy_rate 0.036676 # FU busy rate (busy events/executed inst) 250system.cpu.iq.int_inst_queue_reads 6281789129 # Number of integer instruction queue reads 251system.cpu.iq.int_inst_queue_writes 3788847878 # Number of integer instruction queue writes 252system.cpu.iq.int_inst_queue_wakeup_accesses 2312502456 # Number of integer instruction queue wakeup accesses 253system.cpu.iq.fp_inst_queue_reads 128440391 # Number of floating instruction queue reads 254system.cpu.iq.fp_inst_queue_writes 94088071 # Number of floating instruction queue writes 255system.cpu.iq.fp_inst_queue_wakeup_accesses 58648289 # Number of floating instruction queue wakeup accesses 256system.cpu.iq.int_alu_accesses 2531838073 # Number of integer alu accesses 257system.cpu.iq.fp_alu_accesses 66658203 # Number of floating point alu accesses 258system.cpu.iew.lsq.thread0.forwLoads 81288215 # Number of loads that had data forwarded from stores 259system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 260system.cpu.iew.lsq.thread0.squashedLoads 351270990 # Number of loads squashed 261system.cpu.iew.lsq.thread0.ignoredResponses 24451 # Number of memory responses ignored because the instruction is squashed 262system.cpu.iew.lsq.thread0.memOrderViolation 1405210 # Number of memory ordering violations 263system.cpu.iew.lsq.thread0.squashedStores 237848127 # Number of stores squashed 264system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 265system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 266system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled 267system.cpu.iew.lsq.thread0.cacheBlocked 13 # Number of times an access to memory failed due to the cache being blocked 268system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 269system.cpu.iew.iewSquashCycles 140618298 # Number of cycles IEW is squashing 270system.cpu.iew.iewBlockCycles 16819525 # Number of cycles IEW is blocking 271system.cpu.iew.iewUnblockCycles 1547443 # Number of cycles IEW is unblocking 272system.cpu.iew.iewDispatchedInsts 2890351322 # Number of instructions dispatched to IQ 273system.cpu.iew.iewDispSquashedInsts 8718298 # Number of squashed instructions skipped by dispatch 274system.cpu.iew.iewDispLoadInsts 982659180 # Number of dispatched load instructions 275system.cpu.iew.iewDispStoreInsts 514844433 # Number of dispatched store instructions 276system.cpu.iew.iewDispNonSpecInsts 22537 # Number of dispatched non-speculative instructions 277system.cpu.iew.iewIQFullEvents 1538114 # Number of times the IQ has become full, causing a stall 278system.cpu.iew.iewLSQFullEvents 1067 # Number of times the LSQ has become full, causing a stall 279system.cpu.iew.memOrderViolationEvents 1405210 # Number of memory order violations 280system.cpu.iew.predictedTakenIncorrect 36121914 # Number of branches that were predicted taken incorrectly 281system.cpu.iew.predictedNotTakenIncorrect 2298987 # Number of branches that were predicted not taken incorrectly 282system.cpu.iew.branchMispredicts 38420901 # Number of branch mispredicts detected at execute 283system.cpu.iew.iewExecutedInsts 2424696979 # Number of executed instructions 284system.cpu.iew.iewExecLoadInsts 800223206 # Number of load instructions executed 285system.cpu.iew.iewExecSquashedInsts 81868076 # Number of squashed instructions skipped in execute 286system.cpu.iew.exec_swp 0 # number of swp insts executed 287system.cpu.iew.exec_nop 14494 # number of nop insts executed 288system.cpu.iew.exec_refs 1240121255 # number of memory reference insts executed 289system.cpu.iew.exec_branches 334180264 # Number of branches executed 290system.cpu.iew.exec_stores 439898049 # Number of stores executed 291system.cpu.iew.exec_rate 1.838997 # Inst execution rate 292system.cpu.iew.wb_sent 2396725321 # cumulative count of insts sent to commit 293system.cpu.iew.wb_count 2371150745 # cumulative count of insts written-back 294system.cpu.iew.wb_producers 1368219909 # num instructions producing a value 295system.cpu.iew.wb_consumers 2564381587 # num instructions consuming a value 296system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 297system.cpu.iew.wb_rate 1.798385 # insts written-back per cycle 298system.cpu.iew.wb_fanout 0.533548 # average fanout of values written-back 299system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 300system.cpu.commit.commitSquashedInsts 1005010225 # The number of squashed insts skipped by commit 301system.cpu.commit.commitNonSpecStalls 22393 # The number of times commit has been forced to stall to communicate backwards 302system.cpu.commit.branchMispredicts 34087773 # The number of times a branch was mispredicted 303system.cpu.commit.committed_per_cycle::samples 1147315511 # Number of insts commited each cycle 304system.cpu.commit.committed_per_cycle::mean 1.643263 # Number of insts commited each cycle 305system.cpu.commit.committed_per_cycle::stdev 2.351044 # Number of insts commited each cycle 306system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 307system.cpu.commit.committed_per_cycle::0 497187613 43.33% 43.33% # Number of insts commited each cycle 308system.cpu.commit.committed_per_cycle::1 300050723 26.15% 69.49% # Number of insts commited each cycle 309system.cpu.commit.committed_per_cycle::2 93458742 8.15% 77.63% # Number of insts commited each cycle 310system.cpu.commit.committed_per_cycle::3 72384885 6.31% 83.94% # Number of insts commited each cycle 311system.cpu.commit.committed_per_cycle::4 45393865 3.96% 87.90% # Number of insts commited each cycle 312system.cpu.commit.committed_per_cycle::5 22818775 1.99% 89.89% # Number of insts commited each cycle 313system.cpu.commit.committed_per_cycle::6 15801520 1.38% 91.26% # Number of insts commited each cycle 314system.cpu.commit.committed_per_cycle::7 11015018 0.96% 92.22% # Number of insts commited each cycle 315system.cpu.commit.committed_per_cycle::8 89204370 7.78% 100.00% # Number of insts commited each cycle 316system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 317system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 318system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 319system.cpu.commit.committed_per_cycle::total 1147315511 # Number of insts commited each cycle 320system.cpu.commit.committedInsts 1384386651 # Number of instructions committed 321system.cpu.commit.committedOps 1885341403 # Number of ops (including micro ops) committed 322system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 323system.cpu.commit.refs 908384496 # Number of memory references committed 324system.cpu.commit.loads 631388190 # Number of loads committed 325system.cpu.commit.membars 9986 # Number of memory barriers committed 326system.cpu.commit.branches 299635404 # Number of branches committed 327system.cpu.commit.fp_insts 52289415 # Number of committed floating point instructions. 328system.cpu.commit.int_insts 1653702903 # Number of committed integer instructions. 329system.cpu.commit.function_calls 41577833 # Number of function calls committed. 330system.cpu.commit.bw_lim_events 89204370 # number cycles where commit BW limit reached 331system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 332system.cpu.rob.rob_reads 3948444424 # The number of ROB reads 333system.cpu.rob.rob_writes 5921335810 # The number of ROB writes 334system.cpu.timesIdled 1335770 # Number of times that the entire CPU went into an idle state and unscheduled itself 335system.cpu.idleCycles 30555124 # Total number of cycles that the CPU has spent unscheduled due to idling 336system.cpu.committedInsts 1384375635 # Number of Instructions Simulated 337system.cpu.committedOps 1885330387 # Number of Ops (including micro ops) Simulated 338system.cpu.committedInsts_total 1384375635 # Number of Instructions Simulated 339system.cpu.cpi 0.952407 # CPI: Cycles Per Instruction 340system.cpu.cpi_total 0.952407 # CPI: Total CPI of All Threads 341system.cpu.ipc 1.049971 # IPC: Instructions Per Cycle 342system.cpu.ipc_total 1.049971 # IPC: Total IPC of All Threads 343system.cpu.int_regfile_reads 12040516185 # number of integer regfile reads 344system.cpu.int_regfile_writes 2278755627 # number of integer regfile writes 345system.cpu.fp_regfile_reads 70304928 # number of floating regfile reads 346system.cpu.fp_regfile_writes 50983418 # number of floating regfile writes 347system.cpu.misc_regfile_reads 3755360027 # number of misc regfile reads 348system.cpu.misc_regfile_writes 13774920 # number of misc regfile writes 349system.cpu.icache.replacements 22971 # number of replacements 350system.cpu.icache.tagsinuse 1659.651348 # Cycle average of tags in use 351system.cpu.icache.total_refs 359526375 # Total number of references to valid blocks. 352system.cpu.icache.sampled_refs 24666 # Sample count of references to valid blocks. 353system.cpu.icache.avg_refs 14575.787521 # Average number of references to valid blocks. 354system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 355system.cpu.icache.occ_blocks::cpu.inst 1659.651348 # Average occupied blocks per requestor 356system.cpu.icache.occ_percent::cpu.inst 0.810377 # Average percentage of cache occupancy 357system.cpu.icache.occ_percent::total 0.810377 # Average percentage of cache occupancy 358system.cpu.icache.ReadReq_hits::cpu.inst 359530551 # number of ReadReq hits 359system.cpu.icache.ReadReq_hits::total 359530551 # number of ReadReq hits 360system.cpu.icache.demand_hits::cpu.inst 359530551 # number of demand (read+write) hits 361system.cpu.icache.demand_hits::total 359530551 # number of demand (read+write) hits 362system.cpu.icache.overall_hits::cpu.inst 359530551 # number of overall hits 363system.cpu.icache.overall_hits::total 359530551 # number of overall hits 364system.cpu.icache.ReadReq_misses::cpu.inst 29629 # number of ReadReq misses 365system.cpu.icache.ReadReq_misses::total 29629 # number of ReadReq misses 366system.cpu.icache.demand_misses::cpu.inst 29629 # number of demand (read+write) misses 367system.cpu.icache.demand_misses::total 29629 # number of demand (read+write) misses 368system.cpu.icache.overall_misses::cpu.inst 29629 # number of overall misses 369system.cpu.icache.overall_misses::total 29629 # number of overall misses 370system.cpu.icache.ReadReq_miss_latency::cpu.inst 243264500 # number of ReadReq miss cycles 371system.cpu.icache.ReadReq_miss_latency::total 243264500 # number of ReadReq miss cycles 372system.cpu.icache.demand_miss_latency::cpu.inst 243264500 # number of demand (read+write) miss cycles 373system.cpu.icache.demand_miss_latency::total 243264500 # number of demand (read+write) miss cycles 374system.cpu.icache.overall_miss_latency::cpu.inst 243264500 # number of overall miss cycles 375system.cpu.icache.overall_miss_latency::total 243264500 # number of overall miss cycles 376system.cpu.icache.ReadReq_accesses::cpu.inst 359560180 # number of ReadReq accesses(hits+misses) 377system.cpu.icache.ReadReq_accesses::total 359560180 # number of ReadReq accesses(hits+misses) 378system.cpu.icache.demand_accesses::cpu.inst 359560180 # number of demand (read+write) accesses 379system.cpu.icache.demand_accesses::total 359560180 # number of demand (read+write) accesses 380system.cpu.icache.overall_accesses::cpu.inst 359560180 # number of overall (read+write) accesses 381system.cpu.icache.overall_accesses::total 359560180 # number of overall (read+write) accesses 382system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000082 # miss rate for ReadReq accesses 383system.cpu.icache.ReadReq_miss_rate::total 0.000082 # miss rate for ReadReq accesses 384system.cpu.icache.demand_miss_rate::cpu.inst 0.000082 # miss rate for demand accesses 385system.cpu.icache.demand_miss_rate::total 0.000082 # miss rate for demand accesses 386system.cpu.icache.overall_miss_rate::cpu.inst 0.000082 # miss rate for overall accesses 387system.cpu.icache.overall_miss_rate::total 0.000082 # miss rate for overall accesses 388system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8210.351345 # average ReadReq miss latency 389system.cpu.icache.ReadReq_avg_miss_latency::total 8210.351345 # average ReadReq miss latency 390system.cpu.icache.demand_avg_miss_latency::cpu.inst 8210.351345 # average overall miss latency 391system.cpu.icache.demand_avg_miss_latency::total 8210.351345 # average overall miss latency 392system.cpu.icache.overall_avg_miss_latency::cpu.inst 8210.351345 # average overall miss latency 393system.cpu.icache.overall_avg_miss_latency::total 8210.351345 # average overall miss latency 394system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 395system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 396system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 397system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 398system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 399system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 400system.cpu.icache.fast_writes 0 # number of fast writes performed 401system.cpu.icache.cache_copies 0 # number of cache copies performed 402system.cpu.icache.ReadReq_mshr_hits::cpu.inst 731 # number of ReadReq MSHR hits 403system.cpu.icache.ReadReq_mshr_hits::total 731 # number of ReadReq MSHR hits 404system.cpu.icache.demand_mshr_hits::cpu.inst 731 # number of demand (read+write) MSHR hits 405system.cpu.icache.demand_mshr_hits::total 731 # number of demand (read+write) MSHR hits 406system.cpu.icache.overall_mshr_hits::cpu.inst 731 # number of overall MSHR hits 407system.cpu.icache.overall_mshr_hits::total 731 # number of overall MSHR hits 408system.cpu.icache.ReadReq_mshr_misses::cpu.inst 28898 # number of ReadReq MSHR misses 409system.cpu.icache.ReadReq_mshr_misses::total 28898 # number of ReadReq MSHR misses 410system.cpu.icache.demand_mshr_misses::cpu.inst 28898 # number of demand (read+write) MSHR misses 411system.cpu.icache.demand_mshr_misses::total 28898 # number of demand (read+write) MSHR misses 412system.cpu.icache.overall_mshr_misses::cpu.inst 28898 # number of overall MSHR misses 413system.cpu.icache.overall_mshr_misses::total 28898 # number of overall MSHR misses 414system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 166216000 # number of ReadReq MSHR miss cycles 415system.cpu.icache.ReadReq_mshr_miss_latency::total 166216000 # number of ReadReq MSHR miss cycles 416system.cpu.icache.demand_mshr_miss_latency::cpu.inst 166216000 # number of demand (read+write) MSHR miss cycles 417system.cpu.icache.demand_mshr_miss_latency::total 166216000 # number of demand (read+write) MSHR miss cycles 418system.cpu.icache.overall_mshr_miss_latency::cpu.inst 166216000 # number of overall MSHR miss cycles 419system.cpu.icache.overall_mshr_miss_latency::total 166216000 # number of overall MSHR miss cycles 420system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for ReadReq accesses 421system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000080 # mshr miss rate for ReadReq accesses 422system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for demand accesses 423system.cpu.icache.demand_mshr_miss_rate::total 0.000080 # mshr miss rate for demand accesses 424system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for overall accesses 425system.cpu.icache.overall_mshr_miss_rate::total 0.000080 # mshr miss rate for overall accesses 426system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 5751.816735 # average ReadReq mshr miss latency 427system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 5751.816735 # average ReadReq mshr miss latency 428system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 5751.816735 # average overall mshr miss latency 429system.cpu.icache.demand_avg_mshr_miss_latency::total 5751.816735 # average overall mshr miss latency 430system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 5751.816735 # average overall mshr miss latency 431system.cpu.icache.overall_avg_mshr_miss_latency::total 5751.816735 # average overall mshr miss latency 432system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 433system.cpu.dcache.replacements 1533081 # number of replacements 434system.cpu.dcache.tagsinuse 4094.855996 # Cycle average of tags in use 435system.cpu.dcache.total_refs 980345028 # Total number of references to valid blocks. 436system.cpu.dcache.sampled_refs 1537177 # Sample count of references to valid blocks. 437system.cpu.dcache.avg_refs 637.756763 # Average number of references to valid blocks. 438system.cpu.dcache.warmup_cycle 283497000 # Cycle when the warmup percentage was hit. 439system.cpu.dcache.occ_blocks::cpu.data 4094.855996 # Average occupied blocks per requestor 440system.cpu.dcache.occ_percent::cpu.data 0.999721 # Average percentage of cache occupancy 441system.cpu.dcache.occ_percent::total 0.999721 # Average percentage of cache occupancy 442system.cpu.dcache.ReadReq_hits::cpu.data 704193068 # number of ReadReq hits 443system.cpu.dcache.ReadReq_hits::total 704193068 # number of ReadReq hits 444system.cpu.dcache.WriteReq_hits::cpu.data 276118274 # number of WriteReq hits 445system.cpu.dcache.WriteReq_hits::total 276118274 # number of WriteReq hits 446system.cpu.dcache.LoadLockedReq_hits::cpu.data 11579 # number of LoadLockedReq hits 447system.cpu.dcache.LoadLockedReq_hits::total 11579 # number of LoadLockedReq hits 448system.cpu.dcache.StoreCondReq_hits::cpu.data 10994 # number of StoreCondReq hits 449system.cpu.dcache.StoreCondReq_hits::total 10994 # number of StoreCondReq hits 450system.cpu.dcache.demand_hits::cpu.data 980311342 # number of demand (read+write) hits 451system.cpu.dcache.demand_hits::total 980311342 # number of demand (read+write) hits 452system.cpu.dcache.overall_hits::cpu.data 980311342 # number of overall hits 453system.cpu.dcache.overall_hits::total 980311342 # number of overall hits 454system.cpu.dcache.ReadReq_misses::cpu.data 2282979 # number of ReadReq misses 455system.cpu.dcache.ReadReq_misses::total 2282979 # number of ReadReq misses 456system.cpu.dcache.WriteReq_misses::cpu.data 817404 # number of WriteReq misses 457system.cpu.dcache.WriteReq_misses::total 817404 # number of WriteReq misses 458system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses 459system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses 460system.cpu.dcache.demand_misses::cpu.data 3100383 # number of demand (read+write) misses 461system.cpu.dcache.demand_misses::total 3100383 # number of demand (read+write) misses 462system.cpu.dcache.overall_misses::cpu.data 3100383 # number of overall misses 463system.cpu.dcache.overall_misses::total 3100383 # number of overall misses 464system.cpu.dcache.ReadReq_miss_latency::cpu.data 77215847500 # number of ReadReq miss cycles 465system.cpu.dcache.ReadReq_miss_latency::total 77215847500 # number of ReadReq miss cycles 466system.cpu.dcache.WriteReq_miss_latency::cpu.data 27888772000 # number of WriteReq miss cycles 467system.cpu.dcache.WriteReq_miss_latency::total 27888772000 # number of WriteReq miss cycles 468system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 130500 # number of LoadLockedReq miss cycles 469system.cpu.dcache.LoadLockedReq_miss_latency::total 130500 # number of LoadLockedReq miss cycles 470system.cpu.dcache.demand_miss_latency::cpu.data 105104619500 # number of demand (read+write) miss cycles 471system.cpu.dcache.demand_miss_latency::total 105104619500 # number of demand (read+write) miss cycles 472system.cpu.dcache.overall_miss_latency::cpu.data 105104619500 # number of overall miss cycles 473system.cpu.dcache.overall_miss_latency::total 105104619500 # number of overall miss cycles 474system.cpu.dcache.ReadReq_accesses::cpu.data 706476047 # number of ReadReq accesses(hits+misses) 475system.cpu.dcache.ReadReq_accesses::total 706476047 # number of ReadReq accesses(hits+misses) 476system.cpu.dcache.WriteReq_accesses::cpu.data 276935678 # number of WriteReq accesses(hits+misses) 477system.cpu.dcache.WriteReq_accesses::total 276935678 # number of WriteReq accesses(hits+misses) 478system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11582 # number of LoadLockedReq accesses(hits+misses) 479system.cpu.dcache.LoadLockedReq_accesses::total 11582 # number of LoadLockedReq accesses(hits+misses) 480system.cpu.dcache.StoreCondReq_accesses::cpu.data 10994 # number of StoreCondReq accesses(hits+misses) 481system.cpu.dcache.StoreCondReq_accesses::total 10994 # number of StoreCondReq accesses(hits+misses) 482system.cpu.dcache.demand_accesses::cpu.data 983411725 # number of demand (read+write) accesses 483system.cpu.dcache.demand_accesses::total 983411725 # number of demand (read+write) accesses 484system.cpu.dcache.overall_accesses::cpu.data 983411725 # number of overall (read+write) accesses 485system.cpu.dcache.overall_accesses::total 983411725 # number of overall (read+write) accesses 486system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003232 # miss rate for ReadReq accesses 487system.cpu.dcache.ReadReq_miss_rate::total 0.003232 # miss rate for ReadReq accesses 488system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002952 # miss rate for WriteReq accesses 489system.cpu.dcache.WriteReq_miss_rate::total 0.002952 # miss rate for WriteReq accesses 490system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000259 # miss rate for LoadLockedReq accesses 491system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000259 # miss rate for LoadLockedReq accesses 492system.cpu.dcache.demand_miss_rate::cpu.data 0.003153 # miss rate for demand accesses 493system.cpu.dcache.demand_miss_rate::total 0.003153 # miss rate for demand accesses 494system.cpu.dcache.overall_miss_rate::cpu.data 0.003153 # miss rate for overall accesses 495system.cpu.dcache.overall_miss_rate::total 0.003153 # miss rate for overall accesses 496system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 33822.408134 # average ReadReq miss latency 497system.cpu.dcache.ReadReq_avg_miss_latency::total 33822.408134 # average ReadReq miss latency 498system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34118.712411 # average WriteReq miss latency 499system.cpu.dcache.WriteReq_avg_miss_latency::total 34118.712411 # average WriteReq miss latency 500system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 43500 # average LoadLockedReq miss latency 501system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 43500 # average LoadLockedReq miss latency 502system.cpu.dcache.demand_avg_miss_latency::cpu.data 33900.527612 # average overall miss latency 503system.cpu.dcache.demand_avg_miss_latency::total 33900.527612 # average overall miss latency 504system.cpu.dcache.overall_avg_miss_latency::cpu.data 33900.527612 # average overall miss latency 505system.cpu.dcache.overall_avg_miss_latency::total 33900.527612 # average overall miss latency 506system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 507system.cpu.dcache.blocked_cycles::no_targets 52500 # number of cycles access was blocked 508system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 509system.cpu.dcache.blocked::no_targets 3 # number of cycles access was blocked 510system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 511system.cpu.dcache.avg_blocked_cycles::no_targets 17500 # average number of cycles each access was blocked 512system.cpu.dcache.fast_writes 0 # number of fast writes performed 513system.cpu.dcache.cache_copies 0 # number of cache copies performed 514system.cpu.dcache.writebacks::writebacks 108430 # number of writebacks 515system.cpu.dcache.writebacks::total 108430 # number of writebacks 516system.cpu.dcache.ReadReq_mshr_hits::cpu.data 818362 # number of ReadReq MSHR hits 517system.cpu.dcache.ReadReq_mshr_hits::total 818362 # number of ReadReq MSHR hits 518system.cpu.dcache.WriteReq_mshr_hits::cpu.data 740610 # number of WriteReq MSHR hits 519system.cpu.dcache.WriteReq_mshr_hits::total 740610 # number of WriteReq MSHR hits 520system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits 521system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits 522system.cpu.dcache.demand_mshr_hits::cpu.data 1558972 # number of demand (read+write) MSHR hits 523system.cpu.dcache.demand_mshr_hits::total 1558972 # number of demand (read+write) MSHR hits 524system.cpu.dcache.overall_mshr_hits::cpu.data 1558972 # number of overall MSHR hits 525system.cpu.dcache.overall_mshr_hits::total 1558972 # number of overall MSHR hits 526system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1464617 # number of ReadReq MSHR misses 527system.cpu.dcache.ReadReq_mshr_misses::total 1464617 # number of ReadReq MSHR misses 528system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76794 # number of WriteReq MSHR misses 529system.cpu.dcache.WriteReq_mshr_misses::total 76794 # number of WriteReq MSHR misses 530system.cpu.dcache.demand_mshr_misses::cpu.data 1541411 # number of demand (read+write) MSHR misses 531system.cpu.dcache.demand_mshr_misses::total 1541411 # number of demand (read+write) MSHR misses 532system.cpu.dcache.overall_mshr_misses::cpu.data 1541411 # number of overall MSHR misses 533system.cpu.dcache.overall_mshr_misses::total 1541411 # number of overall MSHR misses 534system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 50261586500 # number of ReadReq MSHR miss cycles 535system.cpu.dcache.ReadReq_mshr_miss_latency::total 50261586500 # number of ReadReq MSHR miss cycles 536system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2476957500 # number of WriteReq MSHR miss cycles 537system.cpu.dcache.WriteReq_mshr_miss_latency::total 2476957500 # number of WriteReq MSHR miss cycles 538system.cpu.dcache.demand_mshr_miss_latency::cpu.data 52738544000 # number of demand (read+write) MSHR miss cycles 539system.cpu.dcache.demand_mshr_miss_latency::total 52738544000 # number of demand (read+write) MSHR miss cycles 540system.cpu.dcache.overall_mshr_miss_latency::cpu.data 52738544000 # number of overall MSHR miss cycles 541system.cpu.dcache.overall_mshr_miss_latency::total 52738544000 # number of overall MSHR miss cycles 542system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002073 # mshr miss rate for ReadReq accesses 543system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002073 # mshr miss rate for ReadReq accesses 544system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000277 # mshr miss rate for WriteReq accesses 545system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000277 # mshr miss rate for WriteReq accesses 546system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001567 # mshr miss rate for demand accesses 547system.cpu.dcache.demand_mshr_miss_rate::total 0.001567 # mshr miss rate for demand accesses 548system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001567 # mshr miss rate for overall accesses 549system.cpu.dcache.overall_mshr_miss_rate::total 0.001567 # mshr miss rate for overall accesses 550system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34317.221840 # average ReadReq mshr miss latency 551system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34317.221840 # average ReadReq mshr miss latency 552system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32254.570670 # average WriteReq mshr miss latency 553system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32254.570670 # average WriteReq mshr miss latency 554system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34214.459349 # average overall mshr miss latency 555system.cpu.dcache.demand_avg_mshr_miss_latency::total 34214.459349 # average overall mshr miss latency 556system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34214.459349 # average overall mshr miss latency 557system.cpu.dcache.overall_avg_mshr_miss_latency::total 34214.459349 # average overall mshr miss latency 558system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 559system.cpu.l2cache.replacements 1480118 # number of replacements 560system.cpu.l2cache.tagsinuse 32698.465426 # Cycle average of tags in use 561system.cpu.l2cache.total_refs 83907 # Total number of references to valid blocks. 562system.cpu.l2cache.sampled_refs 1512862 # Sample count of references to valid blocks. 563system.cpu.l2cache.avg_refs 0.055462 # Average number of references to valid blocks. 564system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 565system.cpu.l2cache.occ_blocks::writebacks 3079.828905 # Average occupied blocks per requestor 566system.cpu.l2cache.occ_blocks::cpu.inst 55.596030 # Average occupied blocks per requestor 567system.cpu.l2cache.occ_blocks::cpu.data 29563.040491 # Average occupied blocks per requestor 568system.cpu.l2cache.occ_percent::writebacks 0.093989 # Average percentage of cache occupancy 569system.cpu.l2cache.occ_percent::cpu.inst 0.001697 # Average percentage of cache occupancy 570system.cpu.l2cache.occ_percent::cpu.data 0.902192 # Average percentage of cache occupancy 571system.cpu.l2cache.occ_percent::total 0.997878 # Average percentage of cache occupancy 572system.cpu.l2cache.ReadReq_hits::cpu.inst 21536 # number of ReadReq hits 573system.cpu.l2cache.ReadReq_hits::cpu.data 53875 # number of ReadReq hits 574system.cpu.l2cache.ReadReq_hits::total 75411 # number of ReadReq hits 575system.cpu.l2cache.Writeback_hits::writebacks 108430 # number of Writeback hits 576system.cpu.l2cache.Writeback_hits::total 108430 # number of Writeback hits 577system.cpu.l2cache.UpgradeReq_hits::cpu.data 3 # number of UpgradeReq hits 578system.cpu.l2cache.UpgradeReq_hits::total 3 # number of UpgradeReq hits 579system.cpu.l2cache.ReadExReq_hits::cpu.data 6481 # number of ReadExReq hits 580system.cpu.l2cache.ReadExReq_hits::total 6481 # number of ReadExReq hits 581system.cpu.l2cache.demand_hits::cpu.inst 21536 # number of demand (read+write) hits 582system.cpu.l2cache.demand_hits::cpu.data 60356 # number of demand (read+write) hits 583system.cpu.l2cache.demand_hits::total 81892 # number of demand (read+write) hits 584system.cpu.l2cache.overall_hits::cpu.inst 21536 # number of overall hits 585system.cpu.l2cache.overall_hits::cpu.data 60356 # number of overall hits 586system.cpu.l2cache.overall_hits::total 81892 # number of overall hits 587system.cpu.l2cache.ReadReq_misses::cpu.inst 3130 # number of ReadReq misses 588system.cpu.l2cache.ReadReq_misses::cpu.data 1410741 # number of ReadReq misses 589system.cpu.l2cache.ReadReq_misses::total 1413871 # number of ReadReq misses 590system.cpu.l2cache.UpgradeReq_misses::cpu.data 4230 # number of UpgradeReq misses 591system.cpu.l2cache.UpgradeReq_misses::total 4230 # number of UpgradeReq misses 592system.cpu.l2cache.ReadExReq_misses::cpu.data 66081 # number of ReadExReq misses 593system.cpu.l2cache.ReadExReq_misses::total 66081 # number of ReadExReq misses 594system.cpu.l2cache.demand_misses::cpu.inst 3130 # number of demand (read+write) misses 595system.cpu.l2cache.demand_misses::cpu.data 1476822 # number of demand (read+write) misses 596system.cpu.l2cache.demand_misses::total 1479952 # number of demand (read+write) misses 597system.cpu.l2cache.overall_misses::cpu.inst 3130 # number of overall misses 598system.cpu.l2cache.overall_misses::cpu.data 1476822 # number of overall misses 599system.cpu.l2cache.overall_misses::total 1479952 # number of overall misses 600system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 111250000 # number of ReadReq miss cycles 601system.cpu.l2cache.ReadReq_miss_latency::cpu.data 48742266500 # number of ReadReq miss cycles 602system.cpu.l2cache.ReadReq_miss_latency::total 48853516500 # number of ReadReq miss cycles 603system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2253271500 # number of ReadExReq miss cycles 604system.cpu.l2cache.ReadExReq_miss_latency::total 2253271500 # number of ReadExReq miss cycles 605system.cpu.l2cache.demand_miss_latency::cpu.inst 111250000 # number of demand (read+write) miss cycles 606system.cpu.l2cache.demand_miss_latency::cpu.data 50995538000 # number of demand (read+write) miss cycles 607system.cpu.l2cache.demand_miss_latency::total 51106788000 # number of demand (read+write) miss cycles 608system.cpu.l2cache.overall_miss_latency::cpu.inst 111250000 # number of overall miss cycles 609system.cpu.l2cache.overall_miss_latency::cpu.data 50995538000 # number of overall miss cycles 610system.cpu.l2cache.overall_miss_latency::total 51106788000 # number of overall miss cycles 611system.cpu.l2cache.ReadReq_accesses::cpu.inst 24666 # number of ReadReq accesses(hits+misses) 612system.cpu.l2cache.ReadReq_accesses::cpu.data 1464616 # number of ReadReq accesses(hits+misses) 613system.cpu.l2cache.ReadReq_accesses::total 1489282 # number of ReadReq accesses(hits+misses) 614system.cpu.l2cache.Writeback_accesses::writebacks 108430 # number of Writeback accesses(hits+misses) 615system.cpu.l2cache.Writeback_accesses::total 108430 # number of Writeback accesses(hits+misses) 616system.cpu.l2cache.UpgradeReq_accesses::cpu.data 4233 # number of UpgradeReq accesses(hits+misses) 617system.cpu.l2cache.UpgradeReq_accesses::total 4233 # number of UpgradeReq accesses(hits+misses) 618system.cpu.l2cache.ReadExReq_accesses::cpu.data 72562 # number of ReadExReq accesses(hits+misses) 619system.cpu.l2cache.ReadExReq_accesses::total 72562 # number of ReadExReq accesses(hits+misses) 620system.cpu.l2cache.demand_accesses::cpu.inst 24666 # number of demand (read+write) accesses 621system.cpu.l2cache.demand_accesses::cpu.data 1537178 # number of demand (read+write) accesses 622system.cpu.l2cache.demand_accesses::total 1561844 # number of demand (read+write) accesses 623system.cpu.l2cache.overall_accesses::cpu.inst 24666 # number of overall (read+write) accesses 624system.cpu.l2cache.overall_accesses::cpu.data 1537178 # number of overall (read+write) accesses 625system.cpu.l2cache.overall_accesses::total 1561844 # number of overall (read+write) accesses 626system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.126895 # miss rate for ReadReq accesses 627system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.963216 # miss rate for ReadReq accesses 628system.cpu.l2cache.ReadReq_miss_rate::total 0.949364 # miss rate for ReadReq accesses 629system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.999291 # miss rate for UpgradeReq accesses 630system.cpu.l2cache.UpgradeReq_miss_rate::total 0.999291 # miss rate for UpgradeReq accesses 631system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.910683 # miss rate for ReadExReq accesses 632system.cpu.l2cache.ReadExReq_miss_rate::total 0.910683 # miss rate for ReadExReq accesses 633system.cpu.l2cache.demand_miss_rate::cpu.inst 0.126895 # miss rate for demand accesses 634system.cpu.l2cache.demand_miss_rate::cpu.data 0.960736 # miss rate for demand accesses 635system.cpu.l2cache.demand_miss_rate::total 0.947567 # miss rate for demand accesses 636system.cpu.l2cache.overall_miss_rate::cpu.inst 0.126895 # miss rate for overall accesses 637system.cpu.l2cache.overall_miss_rate::cpu.data 0.960736 # miss rate for overall accesses 638system.cpu.l2cache.overall_miss_rate::total 0.947567 # miss rate for overall accesses 639system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35543.130990 # average ReadReq miss latency 640system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34550.825772 # average ReadReq miss latency 641system.cpu.l2cache.ReadReq_avg_miss_latency::total 34553.022518 # average ReadReq miss latency 642system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34098.628955 # average ReadExReq miss latency 643system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34098.628955 # average ReadExReq miss latency 644system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35543.130990 # average overall miss latency 645system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34530.592042 # average overall miss latency 646system.cpu.l2cache.demand_avg_miss_latency::total 34532.733494 # average overall miss latency 647system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35543.130990 # average overall miss latency 648system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34530.592042 # average overall miss latency 649system.cpu.l2cache.overall_avg_miss_latency::total 34532.733494 # average overall miss latency 650system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 651system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 652system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 653system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 654system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 655system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 656system.cpu.l2cache.fast_writes 0 # number of fast writes performed 657system.cpu.l2cache.cache_copies 0 # number of cache copies performed 658system.cpu.l2cache.writebacks::writebacks 66099 # number of writebacks 659system.cpu.l2cache.writebacks::total 66099 # number of writebacks 660system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 11 # number of ReadReq MSHR hits 661system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 22 # number of ReadReq MSHR hits 662system.cpu.l2cache.ReadReq_mshr_hits::total 33 # number of ReadReq MSHR hits 663system.cpu.l2cache.demand_mshr_hits::cpu.inst 11 # number of demand (read+write) MSHR hits 664system.cpu.l2cache.demand_mshr_hits::cpu.data 22 # number of demand (read+write) MSHR hits 665system.cpu.l2cache.demand_mshr_hits::total 33 # number of demand (read+write) MSHR hits 666system.cpu.l2cache.overall_mshr_hits::cpu.inst 11 # number of overall MSHR hits 667system.cpu.l2cache.overall_mshr_hits::cpu.data 22 # number of overall MSHR hits 668system.cpu.l2cache.overall_mshr_hits::total 33 # number of overall MSHR hits 669system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3119 # number of ReadReq MSHR misses 670system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1410719 # number of ReadReq MSHR misses 671system.cpu.l2cache.ReadReq_mshr_misses::total 1413838 # number of ReadReq MSHR misses 672system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 4230 # number of UpgradeReq MSHR misses 673system.cpu.l2cache.UpgradeReq_mshr_misses::total 4230 # number of UpgradeReq MSHR misses 674system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66081 # number of ReadExReq MSHR misses 675system.cpu.l2cache.ReadExReq_mshr_misses::total 66081 # number of ReadExReq MSHR misses 676system.cpu.l2cache.demand_mshr_misses::cpu.inst 3119 # number of demand (read+write) MSHR misses 677system.cpu.l2cache.demand_mshr_misses::cpu.data 1476800 # number of demand (read+write) MSHR misses 678system.cpu.l2cache.demand_mshr_misses::total 1479919 # number of demand (read+write) MSHR misses 679system.cpu.l2cache.overall_mshr_misses::cpu.inst 3119 # number of overall MSHR misses 680system.cpu.l2cache.overall_mshr_misses::cpu.data 1476800 # number of overall MSHR misses 681system.cpu.l2cache.overall_mshr_misses::total 1479919 # number of overall MSHR misses 682system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 101115000 # number of ReadReq MSHR miss cycles 683system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 44173599500 # number of ReadReq MSHR miss cycles 684system.cpu.l2cache.ReadReq_mshr_miss_latency::total 44274714500 # number of ReadReq MSHR miss cycles 685system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 131130000 # number of UpgradeReq MSHR miss cycles 686system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 131130000 # number of UpgradeReq MSHR miss cycles 687system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2049298500 # number of ReadExReq MSHR miss cycles 688system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2049298500 # number of ReadExReq MSHR miss cycles 689system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 101115000 # number of demand (read+write) MSHR miss cycles 690system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 46222898000 # number of demand (read+write) MSHR miss cycles 691system.cpu.l2cache.demand_mshr_miss_latency::total 46324013000 # number of demand (read+write) MSHR miss cycles 692system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 101115000 # number of overall MSHR miss cycles 693system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 46222898000 # number of overall MSHR miss cycles 694system.cpu.l2cache.overall_mshr_miss_latency::total 46324013000 # number of overall MSHR miss cycles 695system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.126449 # mshr miss rate for ReadReq accesses 696system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.963201 # mshr miss rate for ReadReq accesses 697system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.949342 # mshr miss rate for ReadReq accesses 698system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.999291 # mshr miss rate for UpgradeReq accesses 699system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.999291 # mshr miss rate for UpgradeReq accesses 700system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.910683 # mshr miss rate for ReadExReq accesses 701system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.910683 # mshr miss rate for ReadExReq accesses 702system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.126449 # mshr miss rate for demand accesses 703system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.960722 # mshr miss rate for demand accesses 704system.cpu.l2cache.demand_mshr_miss_rate::total 0.947546 # mshr miss rate for demand accesses 705system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.126449 # mshr miss rate for overall accesses 706system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.960722 # mshr miss rate for overall accesses 707system.cpu.l2cache.overall_mshr_miss_rate::total 0.947546 # mshr miss rate for overall accesses 708system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32419.044566 # average ReadReq mshr miss latency 709system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31312.826651 # average ReadReq mshr miss latency 710system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31315.267025 # average ReadReq mshr miss latency 711system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31000 # average UpgradeReq mshr miss latency 712system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31000 # average UpgradeReq mshr miss latency 713system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31011.917193 # average ReadExReq mshr miss latency 714system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31011.917193 # average ReadExReq mshr miss latency 715system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32419.044566 # average overall mshr miss latency 716system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31299.362134 # average overall mshr miss latency 717system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31301.721919 # average overall mshr miss latency 718system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32419.044566 # average overall mshr miss latency 719system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31299.362134 # average overall mshr miss latency 720system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31301.721919 # average overall mshr miss latency 721system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 722 723---------- End Simulation Statistics ---------- 724