stats.txt revision 8911:4da2ea94319f
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.735495 # Number of seconds simulated 4sim_ticks 735495062500 # Number of ticks simulated 5final_tick 735495062500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 126424 # Simulator instruction rate (inst/s) 8host_op_rate 172171 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 67166483 # Simulator tick rate (ticks/s) 10host_mem_usage 230552 # Number of bytes of host memory used 11host_seconds 10950.33 # Real time elapsed on the host 12sim_insts 1384379503 # Number of instructions simulated 13sim_ops 1885334256 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read 94839680 # Number of bytes read from this memory 15system.physmem.bytes_inst_read 213952 # Number of instructions bytes read from this memory 16system.physmem.bytes_written 4230336 # Number of bytes written to this memory 17system.physmem.num_reads 1481870 # Number of read requests responded to by this memory 18system.physmem.num_writes 66099 # Number of write requests responded to by this memory 19system.physmem.num_other 0 # Number of other requests responded to by this memory 20system.physmem.bw_read 128946726 # Total read bandwidth from this memory (bytes/s) 21system.physmem.bw_inst_read 290895 # Instruction read bandwidth from this memory (bytes/s) 22system.physmem.bw_write 5751685 # Write bandwidth from this memory (bytes/s) 23system.physmem.bw_total 134698411 # Total bandwidth to/from this memory (bytes/s) 24system.cpu.dtb.inst_hits 0 # ITB inst hits 25system.cpu.dtb.inst_misses 0 # ITB inst misses 26system.cpu.dtb.read_hits 0 # DTB read hits 27system.cpu.dtb.read_misses 0 # DTB read misses 28system.cpu.dtb.write_hits 0 # DTB write hits 29system.cpu.dtb.write_misses 0 # DTB write misses 30system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 31system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 32system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 33system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 34system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 35system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 36system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 37system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 38system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 39system.cpu.dtb.read_accesses 0 # DTB read accesses 40system.cpu.dtb.write_accesses 0 # DTB write accesses 41system.cpu.dtb.inst_accesses 0 # ITB inst accesses 42system.cpu.dtb.hits 0 # DTB hits 43system.cpu.dtb.misses 0 # DTB misses 44system.cpu.dtb.accesses 0 # DTB accesses 45system.cpu.itb.inst_hits 0 # ITB inst hits 46system.cpu.itb.inst_misses 0 # ITB inst misses 47system.cpu.itb.read_hits 0 # DTB read hits 48system.cpu.itb.read_misses 0 # DTB read misses 49system.cpu.itb.write_hits 0 # DTB write hits 50system.cpu.itb.write_misses 0 # DTB write misses 51system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 52system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 53system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 54system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 55system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 56system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 57system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 58system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 59system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 60system.cpu.itb.read_accesses 0 # DTB read accesses 61system.cpu.itb.write_accesses 0 # DTB write accesses 62system.cpu.itb.inst_accesses 0 # ITB inst accesses 63system.cpu.itb.hits 0 # DTB hits 64system.cpu.itb.misses 0 # DTB misses 65system.cpu.itb.accesses 0 # DTB accesses 66system.cpu.workload.num_syscalls 1411 # Number of system calls 67system.cpu.numCycles 1470990126 # number of cpu cycles simulated 68system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 69system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 70system.cpu.BPredUnit.lookups 524657246 # Number of BP lookups 71system.cpu.BPredUnit.condPredicted 401089358 # Number of conditional branches predicted 72system.cpu.BPredUnit.condIncorrect 35661760 # Number of conditional branches incorrect 73system.cpu.BPredUnit.BTBLookups 339540356 # Number of BTB lookups 74system.cpu.BPredUnit.BTBHits 278948773 # Number of BTB hits 75system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 76system.cpu.BPredUnit.usedRAS 59722038 # Number of times the RAS was used to get a target. 77system.cpu.BPredUnit.RASInCorrect 2842670 # Number of incorrect RAS predictions. 78system.cpu.fetch.icacheStallCycles 444619593 # Number of cycles fetch is stalled on an Icache miss 79system.cpu.fetch.Insts 2613573524 # Number of instructions fetch has processed 80system.cpu.fetch.Branches 524657246 # Number of branches that fetch encountered 81system.cpu.fetch.predictedBranches 338670811 # Number of branches that fetch has predicted taken 82system.cpu.fetch.Cycles 712273911 # Number of cycles fetch has run and was not squashing or blocked 83system.cpu.fetch.SquashCycles 223851331 # Number of cycles fetch has spent squashing 84system.cpu.fetch.BlockedCycles 98512911 # Number of cycles fetch has spent blocked 85system.cpu.fetch.MiscStallCycles 2271 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 86system.cpu.fetch.PendingTrapStallCycles 29657 # Number of stall cycles due to pending traps 87system.cpu.fetch.CacheLines 414743940 # Number of cache lines fetched 88system.cpu.fetch.IcacheSquashes 11577936 # Number of outstanding Icache misses that were squashed 89system.cpu.fetch.rateDist::samples 1438039773 # Number of instructions fetched each cycle (Total) 90system.cpu.fetch.rateDist::mean 2.556437 # Number of instructions fetched each cycle (Total) 91system.cpu.fetch.rateDist::stdev 3.167543 # Number of instructions fetched each cycle (Total) 92system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 93system.cpu.fetch.rateDist::0 725823899 50.47% 50.47% # Number of instructions fetched each cycle (Total) 94system.cpu.fetch.rateDist::1 56807029 3.95% 54.42% # Number of instructions fetched each cycle (Total) 95system.cpu.fetch.rateDist::2 112550044 7.83% 62.25% # Number of instructions fetched each cycle (Total) 96system.cpu.fetch.rateDist::3 69779758 4.85% 67.10% # Number of instructions fetched each cycle (Total) 97system.cpu.fetch.rateDist::4 84813159 5.90% 73.00% # Number of instructions fetched each cycle (Total) 98system.cpu.fetch.rateDist::5 53785792 3.74% 76.74% # Number of instructions fetched each cycle (Total) 99system.cpu.fetch.rateDist::6 34099274 2.37% 79.11% # Number of instructions fetched each cycle (Total) 100system.cpu.fetch.rateDist::7 30811930 2.14% 81.25% # Number of instructions fetched each cycle (Total) 101system.cpu.fetch.rateDist::8 269568888 18.75% 100.00% # Number of instructions fetched each cycle (Total) 102system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 103system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 104system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 105system.cpu.fetch.rateDist::total 1438039773 # Number of instructions fetched each cycle (Total) 106system.cpu.fetch.branchRate 0.356669 # Number of branch fetches per cycle 107system.cpu.fetch.rate 1.776744 # Number of inst fetches per cycle 108system.cpu.decode.IdleCycles 492128614 # Number of cycles decode is idle 109system.cpu.decode.BlockedCycles 78582078 # Number of cycles decode is blocked 110system.cpu.decode.RunCycles 673411779 # Number of cycles decode is running 111system.cpu.decode.UnblockCycles 11338206 # Number of cycles decode is unblocking 112system.cpu.decode.SquashCycles 182579096 # Number of cycles decode is squashing 113system.cpu.decode.BranchResolved 79653725 # Number of times decode resolved a branch 114system.cpu.decode.BranchMispred 23825 # Number of times decode detected a branch misprediction 115system.cpu.decode.DecodedInsts 3539524175 # Number of instructions handled by decode 116system.cpu.decode.SquashedInsts 54394 # Number of squashed instructions handled by decode 117system.cpu.rename.SquashCycles 182579096 # Number of cycles rename is squashing 118system.cpu.rename.IdleCycles 529782652 # Number of cycles rename is idle 119system.cpu.rename.BlockCycles 30198632 # Number of cycles rename is blocking 120system.cpu.rename.serializeStallCycles 660985 # count of cycles rename stalled for serializing inst 121system.cpu.rename.RunCycles 645094382 # Number of cycles rename is running 122system.cpu.rename.UnblockCycles 49724026 # Number of cycles rename is unblocking 123system.cpu.rename.RenamedInsts 3431194053 # Number of instructions processed by rename 124system.cpu.rename.ROBFullEvents 133 # Number of times rename has blocked due to ROB full 125system.cpu.rename.IQFullEvents 4188042 # Number of times rename has blocked due to IQ full 126system.cpu.rename.LSQFullEvents 40587721 # Number of times rename has blocked due to LSQ full 127system.cpu.rename.FullRegisterEvents 1707 # Number of times there has been no free registers 128system.cpu.rename.RenamedOperands 3342681891 # Number of destination operands rename has renamed 129system.cpu.rename.RenameLookups 16249059655 # Number of register rename lookups that rename has made 130system.cpu.rename.int_rename_lookups 15604311677 # Number of integer rename lookups 131system.cpu.rename.fp_rename_lookups 644747978 # Number of floating rename lookups 132system.cpu.rename.CommittedMaps 1993154351 # Number of HB maps that are committed 133system.cpu.rename.UndoneMaps 1349527540 # Number of HB maps that are undone due to squashing 134system.cpu.rename.serializingInsts 64268 # count of serializing insts renamed 135system.cpu.rename.tempSerializingInsts 59597 # count of temporary serializing insts renamed 136system.cpu.rename.skidInsts 138053548 # count of insts added to the skid buffer 137system.cpu.memDep0.insertedLoads 1061160981 # Number of loads inserted to the mem dependence unit. 138system.cpu.memDep0.insertedStores 575711799 # Number of stores inserted to the mem dependence unit. 139system.cpu.memDep0.conflictingLoads 34121400 # Number of conflicting loads. 140system.cpu.memDep0.conflictingStores 39206197 # Number of conflicting stores. 141system.cpu.iq.iqInstsAdded 3192585936 # Number of instructions added to the IQ (excludes non-spec) 142system.cpu.iq.iqNonSpecInstsAdded 69047 # Number of non-speculative instructions added to the IQ 143system.cpu.iq.iqInstsIssued 2718019401 # Number of instructions issued 144system.cpu.iq.iqSquashedInstsIssued 27726721 # Number of squashed instructions issued 145system.cpu.iq.iqSquashedInstsExamined 1306902480 # Number of squashed instructions iterated over during squash; mainly for profiling 146system.cpu.iq.iqSquashedOperandsExamined 3048220381 # Number of squashed operands that are examined and possibly removed from graph 147system.cpu.iq.iqSquashedNonSpecRemoved 45882 # Number of squashed non-spec instructions that were removed 148system.cpu.iq.issued_per_cycle::samples 1438039773 # Number of insts issued each cycle 149system.cpu.iq.issued_per_cycle::mean 1.890086 # Number of insts issued each cycle 150system.cpu.iq.issued_per_cycle::stdev 1.916332 # Number of insts issued each cycle 151system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 152system.cpu.iq.issued_per_cycle::0 521512118 36.27% 36.27% # Number of insts issued each cycle 153system.cpu.iq.issued_per_cycle::1 198246164 13.79% 50.05% # Number of insts issued each cycle 154system.cpu.iq.issued_per_cycle::2 216916723 15.08% 65.14% # Number of insts issued each cycle 155system.cpu.iq.issued_per_cycle::3 178677193 12.43% 77.56% # Number of insts issued each cycle 156system.cpu.iq.issued_per_cycle::4 155355732 10.80% 88.36% # Number of insts issued each cycle 157system.cpu.iq.issued_per_cycle::5 100852221 7.01% 95.38% # Number of insts issued each cycle 158system.cpu.iq.issued_per_cycle::6 48369591 3.36% 98.74% # Number of insts issued each cycle 159system.cpu.iq.issued_per_cycle::7 10873615 0.76% 99.50% # Number of insts issued each cycle 160system.cpu.iq.issued_per_cycle::8 7236416 0.50% 100.00% # Number of insts issued each cycle 161system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 162system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 163system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 164system.cpu.iq.issued_per_cycle::total 1438039773 # Number of insts issued each cycle 165system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 166system.cpu.iq.fu_full::IntAlu 1743579 1.83% 1.83% # attempts to use FU when none available 167system.cpu.iq.fu_full::IntMult 23896 0.03% 1.85% # attempts to use FU when none available 168system.cpu.iq.fu_full::IntDiv 0 0.00% 1.85% # attempts to use FU when none available 169system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.85% # attempts to use FU when none available 170system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.85% # attempts to use FU when none available 171system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.85% # attempts to use FU when none available 172system.cpu.iq.fu_full::FloatMult 0 0.00% 1.85% # attempts to use FU when none available 173system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.85% # attempts to use FU when none available 174system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.85% # attempts to use FU when none available 175system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.85% # attempts to use FU when none available 176system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.85% # attempts to use FU when none available 177system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.85% # attempts to use FU when none available 178system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.85% # attempts to use FU when none available 179system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.85% # attempts to use FU when none available 180system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.85% # attempts to use FU when none available 181system.cpu.iq.fu_full::SimdMult 0 0.00% 1.85% # attempts to use FU when none available 182system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.85% # attempts to use FU when none available 183system.cpu.iq.fu_full::SimdShift 0 0.00% 1.85% # attempts to use FU when none available 184system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.85% # attempts to use FU when none available 185system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.85% # attempts to use FU when none available 186system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.85% # attempts to use FU when none available 187system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.85% # attempts to use FU when none available 188system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.85% # attempts to use FU when none available 189system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.85% # attempts to use FU when none available 190system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.85% # attempts to use FU when none available 191system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.85% # attempts to use FU when none available 192system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.85% # attempts to use FU when none available 193system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.85% # attempts to use FU when none available 194system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.85% # attempts to use FU when none available 195system.cpu.iq.fu_full::MemRead 56969230 59.63% 61.48% # attempts to use FU when none available 196system.cpu.iq.fu_full::MemWrite 36797024 38.52% 100.00% # attempts to use FU when none available 197system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 198system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 199system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 200system.cpu.iq.FU_type_0::IntAlu 1258053988 46.29% 46.29% # Type of FU issued 201system.cpu.iq.FU_type_0::IntMult 11231448 0.41% 46.70% # Type of FU issued 202system.cpu.iq.FU_type_0::IntDiv 0 0.00% 46.70% # Type of FU issued 203system.cpu.iq.FU_type_0::FloatAdd 1 0.00% 46.70% # Type of FU issued 204system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 46.70% # Type of FU issued 205system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 46.70% # Type of FU issued 206system.cpu.iq.FU_type_0::FloatMult 0 0.00% 46.70% # Type of FU issued 207system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 46.70% # Type of FU issued 208system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 46.70% # Type of FU issued 209system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 46.70% # Type of FU issued 210system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 46.70% # Type of FU issued 211system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 46.70% # Type of FU issued 212system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 46.70% # Type of FU issued 213system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 46.70% # Type of FU issued 214system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 46.70% # Type of FU issued 215system.cpu.iq.FU_type_0::SimdMult 0 0.00% 46.70% # Type of FU issued 216system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 46.70% # Type of FU issued 217system.cpu.iq.FU_type_0::SimdShift 0 0.00% 46.70% # Type of FU issued 218system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 46.70% # Type of FU issued 219system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 46.70% # Type of FU issued 220system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.05% 46.75% # Type of FU issued 221system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 46.75% # Type of FU issued 222system.cpu.iq.FU_type_0::SimdFloatCmp 6876560 0.25% 47.00% # Type of FU issued 223system.cpu.iq.FU_type_0::SimdFloatCvt 5503486 0.20% 47.20% # Type of FU issued 224system.cpu.iq.FU_type_0::SimdFloatDiv 73 0.00% 47.20% # Type of FU issued 225system.cpu.iq.FU_type_0::SimdFloatMisc 23204970 0.85% 48.06% # Type of FU issued 226system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 48.06% # Type of FU issued 227system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.06% # Type of FU issued 228system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.06% # Type of FU issued 229system.cpu.iq.FU_type_0::MemRead 902246151 33.19% 81.25% # Type of FU issued 230system.cpu.iq.FU_type_0::MemWrite 509527435 18.75% 100.00% # Type of FU issued 231system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 232system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 233system.cpu.iq.FU_type_0::total 2718019401 # Type of FU issued 234system.cpu.iq.rate 1.847748 # Inst issue rate 235system.cpu.iq.fu_busy_cnt 95533729 # FU busy when requested 236system.cpu.iq.fu_busy_rate 0.035148 # FU busy rate (busy events/executed inst) 237system.cpu.iq.int_inst_queue_reads 6864166409 # Number of integer instruction queue reads 238system.cpu.iq.int_inst_queue_writes 4398397135 # Number of integer instruction queue writes 239system.cpu.iq.int_inst_queue_wakeup_accesses 2490268759 # Number of integer instruction queue wakeup accesses 240system.cpu.iq.fp_inst_queue_reads 133172616 # Number of floating instruction queue reads 241system.cpu.iq.fp_inst_queue_writes 101224152 # Number of floating instruction queue writes 242system.cpu.iq.fp_inst_queue_wakeup_accesses 59789124 # Number of floating instruction queue wakeup accesses 243system.cpu.iq.int_alu_accesses 2745104459 # Number of integer alu accesses 244system.cpu.iq.fp_alu_accesses 68448671 # Number of floating point alu accesses 245system.cpu.iew.lsq.thread0.forwLoads 72240187 # Number of loads that had data forwarded from stores 246system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 247system.cpu.iew.lsq.thread0.squashedLoads 429772018 # Number of loads squashed 248system.cpu.iew.lsq.thread0.ignoredResponses 278201 # Number of memory responses ignored because the instruction is squashed 249system.cpu.iew.lsq.thread0.memOrderViolation 1347099 # Number of memory ordering violations 250system.cpu.iew.lsq.thread0.squashedStores 298714721 # Number of stores squashed 251system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 252system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 253system.cpu.iew.lsq.thread0.rescheduledLoads 14 # Number of loads that were rescheduled 254system.cpu.iew.lsq.thread0.cacheBlocked 26 # Number of times an access to memory failed due to the cache being blocked 255system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 256system.cpu.iew.iewSquashCycles 182579096 # Number of cycles IEW is squashing 257system.cpu.iew.iewBlockCycles 16373982 # Number of cycles IEW is blocking 258system.cpu.iew.iewUnblockCycles 1591067 # Number of cycles IEW is unblocking 259system.cpu.iew.iewDispatchedInsts 3192732241 # Number of instructions dispatched to IQ 260system.cpu.iew.iewDispSquashedInsts 7809183 # Number of squashed instructions skipped by dispatch 261system.cpu.iew.iewDispLoadInsts 1061160981 # Number of dispatched load instructions 262system.cpu.iew.iewDispStoreInsts 575711799 # Number of dispatched store instructions 263system.cpu.iew.iewDispNonSpecInsts 58058 # Number of dispatched non-speculative instructions 264system.cpu.iew.iewIQFullEvents 1589162 # Number of times the IQ has become full, causing a stall 265system.cpu.iew.iewLSQFullEvents 317 # Number of times the LSQ has become full, causing a stall 266system.cpu.iew.memOrderViolationEvents 1347099 # Number of memory order violations 267system.cpu.iew.predictedTakenIncorrect 36984086 # Number of branches that were predicted taken incorrectly 268system.cpu.iew.predictedNotTakenIncorrect 8972300 # Number of branches that were predicted not taken incorrectly 269system.cpu.iew.branchMispredicts 45956386 # Number of branch mispredicts detected at execute 270system.cpu.iew.iewExecutedInsts 2617990910 # Number of executed instructions 271system.cpu.iew.iewExecLoadInsts 846641153 # Number of load instructions executed 272system.cpu.iew.iewExecSquashedInsts 100028491 # Number of squashed instructions skipped in execute 273system.cpu.iew.exec_swp 0 # number of swp insts executed 274system.cpu.iew.exec_nop 77258 # number of nop insts executed 275system.cpu.iew.exec_refs 1326395495 # number of memory reference insts executed 276system.cpu.iew.exec_branches 359930496 # Number of branches executed 277system.cpu.iew.exec_stores 479754342 # Number of stores executed 278system.cpu.iew.exec_rate 1.779747 # Inst execution rate 279system.cpu.iew.wb_sent 2578580051 # cumulative count of insts sent to commit 280system.cpu.iew.wb_count 2550057883 # cumulative count of insts written-back 281system.cpu.iew.wb_producers 1472840060 # num instructions producing a value 282system.cpu.iew.wb_consumers 2760220207 # num instructions consuming a value 283system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 284system.cpu.iew.wb_rate 1.733566 # insts written-back per cycle 285system.cpu.iew.wb_fanout 0.533595 # average fanout of values written-back 286system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 287system.cpu.commit.commitCommittedInsts 1384390519 # The number of committed instructions 288system.cpu.commit.commitCommittedOps 1885345272 # The number of committed instructions 289system.cpu.commit.commitSquashedInsts 1307387427 # The number of squashed insts skipped by commit 290system.cpu.commit.commitNonSpecStalls 23165 # The number of times commit has been forced to stall to communicate backwards 291system.cpu.commit.branchMispredicts 41179561 # The number of times a branch was mispredicted 292system.cpu.commit.committed_per_cycle::samples 1255460679 # Number of insts commited each cycle 293system.cpu.commit.committed_per_cycle::mean 1.501716 # Number of insts commited each cycle 294system.cpu.commit.committed_per_cycle::stdev 2.213055 # Number of insts commited each cycle 295system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 296system.cpu.commit.committed_per_cycle::0 576199063 45.90% 45.90% # Number of insts commited each cycle 297system.cpu.commit.committed_per_cycle::1 316668907 25.22% 71.12% # Number of insts commited each cycle 298system.cpu.commit.committed_per_cycle::2 101245126 8.06% 79.18% # Number of insts commited each cycle 299system.cpu.commit.committed_per_cycle::3 79298067 6.32% 85.50% # Number of insts commited each cycle 300system.cpu.commit.committed_per_cycle::4 52885974 4.21% 89.71% # Number of insts commited each cycle 301system.cpu.commit.committed_per_cycle::5 24348674 1.94% 91.65% # Number of insts commited each cycle 302system.cpu.commit.committed_per_cycle::6 17176683 1.37% 93.02% # Number of insts commited each cycle 303system.cpu.commit.committed_per_cycle::7 9160932 0.73% 93.75% # Number of insts commited each cycle 304system.cpu.commit.committed_per_cycle::8 78477253 6.25% 100.00% # Number of insts commited each cycle 305system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 306system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 307system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 308system.cpu.commit.committed_per_cycle::total 1255460679 # Number of insts commited each cycle 309system.cpu.commit.committedInsts 1384390519 # Number of instructions committed 310system.cpu.commit.committedOps 1885345272 # Number of ops (including micro ops) committed 311system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 312system.cpu.commit.refs 908386041 # Number of memory references committed 313system.cpu.commit.loads 631388963 # Number of loads committed 314system.cpu.commit.membars 9986 # Number of memory barriers committed 315system.cpu.commit.branches 291350326 # Number of branches committed 316system.cpu.commit.fp_insts 52289415 # Number of committed floating point instructions. 317system.cpu.commit.int_insts 1653705999 # Number of committed integer instructions. 318system.cpu.commit.function_calls 41577833 # Number of function calls committed. 319system.cpu.commit.bw_lim_events 78477253 # number cycles where commit BW limit reached 320system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 321system.cpu.rob.rob_reads 4369697780 # The number of ROB reads 322system.cpu.rob.rob_writes 6568059146 # The number of ROB writes 323system.cpu.timesIdled 1341236 # Number of times that the entire CPU went into an idle state and unscheduled itself 324system.cpu.idleCycles 32950353 # Total number of cycles that the CPU has spent unscheduled due to idling 325system.cpu.committedInsts 1384379503 # Number of Instructions Simulated 326system.cpu.committedOps 1885334256 # Number of Ops (including micro ops) Simulated 327system.cpu.committedInsts_total 1384379503 # Number of Instructions Simulated 328system.cpu.cpi 1.062563 # CPI: Cycles Per Instruction 329system.cpu.cpi_total 1.062563 # CPI: Total CPI of All Threads 330system.cpu.ipc 0.941121 # IPC: Instructions Per Cycle 331system.cpu.ipc_total 0.941121 # IPC: Total IPC of All Threads 332system.cpu.int_regfile_reads 12914363689 # number of integer regfile reads 333system.cpu.int_regfile_writes 2421503464 # number of integer regfile writes 334system.cpu.fp_regfile_reads 71102089 # number of floating regfile reads 335system.cpu.fp_regfile_writes 50855882 # number of floating regfile writes 336system.cpu.misc_regfile_reads 4088825153 # number of misc regfile reads 337system.cpu.misc_regfile_writes 13776464 # number of misc regfile writes 338system.cpu.icache.replacements 29072 # number of replacements 339system.cpu.icache.tagsinuse 1666.420003 # Cycle average of tags in use 340system.cpu.icache.total_refs 414707358 # Total number of references to valid blocks. 341system.cpu.icache.sampled_refs 30775 # Sample count of references to valid blocks. 342system.cpu.icache.avg_refs 13475.462486 # Average number of references to valid blocks. 343system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 344system.cpu.icache.occ_blocks::cpu.inst 1666.420003 # Average occupied blocks per requestor 345system.cpu.icache.occ_percent::cpu.inst 0.813682 # Average percentage of cache occupancy 346system.cpu.icache.occ_percent::total 0.813682 # Average percentage of cache occupancy 347system.cpu.icache.ReadReq_hits::cpu.inst 414707364 # number of ReadReq hits 348system.cpu.icache.ReadReq_hits::total 414707364 # number of ReadReq hits 349system.cpu.icache.demand_hits::cpu.inst 414707364 # number of demand (read+write) hits 350system.cpu.icache.demand_hits::total 414707364 # number of demand (read+write) hits 351system.cpu.icache.overall_hits::cpu.inst 414707364 # number of overall hits 352system.cpu.icache.overall_hits::total 414707364 # number of overall hits 353system.cpu.icache.ReadReq_misses::cpu.inst 36576 # number of ReadReq misses 354system.cpu.icache.ReadReq_misses::total 36576 # number of ReadReq misses 355system.cpu.icache.demand_misses::cpu.inst 36576 # number of demand (read+write) misses 356system.cpu.icache.demand_misses::total 36576 # number of demand (read+write) misses 357system.cpu.icache.overall_misses::cpu.inst 36576 # number of overall misses 358system.cpu.icache.overall_misses::total 36576 # number of overall misses 359system.cpu.icache.ReadReq_miss_latency::cpu.inst 322136500 # number of ReadReq miss cycles 360system.cpu.icache.ReadReq_miss_latency::total 322136500 # number of ReadReq miss cycles 361system.cpu.icache.demand_miss_latency::cpu.inst 322136500 # number of demand (read+write) miss cycles 362system.cpu.icache.demand_miss_latency::total 322136500 # number of demand (read+write) miss cycles 363system.cpu.icache.overall_miss_latency::cpu.inst 322136500 # number of overall miss cycles 364system.cpu.icache.overall_miss_latency::total 322136500 # number of overall miss cycles 365system.cpu.icache.ReadReq_accesses::cpu.inst 414743940 # number of ReadReq accesses(hits+misses) 366system.cpu.icache.ReadReq_accesses::total 414743940 # number of ReadReq accesses(hits+misses) 367system.cpu.icache.demand_accesses::cpu.inst 414743940 # number of demand (read+write) accesses 368system.cpu.icache.demand_accesses::total 414743940 # number of demand (read+write) accesses 369system.cpu.icache.overall_accesses::cpu.inst 414743940 # number of overall (read+write) accesses 370system.cpu.icache.overall_accesses::total 414743940 # number of overall (read+write) accesses 371system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000088 # miss rate for ReadReq accesses 372system.cpu.icache.demand_miss_rate::cpu.inst 0.000088 # miss rate for demand accesses 373system.cpu.icache.overall_miss_rate::cpu.inst 0.000088 # miss rate for overall accesses 374system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8807.319007 # average ReadReq miss latency 375system.cpu.icache.demand_avg_miss_latency::cpu.inst 8807.319007 # average overall miss latency 376system.cpu.icache.overall_avg_miss_latency::cpu.inst 8807.319007 # average overall miss latency 377system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 378system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 379system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 380system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 381system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 382system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 383system.cpu.icache.fast_writes 0 # number of fast writes performed 384system.cpu.icache.cache_copies 0 # number of cache copies performed 385system.cpu.icache.ReadReq_mshr_hits::cpu.inst 853 # number of ReadReq MSHR hits 386system.cpu.icache.ReadReq_mshr_hits::total 853 # number of ReadReq MSHR hits 387system.cpu.icache.demand_mshr_hits::cpu.inst 853 # number of demand (read+write) MSHR hits 388system.cpu.icache.demand_mshr_hits::total 853 # number of demand (read+write) MSHR hits 389system.cpu.icache.overall_mshr_hits::cpu.inst 853 # number of overall MSHR hits 390system.cpu.icache.overall_mshr_hits::total 853 # number of overall MSHR hits 391system.cpu.icache.ReadReq_mshr_misses::cpu.inst 35723 # number of ReadReq MSHR misses 392system.cpu.icache.ReadReq_mshr_misses::total 35723 # number of ReadReq MSHR misses 393system.cpu.icache.demand_mshr_misses::cpu.inst 35723 # number of demand (read+write) MSHR misses 394system.cpu.icache.demand_mshr_misses::total 35723 # number of demand (read+write) MSHR misses 395system.cpu.icache.overall_mshr_misses::cpu.inst 35723 # number of overall MSHR misses 396system.cpu.icache.overall_mshr_misses::total 35723 # number of overall MSHR misses 397system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 192601000 # number of ReadReq MSHR miss cycles 398system.cpu.icache.ReadReq_mshr_miss_latency::total 192601000 # number of ReadReq MSHR miss cycles 399system.cpu.icache.demand_mshr_miss_latency::cpu.inst 192601000 # number of demand (read+write) MSHR miss cycles 400system.cpu.icache.demand_mshr_miss_latency::total 192601000 # number of demand (read+write) MSHR miss cycles 401system.cpu.icache.overall_mshr_miss_latency::cpu.inst 192601000 # number of overall MSHR miss cycles 402system.cpu.icache.overall_mshr_miss_latency::total 192601000 # number of overall MSHR miss cycles 403system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000086 # mshr miss rate for ReadReq accesses 404system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000086 # mshr miss rate for demand accesses 405system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000086 # mshr miss rate for overall accesses 406system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 5391.512471 # average ReadReq mshr miss latency 407system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 5391.512471 # average overall mshr miss latency 408system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 5391.512471 # average overall mshr miss latency 409system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 410system.cpu.dcache.replacements 1532415 # number of replacements 411system.cpu.dcache.tagsinuse 4094.914319 # Cycle average of tags in use 412system.cpu.dcache.total_refs 1032974400 # Total number of references to valid blocks. 413system.cpu.dcache.sampled_refs 1536511 # Sample count of references to valid blocks. 414system.cpu.dcache.avg_refs 672.285717 # Average number of references to valid blocks. 415system.cpu.dcache.warmup_cycle 290267000 # Cycle when the warmup percentage was hit. 416system.cpu.dcache.occ_blocks::cpu.data 4094.914319 # Average occupied blocks per requestor 417system.cpu.dcache.occ_percent::cpu.data 0.999735 # Average percentage of cache occupancy 418system.cpu.dcache.occ_percent::total 0.999735 # Average percentage of cache occupancy 419system.cpu.dcache.ReadReq_hits::cpu.data 756817928 # number of ReadReq hits 420system.cpu.dcache.ReadReq_hits::total 756817928 # number of ReadReq hits 421system.cpu.dcache.WriteReq_hits::cpu.data 276114576 # number of WriteReq hits 422system.cpu.dcache.WriteReq_hits::total 276114576 # number of WriteReq hits 423system.cpu.dcache.LoadLockedReq_hits::cpu.data 13150 # number of LoadLockedReq hits 424system.cpu.dcache.LoadLockedReq_hits::total 13150 # number of LoadLockedReq hits 425system.cpu.dcache.StoreCondReq_hits::cpu.data 11766 # number of StoreCondReq hits 426system.cpu.dcache.StoreCondReq_hits::total 11766 # number of StoreCondReq hits 427system.cpu.dcache.demand_hits::cpu.data 1032932504 # number of demand (read+write) hits 428system.cpu.dcache.demand_hits::total 1032932504 # number of demand (read+write) hits 429system.cpu.dcache.overall_hits::cpu.data 1032932504 # number of overall hits 430system.cpu.dcache.overall_hits::total 1032932504 # number of overall hits 431system.cpu.dcache.ReadReq_misses::cpu.data 2368566 # number of ReadReq misses 432system.cpu.dcache.ReadReq_misses::total 2368566 # number of ReadReq misses 433system.cpu.dcache.WriteReq_misses::cpu.data 821102 # number of WriteReq misses 434system.cpu.dcache.WriteReq_misses::total 821102 # number of WriteReq misses 435system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses 436system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses 437system.cpu.dcache.demand_misses::cpu.data 3189668 # number of demand (read+write) misses 438system.cpu.dcache.demand_misses::total 3189668 # number of demand (read+write) misses 439system.cpu.dcache.overall_misses::cpu.data 3189668 # number of overall misses 440system.cpu.dcache.overall_misses::total 3189668 # number of overall misses 441system.cpu.dcache.ReadReq_miss_latency::cpu.data 80139479500 # number of ReadReq miss cycles 442system.cpu.dcache.ReadReq_miss_latency::total 80139479500 # number of ReadReq miss cycles 443system.cpu.dcache.WriteReq_miss_latency::cpu.data 28569168500 # number of WriteReq miss cycles 444system.cpu.dcache.WriteReq_miss_latency::total 28569168500 # number of WriteReq miss cycles 445system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 114500 # number of LoadLockedReq miss cycles 446system.cpu.dcache.LoadLockedReq_miss_latency::total 114500 # number of LoadLockedReq miss cycles 447system.cpu.dcache.demand_miss_latency::cpu.data 108708648000 # number of demand (read+write) miss cycles 448system.cpu.dcache.demand_miss_latency::total 108708648000 # number of demand (read+write) miss cycles 449system.cpu.dcache.overall_miss_latency::cpu.data 108708648000 # number of overall miss cycles 450system.cpu.dcache.overall_miss_latency::total 108708648000 # number of overall miss cycles 451system.cpu.dcache.ReadReq_accesses::cpu.data 759186494 # number of ReadReq accesses(hits+misses) 452system.cpu.dcache.ReadReq_accesses::total 759186494 # number of ReadReq accesses(hits+misses) 453system.cpu.dcache.WriteReq_accesses::cpu.data 276935678 # number of WriteReq accesses(hits+misses) 454system.cpu.dcache.WriteReq_accesses::total 276935678 # number of WriteReq accesses(hits+misses) 455system.cpu.dcache.LoadLockedReq_accesses::cpu.data 13153 # number of LoadLockedReq accesses(hits+misses) 456system.cpu.dcache.LoadLockedReq_accesses::total 13153 # number of LoadLockedReq accesses(hits+misses) 457system.cpu.dcache.StoreCondReq_accesses::cpu.data 11766 # number of StoreCondReq accesses(hits+misses) 458system.cpu.dcache.StoreCondReq_accesses::total 11766 # number of StoreCondReq accesses(hits+misses) 459system.cpu.dcache.demand_accesses::cpu.data 1036122172 # number of demand (read+write) accesses 460system.cpu.dcache.demand_accesses::total 1036122172 # number of demand (read+write) accesses 461system.cpu.dcache.overall_accesses::cpu.data 1036122172 # number of overall (read+write) accesses 462system.cpu.dcache.overall_accesses::total 1036122172 # number of overall (read+write) accesses 463system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003120 # miss rate for ReadReq accesses 464system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002965 # miss rate for WriteReq accesses 465system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000228 # miss rate for LoadLockedReq accesses 466system.cpu.dcache.demand_miss_rate::cpu.data 0.003078 # miss rate for demand accesses 467system.cpu.dcache.overall_miss_rate::cpu.data 0.003078 # miss rate for overall accesses 468system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 33834.598445 # average ReadReq miss latency 469system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34793.690065 # average WriteReq miss latency 470system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 38166.666667 # average LoadLockedReq miss latency 471system.cpu.dcache.demand_avg_miss_latency::cpu.data 34081.493121 # average overall miss latency 472system.cpu.dcache.overall_avg_miss_latency::cpu.data 34081.493121 # average overall miss latency 473system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 474system.cpu.dcache.blocked_cycles::no_targets 81500 # number of cycles access was blocked 475system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 476system.cpu.dcache.blocked::no_targets 4 # number of cycles access was blocked 477system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 478system.cpu.dcache.avg_blocked_cycles::no_targets 20375 # average number of cycles each access was blocked 479system.cpu.dcache.fast_writes 0 # number of fast writes performed 480system.cpu.dcache.cache_copies 0 # number of cache copies performed 481system.cpu.dcache.writebacks::writebacks 106560 # number of writebacks 482system.cpu.dcache.writebacks::total 106560 # number of writebacks 483system.cpu.dcache.ReadReq_mshr_hits::cpu.data 904767 # number of ReadReq MSHR hits 484system.cpu.dcache.ReadReq_mshr_hits::total 904767 # number of ReadReq MSHR hits 485system.cpu.dcache.WriteReq_mshr_hits::cpu.data 743443 # number of WriteReq MSHR hits 486system.cpu.dcache.WriteReq_mshr_hits::total 743443 # number of WriteReq MSHR hits 487system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits 488system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits 489system.cpu.dcache.demand_mshr_hits::cpu.data 1648210 # number of demand (read+write) MSHR hits 490system.cpu.dcache.demand_mshr_hits::total 1648210 # number of demand (read+write) MSHR hits 491system.cpu.dcache.overall_mshr_hits::cpu.data 1648210 # number of overall MSHR hits 492system.cpu.dcache.overall_mshr_hits::total 1648210 # number of overall MSHR hits 493system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1463799 # number of ReadReq MSHR misses 494system.cpu.dcache.ReadReq_mshr_misses::total 1463799 # number of ReadReq MSHR misses 495system.cpu.dcache.WriteReq_mshr_misses::cpu.data 77659 # number of WriteReq MSHR misses 496system.cpu.dcache.WriteReq_mshr_misses::total 77659 # number of WriteReq MSHR misses 497system.cpu.dcache.demand_mshr_misses::cpu.data 1541458 # number of demand (read+write) MSHR misses 498system.cpu.dcache.demand_mshr_misses::total 1541458 # number of demand (read+write) MSHR misses 499system.cpu.dcache.overall_mshr_misses::cpu.data 1541458 # number of overall MSHR misses 500system.cpu.dcache.overall_mshr_misses::total 1541458 # number of overall MSHR misses 501system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 50029877000 # number of ReadReq MSHR miss cycles 502system.cpu.dcache.ReadReq_mshr_miss_latency::total 50029877000 # number of ReadReq MSHR miss cycles 503system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2502958500 # number of WriteReq MSHR miss cycles 504system.cpu.dcache.WriteReq_mshr_miss_latency::total 2502958500 # number of WriteReq MSHR miss cycles 505system.cpu.dcache.demand_mshr_miss_latency::cpu.data 52532835500 # number of demand (read+write) MSHR miss cycles 506system.cpu.dcache.demand_mshr_miss_latency::total 52532835500 # number of demand (read+write) MSHR miss cycles 507system.cpu.dcache.overall_mshr_miss_latency::cpu.data 52532835500 # number of overall MSHR miss cycles 508system.cpu.dcache.overall_mshr_miss_latency::total 52532835500 # number of overall MSHR miss cycles 509system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001928 # mshr miss rate for ReadReq accesses 510system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000280 # mshr miss rate for WriteReq accesses 511system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001488 # mshr miss rate for demand accesses 512system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001488 # mshr miss rate for overall accesses 513system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34178.105737 # average ReadReq mshr miss latency 514system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32230.114990 # average WriteReq mshr miss latency 515system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34079.965526 # average overall mshr miss latency 516system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34079.965526 # average overall mshr miss latency 517system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 518system.cpu.l2cache.replacements 1480284 # number of replacements 519system.cpu.l2cache.tagsinuse 31973.508020 # Cycle average of tags in use 520system.cpu.l2cache.total_refs 87070 # Total number of references to valid blocks. 521system.cpu.l2cache.sampled_refs 1513005 # Sample count of references to valid blocks. 522system.cpu.l2cache.avg_refs 0.057548 # Average number of references to valid blocks. 523system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 524system.cpu.l2cache.occ_blocks::writebacks 2965.813236 # Average occupied blocks per requestor 525system.cpu.l2cache.occ_blocks::cpu.inst 61.172380 # Average occupied blocks per requestor 526system.cpu.l2cache.occ_blocks::cpu.data 28946.522403 # Average occupied blocks per requestor 527system.cpu.l2cache.occ_percent::writebacks 0.090509 # Average percentage of cache occupancy 528system.cpu.l2cache.occ_percent::cpu.inst 0.001867 # Average percentage of cache occupancy 529system.cpu.l2cache.occ_percent::cpu.data 0.883378 # Average percentage of cache occupancy 530system.cpu.l2cache.occ_percent::total 0.975754 # Average percentage of cache occupancy 531system.cpu.l2cache.ReadReq_hits::cpu.inst 27428 # number of ReadReq hits 532system.cpu.l2cache.ReadReq_hits::cpu.data 51328 # number of ReadReq hits 533system.cpu.l2cache.ReadReq_hits::total 78756 # number of ReadReq hits 534system.cpu.l2cache.Writeback_hits::writebacks 106560 # number of Writeback hits 535system.cpu.l2cache.Writeback_hits::total 106560 # number of Writeback hits 536system.cpu.l2cache.UpgradeReq_hits::cpu.data 3 # number of UpgradeReq hits 537system.cpu.l2cache.UpgradeReq_hits::total 3 # number of UpgradeReq hits 538system.cpu.l2cache.ReadExReq_hits::cpu.data 6632 # number of ReadExReq hits 539system.cpu.l2cache.ReadExReq_hits::total 6632 # number of ReadExReq hits 540system.cpu.l2cache.demand_hits::cpu.inst 27428 # number of demand (read+write) hits 541system.cpu.l2cache.demand_hits::cpu.data 57960 # number of demand (read+write) hits 542system.cpu.l2cache.demand_hits::total 85388 # number of demand (read+write) hits 543system.cpu.l2cache.overall_hits::cpu.inst 27428 # number of overall hits 544system.cpu.l2cache.overall_hits::cpu.data 57960 # number of overall hits 545system.cpu.l2cache.overall_hits::total 85388 # number of overall hits 546system.cpu.l2cache.ReadReq_misses::cpu.inst 3348 # number of ReadReq misses 547system.cpu.l2cache.ReadReq_misses::cpu.data 1412471 # number of ReadReq misses 548system.cpu.l2cache.ReadReq_misses::total 1415819 # number of ReadReq misses 549system.cpu.l2cache.UpgradeReq_misses::cpu.data 4944 # number of UpgradeReq misses 550system.cpu.l2cache.UpgradeReq_misses::total 4944 # number of UpgradeReq misses 551system.cpu.l2cache.ReadExReq_misses::cpu.data 66080 # number of ReadExReq misses 552system.cpu.l2cache.ReadExReq_misses::total 66080 # number of ReadExReq misses 553system.cpu.l2cache.demand_misses::cpu.inst 3348 # number of demand (read+write) misses 554system.cpu.l2cache.demand_misses::cpu.data 1478551 # number of demand (read+write) misses 555system.cpu.l2cache.demand_misses::total 1481899 # number of demand (read+write) misses 556system.cpu.l2cache.overall_misses::cpu.inst 3348 # number of overall misses 557system.cpu.l2cache.overall_misses::cpu.data 1478551 # number of overall misses 558system.cpu.l2cache.overall_misses::total 1481899 # number of overall misses 559system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 114766000 # number of ReadReq miss cycles 560system.cpu.l2cache.ReadReq_miss_latency::cpu.data 48456356500 # number of ReadReq miss cycles 561system.cpu.l2cache.ReadReq_miss_latency::total 48571122500 # number of ReadReq miss cycles 562system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2252292000 # number of ReadExReq miss cycles 563system.cpu.l2cache.ReadExReq_miss_latency::total 2252292000 # number of ReadExReq miss cycles 564system.cpu.l2cache.demand_miss_latency::cpu.inst 114766000 # number of demand (read+write) miss cycles 565system.cpu.l2cache.demand_miss_latency::cpu.data 50708648500 # number of demand (read+write) miss cycles 566system.cpu.l2cache.demand_miss_latency::total 50823414500 # number of demand (read+write) miss cycles 567system.cpu.l2cache.overall_miss_latency::cpu.inst 114766000 # number of overall miss cycles 568system.cpu.l2cache.overall_miss_latency::cpu.data 50708648500 # number of overall miss cycles 569system.cpu.l2cache.overall_miss_latency::total 50823414500 # number of overall miss cycles 570system.cpu.l2cache.ReadReq_accesses::cpu.inst 30776 # number of ReadReq accesses(hits+misses) 571system.cpu.l2cache.ReadReq_accesses::cpu.data 1463799 # number of ReadReq accesses(hits+misses) 572system.cpu.l2cache.ReadReq_accesses::total 1494575 # number of ReadReq accesses(hits+misses) 573system.cpu.l2cache.Writeback_accesses::writebacks 106560 # number of Writeback accesses(hits+misses) 574system.cpu.l2cache.Writeback_accesses::total 106560 # number of Writeback accesses(hits+misses) 575system.cpu.l2cache.UpgradeReq_accesses::cpu.data 4947 # number of UpgradeReq accesses(hits+misses) 576system.cpu.l2cache.UpgradeReq_accesses::total 4947 # number of UpgradeReq accesses(hits+misses) 577system.cpu.l2cache.ReadExReq_accesses::cpu.data 72712 # number of ReadExReq accesses(hits+misses) 578system.cpu.l2cache.ReadExReq_accesses::total 72712 # number of ReadExReq accesses(hits+misses) 579system.cpu.l2cache.demand_accesses::cpu.inst 30776 # number of demand (read+write) accesses 580system.cpu.l2cache.demand_accesses::cpu.data 1536511 # number of demand (read+write) accesses 581system.cpu.l2cache.demand_accesses::total 1567287 # number of demand (read+write) accesses 582system.cpu.l2cache.overall_accesses::cpu.inst 30776 # number of overall (read+write) accesses 583system.cpu.l2cache.overall_accesses::cpu.data 1536511 # number of overall (read+write) accesses 584system.cpu.l2cache.overall_accesses::total 1567287 # number of overall (read+write) accesses 585system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.108786 # miss rate for ReadReq accesses 586system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.964935 # miss rate for ReadReq accesses 587system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.999394 # miss rate for UpgradeReq accesses 588system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.908791 # miss rate for ReadExReq accesses 589system.cpu.l2cache.demand_miss_rate::cpu.inst 0.108786 # miss rate for demand accesses 590system.cpu.l2cache.demand_miss_rate::cpu.data 0.962278 # miss rate for demand accesses 591system.cpu.l2cache.overall_miss_rate::cpu.inst 0.108786 # miss rate for overall accesses 592system.cpu.l2cache.overall_miss_rate::cpu.data 0.962278 # miss rate for overall accesses 593system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34278.972521 # average ReadReq miss latency 594system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34306.089470 # average ReadReq miss latency 595system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34084.322034 # average ReadExReq miss latency 596system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34278.972521 # average overall miss latency 597system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34296.178150 # average overall miss latency 598system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34278.972521 # average overall miss latency 599system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34296.178150 # average overall miss latency 600system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 601system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 602system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 603system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 604system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 605system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 606system.cpu.l2cache.fast_writes 0 # number of fast writes performed 607system.cpu.l2cache.cache_copies 0 # number of cache copies performed 608system.cpu.l2cache.writebacks::writebacks 66099 # number of writebacks 609system.cpu.l2cache.writebacks::total 66099 # number of writebacks 610system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 5 # number of ReadReq MSHR hits 611system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 24 # number of ReadReq MSHR hits 612system.cpu.l2cache.ReadReq_mshr_hits::total 29 # number of ReadReq MSHR hits 613system.cpu.l2cache.demand_mshr_hits::cpu.inst 5 # number of demand (read+write) MSHR hits 614system.cpu.l2cache.demand_mshr_hits::cpu.data 24 # number of demand (read+write) MSHR hits 615system.cpu.l2cache.demand_mshr_hits::total 29 # number of demand (read+write) MSHR hits 616system.cpu.l2cache.overall_mshr_hits::cpu.inst 5 # number of overall MSHR hits 617system.cpu.l2cache.overall_mshr_hits::cpu.data 24 # number of overall MSHR hits 618system.cpu.l2cache.overall_mshr_hits::total 29 # number of overall MSHR hits 619system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3343 # number of ReadReq MSHR misses 620system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1412447 # number of ReadReq MSHR misses 621system.cpu.l2cache.ReadReq_mshr_misses::total 1415790 # number of ReadReq MSHR misses 622system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 4944 # number of UpgradeReq MSHR misses 623system.cpu.l2cache.UpgradeReq_mshr_misses::total 4944 # number of UpgradeReq MSHR misses 624system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66080 # number of ReadExReq MSHR misses 625system.cpu.l2cache.ReadExReq_mshr_misses::total 66080 # number of ReadExReq MSHR misses 626system.cpu.l2cache.demand_mshr_misses::cpu.inst 3343 # number of demand (read+write) MSHR misses 627system.cpu.l2cache.demand_mshr_misses::cpu.data 1478527 # number of demand (read+write) MSHR misses 628system.cpu.l2cache.demand_mshr_misses::total 1481870 # number of demand (read+write) MSHR misses 629system.cpu.l2cache.overall_mshr_misses::cpu.inst 3343 # number of overall MSHR misses 630system.cpu.l2cache.overall_mshr_misses::cpu.data 1478527 # number of overall MSHR misses 631system.cpu.l2cache.overall_mshr_misses::total 1481870 # number of overall MSHR misses 632system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 103877000 # number of ReadReq MSHR miss cycles 633system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 43883033500 # number of ReadReq MSHR miss cycles 634system.cpu.l2cache.ReadReq_mshr_miss_latency::total 43986910500 # number of ReadReq MSHR miss cycles 635system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 153264000 # number of UpgradeReq MSHR miss cycles 636system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 153264000 # number of UpgradeReq MSHR miss cycles 637system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2048525000 # number of ReadExReq MSHR miss cycles 638system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2048525000 # number of ReadExReq MSHR miss cycles 639system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 103877000 # number of demand (read+write) MSHR miss cycles 640system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 45931558500 # number of demand (read+write) MSHR miss cycles 641system.cpu.l2cache.demand_mshr_miss_latency::total 46035435500 # number of demand (read+write) MSHR miss cycles 642system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 103877000 # number of overall MSHR miss cycles 643system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 45931558500 # number of overall MSHR miss cycles 644system.cpu.l2cache.overall_mshr_miss_latency::total 46035435500 # number of overall MSHR miss cycles 645system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.108624 # mshr miss rate for ReadReq accesses 646system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.964919 # mshr miss rate for ReadReq accesses 647system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.999394 # mshr miss rate for UpgradeReq accesses 648system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.908791 # mshr miss rate for ReadExReq accesses 649system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.108624 # mshr miss rate for demand accesses 650system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.962263 # mshr miss rate for demand accesses 651system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.108624 # mshr miss rate for overall accesses 652system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.962263 # mshr miss rate for overall accesses 653system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31072.988334 # average ReadReq mshr miss latency 654system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31068.800104 # average ReadReq mshr miss latency 655system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31000 # average UpgradeReq mshr miss latency 656system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31000.680993 # average ReadExReq mshr miss latency 657system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31072.988334 # average overall mshr miss latency 658system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31065.755647 # average overall mshr miss latency 659system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31072.988334 # average overall mshr miss latency 660system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31065.755647 # average overall mshr miss latency 661system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 662 663---------- End Simulation Statistics ---------- 664