stats.txt revision 11214:966091379ded
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.452586 # Number of seconds simulated 4sim_ticks 452585997000 # Number of ticks simulated 5final_tick 452585997000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 89374 # Simulator instruction rate (inst/s) 8host_op_rate 110031 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 63138171 # Simulator tick rate (ticks/s) 10host_mem_usage 323296 # Number of bytes of host memory used 11host_seconds 7168.18 # Real time elapsed on the host 12sim_insts 640649299 # Number of instructions simulated 13sim_ops 788724958 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 234368 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 47997568 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.l2cache.prefetcher 12828032 # Number of bytes read from this memory 19system.physmem.bytes_read::total 61059968 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 234368 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 234368 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 4243520 # Number of bytes written to this memory 23system.physmem.bytes_written::total 4243520 # Number of bytes written to this memory 24system.physmem.num_reads::cpu.inst 3662 # Number of read requests responded to by this memory 25system.physmem.num_reads::cpu.data 749962 # Number of read requests responded to by this memory 26system.physmem.num_reads::cpu.l2cache.prefetcher 200438 # Number of read requests responded to by this memory 27system.physmem.num_reads::total 954062 # Number of read requests responded to by this memory 28system.physmem.num_writes::writebacks 66305 # Number of write requests responded to by this memory 29system.physmem.num_writes::total 66305 # Number of write requests responded to by this memory 30system.physmem.bw_read::cpu.inst 517842 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_read::cpu.data 106051818 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_read::cpu.l2cache.prefetcher 28343855 # Total read bandwidth from this memory (bytes/s) 33system.physmem.bw_read::total 134913516 # Total read bandwidth from this memory (bytes/s) 34system.physmem.bw_inst_read::cpu.inst 517842 # Instruction read bandwidth from this memory (bytes/s) 35system.physmem.bw_inst_read::total 517842 # Instruction read bandwidth from this memory (bytes/s) 36system.physmem.bw_write::writebacks 9376163 # Write bandwidth from this memory (bytes/s) 37system.physmem.bw_write::total 9376163 # Write bandwidth from this memory (bytes/s) 38system.physmem.bw_total::writebacks 9376163 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.bw_total::cpu.inst 517842 # Total bandwidth to/from this memory (bytes/s) 40system.physmem.bw_total::cpu.data 106051818 # Total bandwidth to/from this memory (bytes/s) 41system.physmem.bw_total::cpu.l2cache.prefetcher 28343855 # Total bandwidth to/from this memory (bytes/s) 42system.physmem.bw_total::total 144289678 # Total bandwidth to/from this memory (bytes/s) 43system.physmem.readReqs 954063 # Number of read requests accepted 44system.physmem.writeReqs 66305 # Number of write requests accepted 45system.physmem.readBursts 954063 # Number of DRAM read bursts, including those serviced by the write queue 46system.physmem.writeBursts 66305 # Number of DRAM write bursts, including those merged in the write queue 47system.physmem.bytesReadDRAM 61041664 # Total number of bytes read from DRAM 48system.physmem.bytesReadWrQ 18368 # Total number of bytes read from write queue 49system.physmem.bytesWritten 4238400 # Total number of bytes written to DRAM 50system.physmem.bytesReadSys 61060032 # Total read bytes from the system interface side 51system.physmem.bytesWrittenSys 4243520 # Total written bytes from the system interface side 52system.physmem.servicedByWrQ 287 # Number of DRAM read bursts serviced by the write queue 53system.physmem.mergedWrBursts 63 # Number of DRAM write bursts merged with an existing one 54system.physmem.neitherReadNorWriteReqs 227627 # Number of requests that are neither read nor write 55system.physmem.perBankRdBursts::0 19636 # Per bank write bursts 56system.physmem.perBankRdBursts::1 19225 # Per bank write bursts 57system.physmem.perBankRdBursts::2 656809 # Per bank write bursts 58system.physmem.perBankRdBursts::3 20104 # Per bank write bursts 59system.physmem.perBankRdBursts::4 19566 # Per bank write bursts 60system.physmem.perBankRdBursts::5 20746 # Per bank write bursts 61system.physmem.perBankRdBursts::6 19449 # Per bank write bursts 62system.physmem.perBankRdBursts::7 19830 # Per bank write bursts 63system.physmem.perBankRdBursts::8 19282 # Per bank write bursts 64system.physmem.perBankRdBursts::9 19792 # Per bank write bursts 65system.physmem.perBankRdBursts::10 19287 # Per bank write bursts 66system.physmem.perBankRdBursts::11 19476 # Per bank write bursts 67system.physmem.perBankRdBursts::12 19427 # Per bank write bursts 68system.physmem.perBankRdBursts::13 20933 # Per bank write bursts 69system.physmem.perBankRdBursts::14 19357 # Per bank write bursts 70system.physmem.perBankRdBursts::15 20857 # Per bank write bursts 71system.physmem.perBankWrBursts::0 4254 # Per bank write bursts 72system.physmem.perBankWrBursts::1 4108 # Per bank write bursts 73system.physmem.perBankWrBursts::2 4140 # Per bank write bursts 74system.physmem.perBankWrBursts::3 4154 # Per bank write bursts 75system.physmem.perBankWrBursts::4 4243 # Per bank write bursts 76system.physmem.perBankWrBursts::5 4230 # Per bank write bursts 77system.physmem.perBankWrBursts::6 4174 # Per bank write bursts 78system.physmem.perBankWrBursts::7 4094 # Per bank write bursts 79system.physmem.perBankWrBursts::8 4096 # Per bank write bursts 80system.physmem.perBankWrBursts::9 4096 # Per bank write bursts 81system.physmem.perBankWrBursts::10 4096 # Per bank write bursts 82system.physmem.perBankWrBursts::11 4097 # Per bank write bursts 83system.physmem.perBankWrBursts::12 4098 # Per bank write bursts 84system.physmem.perBankWrBursts::13 4096 # Per bank write bursts 85system.physmem.perBankWrBursts::14 4096 # Per bank write bursts 86system.physmem.perBankWrBursts::15 4153 # Per bank write bursts 87system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 88system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 89system.physmem.totGap 452585986500 # Total gap between requests 90system.physmem.readPktSize::0 0 # Read request sizes (log2) 91system.physmem.readPktSize::1 0 # Read request sizes (log2) 92system.physmem.readPktSize::2 0 # Read request sizes (log2) 93system.physmem.readPktSize::3 0 # Read request sizes (log2) 94system.physmem.readPktSize::4 0 # Read request sizes (log2) 95system.physmem.readPktSize::5 0 # Read request sizes (log2) 96system.physmem.readPktSize::6 954063 # Read request sizes (log2) 97system.physmem.writePktSize::0 0 # Write request sizes (log2) 98system.physmem.writePktSize::1 0 # Write request sizes (log2) 99system.physmem.writePktSize::2 0 # Write request sizes (log2) 100system.physmem.writePktSize::3 0 # Write request sizes (log2) 101system.physmem.writePktSize::4 0 # Write request sizes (log2) 102system.physmem.writePktSize::5 0 # Write request sizes (log2) 103system.physmem.writePktSize::6 66305 # Write request sizes (log2) 104system.physmem.rdQLenPdf::0 760072 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::1 121484 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::2 14330 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::3 6788 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::4 6461 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::5 7610 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::6 8751 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::7 9237 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::8 8035 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::9 3854 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::10 2788 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::11 1992 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::12 1474 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::13 900 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 136system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::15 585 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::16 609 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::17 993 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::18 1785 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::19 2648 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::20 3331 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::21 3815 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::22 4179 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::23 4467 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::24 4678 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::25 4996 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::26 5065 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::27 5200 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::28 5020 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::29 4895 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::30 4192 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::31 4082 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::32 4082 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::33 139 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::34 103 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::35 86 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::36 93 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::37 81 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::38 81 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::39 81 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::40 77 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::41 77 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::42 85 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::43 74 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::44 76 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::45 67 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::46 65 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::47 61 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::48 52 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::49 52 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::50 54 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::51 55 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::52 49 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::53 39 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::54 37 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::55 18 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::56 3 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 200system.physmem.bytesPerActivate::samples 205647 # Bytes accessed per row activation 201system.physmem.bytesPerActivate::mean 317.429381 # Bytes accessed per row activation 202system.physmem.bytesPerActivate::gmean 201.568290 # Bytes accessed per row activation 203system.physmem.bytesPerActivate::stdev 286.974442 # Bytes accessed per row activation 204system.physmem.bytesPerActivate::0-127 59802 29.08% 29.08% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::128-255 62661 30.47% 59.55% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::256-383 15924 7.74% 67.29% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::384-511 3207 1.56% 68.85% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::512-639 3374 1.64% 70.49% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::640-767 48035 23.36% 93.85% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::768-895 7705 3.75% 97.60% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::896-1023 1172 0.57% 98.17% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::1024-1151 3767 1.83% 100.00% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::total 205647 # Bytes accessed per row activation 214system.physmem.rdPerTurnAround::samples 4029 # Reads before turning the bus around for writes 215system.physmem.rdPerTurnAround::mean 234.045421 # Reads before turning the bus around for writes 216system.physmem.rdPerTurnAround::gmean 40.559432 # Reads before turning the bus around for writes 217system.physmem.rdPerTurnAround::stdev 3989.674296 # Reads before turning the bus around for writes 218system.physmem.rdPerTurnAround::0-8191 4017 99.70% 99.70% # Reads before turning the bus around for writes 219system.physmem.rdPerTurnAround::8192-16383 7 0.17% 99.88% # Reads before turning the bus around for writes 220system.physmem.rdPerTurnAround::24576-32767 2 0.05% 99.93% # Reads before turning the bus around for writes 221system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.95% # Reads before turning the bus around for writes 222system.physmem.rdPerTurnAround::90112-98303 1 0.02% 99.98% # Reads before turning the bus around for writes 223system.physmem.rdPerTurnAround::212992-221183 1 0.02% 100.00% # Reads before turning the bus around for writes 224system.physmem.rdPerTurnAround::total 4029 # Reads before turning the bus around for writes 225system.physmem.wrPerTurnAround::samples 4029 # Writes before turning the bus around for reads 226system.physmem.wrPerTurnAround::mean 16.437081 # Writes before turning the bus around for reads 227system.physmem.wrPerTurnAround::gmean 16.396271 # Writes before turning the bus around for reads 228system.physmem.wrPerTurnAround::stdev 1.276876 # Writes before turning the bus around for reads 229system.physmem.wrPerTurnAround::16 3401 84.41% 84.41% # Writes before turning the bus around for reads 230system.physmem.wrPerTurnAround::17 9 0.22% 84.64% # Writes before turning the bus around for reads 231system.physmem.wrPerTurnAround::18 462 11.47% 96.10% # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::19 50 1.24% 97.34% # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::20 36 0.89% 98.24% # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::21 16 0.40% 98.63% # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::22 18 0.45% 99.08% # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::23 10 0.25% 99.33% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::24 6 0.15% 99.48% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::25 6 0.15% 99.63% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::26 4 0.10% 99.73% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::27 4 0.10% 99.83% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::28 3 0.07% 99.90% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::29 2 0.05% 99.95% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::30 2 0.05% 100.00% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::total 4029 # Writes before turning the bus around for reads 245system.physmem.totQLat 15106541272 # Total ticks spent queuing 246system.physmem.totMemAccLat 32989841272 # Total ticks spent from burst creation until serviced by the DRAM 247system.physmem.totBusLat 4768880000 # Total ticks spent in databus transfers 248system.physmem.avgQLat 15838.67 # Average queueing delay per DRAM burst 249system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 250system.physmem.avgMemAccLat 34588.67 # Average memory access latency per DRAM burst 251system.physmem.avgRdBW 134.87 # Average DRAM read bandwidth in MiByte/s 252system.physmem.avgWrBW 9.36 # Average achieved write bandwidth in MiByte/s 253system.physmem.avgRdBWSys 134.91 # Average system read bandwidth in MiByte/s 254system.physmem.avgWrBWSys 9.38 # Average system write bandwidth in MiByte/s 255system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 256system.physmem.busUtil 1.13 # Data bus utilization in percentage 257system.physmem.busUtilRead 1.05 # Data bus utilization in percentage for reads 258system.physmem.busUtilWrite 0.07 # Data bus utilization in percentage for writes 259system.physmem.avgRdQLen 1.08 # Average read queue length when enqueuing 260system.physmem.avgWrQLen 24.93 # Average write queue length when enqueuing 261system.physmem.readRowHits 788463 # Number of row buffer hits during reads 262system.physmem.writeRowHits 25883 # Number of row buffer hits during writes 263system.physmem.readRowHitRate 82.67 # Row buffer hit rate for reads 264system.physmem.writeRowHitRate 39.07 # Row buffer hit rate for writes 265system.physmem.avgGap 443551.72 # Average gap between requests 266system.physmem.pageHitRate 79.84 # Row buffer hit rate, read and write combined 267system.physmem_0.actEnergy 1032091200 # Energy for activate commands per rank (pJ) 268system.physmem_0.preEnergy 563145000 # Energy for precharge commands per rank (pJ) 269system.physmem_0.readEnergy 6203792400 # Energy for read commands per rank (pJ) 270system.physmem_0.writeEnergy 216412560 # Energy for write commands per rank (pJ) 271system.physmem_0.refreshEnergy 29560558560 # Energy for refresh commands per rank (pJ) 272system.physmem_0.actBackEnergy 305512170480 # Energy for active background per rank (pJ) 273system.physmem_0.preBackEnergy 3557164500 # Energy for precharge background per rank (pJ) 274system.physmem_0.totalEnergy 346645334700 # Total energy per rank (pJ) 275system.physmem_0.averagePower 765.925147 # Core power per rank (mW) 276system.physmem_0.memoryStateTime::IDLE 4194914578 # Time in different power states 277system.physmem_0.memoryStateTime::REF 15112760000 # Time in different power states 278system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 279system.physmem_0.memoryStateTime::ACT 433276166672 # Time in different power states 280system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 281system.physmem_1.actEnergy 522539640 # Energy for activate commands per rank (pJ) 282system.physmem_1.preEnergy 285115875 # Energy for precharge commands per rank (pJ) 283system.physmem_1.readEnergy 1235348400 # Energy for read commands per rank (pJ) 284system.physmem_1.writeEnergy 212725440 # Energy for write commands per rank (pJ) 285system.physmem_1.refreshEnergy 29560558560 # Energy for refresh commands per rank (pJ) 286system.physmem_1.actBackEnergy 96876011835 # Energy for active background per rank (pJ) 287system.physmem_1.preBackEnergy 186571355250 # Energy for precharge background per rank (pJ) 288system.physmem_1.totalEnergy 315263655000 # Total energy per rank (pJ) 289system.physmem_1.averagePower 696.586172 # Core power per rank (mW) 290system.physmem_1.memoryStateTime::IDLE 309737229647 # Time in different power states 291system.physmem_1.memoryStateTime::REF 15112760000 # Time in different power states 292system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 293system.physmem_1.memoryStateTime::ACT 127733879103 # Time in different power states 294system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 295system.cpu.branchPred.lookups 234612390 # Number of BP lookups 296system.cpu.branchPred.condPredicted 162472835 # Number of conditional branches predicted 297system.cpu.branchPred.condIncorrect 15514556 # Number of conditional branches incorrect 298system.cpu.branchPred.BTBLookups 121579993 # Number of BTB lookups 299system.cpu.branchPred.BTBHits 107625887 # Number of BTB hits 300system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 301system.cpu.branchPred.BTBHitPct 88.522696 # BTB Hit Percentage 302system.cpu.branchPred.usedRAS 25035644 # Number of times the RAS was used to get a target. 303system.cpu.branchPred.RASInCorrect 1300133 # Number of incorrect RAS predictions. 304system.cpu_clk_domain.clock 500 # Clock period in ticks 305system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 306system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 307system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 308system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 309system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 310system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 311system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 312system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 313system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 314system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 315system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 316system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 317system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 318system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 319system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 320system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 321system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 322system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 323system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 324system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 325system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 326system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 327system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 328system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 329system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 330system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 331system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 332system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 333system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 334system.cpu.dtb.walker.walks 0 # Table walker walks requested 335system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 336system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 337system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 338system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 339system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 340system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 341system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 342system.cpu.dtb.inst_hits 0 # ITB inst hits 343system.cpu.dtb.inst_misses 0 # ITB inst misses 344system.cpu.dtb.read_hits 0 # DTB read hits 345system.cpu.dtb.read_misses 0 # DTB read misses 346system.cpu.dtb.write_hits 0 # DTB write hits 347system.cpu.dtb.write_misses 0 # DTB write misses 348system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 349system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 350system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 351system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 352system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 353system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 354system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 355system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 356system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 357system.cpu.dtb.read_accesses 0 # DTB read accesses 358system.cpu.dtb.write_accesses 0 # DTB write accesses 359system.cpu.dtb.inst_accesses 0 # ITB inst accesses 360system.cpu.dtb.hits 0 # DTB hits 361system.cpu.dtb.misses 0 # DTB misses 362system.cpu.dtb.accesses 0 # DTB accesses 363system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 364system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 365system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 366system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 367system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 368system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 369system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 370system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 371system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 372system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 373system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 374system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 375system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 376system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 377system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 378system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 379system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 380system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 381system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 382system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 383system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 384system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 385system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 386system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 387system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 388system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 389system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 390system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 391system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 392system.cpu.itb.walker.walks 0 # Table walker walks requested 393system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 394system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 395system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 396system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 397system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 398system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 399system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 400system.cpu.itb.inst_hits 0 # ITB inst hits 401system.cpu.itb.inst_misses 0 # ITB inst misses 402system.cpu.itb.read_hits 0 # DTB read hits 403system.cpu.itb.read_misses 0 # DTB read misses 404system.cpu.itb.write_hits 0 # DTB write hits 405system.cpu.itb.write_misses 0 # DTB write misses 406system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 407system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 408system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 409system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 410system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 411system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 412system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 413system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 414system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 415system.cpu.itb.read_accesses 0 # DTB read accesses 416system.cpu.itb.write_accesses 0 # DTB write accesses 417system.cpu.itb.inst_accesses 0 # ITB inst accesses 418system.cpu.itb.hits 0 # DTB hits 419system.cpu.itb.misses 0 # DTB misses 420system.cpu.itb.accesses 0 # DTB accesses 421system.cpu.workload.num_syscalls 673 # Number of system calls 422system.cpu.numCycles 905171995 # number of cpu cycles simulated 423system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 424system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 425system.cpu.fetch.icacheStallCycles 86003110 # Number of cycles fetch is stalled on an Icache miss 426system.cpu.fetch.Insts 1202048869 # Number of instructions fetch has processed 427system.cpu.fetch.Branches 234612390 # Number of branches that fetch encountered 428system.cpu.fetch.predictedBranches 132661531 # Number of branches that fetch has predicted taken 429system.cpu.fetch.Cycles 803279049 # Number of cycles fetch has run and was not squashing or blocked 430system.cpu.fetch.SquashCycles 31064713 # Number of cycles fetch has spent squashing 431system.cpu.fetch.MiscStallCycles 1868 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 432system.cpu.fetch.PendingTrapStallCycles 31 # Number of stall cycles due to pending traps 433system.cpu.fetch.IcacheWaitRetryStallCycles 3204 # Number of stall cycles due to full MSHR 434system.cpu.fetch.CacheLines 370083974 # Number of cache lines fetched 435system.cpu.fetch.IcacheSquashes 652982 # Number of outstanding Icache misses that were squashed 436system.cpu.fetch.rateDist::samples 904819618 # Number of instructions fetched each cycle (Total) 437system.cpu.fetch.rateDist::mean 1.657214 # Number of instructions fetched each cycle (Total) 438system.cpu.fetch.rateDist::stdev 1.229926 # Number of instructions fetched each cycle (Total) 439system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 440system.cpu.fetch.rateDist::0 222849160 24.63% 24.63% # Number of instructions fetched each cycle (Total) 441system.cpu.fetch.rateDist::1 224059075 24.76% 49.39% # Number of instructions fetched each cycle (Total) 442system.cpu.fetch.rateDist::2 98313082 10.87% 60.26% # Number of instructions fetched each cycle (Total) 443system.cpu.fetch.rateDist::3 359598301 39.74% 100.00% # Number of instructions fetched each cycle (Total) 444system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 445system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 446system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) 447system.cpu.fetch.rateDist::total 904819618 # Number of instructions fetched each cycle (Total) 448system.cpu.fetch.branchRate 0.259191 # Number of branch fetches per cycle 449system.cpu.fetch.rate 1.327978 # Number of inst fetches per cycle 450system.cpu.decode.IdleCycles 121904104 # Number of cycles decode is idle 451system.cpu.decode.BlockedCycles 244100755 # Number of cycles decode is blocked 452system.cpu.decode.RunCycles 484657410 # Number of cycles decode is running 453system.cpu.decode.UnblockCycles 38638668 # Number of cycles decode is unblocking 454system.cpu.decode.SquashCycles 15518681 # Number of cycles decode is squashing 455system.cpu.decode.BranchResolved 24546049 # Number of times decode resolved a branch 456system.cpu.decode.BranchMispred 13811 # Number of times decode detected a branch misprediction 457system.cpu.decode.DecodedInsts 1248144086 # Number of instructions handled by decode 458system.cpu.decode.SquashedInsts 39968857 # Number of squashed instructions handled by decode 459system.cpu.rename.SquashCycles 15518681 # Number of cycles rename is squashing 460system.cpu.rename.IdleCycles 178914873 # Number of cycles rename is idle 461system.cpu.rename.BlockCycles 163328471 # Number of cycles rename is blocking 462system.cpu.rename.serializeStallCycles 207028 # count of cycles rename stalled for serializing inst 463system.cpu.rename.RunCycles 464319861 # Number of cycles rename is running 464system.cpu.rename.UnblockCycles 82530704 # Number of cycles rename is unblocking 465system.cpu.rename.RenamedInsts 1190654266 # Number of instructions processed by rename 466system.cpu.rename.SquashedInsts 24276153 # Number of squashed instructions processed by rename 467system.cpu.rename.ROBFullEvents 24946873 # Number of times rename has blocked due to ROB full 468system.cpu.rename.IQFullEvents 2269725 # Number of times rename has blocked due to IQ full 469system.cpu.rename.LQFullEvents 41528835 # Number of times rename has blocked due to LQ full 470system.cpu.rename.SQFullEvents 1707155 # Number of times rename has blocked due to SQ full 471system.cpu.rename.RenamedOperands 1226040359 # Number of destination operands rename has renamed 472system.cpu.rename.RenameLookups 5813734095 # Number of register rename lookups that rename has made 473system.cpu.rename.int_rename_lookups 1358184137 # Number of integer rename lookups 474system.cpu.rename.fp_rename_lookups 40876447 # Number of floating rename lookups 475system.cpu.rename.CommittedMaps 874778230 # Number of HB maps that are committed 476system.cpu.rename.UndoneMaps 351262129 # Number of HB maps that are undone due to squashing 477system.cpu.rename.serializingInsts 7265 # count of serializing insts renamed 478system.cpu.rename.tempSerializingInsts 7257 # count of temporary serializing insts renamed 479system.cpu.rename.skidInsts 108789591 # count of insts added to the skid buffer 480system.cpu.memDep0.insertedLoads 367388897 # Number of loads inserted to the mem dependence unit. 481system.cpu.memDep0.insertedStores 236094901 # Number of stores inserted to the mem dependence unit. 482system.cpu.memDep0.conflictingLoads 1672944 # Number of conflicting loads. 483system.cpu.memDep0.conflictingStores 5307285 # Number of conflicting stores. 484system.cpu.iq.iqInstsAdded 1169836169 # Number of instructions added to the IQ (excludes non-spec) 485system.cpu.iq.iqNonSpecInstsAdded 12331 # Number of non-speculative instructions added to the IQ 486system.cpu.iq.iqInstsIssued 1017123135 # Number of instructions issued 487system.cpu.iq.iqSquashedInstsIssued 19093941 # Number of squashed instructions issued 488system.cpu.iq.iqSquashedInstsExamined 381123542 # Number of squashed instructions iterated over during squash; mainly for profiling 489system.cpu.iq.iqSquashedOperandsExamined 1038508983 # Number of squashed operands that are examined and possibly removed from graph 490system.cpu.iq.iqSquashedNonSpecRemoved 177 # Number of squashed non-spec instructions that were removed 491system.cpu.iq.issued_per_cycle::samples 904819618 # Number of insts issued each cycle 492system.cpu.iq.issued_per_cycle::mean 1.124117 # Number of insts issued each cycle 493system.cpu.iq.issued_per_cycle::stdev 1.093910 # Number of insts issued each cycle 494system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 495system.cpu.iq.issued_per_cycle::0 347160042 38.37% 38.37% # Number of insts issued each cycle 496system.cpu.iq.issued_per_cycle::1 227103662 25.10% 63.47% # Number of insts issued each cycle 497system.cpu.iq.issued_per_cycle::2 217769500 24.07% 87.53% # Number of insts issued each cycle 498system.cpu.iq.issued_per_cycle::3 96665190 10.68% 98.22% # Number of insts issued each cycle 499system.cpu.iq.issued_per_cycle::4 16121217 1.78% 100.00% # Number of insts issued each cycle 500system.cpu.iq.issued_per_cycle::5 7 0.00% 100.00% # Number of insts issued each cycle 501system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 502system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 503system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 504system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 505system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 506system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle 507system.cpu.iq.issued_per_cycle::total 904819618 # Number of insts issued each cycle 508system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 509system.cpu.iq.fu_full::IntAlu 63881232 18.86% 18.86% # attempts to use FU when none available 510system.cpu.iq.fu_full::IntMult 18143 0.01% 18.87% # attempts to use FU when none available 511system.cpu.iq.fu_full::IntDiv 0 0.00% 18.87% # attempts to use FU when none available 512system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.87% # attempts to use FU when none available 513system.cpu.iq.fu_full::FloatCmp 0 0.00% 18.87% # attempts to use FU when none available 514system.cpu.iq.fu_full::FloatCvt 0 0.00% 18.87% # attempts to use FU when none available 515system.cpu.iq.fu_full::FloatMult 0 0.00% 18.87% # attempts to use FU when none available 516system.cpu.iq.fu_full::FloatDiv 0 0.00% 18.87% # attempts to use FU when none available 517system.cpu.iq.fu_full::FloatSqrt 0 0.00% 18.87% # attempts to use FU when none available 518system.cpu.iq.fu_full::SimdAdd 0 0.00% 18.87% # attempts to use FU when none available 519system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 18.87% # attempts to use FU when none available 520system.cpu.iq.fu_full::SimdAlu 0 0.00% 18.87% # attempts to use FU when none available 521system.cpu.iq.fu_full::SimdCmp 0 0.00% 18.87% # attempts to use FU when none available 522system.cpu.iq.fu_full::SimdCvt 0 0.00% 18.87% # attempts to use FU when none available 523system.cpu.iq.fu_full::SimdMisc 0 0.00% 18.87% # attempts to use FU when none available 524system.cpu.iq.fu_full::SimdMult 0 0.00% 18.87% # attempts to use FU when none available 525system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 18.87% # attempts to use FU when none available 526system.cpu.iq.fu_full::SimdShift 0 0.00% 18.87% # attempts to use FU when none available 527system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.87% # attempts to use FU when none available 528system.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.87% # attempts to use FU when none available 529system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 18.87% # attempts to use FU when none available 530system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.87% # attempts to use FU when none available 531system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.87% # attempts to use FU when none available 532system.cpu.iq.fu_full::SimdFloatCvt 636889 0.19% 19.06% # attempts to use FU when none available 533system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 19.06% # attempts to use FU when none available 534system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 19.06% # attempts to use FU when none available 535system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 19.06% # attempts to use FU when none available 536system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 19.06% # attempts to use FU when none available 537system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 19.06% # attempts to use FU when none available 538system.cpu.iq.fu_full::MemRead 158064095 46.67% 65.73% # attempts to use FU when none available 539system.cpu.iq.fu_full::MemWrite 116064822 34.27% 100.00% # attempts to use FU when none available 540system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 541system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 542system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 543system.cpu.iq.FU_type_0::IntAlu 456367780 44.87% 44.87% # Type of FU issued 544system.cpu.iq.FU_type_0::IntMult 5195678 0.51% 45.38% # Type of FU issued 545system.cpu.iq.FU_type_0::IntDiv 0 0.00% 45.38% # Type of FU issued 546system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 45.38% # Type of FU issued 547system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 45.38% # Type of FU issued 548system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 45.38% # Type of FU issued 549system.cpu.iq.FU_type_0::FloatMult 0 0.00% 45.38% # Type of FU issued 550system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 45.38% # Type of FU issued 551system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 45.38% # Type of FU issued 552system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 45.38% # Type of FU issued 553system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 45.38% # Type of FU issued 554system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 45.38% # Type of FU issued 555system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 45.38% # Type of FU issued 556system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 45.38% # Type of FU issued 557system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 45.38% # Type of FU issued 558system.cpu.iq.FU_type_0::SimdMult 0 0.00% 45.38% # Type of FU issued 559system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 45.38% # Type of FU issued 560system.cpu.iq.FU_type_0::SimdShift 0 0.00% 45.38% # Type of FU issued 561system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 45.38% # Type of FU issued 562system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 45.38% # Type of FU issued 563system.cpu.iq.FU_type_0::SimdFloatAdd 637528 0.06% 45.44% # Type of FU issued 564system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 45.44% # Type of FU issued 565system.cpu.iq.FU_type_0::SimdFloatCmp 3187675 0.31% 45.76% # Type of FU issued 566system.cpu.iq.FU_type_0::SimdFloatCvt 2550147 0.25% 46.01% # Type of FU issued 567system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 46.01% # Type of FU issued 568system.cpu.iq.FU_type_0::SimdFloatMisc 11478995 1.13% 47.13% # Type of FU issued 569system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.13% # Type of FU issued 570system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.13% # Type of FU issued 571system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.13% # Type of FU issued 572system.cpu.iq.FU_type_0::MemRead 322109040 31.67% 78.80% # Type of FU issued 573system.cpu.iq.FU_type_0::MemWrite 215596292 21.20% 100.00% # Type of FU issued 574system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 575system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 576system.cpu.iq.FU_type_0::total 1017123135 # Type of FU issued 577system.cpu.iq.rate 1.123679 # Inst issue rate 578system.cpu.iq.fu_busy_cnt 338665181 # FU busy when requested 579system.cpu.iq.fu_busy_rate 0.332964 # FU busy rate (busy events/executed inst) 580system.cpu.iq.int_inst_queue_reads 3234948583 # Number of integer instruction queue reads 581system.cpu.iq.int_inst_queue_writes 1507425320 # Number of integer instruction queue writes 582system.cpu.iq.int_inst_queue_wakeup_accesses 934275773 # Number of integer instruction queue wakeup accesses 583system.cpu.iq.fp_inst_queue_reads 61876427 # Number of floating instruction queue reads 584system.cpu.iq.fp_inst_queue_writes 43565693 # Number of floating instruction queue writes 585system.cpu.iq.fp_inst_queue_wakeup_accesses 26152450 # Number of floating instruction queue wakeup accesses 586system.cpu.iq.int_alu_accesses 1321978571 # Number of integer alu accesses 587system.cpu.iq.fp_alu_accesses 33809745 # Number of floating point alu accesses 588system.cpu.iew.lsq.thread0.forwLoads 9959468 # Number of loads that had data forwarded from stores 589system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 590system.cpu.iew.lsq.thread0.squashedLoads 115147959 # Number of loads squashed 591system.cpu.iew.lsq.thread0.ignoredResponses 1090 # Number of memory responses ignored because the instruction is squashed 592system.cpu.iew.lsq.thread0.memOrderViolation 18974 # Number of memory ordering violations 593system.cpu.iew.lsq.thread0.squashedStores 107114405 # Number of stores squashed 594system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 595system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 596system.cpu.iew.lsq.thread0.rescheduledLoads 2065764 # Number of loads that were rescheduled 597system.cpu.iew.lsq.thread0.cacheBlocked 19863 # Number of times an access to memory failed due to the cache being blocked 598system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 599system.cpu.iew.iewSquashCycles 15518681 # Number of cycles IEW is squashing 600system.cpu.iew.iewBlockCycles 35329232 # Number of cycles IEW is blocking 601system.cpu.iew.iewUnblockCycles 27153 # Number of cycles IEW is unblocking 602system.cpu.iew.iewDispatchedInsts 1169854056 # Number of instructions dispatched to IQ 603system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch 604system.cpu.iew.iewDispLoadInsts 367388897 # Number of dispatched load instructions 605system.cpu.iew.iewDispStoreInsts 236094901 # Number of dispatched store instructions 606system.cpu.iew.iewDispNonSpecInsts 6591 # Number of dispatched non-speculative instructions 607system.cpu.iew.iewIQFullEvents 89 # Number of times the IQ has become full, causing a stall 608system.cpu.iew.iewLSQFullEvents 29598 # Number of times the LSQ has become full, causing a stall 609system.cpu.iew.memOrderViolationEvents 18974 # Number of memory order violations 610system.cpu.iew.predictedTakenIncorrect 15437212 # Number of branches that were predicted taken incorrectly 611system.cpu.iew.predictedNotTakenIncorrect 3784515 # Number of branches that were predicted not taken incorrectly 612system.cpu.iew.branchMispredicts 19221727 # Number of branch mispredicts detected at execute 613system.cpu.iew.iewExecutedInsts 974753111 # Number of executed instructions 614system.cpu.iew.iewExecLoadInsts 303296723 # Number of load instructions executed 615system.cpu.iew.iewExecSquashedInsts 42370024 # Number of squashed instructions skipped in execute 616system.cpu.iew.exec_swp 0 # number of swp insts executed 617system.cpu.iew.exec_nop 5556 # number of nop insts executed 618system.cpu.iew.exec_refs 497769972 # number of memory reference insts executed 619system.cpu.iew.exec_branches 150611064 # Number of branches executed 620system.cpu.iew.exec_stores 194473249 # Number of stores executed 621system.cpu.iew.exec_rate 1.076871 # Inst execution rate 622system.cpu.iew.wb_sent 963726707 # cumulative count of insts sent to commit 623system.cpu.iew.wb_count 960428223 # cumulative count of insts written-back 624system.cpu.iew.wb_producers 536045857 # num instructions producing a value 625system.cpu.iew.wb_consumers 893287669 # num instructions consuming a value 626system.cpu.iew.wb_rate 1.061045 # insts written-back per cycle 627system.cpu.iew.wb_fanout 0.600082 # average fanout of values written-back 628system.cpu.commit.commitSquashedInsts 357425551 # The number of squashed insts skipped by commit 629system.cpu.commit.commitNonSpecStalls 12154 # The number of times commit has been forced to stall to communicate backwards 630system.cpu.commit.branchMispredicts 15500881 # The number of times a branch was mispredicted 631system.cpu.commit.committed_per_cycle::samples 853996264 # Number of insts commited each cycle 632system.cpu.commit.committed_per_cycle::mean 0.923576 # Number of insts commited each cycle 633system.cpu.commit.committed_per_cycle::stdev 1.715161 # Number of insts commited each cycle 634system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 635system.cpu.commit.committed_per_cycle::0 515355287 60.35% 60.35% # Number of insts commited each cycle 636system.cpu.commit.committed_per_cycle::1 174404345 20.42% 80.77% # Number of insts commited each cycle 637system.cpu.commit.committed_per_cycle::2 72937486 8.54% 89.31% # Number of insts commited each cycle 638system.cpu.commit.committed_per_cycle::3 32899801 3.85% 93.16% # Number of insts commited each cycle 639system.cpu.commit.committed_per_cycle::4 8539084 1.00% 94.16% # Number of insts commited each cycle 640system.cpu.commit.committed_per_cycle::5 14259189 1.67% 95.83% # Number of insts commited each cycle 641system.cpu.commit.committed_per_cycle::6 7267219 0.85% 96.68% # Number of insts commited each cycle 642system.cpu.commit.committed_per_cycle::7 5975069 0.70% 97.38% # Number of insts commited each cycle 643system.cpu.commit.committed_per_cycle::8 22358784 2.62% 100.00% # Number of insts commited each cycle 644system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 645system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 646system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 647system.cpu.commit.committed_per_cycle::total 853996264 # Number of insts commited each cycle 648system.cpu.commit.committedInsts 640654411 # Number of instructions committed 649system.cpu.commit.committedOps 788730070 # Number of ops (including micro ops) committed 650system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 651system.cpu.commit.refs 381221434 # Number of memory references committed 652system.cpu.commit.loads 252240938 # Number of loads committed 653system.cpu.commit.membars 5740 # Number of memory barriers committed 654system.cpu.commit.branches 137364860 # Number of branches committed 655system.cpu.commit.fp_insts 24239771 # Number of committed floating point instructions. 656system.cpu.commit.int_insts 682251399 # Number of committed integer instructions. 657system.cpu.commit.function_calls 19275340 # Number of function calls committed. 658system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 659system.cpu.commit.op_class_0::IntAlu 385756794 48.91% 48.91% # Class of committed instruction 660system.cpu.commit.op_class_0::IntMult 5173441 0.66% 49.56% # Class of committed instruction 661system.cpu.commit.op_class_0::IntDiv 0 0.00% 49.56% # Class of committed instruction 662system.cpu.commit.op_class_0::FloatAdd 0 0.00% 49.56% # Class of committed instruction 663system.cpu.commit.op_class_0::FloatCmp 0 0.00% 49.56% # Class of committed instruction 664system.cpu.commit.op_class_0::FloatCvt 0 0.00% 49.56% # Class of committed instruction 665system.cpu.commit.op_class_0::FloatMult 0 0.00% 49.56% # Class of committed instruction 666system.cpu.commit.op_class_0::FloatDiv 0 0.00% 49.56% # Class of committed instruction 667system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 49.56% # Class of committed instruction 668system.cpu.commit.op_class_0::SimdAdd 0 0.00% 49.56% # Class of committed instruction 669system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 49.56% # Class of committed instruction 670system.cpu.commit.op_class_0::SimdAlu 0 0.00% 49.56% # Class of committed instruction 671system.cpu.commit.op_class_0::SimdCmp 0 0.00% 49.56% # Class of committed instruction 672system.cpu.commit.op_class_0::SimdCvt 0 0.00% 49.56% # Class of committed instruction 673system.cpu.commit.op_class_0::SimdMisc 0 0.00% 49.56% # Class of committed instruction 674system.cpu.commit.op_class_0::SimdMult 0 0.00% 49.56% # Class of committed instruction 675system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 49.56% # Class of committed instruction 676system.cpu.commit.op_class_0::SimdShift 0 0.00% 49.56% # Class of committed instruction 677system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 49.56% # Class of committed instruction 678system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 49.56% # Class of committed instruction 679system.cpu.commit.op_class_0::SimdFloatAdd 637528 0.08% 49.65% # Class of committed instruction 680system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 49.65% # Class of committed instruction 681system.cpu.commit.op_class_0::SimdFloatCmp 3187668 0.40% 50.05% # Class of committed instruction 682system.cpu.commit.op_class_0::SimdFloatCvt 2550131 0.32% 50.37% # Class of committed instruction 683system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 50.37% # Class of committed instruction 684system.cpu.commit.op_class_0::SimdFloatMisc 10203074 1.29% 51.67% # Class of committed instruction 685system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 51.67% # Class of committed instruction 686system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 51.67% # Class of committed instruction 687system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 51.67% # Class of committed instruction 688system.cpu.commit.op_class_0::MemRead 252240938 31.98% 83.65% # Class of committed instruction 689system.cpu.commit.op_class_0::MemWrite 128980496 16.35% 100.00% # Class of committed instruction 690system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 691system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 692system.cpu.commit.op_class_0::total 788730070 # Class of committed instruction 693system.cpu.commit.bw_lim_events 22358784 # number cycles where commit BW limit reached 694system.cpu.rob.rob_reads 1977784350 # The number of ROB reads 695system.cpu.rob.rob_writes 2343138350 # The number of ROB writes 696system.cpu.timesIdled 648611 # Number of times that the entire CPU went into an idle state and unscheduled itself 697system.cpu.idleCycles 352377 # Total number of cycles that the CPU has spent unscheduled due to idling 698system.cpu.committedInsts 640649299 # Number of Instructions Simulated 699system.cpu.committedOps 788724958 # Number of Ops (including micro ops) Simulated 700system.cpu.cpi 1.412898 # CPI: Cycles Per Instruction 701system.cpu.cpi_total 1.412898 # CPI: Total CPI of All Threads 702system.cpu.ipc 0.707765 # IPC: Instructions Per Cycle 703system.cpu.ipc_total 0.707765 # IPC: Total IPC of All Threads 704system.cpu.int_regfile_reads 995811618 # number of integer regfile reads 705system.cpu.int_regfile_writes 567906414 # number of integer regfile writes 706system.cpu.fp_regfile_reads 31889839 # number of floating regfile reads 707system.cpu.fp_regfile_writes 22959494 # number of floating regfile writes 708system.cpu.cc_regfile_reads 3794441379 # number of cc regfile reads 709system.cpu.cc_regfile_writes 384896518 # number of cc regfile writes 710system.cpu.misc_regfile_reads 715823215 # number of misc regfile reads 711system.cpu.misc_regfile_writes 6386808 # number of misc regfile writes 712system.cpu.dcache.tags.replacements 2756185 # number of replacements 713system.cpu.dcache.tags.tagsinuse 511.937157 # Cycle average of tags in use 714system.cpu.dcache.tags.total_refs 414216587 # Total number of references to valid blocks. 715system.cpu.dcache.tags.sampled_refs 2756697 # Sample count of references to valid blocks. 716system.cpu.dcache.tags.avg_refs 150.258294 # Average number of references to valid blocks. 717system.cpu.dcache.tags.warmup_cycle 267553000 # Cycle when the warmup percentage was hit. 718system.cpu.dcache.tags.occ_blocks::cpu.data 511.937157 # Average occupied blocks per requestor 719system.cpu.dcache.tags.occ_percent::cpu.data 0.999877 # Average percentage of cache occupancy 720system.cpu.dcache.tags.occ_percent::total 0.999877 # Average percentage of cache occupancy 721system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 722system.cpu.dcache.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id 723system.cpu.dcache.tags.age_task_id_blocks_1024::1 217 # Occupied blocks per task id 724system.cpu.dcache.tags.age_task_id_blocks_1024::2 199 # Occupied blocks per task id 725system.cpu.dcache.tags.age_task_id_blocks_1024::4 56 # Occupied blocks per task id 726system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 727system.cpu.dcache.tags.tag_accesses 839347973 # Number of tag accesses 728system.cpu.dcache.tags.data_accesses 839347973 # Number of data accesses 729system.cpu.dcache.ReadReq_hits::cpu.data 286293800 # number of ReadReq hits 730system.cpu.dcache.ReadReq_hits::total 286293800 # number of ReadReq hits 731system.cpu.dcache.WriteReq_hits::cpu.data 127906811 # number of WriteReq hits 732system.cpu.dcache.WriteReq_hits::total 127906811 # number of WriteReq hits 733system.cpu.dcache.SoftPFReq_hits::cpu.data 3157 # number of SoftPFReq hits 734system.cpu.dcache.SoftPFReq_hits::total 3157 # number of SoftPFReq hits 735system.cpu.dcache.LoadLockedReq_hits::cpu.data 5737 # number of LoadLockedReq hits 736system.cpu.dcache.LoadLockedReq_hits::total 5737 # number of LoadLockedReq hits 737system.cpu.dcache.StoreCondReq_hits::cpu.data 5739 # number of StoreCondReq hits 738system.cpu.dcache.StoreCondReq_hits::total 5739 # number of StoreCondReq hits 739system.cpu.dcache.demand_hits::cpu.data 414200611 # number of demand (read+write) hits 740system.cpu.dcache.demand_hits::total 414200611 # number of demand (read+write) hits 741system.cpu.dcache.overall_hits::cpu.data 414203768 # number of overall hits 742system.cpu.dcache.overall_hits::total 414203768 # number of overall hits 743system.cpu.dcache.ReadReq_misses::cpu.data 3035079 # number of ReadReq misses 744system.cpu.dcache.ReadReq_misses::total 3035079 # number of ReadReq misses 745system.cpu.dcache.WriteReq_misses::cpu.data 1044666 # number of WriteReq misses 746system.cpu.dcache.WriteReq_misses::total 1044666 # number of WriteReq misses 747system.cpu.dcache.SoftPFReq_misses::cpu.data 646 # number of SoftPFReq misses 748system.cpu.dcache.SoftPFReq_misses::total 646 # number of SoftPFReq misses 749system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses 750system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses 751system.cpu.dcache.demand_misses::cpu.data 4079745 # number of demand (read+write) misses 752system.cpu.dcache.demand_misses::total 4079745 # number of demand (read+write) misses 753system.cpu.dcache.overall_misses::cpu.data 4080391 # number of overall misses 754system.cpu.dcache.overall_misses::total 4080391 # number of overall misses 755system.cpu.dcache.ReadReq_miss_latency::cpu.data 76869214000 # number of ReadReq miss cycles 756system.cpu.dcache.ReadReq_miss_latency::total 76869214000 # number of ReadReq miss cycles 757system.cpu.dcache.WriteReq_miss_latency::cpu.data 10006334850 # number of WriteReq miss cycles 758system.cpu.dcache.WriteReq_miss_latency::total 10006334850 # number of WriteReq miss cycles 759system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 187500 # number of LoadLockedReq miss cycles 760system.cpu.dcache.LoadLockedReq_miss_latency::total 187500 # number of LoadLockedReq miss cycles 761system.cpu.dcache.demand_miss_latency::cpu.data 86875548850 # number of demand (read+write) miss cycles 762system.cpu.dcache.demand_miss_latency::total 86875548850 # number of demand (read+write) miss cycles 763system.cpu.dcache.overall_miss_latency::cpu.data 86875548850 # number of overall miss cycles 764system.cpu.dcache.overall_miss_latency::total 86875548850 # number of overall miss cycles 765system.cpu.dcache.ReadReq_accesses::cpu.data 289328879 # number of ReadReq accesses(hits+misses) 766system.cpu.dcache.ReadReq_accesses::total 289328879 # number of ReadReq accesses(hits+misses) 767system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses) 768system.cpu.dcache.WriteReq_accesses::total 128951477 # number of WriteReq accesses(hits+misses) 769system.cpu.dcache.SoftPFReq_accesses::cpu.data 3803 # number of SoftPFReq accesses(hits+misses) 770system.cpu.dcache.SoftPFReq_accesses::total 3803 # number of SoftPFReq accesses(hits+misses) 771system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5740 # number of LoadLockedReq accesses(hits+misses) 772system.cpu.dcache.LoadLockedReq_accesses::total 5740 # number of LoadLockedReq accesses(hits+misses) 773system.cpu.dcache.StoreCondReq_accesses::cpu.data 5739 # number of StoreCondReq accesses(hits+misses) 774system.cpu.dcache.StoreCondReq_accesses::total 5739 # number of StoreCondReq accesses(hits+misses) 775system.cpu.dcache.demand_accesses::cpu.data 418280356 # number of demand (read+write) accesses 776system.cpu.dcache.demand_accesses::total 418280356 # number of demand (read+write) accesses 777system.cpu.dcache.overall_accesses::cpu.data 418284159 # number of overall (read+write) accesses 778system.cpu.dcache.overall_accesses::total 418284159 # number of overall (read+write) accesses 779system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.010490 # miss rate for ReadReq accesses 780system.cpu.dcache.ReadReq_miss_rate::total 0.010490 # miss rate for ReadReq accesses 781system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.008101 # miss rate for WriteReq accesses 782system.cpu.dcache.WriteReq_miss_rate::total 0.008101 # miss rate for WriteReq accesses 783system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.169866 # miss rate for SoftPFReq accesses 784system.cpu.dcache.SoftPFReq_miss_rate::total 0.169866 # miss rate for SoftPFReq accesses 785system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000523 # miss rate for LoadLockedReq accesses 786system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000523 # miss rate for LoadLockedReq accesses 787system.cpu.dcache.demand_miss_rate::cpu.data 0.009754 # miss rate for demand accesses 788system.cpu.dcache.demand_miss_rate::total 0.009754 # miss rate for demand accesses 789system.cpu.dcache.overall_miss_rate::cpu.data 0.009755 # miss rate for overall accesses 790system.cpu.dcache.overall_miss_rate::total 0.009755 # miss rate for overall accesses 791system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 25326.923615 # average ReadReq miss latency 792system.cpu.dcache.ReadReq_avg_miss_latency::total 25326.923615 # average ReadReq miss latency 793system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 9578.501502 # average WriteReq miss latency 794system.cpu.dcache.WriteReq_avg_miss_latency::total 9578.501502 # average WriteReq miss latency 795system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 62500 # average LoadLockedReq miss latency 796system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 62500 # average LoadLockedReq miss latency 797system.cpu.dcache.demand_avg_miss_latency::cpu.data 21294.357576 # average overall miss latency 798system.cpu.dcache.demand_avg_miss_latency::total 21294.357576 # average overall miss latency 799system.cpu.dcache.overall_avg_miss_latency::cpu.data 21290.986293 # average overall miss latency 800system.cpu.dcache.overall_avg_miss_latency::total 21290.986293 # average overall miss latency 801system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 802system.cpu.dcache.blocked_cycles::no_targets 352038 # number of cycles access was blocked 803system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 804system.cpu.dcache.blocked::no_targets 4878 # number of cycles access was blocked 805system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 806system.cpu.dcache.avg_blocked_cycles::no_targets 72.168512 # average number of cycles each access was blocked 807system.cpu.dcache.fast_writes 0 # number of fast writes performed 808system.cpu.dcache.cache_copies 0 # number of cache copies performed 809system.cpu.dcache.writebacks::writebacks 2756185 # number of writebacks 810system.cpu.dcache.writebacks::total 2756185 # number of writebacks 811system.cpu.dcache.ReadReq_mshr_hits::cpu.data 999872 # number of ReadReq MSHR hits 812system.cpu.dcache.ReadReq_mshr_hits::total 999872 # number of ReadReq MSHR hits 813system.cpu.dcache.WriteReq_mshr_hits::cpu.data 323643 # number of WriteReq MSHR hits 814system.cpu.dcache.WriteReq_mshr_hits::total 323643 # number of WriteReq MSHR hits 815system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits 816system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits 817system.cpu.dcache.demand_mshr_hits::cpu.data 1323515 # number of demand (read+write) MSHR hits 818system.cpu.dcache.demand_mshr_hits::total 1323515 # number of demand (read+write) MSHR hits 819system.cpu.dcache.overall_mshr_hits::cpu.data 1323515 # number of overall MSHR hits 820system.cpu.dcache.overall_mshr_hits::total 1323515 # number of overall MSHR hits 821system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2035207 # number of ReadReq MSHR misses 822system.cpu.dcache.ReadReq_mshr_misses::total 2035207 # number of ReadReq MSHR misses 823system.cpu.dcache.WriteReq_mshr_misses::cpu.data 721023 # number of WriteReq MSHR misses 824system.cpu.dcache.WriteReq_mshr_misses::total 721023 # number of WriteReq MSHR misses 825system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 641 # number of SoftPFReq MSHR misses 826system.cpu.dcache.SoftPFReq_mshr_misses::total 641 # number of SoftPFReq MSHR misses 827system.cpu.dcache.demand_mshr_misses::cpu.data 2756230 # number of demand (read+write) MSHR misses 828system.cpu.dcache.demand_mshr_misses::total 2756230 # number of demand (read+write) MSHR misses 829system.cpu.dcache.overall_mshr_misses::cpu.data 2756871 # number of overall MSHR misses 830system.cpu.dcache.overall_mshr_misses::total 2756871 # number of overall MSHR misses 831system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 65569114500 # number of ReadReq MSHR miss cycles 832system.cpu.dcache.ReadReq_mshr_miss_latency::total 65569114500 # number of ReadReq MSHR miss cycles 833system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5957184350 # number of WriteReq MSHR miss cycles 834system.cpu.dcache.WriteReq_mshr_miss_latency::total 5957184350 # number of WriteReq MSHR miss cycles 835system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5576500 # number of SoftPFReq MSHR miss cycles 836system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5576500 # number of SoftPFReq MSHR miss cycles 837system.cpu.dcache.demand_mshr_miss_latency::cpu.data 71526298850 # number of demand (read+write) MSHR miss cycles 838system.cpu.dcache.demand_mshr_miss_latency::total 71526298850 # number of demand (read+write) MSHR miss cycles 839system.cpu.dcache.overall_mshr_miss_latency::cpu.data 71531875350 # number of overall MSHR miss cycles 840system.cpu.dcache.overall_mshr_miss_latency::total 71531875350 # number of overall MSHR miss cycles 841system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007034 # mshr miss rate for ReadReq accesses 842system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007034 # mshr miss rate for ReadReq accesses 843system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005591 # mshr miss rate for WriteReq accesses 844system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005591 # mshr miss rate for WriteReq accesses 845system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.168551 # mshr miss rate for SoftPFReq accesses 846system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.168551 # mshr miss rate for SoftPFReq accesses 847system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006589 # mshr miss rate for demand accesses 848system.cpu.dcache.demand_mshr_miss_rate::total 0.006589 # mshr miss rate for demand accesses 849system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006591 # mshr miss rate for overall accesses 850system.cpu.dcache.overall_mshr_miss_rate::total 0.006591 # mshr miss rate for overall accesses 851system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 32217.417933 # average ReadReq mshr miss latency 852system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 32217.417933 # average ReadReq mshr miss latency 853system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8262.128046 # average WriteReq mshr miss latency 854system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8262.128046 # average WriteReq mshr miss latency 855system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 8699.687988 # average SoftPFReq mshr miss latency 856system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 8699.687988 # average SoftPFReq mshr miss latency 857system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25950.772922 # average overall mshr miss latency 858system.cpu.dcache.demand_avg_mshr_miss_latency::total 25950.772922 # average overall mshr miss latency 859system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25946.761872 # average overall mshr miss latency 860system.cpu.dcache.overall_avg_mshr_miss_latency::total 25946.761872 # average overall mshr miss latency 861system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 862system.cpu.icache.tags.replacements 5169363 # number of replacements 863system.cpu.icache.tags.tagsinuse 510.872217 # Cycle average of tags in use 864system.cpu.icache.tags.total_refs 364909729 # Total number of references to valid blocks. 865system.cpu.icache.tags.sampled_refs 5169873 # Sample count of references to valid blocks. 866system.cpu.icache.tags.avg_refs 70.583886 # Average number of references to valid blocks. 867system.cpu.icache.tags.warmup_cycle 257528500 # Cycle when the warmup percentage was hit. 868system.cpu.icache.tags.occ_blocks::cpu.inst 510.872217 # Average occupied blocks per requestor 869system.cpu.icache.tags.occ_percent::cpu.inst 0.997797 # Average percentage of cache occupancy 870system.cpu.icache.tags.occ_percent::total 0.997797 # Average percentage of cache occupancy 871system.cpu.icache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id 872system.cpu.icache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id 873system.cpu.icache.tags.age_task_id_blocks_1024::1 121 # Occupied blocks per task id 874system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id 875system.cpu.icache.tags.age_task_id_blocks_1024::4 328 # Occupied blocks per task id 876system.cpu.icache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id 877system.cpu.icache.tags.tag_accesses 745337941 # Number of tag accesses 878system.cpu.icache.tags.data_accesses 745337941 # Number of data accesses 879system.cpu.icache.ReadReq_hits::cpu.inst 364909744 # number of ReadReq hits 880system.cpu.icache.ReadReq_hits::total 364909744 # number of ReadReq hits 881system.cpu.icache.demand_hits::cpu.inst 364909744 # number of demand (read+write) hits 882system.cpu.icache.demand_hits::total 364909744 # number of demand (read+write) hits 883system.cpu.icache.overall_hits::cpu.inst 364909744 # number of overall hits 884system.cpu.icache.overall_hits::total 364909744 # number of overall hits 885system.cpu.icache.ReadReq_misses::cpu.inst 5174203 # number of ReadReq misses 886system.cpu.icache.ReadReq_misses::total 5174203 # number of ReadReq misses 887system.cpu.icache.demand_misses::cpu.inst 5174203 # number of demand (read+write) misses 888system.cpu.icache.demand_misses::total 5174203 # number of demand (read+write) misses 889system.cpu.icache.overall_misses::cpu.inst 5174203 # number of overall misses 890system.cpu.icache.overall_misses::total 5174203 # number of overall misses 891system.cpu.icache.ReadReq_miss_latency::cpu.inst 41972246420 # number of ReadReq miss cycles 892system.cpu.icache.ReadReq_miss_latency::total 41972246420 # number of ReadReq miss cycles 893system.cpu.icache.demand_miss_latency::cpu.inst 41972246420 # number of demand (read+write) miss cycles 894system.cpu.icache.demand_miss_latency::total 41972246420 # number of demand (read+write) miss cycles 895system.cpu.icache.overall_miss_latency::cpu.inst 41972246420 # number of overall miss cycles 896system.cpu.icache.overall_miss_latency::total 41972246420 # number of overall miss cycles 897system.cpu.icache.ReadReq_accesses::cpu.inst 370083947 # number of ReadReq accesses(hits+misses) 898system.cpu.icache.ReadReq_accesses::total 370083947 # number of ReadReq accesses(hits+misses) 899system.cpu.icache.demand_accesses::cpu.inst 370083947 # number of demand (read+write) accesses 900system.cpu.icache.demand_accesses::total 370083947 # number of demand (read+write) accesses 901system.cpu.icache.overall_accesses::cpu.inst 370083947 # number of overall (read+write) accesses 902system.cpu.icache.overall_accesses::total 370083947 # number of overall (read+write) accesses 903system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013981 # miss rate for ReadReq accesses 904system.cpu.icache.ReadReq_miss_rate::total 0.013981 # miss rate for ReadReq accesses 905system.cpu.icache.demand_miss_rate::cpu.inst 0.013981 # miss rate for demand accesses 906system.cpu.icache.demand_miss_rate::total 0.013981 # miss rate for demand accesses 907system.cpu.icache.overall_miss_rate::cpu.inst 0.013981 # miss rate for overall accesses 908system.cpu.icache.overall_miss_rate::total 0.013981 # miss rate for overall accesses 909system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8111.828318 # average ReadReq miss latency 910system.cpu.icache.ReadReq_avg_miss_latency::total 8111.828318 # average ReadReq miss latency 911system.cpu.icache.demand_avg_miss_latency::cpu.inst 8111.828318 # average overall miss latency 912system.cpu.icache.demand_avg_miss_latency::total 8111.828318 # average overall miss latency 913system.cpu.icache.overall_avg_miss_latency::cpu.inst 8111.828318 # average overall miss latency 914system.cpu.icache.overall_avg_miss_latency::total 8111.828318 # average overall miss latency 915system.cpu.icache.blocked_cycles::no_mshrs 80154 # number of cycles access was blocked 916system.cpu.icache.blocked_cycles::no_targets 135 # number of cycles access was blocked 917system.cpu.icache.blocked::no_mshrs 3667 # number of cycles access was blocked 918system.cpu.icache.blocked::no_targets 5 # number of cycles access was blocked 919system.cpu.icache.avg_blocked_cycles::no_mshrs 21.858195 # average number of cycles each access was blocked 920system.cpu.icache.avg_blocked_cycles::no_targets 27 # average number of cycles each access was blocked 921system.cpu.icache.fast_writes 0 # number of fast writes performed 922system.cpu.icache.cache_copies 0 # number of cache copies performed 923system.cpu.icache.writebacks::writebacks 5169363 # number of writebacks 924system.cpu.icache.writebacks::total 5169363 # number of writebacks 925system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4154 # number of ReadReq MSHR hits 926system.cpu.icache.ReadReq_mshr_hits::total 4154 # number of ReadReq MSHR hits 927system.cpu.icache.demand_mshr_hits::cpu.inst 4154 # number of demand (read+write) MSHR hits 928system.cpu.icache.demand_mshr_hits::total 4154 # number of demand (read+write) MSHR hits 929system.cpu.icache.overall_mshr_hits::cpu.inst 4154 # number of overall MSHR hits 930system.cpu.icache.overall_mshr_hits::total 4154 # number of overall MSHR hits 931system.cpu.icache.ReadReq_mshr_misses::cpu.inst 5170049 # number of ReadReq MSHR misses 932system.cpu.icache.ReadReq_mshr_misses::total 5170049 # number of ReadReq MSHR misses 933system.cpu.icache.demand_mshr_misses::cpu.inst 5170049 # number of demand (read+write) MSHR misses 934system.cpu.icache.demand_mshr_misses::total 5170049 # number of demand (read+write) MSHR misses 935system.cpu.icache.overall_mshr_misses::cpu.inst 5170049 # number of overall MSHR misses 936system.cpu.icache.overall_mshr_misses::total 5170049 # number of overall MSHR misses 937system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 39346514434 # number of ReadReq MSHR miss cycles 938system.cpu.icache.ReadReq_mshr_miss_latency::total 39346514434 # number of ReadReq MSHR miss cycles 939system.cpu.icache.demand_mshr_miss_latency::cpu.inst 39346514434 # number of demand (read+write) MSHR miss cycles 940system.cpu.icache.demand_mshr_miss_latency::total 39346514434 # number of demand (read+write) MSHR miss cycles 941system.cpu.icache.overall_mshr_miss_latency::cpu.inst 39346514434 # number of overall MSHR miss cycles 942system.cpu.icache.overall_mshr_miss_latency::total 39346514434 # number of overall MSHR miss cycles 943system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.013970 # mshr miss rate for ReadReq accesses 944system.cpu.icache.ReadReq_mshr_miss_rate::total 0.013970 # mshr miss rate for ReadReq accesses 945system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.013970 # mshr miss rate for demand accesses 946system.cpu.icache.demand_mshr_miss_rate::total 0.013970 # mshr miss rate for demand accesses 947system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.013970 # mshr miss rate for overall accesses 948system.cpu.icache.overall_mshr_miss_rate::total 0.013970 # mshr miss rate for overall accesses 949system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 7610.472248 # average ReadReq mshr miss latency 950system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 7610.472248 # average ReadReq mshr miss latency 951system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 7610.472248 # average overall mshr miss latency 952system.cpu.icache.demand_avg_mshr_miss_latency::total 7610.472248 # average overall mshr miss latency 953system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 7610.472248 # average overall mshr miss latency 954system.cpu.icache.overall_avg_mshr_miss_latency::total 7610.472248 # average overall mshr miss latency 955system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 956system.cpu.l2cache.prefetcher.num_hwpf_issued 1350388 # number of hwpf issued 957system.cpu.l2cache.prefetcher.pfIdentified 1355069 # number of prefetch candidates identified 958system.cpu.l2cache.prefetcher.pfBufferHit 4095 # number of redundant prefetches already in prefetch queue 959system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 960system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 961system.cpu.l2cache.prefetcher.pfSpanPage 4790235 # number of prefetches not generated due to page crossing 962system.cpu.l2cache.tags.replacements 301561 # number of replacements 963system.cpu.l2cache.tags.tagsinuse 16356.089687 # Cycle average of tags in use 964system.cpu.l2cache.tags.total_refs 13502376 # Total number of references to valid blocks. 965system.cpu.l2cache.tags.sampled_refs 317924 # Sample count of references to valid blocks. 966system.cpu.l2cache.tags.avg_refs 42.470452 # Average number of references to valid blocks. 967system.cpu.l2cache.tags.warmup_cycle 60356537500 # Cycle when the warmup percentage was hit. 968system.cpu.l2cache.tags.occ_blocks::writebacks 9847.960617 # Average occupied blocks per requestor 969system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 6508.129070 # Average occupied blocks per requestor 970system.cpu.l2cache.tags.occ_percent::writebacks 0.601072 # Average percentage of cache occupancy 971system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.397225 # Average percentage of cache occupancy 972system.cpu.l2cache.tags.occ_percent::total 0.998296 # Average percentage of cache occupancy 973system.cpu.l2cache.tags.occ_task_id_blocks::1022 6319 # Occupied blocks per task id 974system.cpu.l2cache.tags.occ_task_id_blocks::1024 10044 # Occupied blocks per task id 975system.cpu.l2cache.tags.age_task_id_blocks_1022::1 15 # Occupied blocks per task id 976system.cpu.l2cache.tags.age_task_id_blocks_1022::2 137 # Occupied blocks per task id 977system.cpu.l2cache.tags.age_task_id_blocks_1022::3 1300 # Occupied blocks per task id 978system.cpu.l2cache.tags.age_task_id_blocks_1022::4 4867 # Occupied blocks per task id 979system.cpu.l2cache.tags.age_task_id_blocks_1024::0 60 # Occupied blocks per task id 980system.cpu.l2cache.tags.age_task_id_blocks_1024::1 134 # Occupied blocks per task id 981system.cpu.l2cache.tags.age_task_id_blocks_1024::2 224 # Occupied blocks per task id 982system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1968 # Occupied blocks per task id 983system.cpu.l2cache.tags.age_task_id_blocks_1024::4 7658 # Occupied blocks per task id 984system.cpu.l2cache.tags.occ_task_id_percent::1022 0.385681 # Percentage of cache occupancy per task id 985system.cpu.l2cache.tags.occ_task_id_percent::1024 0.613037 # Percentage of cache occupancy per task id 986system.cpu.l2cache.tags.tag_accesses 244381666 # Number of tag accesses 987system.cpu.l2cache.tags.data_accesses 244381666 # Number of data accesses 988system.cpu.l2cache.WritebackDirty_hits::writebacks 735261 # number of WritebackDirty hits 989system.cpu.l2cache.WritebackDirty_hits::total 735261 # number of WritebackDirty hits 990system.cpu.l2cache.WritebackClean_hits::writebacks 6546111 # number of WritebackClean hits 991system.cpu.l2cache.WritebackClean_hits::total 6546111 # number of WritebackClean hits 992system.cpu.l2cache.ReadExReq_hits::cpu.data 718464 # number of ReadExReq hits 993system.cpu.l2cache.ReadExReq_hits::total 718464 # number of ReadExReq hits 994system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 5166212 # number of ReadCleanReq hits 995system.cpu.l2cache.ReadCleanReq_hits::total 5166212 # number of ReadCleanReq hits 996system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1286380 # number of ReadSharedReq hits 997system.cpu.l2cache.ReadSharedReq_hits::total 1286380 # number of ReadSharedReq hits 998system.cpu.l2cache.demand_hits::cpu.inst 5166212 # number of demand (read+write) hits 999system.cpu.l2cache.demand_hits::cpu.data 2004844 # number of demand (read+write) hits 1000system.cpu.l2cache.demand_hits::total 7171056 # number of demand (read+write) hits 1001system.cpu.l2cache.overall_hits::cpu.inst 5166212 # number of overall hits 1002system.cpu.l2cache.overall_hits::cpu.data 2004844 # number of overall hits 1003system.cpu.l2cache.overall_hits::total 7171056 # number of overall hits 1004system.cpu.l2cache.UpgradeReq_misses::cpu.data 174 # number of UpgradeReq misses 1005system.cpu.l2cache.UpgradeReq_misses::total 174 # number of UpgradeReq misses 1006system.cpu.l2cache.ReadExReq_misses::cpu.data 2385 # number of ReadExReq misses 1007system.cpu.l2cache.ReadExReq_misses::total 2385 # number of ReadExReq misses 1008system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3664 # number of ReadCleanReq misses 1009system.cpu.l2cache.ReadCleanReq_misses::total 3664 # number of ReadCleanReq misses 1010system.cpu.l2cache.ReadSharedReq_misses::cpu.data 749468 # number of ReadSharedReq misses 1011system.cpu.l2cache.ReadSharedReq_misses::total 749468 # number of ReadSharedReq misses 1012system.cpu.l2cache.demand_misses::cpu.inst 3664 # number of demand (read+write) misses 1013system.cpu.l2cache.demand_misses::cpu.data 751853 # number of demand (read+write) misses 1014system.cpu.l2cache.demand_misses::total 755517 # number of demand (read+write) misses 1015system.cpu.l2cache.overall_misses::cpu.inst 3664 # number of overall misses 1016system.cpu.l2cache.overall_misses::cpu.data 751853 # number of overall misses 1017system.cpu.l2cache.overall_misses::total 755517 # number of overall misses 1018system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 195908500 # number of ReadExReq miss cycles 1019system.cpu.l2cache.ReadExReq_miss_latency::total 195908500 # number of ReadExReq miss cycles 1020system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 270114500 # number of ReadCleanReq miss cycles 1021system.cpu.l2cache.ReadCleanReq_miss_latency::total 270114500 # number of ReadCleanReq miss cycles 1022system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 54154115500 # number of ReadSharedReq miss cycles 1023system.cpu.l2cache.ReadSharedReq_miss_latency::total 54154115500 # number of ReadSharedReq miss cycles 1024system.cpu.l2cache.demand_miss_latency::cpu.inst 270114500 # number of demand (read+write) miss cycles 1025system.cpu.l2cache.demand_miss_latency::cpu.data 54350024000 # number of demand (read+write) miss cycles 1026system.cpu.l2cache.demand_miss_latency::total 54620138500 # number of demand (read+write) miss cycles 1027system.cpu.l2cache.overall_miss_latency::cpu.inst 270114500 # number of overall miss cycles 1028system.cpu.l2cache.overall_miss_latency::cpu.data 54350024000 # number of overall miss cycles 1029system.cpu.l2cache.overall_miss_latency::total 54620138500 # number of overall miss cycles 1030system.cpu.l2cache.WritebackDirty_accesses::writebacks 735261 # number of WritebackDirty accesses(hits+misses) 1031system.cpu.l2cache.WritebackDirty_accesses::total 735261 # number of WritebackDirty accesses(hits+misses) 1032system.cpu.l2cache.WritebackClean_accesses::writebacks 6546111 # number of WritebackClean accesses(hits+misses) 1033system.cpu.l2cache.WritebackClean_accesses::total 6546111 # number of WritebackClean accesses(hits+misses) 1034system.cpu.l2cache.UpgradeReq_accesses::cpu.data 174 # number of UpgradeReq accesses(hits+misses) 1035system.cpu.l2cache.UpgradeReq_accesses::total 174 # number of UpgradeReq accesses(hits+misses) 1036system.cpu.l2cache.ReadExReq_accesses::cpu.data 720849 # number of ReadExReq accesses(hits+misses) 1037system.cpu.l2cache.ReadExReq_accesses::total 720849 # number of ReadExReq accesses(hits+misses) 1038system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 5169876 # number of ReadCleanReq accesses(hits+misses) 1039system.cpu.l2cache.ReadCleanReq_accesses::total 5169876 # number of ReadCleanReq accesses(hits+misses) 1040system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 2035848 # number of ReadSharedReq accesses(hits+misses) 1041system.cpu.l2cache.ReadSharedReq_accesses::total 2035848 # number of ReadSharedReq accesses(hits+misses) 1042system.cpu.l2cache.demand_accesses::cpu.inst 5169876 # number of demand (read+write) accesses 1043system.cpu.l2cache.demand_accesses::cpu.data 2756697 # number of demand (read+write) accesses 1044system.cpu.l2cache.demand_accesses::total 7926573 # number of demand (read+write) accesses 1045system.cpu.l2cache.overall_accesses::cpu.inst 5169876 # number of overall (read+write) accesses 1046system.cpu.l2cache.overall_accesses::cpu.data 2756697 # number of overall (read+write) accesses 1047system.cpu.l2cache.overall_accesses::total 7926573 # number of overall (read+write) accesses 1048system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses 1049system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses 1050system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.003309 # miss rate for ReadExReq accesses 1051system.cpu.l2cache.ReadExReq_miss_rate::total 0.003309 # miss rate for ReadExReq accesses 1052system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.000709 # miss rate for ReadCleanReq accesses 1053system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.000709 # miss rate for ReadCleanReq accesses 1054system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.368136 # miss rate for ReadSharedReq accesses 1055system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.368136 # miss rate for ReadSharedReq accesses 1056system.cpu.l2cache.demand_miss_rate::cpu.inst 0.000709 # miss rate for demand accesses 1057system.cpu.l2cache.demand_miss_rate::cpu.data 0.272737 # miss rate for demand accesses 1058system.cpu.l2cache.demand_miss_rate::total 0.095314 # miss rate for demand accesses 1059system.cpu.l2cache.overall_miss_rate::cpu.inst 0.000709 # miss rate for overall accesses 1060system.cpu.l2cache.overall_miss_rate::cpu.data 0.272737 # miss rate for overall accesses 1061system.cpu.l2cache.overall_miss_rate::total 0.095314 # miss rate for overall accesses 1062system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 82141.928721 # average ReadExReq miss latency 1063system.cpu.l2cache.ReadExReq_avg_miss_latency::total 82141.928721 # average ReadExReq miss latency 1064system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 73721.206332 # average ReadCleanReq miss latency 1065system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 73721.206332 # average ReadCleanReq miss latency 1066system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 72256.741449 # average ReadSharedReq miss latency 1067system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 72256.741449 # average ReadSharedReq miss latency 1068system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73721.206332 # average overall miss latency 1069system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72288.098870 # average overall miss latency 1070system.cpu.l2cache.demand_avg_miss_latency::total 72295.048953 # average overall miss latency 1071system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73721.206332 # average overall miss latency 1072system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72288.098870 # average overall miss latency 1073system.cpu.l2cache.overall_avg_miss_latency::total 72295.048953 # average overall miss latency 1074system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1075system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1076system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1077system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1078system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1079system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1080system.cpu.l2cache.fast_writes 0 # number of fast writes performed 1081system.cpu.l2cache.cache_copies 0 # number of cache copies performed 1082system.cpu.l2cache.writebacks::writebacks 66305 # number of writebacks 1083system.cpu.l2cache.writebacks::total 66305 # number of writebacks 1084system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 1019 # number of ReadExReq MSHR hits 1085system.cpu.l2cache.ReadExReq_mshr_hits::total 1019 # number of ReadExReq MSHR hits 1086system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits 1087system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits 1088system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 872 # number of ReadSharedReq MSHR hits 1089system.cpu.l2cache.ReadSharedReq_mshr_hits::total 872 # number of ReadSharedReq MSHR hits 1090system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits 1091system.cpu.l2cache.demand_mshr_hits::cpu.data 1891 # number of demand (read+write) MSHR hits 1092system.cpu.l2cache.demand_mshr_hits::total 1892 # number of demand (read+write) MSHR hits 1093system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits 1094system.cpu.l2cache.overall_mshr_hits::cpu.data 1891 # number of overall MSHR hits 1095system.cpu.l2cache.overall_mshr_hits::total 1892 # number of overall MSHR hits 1096system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 200528 # number of HardPFReq MSHR misses 1097system.cpu.l2cache.HardPFReq_mshr_misses::total 200528 # number of HardPFReq MSHR misses 1098system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 174 # number of UpgradeReq MSHR misses 1099system.cpu.l2cache.UpgradeReq_mshr_misses::total 174 # number of UpgradeReq MSHR misses 1100system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1366 # number of ReadExReq MSHR misses 1101system.cpu.l2cache.ReadExReq_mshr_misses::total 1366 # number of ReadExReq MSHR misses 1102system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3663 # number of ReadCleanReq MSHR misses 1103system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3663 # number of ReadCleanReq MSHR misses 1104system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 748596 # number of ReadSharedReq MSHR misses 1105system.cpu.l2cache.ReadSharedReq_mshr_misses::total 748596 # number of ReadSharedReq MSHR misses 1106system.cpu.l2cache.demand_mshr_misses::cpu.inst 3663 # number of demand (read+write) MSHR misses 1107system.cpu.l2cache.demand_mshr_misses::cpu.data 749962 # number of demand (read+write) MSHR misses 1108system.cpu.l2cache.demand_mshr_misses::total 753625 # number of demand (read+write) MSHR misses 1109system.cpu.l2cache.overall_mshr_misses::cpu.inst 3663 # number of overall MSHR misses 1110system.cpu.l2cache.overall_mshr_misses::cpu.data 749962 # number of overall MSHR misses 1111system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 200528 # number of overall MSHR misses 1112system.cpu.l2cache.overall_mshr_misses::total 954153 # number of overall MSHR misses 1113system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 16518025996 # number of HardPFReq MSHR miss cycles 1114system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 16518025996 # number of HardPFReq MSHR miss cycles 1115system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 2993500 # number of UpgradeReq MSHR miss cycles 1116system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 2993500 # number of UpgradeReq MSHR miss cycles 1117system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 133767000 # number of ReadExReq MSHR miss cycles 1118system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 133767000 # number of ReadExReq MSHR miss cycles 1119system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 248088000 # number of ReadCleanReq MSHR miss cycles 1120system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 248088000 # number of ReadCleanReq MSHR miss cycles 1121system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 49620654000 # number of ReadSharedReq MSHR miss cycles 1122system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 49620654000 # number of ReadSharedReq MSHR miss cycles 1123system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 248088000 # number of demand (read+write) MSHR miss cycles 1124system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 49754421000 # number of demand (read+write) MSHR miss cycles 1125system.cpu.l2cache.demand_mshr_miss_latency::total 50002509000 # number of demand (read+write) MSHR miss cycles 1126system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 248088000 # number of overall MSHR miss cycles 1127system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 49754421000 # number of overall MSHR miss cycles 1128system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 16518025996 # number of overall MSHR miss cycles 1129system.cpu.l2cache.overall_mshr_miss_latency::total 66520534996 # number of overall MSHR miss cycles 1130system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1131system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 1132system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses 1133system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses 1134system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001895 # mshr miss rate for ReadExReq accesses 1135system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001895 # mshr miss rate for ReadExReq accesses 1136system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.000709 # mshr miss rate for ReadCleanReq accesses 1137system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.000709 # mshr miss rate for ReadCleanReq accesses 1138system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.367707 # mshr miss rate for ReadSharedReq accesses 1139system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.367707 # mshr miss rate for ReadSharedReq accesses 1140system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.000709 # mshr miss rate for demand accesses 1141system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.272051 # mshr miss rate for demand accesses 1142system.cpu.l2cache.demand_mshr_miss_rate::total 0.095076 # mshr miss rate for demand accesses 1143system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.000709 # mshr miss rate for overall accesses 1144system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.272051 # mshr miss rate for overall accesses 1145system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses 1146system.cpu.l2cache.overall_mshr_miss_rate::total 0.120374 # mshr miss rate for overall accesses 1147system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 82372.666141 # average HardPFReq mshr miss latency 1148system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 82372.666141 # average HardPFReq mshr miss latency 1149system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17204.022989 # average UpgradeReq mshr miss latency 1150system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17204.022989 # average UpgradeReq mshr miss latency 1151system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 97926.061493 # average ReadExReq mshr miss latency 1152system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 97926.061493 # average ReadExReq mshr miss latency 1153system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67728.091728 # average ReadCleanReq mshr miss latency 1154system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67728.091728 # average ReadCleanReq mshr miss latency 1155system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 66284.957440 # average ReadSharedReq mshr miss latency 1156system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 66284.957440 # average ReadSharedReq mshr miss latency 1157system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67728.091728 # average overall mshr miss latency 1158system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66342.589358 # average overall mshr miss latency 1159system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66349.323603 # average overall mshr miss latency 1160system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67728.091728 # average overall mshr miss latency 1161system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66342.589358 # average overall mshr miss latency 1162system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 82372.666141 # average overall mshr miss latency 1163system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69716.843102 # average overall mshr miss latency 1164system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1165system.cpu.toL2Bus.snoop_filter.tot_requests 15852468 # Total number of requests made to the snoop filter. 1166system.cpu.toL2Bus.snoop_filter.hit_single_requests 7925752 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1167system.cpu.toL2Bus.snoop_filter.hit_multi_requests 644350 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1168system.cpu.toL2Bus.snoop_filter.tot_snoops 760150 # Total number of snoops made to the snoop filter. 1169system.cpu.toL2Bus.snoop_filter.hit_single_snoops 116849 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1170system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 643301 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1171system.cpu.toL2Bus.trans_dist::ReadResp 7205895 # Transaction distribution 1172system.cpu.toL2Bus.trans_dist::WritebackDirty 801566 # Transaction distribution 1173system.cpu.toL2Bus.trans_dist::WritebackClean 6546111 # Transaction distribution 1174system.cpu.toL2Bus.trans_dist::CleanEvict 987513 # Transaction distribution 1175system.cpu.toL2Bus.trans_dist::HardPFReq 243924 # Transaction distribution 1176system.cpu.toL2Bus.trans_dist::UpgradeReq 174 # Transaction distribution 1177system.cpu.toL2Bus.trans_dist::UpgradeResp 174 # Transaction distribution 1178system.cpu.toL2Bus.trans_dist::ReadExReq 720849 # Transaction distribution 1179system.cpu.toL2Bus.trans_dist::ReadExResp 720849 # Transaction distribution 1180system.cpu.toL2Bus.trans_dist::ReadCleanReq 5170049 # Transaction distribution 1181system.cpu.toL2Bus.trans_dist::ReadSharedReq 2035848 # Transaction distribution 1182system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 15508407 # Packet count per connected master and slave (bytes) 1183system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7626630 # Packet count per connected master and slave (bytes) 1184system.cpu.toL2Bus.pkt_count::total 23135037 # Packet count per connected master and slave (bytes) 1185system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 661654912 # Cumulative packet size per connected master and slave (bytes) 1186system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 311653440 # Cumulative packet size per connected master and slave (bytes) 1187system.cpu.toL2Bus.pkt_size::total 973308352 # Cumulative packet size per connected master and slave (bytes) 1188system.cpu.toL2Bus.snoops 1297915 # Total snoops (count) 1189system.cpu.toL2Bus.snoop_fanout::samples 9224662 # Request fanout histogram 1190system.cpu.toL2Bus.snoop_fanout::mean 0.222014 # Request fanout histogram 1191system.cpu.toL2Bus.snoop_fanout::stdev 0.558747 # Request fanout histogram 1192system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1193system.cpu.toL2Bus.snoop_fanout::0 7819958 84.77% 84.77% # Request fanout histogram 1194system.cpu.toL2Bus.snoop_fanout::1 761403 8.25% 93.03% # Request fanout histogram 1195system.cpu.toL2Bus.snoop_fanout::2 643301 6.97% 100.00% # Request fanout histogram 1196system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1197system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1198system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 1199system.cpu.toL2Bus.snoop_fanout::total 9224662 # Request fanout histogram 1200system.cpu.toL2Bus.reqLayer0.occupancy 15851782000 # Layer occupancy (ticks) 1201system.cpu.toL2Bus.reqLayer0.utilization 3.5 # Layer utilization (%) 1202system.cpu.toL2Bus.respLayer0.occupancy 7755313513 # Layer occupancy (ticks) 1203system.cpu.toL2Bus.respLayer0.utilization 1.7 # Layer utilization (%) 1204system.cpu.toL2Bus.respLayer1.occupancy 4135165933 # Layer occupancy (ticks) 1205system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) 1206system.membus.trans_dist::ReadResp 952696 # Transaction distribution 1207system.membus.trans_dist::WritebackDirty 66305 # Transaction distribution 1208system.membus.trans_dist::CleanEvict 227453 # Transaction distribution 1209system.membus.trans_dist::UpgradeReq 174 # Transaction distribution 1210system.membus.trans_dist::UpgradeResp 174 # Transaction distribution 1211system.membus.trans_dist::ReadExReq 1366 # Transaction distribution 1212system.membus.trans_dist::ReadExResp 1366 # Transaction distribution 1213system.membus.trans_dist::ReadSharedReq 952697 # Transaction distribution 1214system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2202231 # Packet count per connected master and slave (bytes) 1215system.membus.pkt_count::total 2202231 # Packet count per connected master and slave (bytes) 1216system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 65303488 # Cumulative packet size per connected master and slave (bytes) 1217system.membus.pkt_size::total 65303488 # Cumulative packet size per connected master and slave (bytes) 1218system.membus.snoops 0 # Total snoops (count) 1219system.membus.snoop_fanout::samples 1247995 # Request fanout histogram 1220system.membus.snoop_fanout::mean 0 # Request fanout histogram 1221system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1222system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1223system.membus.snoop_fanout::0 1247995 100.00% 100.00% # Request fanout histogram 1224system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 1225system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1226system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1227system.membus.snoop_fanout::max_value 0 # Request fanout histogram 1228system.membus.snoop_fanout::total 1247995 # Request fanout histogram 1229system.membus.reqLayer0.occupancy 1752388071 # Layer occupancy (ticks) 1230system.membus.reqLayer0.utilization 0.4 # Layer utilization (%) 1231system.membus.respLayer1.occupancy 5021031104 # Layer occupancy (ticks) 1232system.membus.respLayer1.utilization 1.1 # Layer utilization (%) 1233 1234---------- End Simulation Statistics ---------- 1235