stats.txt revision 10827:7f5467f2f8b8
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.409388 # Number of seconds simulated 4sim_ticks 409388416000 # Number of ticks simulated 5final_tick 409388416000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 93306 # Simulator instruction rate (inst/s) 8host_op_rate 114872 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 59624294 # Simulator tick rate (ticks/s) 10host_mem_usage 320320 # Number of bytes of host memory used 11host_seconds 6866.13 # Real time elapsed on the host 12sim_insts 640649299 # Number of instructions simulated 13sim_ops 788724958 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 226560 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 7024000 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.l2cache.prefetcher 12938624 # Number of bytes read from this memory 19system.physmem.bytes_read::total 20189184 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 226560 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 226560 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 4245888 # Number of bytes written to this memory 23system.physmem.bytes_written::total 4245888 # Number of bytes written to this memory 24system.physmem.num_reads::cpu.inst 3540 # Number of read requests responded to by this memory 25system.physmem.num_reads::cpu.data 109750 # Number of read requests responded to by this memory 26system.physmem.num_reads::cpu.l2cache.prefetcher 202166 # Number of read requests responded to by this memory 27system.physmem.num_reads::total 315456 # Number of read requests responded to by this memory 28system.physmem.num_writes::writebacks 66342 # Number of write requests responded to by this memory 29system.physmem.num_writes::total 66342 # Number of write requests responded to by this memory 30system.physmem.bw_read::cpu.inst 553411 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_read::cpu.data 17157300 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_read::cpu.l2cache.prefetcher 31604763 # Total read bandwidth from this memory (bytes/s) 33system.physmem.bw_read::total 49315475 # Total read bandwidth from this memory (bytes/s) 34system.physmem.bw_inst_read::cpu.inst 553411 # Instruction read bandwidth from this memory (bytes/s) 35system.physmem.bw_inst_read::total 553411 # Instruction read bandwidth from this memory (bytes/s) 36system.physmem.bw_write::writebacks 10371295 # Write bandwidth from this memory (bytes/s) 37system.physmem.bw_write::total 10371295 # Write bandwidth from this memory (bytes/s) 38system.physmem.bw_total::writebacks 10371295 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.bw_total::cpu.inst 553411 # Total bandwidth to/from this memory (bytes/s) 40system.physmem.bw_total::cpu.data 17157300 # Total bandwidth to/from this memory (bytes/s) 41system.physmem.bw_total::cpu.l2cache.prefetcher 31604763 # Total bandwidth to/from this memory (bytes/s) 42system.physmem.bw_total::total 59686769 # Total bandwidth to/from this memory (bytes/s) 43system.physmem.readReqs 315456 # Number of read requests accepted 44system.physmem.writeReqs 66342 # Number of write requests accepted 45system.physmem.readBursts 315456 # Number of DRAM read bursts, including those serviced by the write queue 46system.physmem.writeBursts 66342 # Number of DRAM write bursts, including those merged in the write queue 47system.physmem.bytesReadDRAM 20169600 # Total number of bytes read from DRAM 48system.physmem.bytesReadWrQ 19584 # Total number of bytes read from write queue 49system.physmem.bytesWritten 4238784 # Total number of bytes written to DRAM 50system.physmem.bytesReadSys 20189184 # Total read bytes from the system interface side 51system.physmem.bytesWrittenSys 4245888 # Total written bytes from the system interface side 52system.physmem.servicedByWrQ 306 # Number of DRAM read bursts serviced by the write queue 53system.physmem.mergedWrBursts 81 # Number of DRAM write bursts merged with an existing one 54system.physmem.neitherReadNorWriteReqs 19 # Number of requests that are neither read nor write 55system.physmem.perBankRdBursts::0 19899 # Per bank write bursts 56system.physmem.perBankRdBursts::1 19575 # Per bank write bursts 57system.physmem.perBankRdBursts::2 19715 # Per bank write bursts 58system.physmem.perBankRdBursts::3 19833 # Per bank write bursts 59system.physmem.perBankRdBursts::4 19635 # Per bank write bursts 60system.physmem.perBankRdBursts::5 20130 # Per bank write bursts 61system.physmem.perBankRdBursts::6 19631 # Per bank write bursts 62system.physmem.perBankRdBursts::7 19419 # Per bank write bursts 63system.physmem.perBankRdBursts::8 19547 # Per bank write bursts 64system.physmem.perBankRdBursts::9 19463 # Per bank write bursts 65system.physmem.perBankRdBursts::10 19540 # Per bank write bursts 66system.physmem.perBankRdBursts::11 19765 # Per bank write bursts 67system.physmem.perBankRdBursts::12 19604 # Per bank write bursts 68system.physmem.perBankRdBursts::13 19959 # Per bank write bursts 69system.physmem.perBankRdBursts::14 19457 # Per bank write bursts 70system.physmem.perBankRdBursts::15 19978 # Per bank write bursts 71system.physmem.perBankWrBursts::0 4260 # Per bank write bursts 72system.physmem.perBankWrBursts::1 4107 # Per bank write bursts 73system.physmem.perBankWrBursts::2 4142 # Per bank write bursts 74system.physmem.perBankWrBursts::3 4156 # Per bank write bursts 75system.physmem.perBankWrBursts::4 4244 # Per bank write bursts 76system.physmem.perBankWrBursts::5 4228 # Per bank write bursts 77system.physmem.perBankWrBursts::6 4174 # Per bank write bursts 78system.physmem.perBankWrBursts::7 4095 # Per bank write bursts 79system.physmem.perBankWrBursts::8 4096 # Per bank write bursts 80system.physmem.perBankWrBursts::9 4096 # Per bank write bursts 81system.physmem.perBankWrBursts::10 4096 # Per bank write bursts 82system.physmem.perBankWrBursts::11 4097 # Per bank write bursts 83system.physmem.perBankWrBursts::12 4098 # Per bank write bursts 84system.physmem.perBankWrBursts::13 4096 # Per bank write bursts 85system.physmem.perBankWrBursts::14 4096 # Per bank write bursts 86system.physmem.perBankWrBursts::15 4150 # Per bank write bursts 87system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 88system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 89system.physmem.totGap 409388361500 # Total gap between requests 90system.physmem.readPktSize::0 0 # Read request sizes (log2) 91system.physmem.readPktSize::1 0 # Read request sizes (log2) 92system.physmem.readPktSize::2 0 # Read request sizes (log2) 93system.physmem.readPktSize::3 0 # Read request sizes (log2) 94system.physmem.readPktSize::4 0 # Read request sizes (log2) 95system.physmem.readPktSize::5 0 # Read request sizes (log2) 96system.physmem.readPktSize::6 315456 # Read request sizes (log2) 97system.physmem.writePktSize::0 0 # Write request sizes (log2) 98system.physmem.writePktSize::1 0 # Write request sizes (log2) 99system.physmem.writePktSize::2 0 # Write request sizes (log2) 100system.physmem.writePktSize::3 0 # Write request sizes (log2) 101system.physmem.writePktSize::4 0 # Write request sizes (log2) 102system.physmem.writePktSize::5 0 # Write request sizes (log2) 103system.physmem.writePktSize::6 66342 # Write request sizes (log2) 104system.physmem.rdQLenPdf::0 122394 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::1 117234 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::2 14139 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::3 6795 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::4 6485 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::5 7459 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::6 8460 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::7 8297 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::8 10473 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::9 4424 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::10 3291 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::11 2480 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::12 1879 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::13 1340 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 136system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::15 583 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::16 594 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::17 991 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::18 1792 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::19 2650 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::20 3281 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::21 3720 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::22 4073 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::23 4400 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::24 4678 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::25 4898 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::26 5046 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::27 5138 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::28 5067 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::29 4902 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::30 4379 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::31 4185 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::32 4077 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::33 158 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::34 114 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::35 100 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::36 86 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::37 91 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::38 103 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::39 81 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::40 97 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::41 91 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::42 87 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::43 83 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::44 68 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::45 64 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::46 63 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::47 60 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::48 63 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::49 64 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::50 65 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::51 63 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::52 58 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::53 56 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::54 52 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::55 20 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::56 5 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 200system.physmem.bytesPerActivate::samples 136710 # Bytes accessed per row activation 201system.physmem.bytesPerActivate::mean 178.527277 # Bytes accessed per row activation 202system.physmem.bytesPerActivate::gmean 128.653997 # Bytes accessed per row activation 203system.physmem.bytesPerActivate::stdev 198.191580 # Bytes accessed per row activation 204system.physmem.bytesPerActivate::0-127 54126 39.59% 39.59% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::128-255 57414 42.00% 81.59% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::256-383 14737 10.78% 92.37% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::384-511 1353 0.99% 93.36% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::512-639 1490 1.09% 94.45% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::640-767 1455 1.06% 95.51% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::768-895 1216 0.89% 96.40% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::896-1023 1169 0.86% 97.26% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::1024-1151 3750 2.74% 100.00% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::total 136710 # Bytes accessed per row activation 214system.physmem.rdPerTurnAround::samples 4038 # Reads before turning the bus around for writes 215system.physmem.rdPerTurnAround::mean 65.701585 # Reads before turning the bus around for writes 216system.physmem.rdPerTurnAround::gmean 34.708310 # Reads before turning the bus around for writes 217system.physmem.rdPerTurnAround::stdev 449.952316 # Reads before turning the bus around for writes 218system.physmem.rdPerTurnAround::0-511 3996 98.96% 98.96% # Reads before turning the bus around for writes 219system.physmem.rdPerTurnAround::512-1023 21 0.52% 99.48% # Reads before turning the bus around for writes 220system.physmem.rdPerTurnAround::1024-1535 8 0.20% 99.68% # Reads before turning the bus around for writes 221system.physmem.rdPerTurnAround::1536-2047 4 0.10% 99.78% # Reads before turning the bus around for writes 222system.physmem.rdPerTurnAround::2560-3071 1 0.02% 99.80% # Reads before turning the bus around for writes 223system.physmem.rdPerTurnAround::3072-3583 1 0.02% 99.83% # Reads before turning the bus around for writes 224system.physmem.rdPerTurnAround::4096-4607 1 0.02% 99.85% # Reads before turning the bus around for writes 225system.physmem.rdPerTurnAround::4608-5119 1 0.02% 99.88% # Reads before turning the bus around for writes 226system.physmem.rdPerTurnAround::5120-5631 1 0.02% 99.90% # Reads before turning the bus around for writes 227system.physmem.rdPerTurnAround::9728-10239 1 0.02% 99.93% # Reads before turning the bus around for writes 228system.physmem.rdPerTurnAround::10240-10751 1 0.02% 99.95% # Reads before turning the bus around for writes 229system.physmem.rdPerTurnAround::14336-14847 1 0.02% 99.98% # Reads before turning the bus around for writes 230system.physmem.rdPerTurnAround::15872-16383 1 0.02% 100.00% # Reads before turning the bus around for writes 231system.physmem.rdPerTurnAround::total 4038 # Reads before turning the bus around for writes 232system.physmem.wrPerTurnAround::samples 4038 # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::mean 16.401932 # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::gmean 16.368431 # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::stdev 1.138933 # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::16 3429 84.92% 84.92% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::17 6 0.15% 85.07% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::18 436 10.80% 95.86% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::19 81 2.01% 97.87% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::20 33 0.82% 98.69% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::21 20 0.50% 99.18% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::22 10 0.25% 99.43% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::23 9 0.22% 99.65% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::24 1 0.02% 99.68% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::25 2 0.05% 99.73% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::26 6 0.15% 99.88% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::27 2 0.05% 99.93% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::28 2 0.05% 99.98% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::31 1 0.02% 100.00% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::total 4038 # Writes before turning the bus around for reads 251system.physmem.totQLat 9474850817 # Total ticks spent queuing 252system.physmem.totMemAccLat 15383913317 # Total ticks spent from burst creation until serviced by the DRAM 253system.physmem.totBusLat 1575750000 # Total ticks spent in databus transfers 254system.physmem.avgQLat 30064.58 # Average queueing delay per DRAM burst 255system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 256system.physmem.avgMemAccLat 48814.58 # Average memory access latency per DRAM burst 257system.physmem.avgRdBW 49.27 # Average DRAM read bandwidth in MiByte/s 258system.physmem.avgWrBW 10.35 # Average achieved write bandwidth in MiByte/s 259system.physmem.avgRdBWSys 49.32 # Average system read bandwidth in MiByte/s 260system.physmem.avgWrBWSys 10.37 # Average system write bandwidth in MiByte/s 261system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 262system.physmem.busUtil 0.47 # Data bus utilization in percentage 263system.physmem.busUtilRead 0.38 # Data bus utilization in percentage for reads 264system.physmem.busUtilWrite 0.08 # Data bus utilization in percentage for writes 265system.physmem.avgRdQLen 1.56 # Average read queue length when enqueuing 266system.physmem.avgWrQLen 24.70 # Average write queue length when enqueuing 267system.physmem.readRowHits 218195 # Number of row buffer hits during reads 268system.physmem.writeRowHits 26465 # Number of row buffer hits during writes 269system.physmem.readRowHitRate 69.24 # Row buffer hit rate for reads 270system.physmem.writeRowHitRate 39.94 # Row buffer hit rate for writes 271system.physmem.avgGap 1072264.29 # Average gap between requests 272system.physmem.pageHitRate 64.15 # Row buffer hit rate, read and write combined 273system.physmem_0.actEnergy 518729400 # Energy for activate commands per rank (pJ) 274system.physmem_0.preEnergy 283036875 # Energy for precharge commands per rank (pJ) 275system.physmem_0.readEnergy 1231058400 # Energy for read commands per rank (pJ) 276system.physmem_0.writeEnergy 216470880 # Energy for write commands per rank (pJ) 277system.physmem_0.refreshEnergy 26739067680 # Energy for refresh commands per rank (pJ) 278system.physmem_0.actBackEnergy 96374211480 # Energy for active background per rank (pJ) 279system.physmem_0.preBackEnergy 161092645500 # Energy for precharge background per rank (pJ) 280system.physmem_0.totalEnergy 286455220215 # Total energy per rank (pJ) 281system.physmem_0.averagePower 699.719632 # Core power per rank (mW) 282system.physmem_0.memoryStateTime::IDLE 267357262270 # Time in different power states 283system.physmem_0.memoryStateTime::REF 13670280000 # Time in different power states 284system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 285system.physmem_0.memoryStateTime::ACT 128358277730 # Time in different power states 286system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 287system.physmem_1.actEnergy 514722600 # Energy for activate commands per rank (pJ) 288system.physmem_1.preEnergy 280850625 # Energy for precharge commands per rank (pJ) 289system.physmem_1.readEnergy 1226721600 # Energy for read commands per rank (pJ) 290system.physmem_1.writeEnergy 212706000 # Energy for write commands per rank (pJ) 291system.physmem_1.refreshEnergy 26739067680 # Energy for refresh commands per rank (pJ) 292system.physmem_1.actBackEnergy 96210213075 # Energy for active background per rank (pJ) 293system.physmem_1.preBackEnergy 161236503750 # Energy for precharge background per rank (pJ) 294system.physmem_1.totalEnergy 286420785330 # Total energy per rank (pJ) 295system.physmem_1.averagePower 699.635519 # Core power per rank (mW) 296system.physmem_1.memoryStateTime::IDLE 267597865087 # Time in different power states 297system.physmem_1.memoryStateTime::REF 13670280000 # Time in different power states 298system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 299system.physmem_1.memoryStateTime::ACT 128117581163 # Time in different power states 300system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 301system.cpu.branchPred.lookups 233960267 # Number of BP lookups 302system.cpu.branchPred.condPredicted 161822378 # Number of conditional branches predicted 303system.cpu.branchPred.condIncorrect 15514618 # Number of conditional branches incorrect 304system.cpu.branchPred.BTBLookups 121575807 # Number of BTB lookups 305system.cpu.branchPred.BTBHits 108259798 # Number of BTB hits 306system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 307system.cpu.branchPred.BTBHitPct 89.047156 # BTB Hit Percentage 308system.cpu.branchPred.usedRAS 25036830 # Number of times the RAS was used to get a target. 309system.cpu.branchPred.RASInCorrect 1300193 # Number of incorrect RAS predictions. 310system.cpu_clk_domain.clock 500 # Clock period in ticks 311system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 312system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 313system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 314system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 315system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 316system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 317system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 318system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 319system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 320system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 321system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 322system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 323system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 324system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 325system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 326system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 327system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 328system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 329system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 330system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 331system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 332system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 333system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 334system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 335system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 336system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 337system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 338system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 339system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 340system.cpu.dtb.walker.walks 0 # Table walker walks requested 341system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 342system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 343system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 344system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 345system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 346system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 347system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 348system.cpu.dtb.inst_hits 0 # ITB inst hits 349system.cpu.dtb.inst_misses 0 # ITB inst misses 350system.cpu.dtb.read_hits 0 # DTB read hits 351system.cpu.dtb.read_misses 0 # DTB read misses 352system.cpu.dtb.write_hits 0 # DTB write hits 353system.cpu.dtb.write_misses 0 # DTB write misses 354system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 355system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 356system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 357system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 358system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 359system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 360system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 361system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 362system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 363system.cpu.dtb.read_accesses 0 # DTB read accesses 364system.cpu.dtb.write_accesses 0 # DTB write accesses 365system.cpu.dtb.inst_accesses 0 # ITB inst accesses 366system.cpu.dtb.hits 0 # DTB hits 367system.cpu.dtb.misses 0 # DTB misses 368system.cpu.dtb.accesses 0 # DTB accesses 369system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 370system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 371system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 372system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 373system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 374system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 375system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 376system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 377system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 378system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 379system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 380system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 381system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 382system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 383system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 384system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 385system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 386system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 387system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 388system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 389system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 390system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 391system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 392system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 393system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 394system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 395system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 396system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 397system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 398system.cpu.itb.walker.walks 0 # Table walker walks requested 399system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 400system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 401system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 402system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 403system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 404system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 405system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 406system.cpu.itb.inst_hits 0 # ITB inst hits 407system.cpu.itb.inst_misses 0 # ITB inst misses 408system.cpu.itb.read_hits 0 # DTB read hits 409system.cpu.itb.read_misses 0 # DTB read misses 410system.cpu.itb.write_hits 0 # DTB write hits 411system.cpu.itb.write_misses 0 # DTB write misses 412system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 413system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 414system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 415system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 416system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 417system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 418system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 419system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 420system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 421system.cpu.itb.read_accesses 0 # DTB read accesses 422system.cpu.itb.write_accesses 0 # DTB write accesses 423system.cpu.itb.inst_accesses 0 # ITB inst accesses 424system.cpu.itb.hits 0 # DTB hits 425system.cpu.itb.misses 0 # DTB misses 426system.cpu.itb.accesses 0 # DTB accesses 427system.cpu.workload.num_syscalls 673 # Number of system calls 428system.cpu.numCycles 818776833 # number of cpu cycles simulated 429system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 430system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 431system.cpu.fetch.icacheStallCycles 84080281 # Number of cycles fetch is stalled on an Icache miss 432system.cpu.fetch.Insts 1200690651 # Number of instructions fetch has processed 433system.cpu.fetch.Branches 233960267 # Number of branches that fetch encountered 434system.cpu.fetch.predictedBranches 133296628 # Number of branches that fetch has predicted taken 435system.cpu.fetch.Cycles 718834157 # Number of cycles fetch has run and was not squashing or blocked 436system.cpu.fetch.SquashCycles 31063665 # Number of cycles fetch has spent squashing 437system.cpu.fetch.MiscStallCycles 2157 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 438system.cpu.fetch.PendingTrapStallCycles 31 # Number of stall cycles due to pending traps 439system.cpu.fetch.IcacheWaitRetryStallCycles 3294 # Number of stall cycles due to full MSHR 440system.cpu.fetch.CacheLines 370702196 # Number of cache lines fetched 441system.cpu.fetch.IcacheSquashes 652814 # Number of outstanding Icache misses that were squashed 442system.cpu.fetch.rateDist::samples 818451752 # Number of instructions fetched each cycle (Total) 443system.cpu.fetch.rateDist::mean 1.833525 # Number of instructions fetched each cycle (Total) 444system.cpu.fetch.rateDist::stdev 1.163546 # Number of instructions fetched each cycle (Total) 445system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 446system.cpu.fetch.rateDist::0 136786252 16.71% 16.71% # Number of instructions fetched each cycle (Total) 447system.cpu.fetch.rateDist::1 223134631 27.26% 43.98% # Number of instructions fetched each cycle (Total) 448system.cpu.fetch.rateDist::2 98075133 11.98% 55.96% # Number of instructions fetched each cycle (Total) 449system.cpu.fetch.rateDist::3 360455736 44.04% 100.00% # Number of instructions fetched each cycle (Total) 450system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 451system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 452system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) 453system.cpu.fetch.rateDist::total 818451752 # Number of instructions fetched each cycle (Total) 454system.cpu.fetch.branchRate 0.285744 # Number of branch fetches per cycle 455system.cpu.fetch.rate 1.466444 # Number of inst fetches per cycle 456system.cpu.decode.IdleCycles 119992574 # Number of cycles decode is idle 457system.cpu.decode.BlockedCycles 159648734 # Number of cycles decode is blocked 458system.cpu.decode.RunCycles 484662553 # Number of cycles decode is running 459system.cpu.decode.UnblockCycles 38629739 # Number of cycles decode is unblocking 460system.cpu.decode.SquashCycles 15518152 # Number of cycles decode is squashing 461system.cpu.decode.BranchResolved 25181029 # Number of times decode resolved a branch 462system.cpu.decode.BranchMispred 13828 # Number of times decode detected a branch misprediction 463system.cpu.decode.DecodedInsts 1248127732 # Number of instructions handled by decode 464system.cpu.decode.SquashedInsts 39967182 # Number of squashed instructions handled by decode 465system.cpu.rename.SquashCycles 15518152 # Number of cycles rename is squashing 466system.cpu.rename.IdleCycles 177000175 # Number of cycles rename is idle 467system.cpu.rename.BlockCycles 78889127 # Number of cycles rename is blocking 468system.cpu.rename.serializeStallCycles 210704 # count of cycles rename stalled for serializing inst 469system.cpu.rename.RunCycles 464955834 # Number of cycles rename is running 470system.cpu.rename.UnblockCycles 81877760 # Number of cycles rename is unblocking 471system.cpu.rename.RenamedInsts 1190635501 # Number of instructions processed by rename 472system.cpu.rename.SquashedInsts 25549976 # Number of squashed instructions processed by rename 473system.cpu.rename.ROBFullEvents 24948594 # Number of times rename has blocked due to ROB full 474system.cpu.rename.IQFullEvents 2267380 # Number of times rename has blocked due to IQ full 475system.cpu.rename.LQFullEvents 41534187 # Number of times rename has blocked due to LQ full 476system.cpu.rename.SQFullEvents 1694237 # Number of times rename has blocked due to SQ full 477system.cpu.rename.RenamedOperands 1225376861 # Number of destination operands rename has renamed 478system.cpu.rename.RenameLookups 5812387733 # Number of register rename lookups that rename has made 479system.cpu.rename.int_rename_lookups 1358166990 # Number of integer rename lookups 480system.cpu.rename.fp_rename_lookups 40876517 # Number of floating rename lookups 481system.cpu.rename.CommittedMaps 874778230 # Number of HB maps that are committed 482system.cpu.rename.UndoneMaps 350598631 # Number of HB maps that are undone due to squashing 483system.cpu.rename.serializingInsts 7265 # count of serializing insts renamed 484system.cpu.rename.tempSerializingInsts 7257 # count of temporary serializing insts renamed 485system.cpu.rename.skidInsts 108139973 # count of insts added to the skid buffer 486system.cpu.memDep0.insertedLoads 366113111 # Number of loads inserted to the mem dependence unit. 487system.cpu.memDep0.insertedStores 236095933 # Number of stores inserted to the mem dependence unit. 488system.cpu.memDep0.conflictingLoads 1592417 # Number of conflicting loads. 489system.cpu.memDep0.conflictingStores 5322589 # Number of conflicting stores. 490system.cpu.iq.iqInstsAdded 1168545131 # Number of instructions added to the IQ (excludes non-spec) 491system.cpu.iq.iqNonSpecInstsAdded 12357 # Number of non-speculative instructions added to the IQ 492system.cpu.iq.iqInstsIssued 1017136914 # Number of instructions issued 493system.cpu.iq.iqSquashedInstsIssued 18518110 # Number of squashed instructions issued 494system.cpu.iq.iqSquashedInstsExamined 379832530 # Number of squashed instructions iterated over during squash; mainly for profiling 495system.cpu.iq.iqSquashedOperandsExamined 1032101126 # Number of squashed operands that are examined and possibly removed from graph 496system.cpu.iq.iqSquashedNonSpecRemoved 203 # Number of squashed non-spec instructions that were removed 497system.cpu.iq.issued_per_cycle::samples 818451752 # Number of insts issued each cycle 498system.cpu.iq.issued_per_cycle::mean 1.242757 # Number of insts issued each cycle 499system.cpu.iq.issued_per_cycle::stdev 1.084999 # Number of insts issued each cycle 500system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 501system.cpu.iq.issued_per_cycle::0 260802028 31.87% 31.87% # Number of insts issued each cycle 502system.cpu.iq.issued_per_cycle::1 227738086 27.83% 59.69% # Number of insts issued each cycle 503system.cpu.iq.issued_per_cycle::2 216482422 26.45% 86.14% # Number of insts issued each cycle 504system.cpu.iq.issued_per_cycle::3 97282889 11.89% 98.03% # Number of insts issued each cycle 505system.cpu.iq.issued_per_cycle::4 16146318 1.97% 100.00% # Number of insts issued each cycle 506system.cpu.iq.issued_per_cycle::5 9 0.00% 100.00% # Number of insts issued each cycle 507system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 508system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 509system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 510system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 511system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 512system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle 513system.cpu.iq.issued_per_cycle::total 818451752 # Number of insts issued each cycle 514system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 515system.cpu.iq.fu_full::IntAlu 64511713 19.12% 19.12% # attempts to use FU when none available 516system.cpu.iq.fu_full::IntMult 18146 0.01% 19.13% # attempts to use FU when none available 517system.cpu.iq.fu_full::IntDiv 0 0.00% 19.13% # attempts to use FU when none available 518system.cpu.iq.fu_full::FloatAdd 0 0.00% 19.13% # attempts to use FU when none available 519system.cpu.iq.fu_full::FloatCmp 0 0.00% 19.13% # attempts to use FU when none available 520system.cpu.iq.fu_full::FloatCvt 0 0.00% 19.13% # attempts to use FU when none available 521system.cpu.iq.fu_full::FloatMult 0 0.00% 19.13% # attempts to use FU when none available 522system.cpu.iq.fu_full::FloatDiv 0 0.00% 19.13% # attempts to use FU when none available 523system.cpu.iq.fu_full::FloatSqrt 0 0.00% 19.13% # attempts to use FU when none available 524system.cpu.iq.fu_full::SimdAdd 0 0.00% 19.13% # attempts to use FU when none available 525system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 19.13% # attempts to use FU when none available 526system.cpu.iq.fu_full::SimdAlu 0 0.00% 19.13% # attempts to use FU when none available 527system.cpu.iq.fu_full::SimdCmp 0 0.00% 19.13% # attempts to use FU when none available 528system.cpu.iq.fu_full::SimdCvt 0 0.00% 19.13% # attempts to use FU when none available 529system.cpu.iq.fu_full::SimdMisc 0 0.00% 19.13% # attempts to use FU when none available 530system.cpu.iq.fu_full::SimdMult 0 0.00% 19.13% # attempts to use FU when none available 531system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 19.13% # attempts to use FU when none available 532system.cpu.iq.fu_full::SimdShift 0 0.00% 19.13% # attempts to use FU when none available 533system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 19.13% # attempts to use FU when none available 534system.cpu.iq.fu_full::SimdSqrt 0 0.00% 19.13% # attempts to use FU when none available 535system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 19.13% # attempts to use FU when none available 536system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 19.13% # attempts to use FU when none available 537system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 19.13% # attempts to use FU when none available 538system.cpu.iq.fu_full::SimdFloatCvt 636889 0.19% 19.32% # attempts to use FU when none available 539system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 19.32% # attempts to use FU when none available 540system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 19.32% # attempts to use FU when none available 541system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 19.32% # attempts to use FU when none available 542system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 19.32% # attempts to use FU when none available 543system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 19.32% # attempts to use FU when none available 544system.cpu.iq.fu_full::MemRead 155540667 46.10% 65.42% # attempts to use FU when none available 545system.cpu.iq.fu_full::MemWrite 116678907 34.58% 100.00% # attempts to use FU when none available 546system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 547system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 548system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 549system.cpu.iq.FU_type_0::IntAlu 456370990 44.87% 44.87% # Type of FU issued 550system.cpu.iq.FU_type_0::IntMult 5195830 0.51% 45.38% # Type of FU issued 551system.cpu.iq.FU_type_0::IntDiv 0 0.00% 45.38% # Type of FU issued 552system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 45.38% # Type of FU issued 553system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 45.38% # Type of FU issued 554system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 45.38% # Type of FU issued 555system.cpu.iq.FU_type_0::FloatMult 0 0.00% 45.38% # Type of FU issued 556system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 45.38% # Type of FU issued 557system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 45.38% # Type of FU issued 558system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 45.38% # Type of FU issued 559system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 45.38% # Type of FU issued 560system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 45.38% # Type of FU issued 561system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 45.38% # Type of FU issued 562system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 45.38% # Type of FU issued 563system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 45.38% # Type of FU issued 564system.cpu.iq.FU_type_0::SimdMult 0 0.00% 45.38% # Type of FU issued 565system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 45.38% # Type of FU issued 566system.cpu.iq.FU_type_0::SimdShift 0 0.00% 45.38% # Type of FU issued 567system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 45.38% # Type of FU issued 568system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 45.38% # Type of FU issued 569system.cpu.iq.FU_type_0::SimdFloatAdd 637528 0.06% 45.44% # Type of FU issued 570system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 45.44% # Type of FU issued 571system.cpu.iq.FU_type_0::SimdFloatCmp 3187675 0.31% 45.76% # Type of FU issued 572system.cpu.iq.FU_type_0::SimdFloatCvt 2550147 0.25% 46.01% # Type of FU issued 573system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 46.01% # Type of FU issued 574system.cpu.iq.FU_type_0::SimdFloatMisc 11478993 1.13% 47.13% # Type of FU issued 575system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.13% # Type of FU issued 576system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.13% # Type of FU issued 577system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.13% # Type of FU issued 578system.cpu.iq.FU_type_0::MemRead 322128333 31.67% 78.80% # Type of FU issued 579system.cpu.iq.FU_type_0::MemWrite 215587418 21.20% 100.00% # Type of FU issued 580system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 581system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 582system.cpu.iq.FU_type_0::total 1017136914 # Type of FU issued 583system.cpu.iq.rate 1.242264 # Inst issue rate 584system.cpu.iq.fu_busy_cnt 337386322 # FU busy when requested 585system.cpu.iq.fu_busy_rate 0.331702 # FU busy rate (busy events/executed inst) 586system.cpu.iq.int_inst_queue_reads 3146752970 # Number of integer instruction queue reads 587system.cpu.iq.int_inst_queue_writes 1504842539 # Number of integer instruction queue writes 588system.cpu.iq.int_inst_queue_wakeup_accesses 934271199 # Number of integer instruction queue wakeup accesses 589system.cpu.iq.fp_inst_queue_reads 61877042 # Number of floating instruction queue reads 590system.cpu.iq.fp_inst_queue_writes 43565869 # Number of floating instruction queue writes 591system.cpu.iq.fp_inst_queue_wakeup_accesses 26152443 # Number of floating instruction queue wakeup accesses 592system.cpu.iq.int_alu_accesses 1320712886 # Number of integer alu accesses 593system.cpu.iq.fp_alu_accesses 33810350 # Number of floating point alu accesses 594system.cpu.iew.lsq.thread0.forwLoads 9960171 # Number of loads that had data forwarded from stores 595system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 596system.cpu.iew.lsq.thread0.squashedLoads 113872173 # Number of loads squashed 597system.cpu.iew.lsq.thread0.ignoredResponses 1090 # Number of memory responses ignored because the instruction is squashed 598system.cpu.iew.lsq.thread0.memOrderViolation 18393 # Number of memory ordering violations 599system.cpu.iew.lsq.thread0.squashedStores 107115437 # Number of stores squashed 600system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 601system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 602system.cpu.iew.lsq.thread0.rescheduledLoads 2065797 # Number of loads that were rescheduled 603system.cpu.iew.lsq.thread0.cacheBlocked 22350 # Number of times an access to memory failed due to the cache being blocked 604system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 605system.cpu.iew.iewSquashCycles 15518152 # Number of cycles IEW is squashing 606system.cpu.iew.iewBlockCycles 35325436 # Number of cycles IEW is blocking 607system.cpu.iew.iewUnblockCycles 42128 # Number of cycles IEW is unblocking 608system.cpu.iew.iewDispatchedInsts 1168563042 # Number of instructions dispatched to IQ 609system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch 610system.cpu.iew.iewDispLoadInsts 366113111 # Number of dispatched load instructions 611system.cpu.iew.iewDispStoreInsts 236095933 # Number of dispatched store instructions 612system.cpu.iew.iewDispNonSpecInsts 6617 # Number of dispatched non-speculative instructions 613system.cpu.iew.iewIQFullEvents 102 # Number of times the IQ has become full, causing a stall 614system.cpu.iew.iewLSQFullEvents 45749 # Number of times the LSQ has become full, causing a stall 615system.cpu.iew.memOrderViolationEvents 18393 # Number of memory order violations 616system.cpu.iew.predictedTakenIncorrect 15437385 # Number of branches that were predicted taken incorrectly 617system.cpu.iew.predictedNotTakenIncorrect 3784510 # Number of branches that were predicted not taken incorrectly 618system.cpu.iew.branchMispredicts 19221895 # Number of branch mispredicts detected at execute 619system.cpu.iew.iewExecutedInsts 974751184 # Number of executed instructions 620system.cpu.iew.iewExecLoadInsts 303297622 # Number of load instructions executed 621system.cpu.iew.iewExecSquashedInsts 42385730 # Number of squashed instructions skipped in execute 622system.cpu.iew.exec_swp 0 # number of swp insts executed 623system.cpu.iew.exec_nop 5554 # number of nop insts executed 624system.cpu.iew.exec_refs 497765238 # number of memory reference insts executed 625system.cpu.iew.exec_branches 150613469 # Number of branches executed 626system.cpu.iew.exec_stores 194467616 # Number of stores executed 627system.cpu.iew.exec_rate 1.190497 # Inst execution rate 628system.cpu.iew.wb_sent 963723937 # cumulative count of insts sent to commit 629system.cpu.iew.wb_count 960423642 # cumulative count of insts written-back 630system.cpu.iew.wb_producers 536680583 # num instructions producing a value 631system.cpu.iew.wb_consumers 893282195 # num instructions consuming a value 632system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 633system.cpu.iew.wb_rate 1.172998 # insts written-back per cycle 634system.cpu.iew.wb_fanout 0.600796 # average fanout of values written-back 635system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 636system.cpu.commit.commitSquashedInsts 357407209 # The number of squashed insts skipped by commit 637system.cpu.commit.commitNonSpecStalls 12154 # The number of times commit has been forced to stall to communicate backwards 638system.cpu.commit.branchMispredicts 15500938 # The number of times a branch was mispredicted 639system.cpu.commit.committed_per_cycle::samples 767631497 # Number of insts commited each cycle 640system.cpu.commit.committed_per_cycle::mean 1.027485 # Number of insts commited each cycle 641system.cpu.commit.committed_per_cycle::stdev 1.786864 # Number of insts commited each cycle 642system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 643system.cpu.commit.committed_per_cycle::0 430923455 56.14% 56.14% # Number of insts commited each cycle 644system.cpu.commit.committed_per_cycle::1 172477669 22.47% 78.61% # Number of insts commited each cycle 645system.cpu.commit.committed_per_cycle::2 73566542 9.58% 88.19% # Number of insts commited each cycle 646system.cpu.commit.committed_per_cycle::3 31624094 4.12% 92.31% # Number of insts commited each cycle 647system.cpu.commit.committed_per_cycle::4 8540357 1.11% 93.42% # Number of insts commited each cycle 648system.cpu.commit.committed_per_cycle::5 14250532 1.86% 95.28% # Number of insts commited each cycle 649system.cpu.commit.committed_per_cycle::6 7269334 0.95% 96.22% # Number of insts commited each cycle 650system.cpu.commit.committed_per_cycle::7 6619169 0.86% 97.09% # Number of insts commited each cycle 651system.cpu.commit.committed_per_cycle::8 22360345 2.91% 100.00% # Number of insts commited each cycle 652system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 653system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 654system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 655system.cpu.commit.committed_per_cycle::total 767631497 # Number of insts commited each cycle 656system.cpu.commit.committedInsts 640654411 # Number of instructions committed 657system.cpu.commit.committedOps 788730070 # Number of ops (including micro ops) committed 658system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 659system.cpu.commit.refs 381221434 # Number of memory references committed 660system.cpu.commit.loads 252240938 # Number of loads committed 661system.cpu.commit.membars 5740 # Number of memory barriers committed 662system.cpu.commit.branches 137364860 # Number of branches committed 663system.cpu.commit.fp_insts 24239771 # Number of committed floating point instructions. 664system.cpu.commit.int_insts 682251399 # Number of committed integer instructions. 665system.cpu.commit.function_calls 19275340 # Number of function calls committed. 666system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 667system.cpu.commit.op_class_0::IntAlu 385756794 48.91% 48.91% # Class of committed instruction 668system.cpu.commit.op_class_0::IntMult 5173441 0.66% 49.56% # Class of committed instruction 669system.cpu.commit.op_class_0::IntDiv 0 0.00% 49.56% # Class of committed instruction 670system.cpu.commit.op_class_0::FloatAdd 0 0.00% 49.56% # Class of committed instruction 671system.cpu.commit.op_class_0::FloatCmp 0 0.00% 49.56% # Class of committed instruction 672system.cpu.commit.op_class_0::FloatCvt 0 0.00% 49.56% # Class of committed instruction 673system.cpu.commit.op_class_0::FloatMult 0 0.00% 49.56% # Class of committed instruction 674system.cpu.commit.op_class_0::FloatDiv 0 0.00% 49.56% # Class of committed instruction 675system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 49.56% # Class of committed instruction 676system.cpu.commit.op_class_0::SimdAdd 0 0.00% 49.56% # Class of committed instruction 677system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 49.56% # Class of committed instruction 678system.cpu.commit.op_class_0::SimdAlu 0 0.00% 49.56% # Class of committed instruction 679system.cpu.commit.op_class_0::SimdCmp 0 0.00% 49.56% # Class of committed instruction 680system.cpu.commit.op_class_0::SimdCvt 0 0.00% 49.56% # Class of committed instruction 681system.cpu.commit.op_class_0::SimdMisc 0 0.00% 49.56% # Class of committed instruction 682system.cpu.commit.op_class_0::SimdMult 0 0.00% 49.56% # Class of committed instruction 683system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 49.56% # Class of committed instruction 684system.cpu.commit.op_class_0::SimdShift 0 0.00% 49.56% # Class of committed instruction 685system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 49.56% # Class of committed instruction 686system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 49.56% # Class of committed instruction 687system.cpu.commit.op_class_0::SimdFloatAdd 637528 0.08% 49.65% # Class of committed instruction 688system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 49.65% # Class of committed instruction 689system.cpu.commit.op_class_0::SimdFloatCmp 3187668 0.40% 50.05% # Class of committed instruction 690system.cpu.commit.op_class_0::SimdFloatCvt 2550131 0.32% 50.37% # Class of committed instruction 691system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 50.37% # Class of committed instruction 692system.cpu.commit.op_class_0::SimdFloatMisc 10203074 1.29% 51.67% # Class of committed instruction 693system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 51.67% # Class of committed instruction 694system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 51.67% # Class of committed instruction 695system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 51.67% # Class of committed instruction 696system.cpu.commit.op_class_0::MemRead 252240938 31.98% 83.65% # Class of committed instruction 697system.cpu.commit.op_class_0::MemWrite 128980496 16.35% 100.00% # Class of committed instruction 698system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 699system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 700system.cpu.commit.op_class_0::total 788730070 # Class of committed instruction 701system.cpu.commit.bw_lim_events 22360345 # number cycles where commit BW limit reached 702system.cpu.rob.rob_reads 1891399680 # The number of ROB reads 703system.cpu.rob.rob_writes 2343098733 # The number of ROB writes 704system.cpu.timesIdled 647345 # Number of times that the entire CPU went into an idle state and unscheduled itself 705system.cpu.idleCycles 325081 # Total number of cycles that the CPU has spent unscheduled due to idling 706system.cpu.committedInsts 640649299 # Number of Instructions Simulated 707system.cpu.committedOps 788724958 # Number of Ops (including micro ops) Simulated 708system.cpu.cpi 1.278042 # CPI: Cycles Per Instruction 709system.cpu.cpi_total 1.278042 # CPI: Total CPI of All Threads 710system.cpu.ipc 0.782447 # IPC: Instructions Per Cycle 711system.cpu.ipc_total 0.782447 # IPC: Total IPC of All Threads 712system.cpu.int_regfile_reads 995806519 # number of integer regfile reads 713system.cpu.int_regfile_writes 567906159 # number of integer regfile writes 714system.cpu.fp_regfile_reads 31889841 # number of floating regfile reads 715system.cpu.fp_regfile_writes 22959492 # number of floating regfile writes 716system.cpu.cc_regfile_reads 3794435468 # number of cc regfile reads 717system.cpu.cc_regfile_writes 384898950 # number of cc regfile writes 718system.cpu.misc_regfile_reads 715817595 # number of misc regfile reads 719system.cpu.misc_regfile_writes 6386808 # number of misc regfile writes 720system.cpu.dcache.tags.replacements 2756184 # number of replacements 721system.cpu.dcache.tags.tagsinuse 511.932971 # Cycle average of tags in use 722system.cpu.dcache.tags.total_refs 414226712 # Total number of references to valid blocks. 723system.cpu.dcache.tags.sampled_refs 2756696 # Sample count of references to valid blocks. 724system.cpu.dcache.tags.avg_refs 150.262021 # Average number of references to valid blocks. 725system.cpu.dcache.tags.warmup_cycle 257775000 # Cycle when the warmup percentage was hit. 726system.cpu.dcache.tags.occ_blocks::cpu.data 511.932971 # Average occupied blocks per requestor 727system.cpu.dcache.tags.occ_percent::cpu.data 0.999869 # Average percentage of cache occupancy 728system.cpu.dcache.tags.occ_percent::total 0.999869 # Average percentage of cache occupancy 729system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 730system.cpu.dcache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id 731system.cpu.dcache.tags.age_task_id_blocks_1024::1 224 # Occupied blocks per task id 732system.cpu.dcache.tags.age_task_id_blocks_1024::2 191 # Occupied blocks per task id 733system.cpu.dcache.tags.age_task_id_blocks_1024::4 56 # Occupied blocks per task id 734system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 735system.cpu.dcache.tags.tag_accesses 839343984 # Number of tag accesses 736system.cpu.dcache.tags.data_accesses 839343984 # Number of data accesses 737system.cpu.dcache.ReadReq_hits::cpu.data 286295259 # number of ReadReq hits 738system.cpu.dcache.ReadReq_hits::total 286295259 # number of ReadReq hits 739system.cpu.dcache.WriteReq_hits::cpu.data 127916705 # number of WriteReq hits 740system.cpu.dcache.WriteReq_hits::total 127916705 # number of WriteReq hits 741system.cpu.dcache.SoftPFReq_hits::cpu.data 3174 # number of SoftPFReq hits 742system.cpu.dcache.SoftPFReq_hits::total 3174 # number of SoftPFReq hits 743system.cpu.dcache.LoadLockedReq_hits::cpu.data 5737 # number of LoadLockedReq hits 744system.cpu.dcache.LoadLockedReq_hits::total 5737 # number of LoadLockedReq hits 745system.cpu.dcache.StoreCondReq_hits::cpu.data 5739 # number of StoreCondReq hits 746system.cpu.dcache.StoreCondReq_hits::total 5739 # number of StoreCondReq hits 747system.cpu.dcache.demand_hits::cpu.data 414211964 # number of demand (read+write) hits 748system.cpu.dcache.demand_hits::total 414211964 # number of demand (read+write) hits 749system.cpu.dcache.overall_hits::cpu.data 414215138 # number of overall hits 750system.cpu.dcache.overall_hits::total 414215138 # number of overall hits 751system.cpu.dcache.ReadReq_misses::cpu.data 3031608 # number of ReadReq misses 752system.cpu.dcache.ReadReq_misses::total 3031608 # number of ReadReq misses 753system.cpu.dcache.WriteReq_misses::cpu.data 1034772 # number of WriteReq misses 754system.cpu.dcache.WriteReq_misses::total 1034772 # number of WriteReq misses 755system.cpu.dcache.SoftPFReq_misses::cpu.data 647 # number of SoftPFReq misses 756system.cpu.dcache.SoftPFReq_misses::total 647 # number of SoftPFReq misses 757system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses 758system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses 759system.cpu.dcache.demand_misses::cpu.data 4066380 # number of demand (read+write) misses 760system.cpu.dcache.demand_misses::total 4066380 # number of demand (read+write) misses 761system.cpu.dcache.overall_misses::cpu.data 4067027 # number of overall misses 762system.cpu.dcache.overall_misses::total 4067027 # number of overall misses 763system.cpu.dcache.ReadReq_miss_latency::cpu.data 35305181420 # number of ReadReq miss cycles 764system.cpu.dcache.ReadReq_miss_latency::total 35305181420 # number of ReadReq miss cycles 765system.cpu.dcache.WriteReq_miss_latency::cpu.data 9981703626 # number of WriteReq miss cycles 766system.cpu.dcache.WriteReq_miss_latency::total 9981703626 # number of WriteReq miss cycles 767system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 189500 # number of LoadLockedReq miss cycles 768system.cpu.dcache.LoadLockedReq_miss_latency::total 189500 # number of LoadLockedReq miss cycles 769system.cpu.dcache.demand_miss_latency::cpu.data 45286885046 # number of demand (read+write) miss cycles 770system.cpu.dcache.demand_miss_latency::total 45286885046 # number of demand (read+write) miss cycles 771system.cpu.dcache.overall_miss_latency::cpu.data 45286885046 # number of overall miss cycles 772system.cpu.dcache.overall_miss_latency::total 45286885046 # number of overall miss cycles 773system.cpu.dcache.ReadReq_accesses::cpu.data 289326867 # number of ReadReq accesses(hits+misses) 774system.cpu.dcache.ReadReq_accesses::total 289326867 # number of ReadReq accesses(hits+misses) 775system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses) 776system.cpu.dcache.WriteReq_accesses::total 128951477 # number of WriteReq accesses(hits+misses) 777system.cpu.dcache.SoftPFReq_accesses::cpu.data 3821 # number of SoftPFReq accesses(hits+misses) 778system.cpu.dcache.SoftPFReq_accesses::total 3821 # number of SoftPFReq accesses(hits+misses) 779system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5740 # number of LoadLockedReq accesses(hits+misses) 780system.cpu.dcache.LoadLockedReq_accesses::total 5740 # number of LoadLockedReq accesses(hits+misses) 781system.cpu.dcache.StoreCondReq_accesses::cpu.data 5739 # number of StoreCondReq accesses(hits+misses) 782system.cpu.dcache.StoreCondReq_accesses::total 5739 # number of StoreCondReq accesses(hits+misses) 783system.cpu.dcache.demand_accesses::cpu.data 418278344 # number of demand (read+write) accesses 784system.cpu.dcache.demand_accesses::total 418278344 # number of demand (read+write) accesses 785system.cpu.dcache.overall_accesses::cpu.data 418282165 # number of overall (read+write) accesses 786system.cpu.dcache.overall_accesses::total 418282165 # number of overall (read+write) accesses 787system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.010478 # miss rate for ReadReq accesses 788system.cpu.dcache.ReadReq_miss_rate::total 0.010478 # miss rate for ReadReq accesses 789system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.008025 # miss rate for WriteReq accesses 790system.cpu.dcache.WriteReq_miss_rate::total 0.008025 # miss rate for WriteReq accesses 791system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.169327 # miss rate for SoftPFReq accesses 792system.cpu.dcache.SoftPFReq_miss_rate::total 0.169327 # miss rate for SoftPFReq accesses 793system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000523 # miss rate for LoadLockedReq accesses 794system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000523 # miss rate for LoadLockedReq accesses 795system.cpu.dcache.demand_miss_rate::cpu.data 0.009722 # miss rate for demand accesses 796system.cpu.dcache.demand_miss_rate::total 0.009722 # miss rate for demand accesses 797system.cpu.dcache.overall_miss_rate::cpu.data 0.009723 # miss rate for overall accesses 798system.cpu.dcache.overall_miss_rate::total 0.009723 # miss rate for overall accesses 799system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11645.694767 # average ReadReq miss latency 800system.cpu.dcache.ReadReq_avg_miss_latency::total 11645.694767 # average ReadReq miss latency 801system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 9646.283071 # average WriteReq miss latency 802system.cpu.dcache.WriteReq_avg_miss_latency::total 9646.283071 # average WriteReq miss latency 803system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 63166.666667 # average LoadLockedReq miss latency 804system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 63166.666667 # average LoadLockedReq miss latency 805system.cpu.dcache.demand_avg_miss_latency::cpu.data 11136.904334 # average overall miss latency 806system.cpu.dcache.demand_avg_miss_latency::total 11136.904334 # average overall miss latency 807system.cpu.dcache.overall_avg_miss_latency::cpu.data 11135.132628 # average overall miss latency 808system.cpu.dcache.overall_avg_miss_latency::total 11135.132628 # average overall miss latency 809system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 810system.cpu.dcache.blocked_cycles::no_targets 343566 # number of cycles access was blocked 811system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 812system.cpu.dcache.blocked::no_targets 5188 # number of cycles access was blocked 813system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 814system.cpu.dcache.avg_blocked_cycles::no_targets 66.223207 # average number of cycles each access was blocked 815system.cpu.dcache.fast_writes 0 # number of fast writes performed 816system.cpu.dcache.cache_copies 0 # number of cache copies performed 817system.cpu.dcache.writebacks::writebacks 735673 # number of writebacks 818system.cpu.dcache.writebacks::total 735673 # number of writebacks 819system.cpu.dcache.ReadReq_mshr_hits::cpu.data 996399 # number of ReadReq MSHR hits 820system.cpu.dcache.ReadReq_mshr_hits::total 996399 # number of ReadReq MSHR hits 821system.cpu.dcache.WriteReq_mshr_hits::cpu.data 313907 # number of WriteReq MSHR hits 822system.cpu.dcache.WriteReq_mshr_hits::total 313907 # number of WriteReq MSHR hits 823system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits 824system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits 825system.cpu.dcache.demand_mshr_hits::cpu.data 1310306 # number of demand (read+write) MSHR hits 826system.cpu.dcache.demand_mshr_hits::total 1310306 # number of demand (read+write) MSHR hits 827system.cpu.dcache.overall_mshr_hits::cpu.data 1310306 # number of overall MSHR hits 828system.cpu.dcache.overall_mshr_hits::total 1310306 # number of overall MSHR hits 829system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2035209 # number of ReadReq MSHR misses 830system.cpu.dcache.ReadReq_mshr_misses::total 2035209 # number of ReadReq MSHR misses 831system.cpu.dcache.WriteReq_mshr_misses::cpu.data 720865 # number of WriteReq MSHR misses 832system.cpu.dcache.WriteReq_mshr_misses::total 720865 # number of WriteReq MSHR misses 833system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 641 # number of SoftPFReq MSHR misses 834system.cpu.dcache.SoftPFReq_mshr_misses::total 641 # number of SoftPFReq MSHR misses 835system.cpu.dcache.demand_mshr_misses::cpu.data 2756074 # number of demand (read+write) MSHR misses 836system.cpu.dcache.demand_mshr_misses::total 2756074 # number of demand (read+write) MSHR misses 837system.cpu.dcache.overall_mshr_misses::cpu.data 2756715 # number of overall MSHR misses 838system.cpu.dcache.overall_mshr_misses::total 2756715 # number of overall MSHR misses 839system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23118028700 # number of ReadReq MSHR miss cycles 840system.cpu.dcache.ReadReq_mshr_miss_latency::total 23118028700 # number of ReadReq MSHR miss cycles 841system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5596519781 # number of WriteReq MSHR miss cycles 842system.cpu.dcache.WriteReq_mshr_miss_latency::total 5596519781 # number of WriteReq MSHR miss cycles 843system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5770003 # number of SoftPFReq MSHR miss cycles 844system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5770003 # number of SoftPFReq MSHR miss cycles 845system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28714548481 # number of demand (read+write) MSHR miss cycles 846system.cpu.dcache.demand_mshr_miss_latency::total 28714548481 # number of demand (read+write) MSHR miss cycles 847system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28720318484 # number of overall MSHR miss cycles 848system.cpu.dcache.overall_mshr_miss_latency::total 28720318484 # number of overall MSHR miss cycles 849system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007034 # mshr miss rate for ReadReq accesses 850system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007034 # mshr miss rate for ReadReq accesses 851system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005590 # mshr miss rate for WriteReq accesses 852system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005590 # mshr miss rate for WriteReq accesses 853system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.167757 # mshr miss rate for SoftPFReq accesses 854system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.167757 # mshr miss rate for SoftPFReq accesses 855system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006589 # mshr miss rate for demand accesses 856system.cpu.dcache.demand_mshr_miss_rate::total 0.006589 # mshr miss rate for demand accesses 857system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006591 # mshr miss rate for overall accesses 858system.cpu.dcache.overall_mshr_miss_rate::total 0.006591 # mshr miss rate for overall accesses 859system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11359.044059 # average ReadReq mshr miss latency 860system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11359.044059 # average ReadReq mshr miss latency 861system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 7763.617017 # average WriteReq mshr miss latency 862system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 7763.617017 # average WriteReq mshr miss latency 863system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 9001.564743 # average SoftPFReq mshr miss latency 864system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 9001.564743 # average SoftPFReq mshr miss latency 865system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 10418.642054 # average overall mshr miss latency 866system.cpu.dcache.demand_avg_mshr_miss_latency::total 10418.642054 # average overall mshr miss latency 867system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 10418.312551 # average overall mshr miss latency 868system.cpu.dcache.overall_avg_mshr_miss_latency::total 10418.312551 # average overall mshr miss latency 869system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 870system.cpu.icache.tags.replacements 5169974 # number of replacements 871system.cpu.icache.tags.tagsinuse 511.005918 # Cycle average of tags in use 872system.cpu.icache.tags.total_refs 365528009 # Total number of references to valid blocks. 873system.cpu.icache.tags.sampled_refs 5170484 # Sample count of references to valid blocks. 874system.cpu.icache.tags.avg_refs 70.695124 # Average number of references to valid blocks. 875system.cpu.icache.tags.warmup_cycle 247768250 # Cycle when the warmup percentage was hit. 876system.cpu.icache.tags.occ_blocks::cpu.inst 511.005918 # Average occupied blocks per requestor 877system.cpu.icache.tags.occ_percent::cpu.inst 0.998058 # Average percentage of cache occupancy 878system.cpu.icache.tags.occ_percent::total 0.998058 # Average percentage of cache occupancy 879system.cpu.icache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id 880system.cpu.icache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id 881system.cpu.icache.tags.age_task_id_blocks_1024::1 119 # Occupied blocks per task id 882system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id 883system.cpu.icache.tags.age_task_id_blocks_1024::4 327 # Occupied blocks per task id 884system.cpu.icache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id 885system.cpu.icache.tags.tag_accesses 746574831 # Number of tag accesses 886system.cpu.icache.tags.data_accesses 746574831 # Number of data accesses 887system.cpu.icache.ReadReq_hits::cpu.inst 365528032 # number of ReadReq hits 888system.cpu.icache.ReadReq_hits::total 365528032 # number of ReadReq hits 889system.cpu.icache.demand_hits::cpu.inst 365528032 # number of demand (read+write) hits 890system.cpu.icache.demand_hits::total 365528032 # number of demand (read+write) hits 891system.cpu.icache.overall_hits::cpu.inst 365528032 # number of overall hits 892system.cpu.icache.overall_hits::total 365528032 # number of overall hits 893system.cpu.icache.ReadReq_misses::cpu.inst 5174132 # number of ReadReq misses 894system.cpu.icache.ReadReq_misses::total 5174132 # number of ReadReq misses 895system.cpu.icache.demand_misses::cpu.inst 5174132 # number of demand (read+write) misses 896system.cpu.icache.demand_misses::total 5174132 # number of demand (read+write) misses 897system.cpu.icache.overall_misses::cpu.inst 5174132 # number of overall misses 898system.cpu.icache.overall_misses::total 5174132 # number of overall misses 899system.cpu.icache.ReadReq_miss_latency::cpu.inst 41647443196 # number of ReadReq miss cycles 900system.cpu.icache.ReadReq_miss_latency::total 41647443196 # number of ReadReq miss cycles 901system.cpu.icache.demand_miss_latency::cpu.inst 41647443196 # number of demand (read+write) miss cycles 902system.cpu.icache.demand_miss_latency::total 41647443196 # number of demand (read+write) miss cycles 903system.cpu.icache.overall_miss_latency::cpu.inst 41647443196 # number of overall miss cycles 904system.cpu.icache.overall_miss_latency::total 41647443196 # number of overall miss cycles 905system.cpu.icache.ReadReq_accesses::cpu.inst 370702164 # number of ReadReq accesses(hits+misses) 906system.cpu.icache.ReadReq_accesses::total 370702164 # number of ReadReq accesses(hits+misses) 907system.cpu.icache.demand_accesses::cpu.inst 370702164 # number of demand (read+write) accesses 908system.cpu.icache.demand_accesses::total 370702164 # number of demand (read+write) accesses 909system.cpu.icache.overall_accesses::cpu.inst 370702164 # number of overall (read+write) accesses 910system.cpu.icache.overall_accesses::total 370702164 # number of overall (read+write) accesses 911system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013958 # miss rate for ReadReq accesses 912system.cpu.icache.ReadReq_miss_rate::total 0.013958 # miss rate for ReadReq accesses 913system.cpu.icache.demand_miss_rate::cpu.inst 0.013958 # miss rate for demand accesses 914system.cpu.icache.demand_miss_rate::total 0.013958 # miss rate for demand accesses 915system.cpu.icache.overall_miss_rate::cpu.inst 0.013958 # miss rate for overall accesses 916system.cpu.icache.overall_miss_rate::total 0.013958 # miss rate for overall accesses 917system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8049.165193 # average ReadReq miss latency 918system.cpu.icache.ReadReq_avg_miss_latency::total 8049.165193 # average ReadReq miss latency 919system.cpu.icache.demand_avg_miss_latency::cpu.inst 8049.165193 # average overall miss latency 920system.cpu.icache.demand_avg_miss_latency::total 8049.165193 # average overall miss latency 921system.cpu.icache.overall_avg_miss_latency::cpu.inst 8049.165193 # average overall miss latency 922system.cpu.icache.overall_avg_miss_latency::total 8049.165193 # average overall miss latency 923system.cpu.icache.blocked_cycles::no_mshrs 75254 # number of cycles access was blocked 924system.cpu.icache.blocked_cycles::no_targets 145 # number of cycles access was blocked 925system.cpu.icache.blocked::no_mshrs 3130 # number of cycles access was blocked 926system.cpu.icache.blocked::no_targets 5 # number of cycles access was blocked 927system.cpu.icache.avg_blocked_cycles::no_mshrs 24.042812 # average number of cycles each access was blocked 928system.cpu.icache.avg_blocked_cycles::no_targets 29 # average number of cycles each access was blocked 929system.cpu.icache.fast_writes 0 # number of fast writes performed 930system.cpu.icache.cache_copies 0 # number of cache copies performed 931system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3628 # number of ReadReq MSHR hits 932system.cpu.icache.ReadReq_mshr_hits::total 3628 # number of ReadReq MSHR hits 933system.cpu.icache.demand_mshr_hits::cpu.inst 3628 # number of demand (read+write) MSHR hits 934system.cpu.icache.demand_mshr_hits::total 3628 # number of demand (read+write) MSHR hits 935system.cpu.icache.overall_mshr_hits::cpu.inst 3628 # number of overall MSHR hits 936system.cpu.icache.overall_mshr_hits::total 3628 # number of overall MSHR hits 937system.cpu.icache.ReadReq_mshr_misses::cpu.inst 5170504 # number of ReadReq MSHR misses 938system.cpu.icache.ReadReq_mshr_misses::total 5170504 # number of ReadReq MSHR misses 939system.cpu.icache.demand_mshr_misses::cpu.inst 5170504 # number of demand (read+write) MSHR misses 940system.cpu.icache.demand_mshr_misses::total 5170504 # number of demand (read+write) MSHR misses 941system.cpu.icache.overall_mshr_misses::cpu.inst 5170504 # number of overall MSHR misses 942system.cpu.icache.overall_mshr_misses::total 5170504 # number of overall MSHR misses 943system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 36431387686 # number of ReadReq MSHR miss cycles 944system.cpu.icache.ReadReq_mshr_miss_latency::total 36431387686 # number of ReadReq MSHR miss cycles 945system.cpu.icache.demand_mshr_miss_latency::cpu.inst 36431387686 # number of demand (read+write) MSHR miss cycles 946system.cpu.icache.demand_mshr_miss_latency::total 36431387686 # number of demand (read+write) MSHR miss cycles 947system.cpu.icache.overall_mshr_miss_latency::cpu.inst 36431387686 # number of overall MSHR miss cycles 948system.cpu.icache.overall_mshr_miss_latency::total 36431387686 # number of overall MSHR miss cycles 949system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.013948 # mshr miss rate for ReadReq accesses 950system.cpu.icache.ReadReq_mshr_miss_rate::total 0.013948 # mshr miss rate for ReadReq accesses 951system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.013948 # mshr miss rate for demand accesses 952system.cpu.icache.demand_mshr_miss_rate::total 0.013948 # mshr miss rate for demand accesses 953system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.013948 # mshr miss rate for overall accesses 954system.cpu.icache.overall_mshr_miss_rate::total 0.013948 # mshr miss rate for overall accesses 955system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 7046.003192 # average ReadReq mshr miss latency 956system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 7046.003192 # average ReadReq mshr miss latency 957system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 7046.003192 # average overall mshr miss latency 958system.cpu.icache.demand_avg_mshr_miss_latency::total 7046.003192 # average overall mshr miss latency 959system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 7046.003192 # average overall mshr miss latency 960system.cpu.icache.overall_avg_mshr_miss_latency::total 7046.003192 # average overall mshr miss latency 961system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 962system.cpu.l2cache.prefetcher.num_hwpf_issued 1347095 # number of hwpf issued 963system.cpu.l2cache.prefetcher.pfIdentified 1354943 # number of prefetch candidates identified 964system.cpu.l2cache.prefetcher.pfBufferHit 6866 # number of redundant prefetches already in prefetch queue 965system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 966system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 967system.cpu.l2cache.prefetcher.pfSpanPage 4789921 # number of prefetches not generated due to page crossing 968system.cpu.l2cache.tags.replacements 299165 # number of replacements 969system.cpu.l2cache.tags.tagsinuse 16361.556320 # Cycle average of tags in use 970system.cpu.l2cache.tags.total_refs 7824806 # Total number of references to valid blocks. 971system.cpu.l2cache.tags.sampled_refs 315529 # Sample count of references to valid blocks. 972system.cpu.l2cache.tags.avg_refs 24.799007 # Average number of references to valid blocks. 973system.cpu.l2cache.tags.warmup_cycle 13406100000 # Cycle when the warmup percentage was hit. 974system.cpu.l2cache.tags.occ_blocks::writebacks 743.986923 # Average occupied blocks per requestor 975system.cpu.l2cache.tags.occ_blocks::cpu.inst 127.512620 # Average occupied blocks per requestor 976system.cpu.l2cache.tags.occ_blocks::cpu.data 8771.582614 # Average occupied blocks per requestor 977system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 6718.474164 # Average occupied blocks per requestor 978system.cpu.l2cache.tags.occ_percent::writebacks 0.045409 # Average percentage of cache occupancy 979system.cpu.l2cache.tags.occ_percent::cpu.inst 0.007783 # Average percentage of cache occupancy 980system.cpu.l2cache.tags.occ_percent::cpu.data 0.535375 # Average percentage of cache occupancy 981system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.410063 # Average percentage of cache occupancy 982system.cpu.l2cache.tags.occ_percent::total 0.998630 # Average percentage of cache occupancy 983system.cpu.l2cache.tags.occ_task_id_blocks::1022 6520 # Occupied blocks per task id 984system.cpu.l2cache.tags.occ_task_id_blocks::1024 9844 # Occupied blocks per task id 985system.cpu.l2cache.tags.age_task_id_blocks_1022::1 16 # Occupied blocks per task id 986system.cpu.l2cache.tags.age_task_id_blocks_1022::2 170 # Occupied blocks per task id 987system.cpu.l2cache.tags.age_task_id_blocks_1022::3 1454 # Occupied blocks per task id 988system.cpu.l2cache.tags.age_task_id_blocks_1022::4 4880 # Occupied blocks per task id 989system.cpu.l2cache.tags.age_task_id_blocks_1024::0 96 # Occupied blocks per task id 990system.cpu.l2cache.tags.age_task_id_blocks_1024::1 169 # Occupied blocks per task id 991system.cpu.l2cache.tags.age_task_id_blocks_1024::2 223 # Occupied blocks per task id 992system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2085 # Occupied blocks per task id 993system.cpu.l2cache.tags.age_task_id_blocks_1024::4 7271 # Occupied blocks per task id 994system.cpu.l2cache.tags.occ_task_id_percent::1022 0.397949 # Percentage of cache occupancy per task id 995system.cpu.l2cache.tags.occ_task_id_percent::1024 0.600830 # Percentage of cache occupancy per task id 996system.cpu.l2cache.tags.tag_accesses 139642360 # Number of tag accesses 997system.cpu.l2cache.tags.data_accesses 139642360 # Number of data accesses 998system.cpu.l2cache.ReadReq_hits::cpu.inst 5166932 # number of ReadReq hits 999system.cpu.l2cache.ReadReq_hits::cpu.data 1926211 # number of ReadReq hits 1000system.cpu.l2cache.ReadReq_hits::total 7093143 # number of ReadReq hits 1001system.cpu.l2cache.Writeback_hits::writebacks 735673 # number of Writeback hits 1002system.cpu.l2cache.Writeback_hits::total 735673 # number of Writeback hits 1003system.cpu.l2cache.ReadExReq_hits::cpu.data 717988 # number of ReadExReq hits 1004system.cpu.l2cache.ReadExReq_hits::total 717988 # number of ReadExReq hits 1005system.cpu.l2cache.demand_hits::cpu.inst 5166932 # number of demand (read+write) hits 1006system.cpu.l2cache.demand_hits::cpu.data 2644199 # number of demand (read+write) hits 1007system.cpu.l2cache.demand_hits::total 7811131 # number of demand (read+write) hits 1008system.cpu.l2cache.overall_hits::cpu.inst 5166932 # number of overall hits 1009system.cpu.l2cache.overall_hits::cpu.data 2644199 # number of overall hits 1010system.cpu.l2cache.overall_hits::total 7811131 # number of overall hits 1011system.cpu.l2cache.ReadReq_misses::cpu.inst 3554 # number of ReadReq misses 1012system.cpu.l2cache.ReadReq_misses::cpu.data 109639 # number of ReadReq misses 1013system.cpu.l2cache.ReadReq_misses::total 113193 # number of ReadReq misses 1014system.cpu.l2cache.UpgradeReq_misses::cpu.data 19 # number of UpgradeReq misses 1015system.cpu.l2cache.UpgradeReq_misses::total 19 # number of UpgradeReq misses 1016system.cpu.l2cache.ReadExReq_misses::cpu.data 2858 # number of ReadExReq misses 1017system.cpu.l2cache.ReadExReq_misses::total 2858 # number of ReadExReq misses 1018system.cpu.l2cache.demand_misses::cpu.inst 3554 # number of demand (read+write) misses 1019system.cpu.l2cache.demand_misses::cpu.data 112497 # number of demand (read+write) misses 1020system.cpu.l2cache.demand_misses::total 116051 # number of demand (read+write) misses 1021system.cpu.l2cache.overall_misses::cpu.inst 3554 # number of overall misses 1022system.cpu.l2cache.overall_misses::cpu.data 112497 # number of overall misses 1023system.cpu.l2cache.overall_misses::total 116051 # number of overall misses 1024system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 260989714 # number of ReadReq miss cycles 1025system.cpu.l2cache.ReadReq_miss_latency::cpu.data 8561938681 # number of ReadReq miss cycles 1026system.cpu.l2cache.ReadReq_miss_latency::total 8822928395 # number of ReadReq miss cycles 1027system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 23499 # number of UpgradeReq miss cycles 1028system.cpu.l2cache.UpgradeReq_miss_latency::total 23499 # number of UpgradeReq miss cycles 1029system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 205223699 # number of ReadExReq miss cycles 1030system.cpu.l2cache.ReadExReq_miss_latency::total 205223699 # number of ReadExReq miss cycles 1031system.cpu.l2cache.demand_miss_latency::cpu.inst 260989714 # number of demand (read+write) miss cycles 1032system.cpu.l2cache.demand_miss_latency::cpu.data 8767162380 # number of demand (read+write) miss cycles 1033system.cpu.l2cache.demand_miss_latency::total 9028152094 # number of demand (read+write) miss cycles 1034system.cpu.l2cache.overall_miss_latency::cpu.inst 260989714 # number of overall miss cycles 1035system.cpu.l2cache.overall_miss_latency::cpu.data 8767162380 # number of overall miss cycles 1036system.cpu.l2cache.overall_miss_latency::total 9028152094 # number of overall miss cycles 1037system.cpu.l2cache.ReadReq_accesses::cpu.inst 5170486 # number of ReadReq accesses(hits+misses) 1038system.cpu.l2cache.ReadReq_accesses::cpu.data 2035850 # number of ReadReq accesses(hits+misses) 1039system.cpu.l2cache.ReadReq_accesses::total 7206336 # number of ReadReq accesses(hits+misses) 1040system.cpu.l2cache.Writeback_accesses::writebacks 735673 # number of Writeback accesses(hits+misses) 1041system.cpu.l2cache.Writeback_accesses::total 735673 # number of Writeback accesses(hits+misses) 1042system.cpu.l2cache.UpgradeReq_accesses::cpu.data 19 # number of UpgradeReq accesses(hits+misses) 1043system.cpu.l2cache.UpgradeReq_accesses::total 19 # number of UpgradeReq accesses(hits+misses) 1044system.cpu.l2cache.ReadExReq_accesses::cpu.data 720846 # number of ReadExReq accesses(hits+misses) 1045system.cpu.l2cache.ReadExReq_accesses::total 720846 # number of ReadExReq accesses(hits+misses) 1046system.cpu.l2cache.demand_accesses::cpu.inst 5170486 # number of demand (read+write) accesses 1047system.cpu.l2cache.demand_accesses::cpu.data 2756696 # number of demand (read+write) accesses 1048system.cpu.l2cache.demand_accesses::total 7927182 # number of demand (read+write) accesses 1049system.cpu.l2cache.overall_accesses::cpu.inst 5170486 # number of overall (read+write) accesses 1050system.cpu.l2cache.overall_accesses::cpu.data 2756696 # number of overall (read+write) accesses 1051system.cpu.l2cache.overall_accesses::total 7927182 # number of overall (read+write) accesses 1052system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.000687 # miss rate for ReadReq accesses 1053system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.053854 # miss rate for ReadReq accesses 1054system.cpu.l2cache.ReadReq_miss_rate::total 0.015707 # miss rate for ReadReq accesses 1055system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses 1056system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses 1057system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.003965 # miss rate for ReadExReq accesses 1058system.cpu.l2cache.ReadExReq_miss_rate::total 0.003965 # miss rate for ReadExReq accesses 1059system.cpu.l2cache.demand_miss_rate::cpu.inst 0.000687 # miss rate for demand accesses 1060system.cpu.l2cache.demand_miss_rate::cpu.data 0.040809 # miss rate for demand accesses 1061system.cpu.l2cache.demand_miss_rate::total 0.014640 # miss rate for demand accesses 1062system.cpu.l2cache.overall_miss_rate::cpu.inst 0.000687 # miss rate for overall accesses 1063system.cpu.l2cache.overall_miss_rate::cpu.data 0.040809 # miss rate for overall accesses 1064system.cpu.l2cache.overall_miss_rate::total 0.014640 # miss rate for overall accesses 1065system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73435.485087 # average ReadReq miss latency 1066system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 78092.090232 # average ReadReq miss latency 1067system.cpu.l2cache.ReadReq_avg_miss_latency::total 77945.883535 # average ReadReq miss latency 1068system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 1236.789474 # average UpgradeReq miss latency 1069system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 1236.789474 # average UpgradeReq miss latency 1070system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71806.752624 # average ReadExReq miss latency 1071system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71806.752624 # average ReadExReq miss latency 1072system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73435.485087 # average overall miss latency 1073system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77932.410464 # average overall miss latency 1074system.cpu.l2cache.demand_avg_miss_latency::total 77794.694522 # average overall miss latency 1075system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73435.485087 # average overall miss latency 1076system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77932.410464 # average overall miss latency 1077system.cpu.l2cache.overall_avg_miss_latency::total 77794.694522 # average overall miss latency 1078system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1079system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1080system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1081system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1082system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1083system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1084system.cpu.l2cache.fast_writes 0 # number of fast writes performed 1085system.cpu.l2cache.cache_copies 0 # number of cache copies performed 1086system.cpu.l2cache.writebacks::writebacks 66342 # number of writebacks 1087system.cpu.l2cache.writebacks::total 66342 # number of writebacks 1088system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 14 # number of ReadReq MSHR hits 1089system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 1287 # number of ReadReq MSHR hits 1090system.cpu.l2cache.ReadReq_mshr_hits::total 1301 # number of ReadReq MSHR hits 1091system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 1460 # number of ReadExReq MSHR hits 1092system.cpu.l2cache.ReadExReq_mshr_hits::total 1460 # number of ReadExReq MSHR hits 1093system.cpu.l2cache.demand_mshr_hits::cpu.inst 14 # number of demand (read+write) MSHR hits 1094system.cpu.l2cache.demand_mshr_hits::cpu.data 2747 # number of demand (read+write) MSHR hits 1095system.cpu.l2cache.demand_mshr_hits::total 2761 # number of demand (read+write) MSHR hits 1096system.cpu.l2cache.overall_mshr_hits::cpu.inst 14 # number of overall MSHR hits 1097system.cpu.l2cache.overall_mshr_hits::cpu.data 2747 # number of overall MSHR hits 1098system.cpu.l2cache.overall_mshr_hits::total 2761 # number of overall MSHR hits 1099system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3540 # number of ReadReq MSHR misses 1100system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 108352 # number of ReadReq MSHR misses 1101system.cpu.l2cache.ReadReq_mshr_misses::total 111892 # number of ReadReq MSHR misses 1102system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 202242 # number of HardPFReq MSHR misses 1103system.cpu.l2cache.HardPFReq_mshr_misses::total 202242 # number of HardPFReq MSHR misses 1104system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 19 # number of UpgradeReq MSHR misses 1105system.cpu.l2cache.UpgradeReq_mshr_misses::total 19 # number of UpgradeReq MSHR misses 1106system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1398 # number of ReadExReq MSHR misses 1107system.cpu.l2cache.ReadExReq_mshr_misses::total 1398 # number of ReadExReq MSHR misses 1108system.cpu.l2cache.demand_mshr_misses::cpu.inst 3540 # number of demand (read+write) MSHR misses 1109system.cpu.l2cache.demand_mshr_misses::cpu.data 109750 # number of demand (read+write) MSHR misses 1110system.cpu.l2cache.demand_mshr_misses::total 113290 # number of demand (read+write) MSHR misses 1111system.cpu.l2cache.overall_mshr_misses::cpu.inst 3540 # number of overall MSHR misses 1112system.cpu.l2cache.overall_mshr_misses::cpu.data 109750 # number of overall MSHR misses 1113system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 202242 # number of overall MSHR misses 1114system.cpu.l2cache.overall_mshr_misses::total 315532 # number of overall MSHR misses 1115system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 229882786 # number of ReadReq MSHR miss cycles 1116system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 7609765250 # number of ReadReq MSHR miss cycles 1117system.cpu.l2cache.ReadReq_mshr_miss_latency::total 7839648036 # number of ReadReq MSHR miss cycles 1118system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 17078829649 # number of HardPFReq MSHR miss cycles 1119system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 17078829649 # number of HardPFReq MSHR miss cycles 1120system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 262019 # number of UpgradeReq MSHR miss cycles 1121system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 262019 # number of UpgradeReq MSHR miss cycles 1122system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 114010508 # number of ReadExReq MSHR miss cycles 1123system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 114010508 # number of ReadExReq MSHR miss cycles 1124system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 229882786 # number of demand (read+write) MSHR miss cycles 1125system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7723775758 # number of demand (read+write) MSHR miss cycles 1126system.cpu.l2cache.demand_mshr_miss_latency::total 7953658544 # number of demand (read+write) MSHR miss cycles 1127system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 229882786 # number of overall MSHR miss cycles 1128system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7723775758 # number of overall MSHR miss cycles 1129system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 17078829649 # number of overall MSHR miss cycles 1130system.cpu.l2cache.overall_mshr_miss_latency::total 25032488193 # number of overall MSHR miss cycles 1131system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.000685 # mshr miss rate for ReadReq accesses 1132system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.053222 # mshr miss rate for ReadReq accesses 1133system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015527 # mshr miss rate for ReadReq accesses 1134system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1135system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 1136system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses 1137system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses 1138system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001939 # mshr miss rate for ReadExReq accesses 1139system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001939 # mshr miss rate for ReadExReq accesses 1140system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.000685 # mshr miss rate for demand accesses 1141system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.039812 # mshr miss rate for demand accesses 1142system.cpu.l2cache.demand_mshr_miss_rate::total 0.014291 # mshr miss rate for demand accesses 1143system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.000685 # mshr miss rate for overall accesses 1144system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.039812 # mshr miss rate for overall accesses 1145system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses 1146system.cpu.l2cache.overall_mshr_miss_rate::total 0.039804 # mshr miss rate for overall accesses 1147system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64938.640113 # average ReadReq mshr miss latency 1148system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 70231.885429 # average ReadReq mshr miss latency 1149system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 70064.419583 # average ReadReq mshr miss latency 1150system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 84447.491861 # average HardPFReq mshr miss latency 1151system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 84447.491861 # average HardPFReq mshr miss latency 1152system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 13790.473684 # average UpgradeReq mshr miss latency 1153system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 13790.473684 # average UpgradeReq mshr miss latency 1154system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 81552.580830 # average ReadExReq mshr miss latency 1155system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 81552.580830 # average ReadExReq mshr miss latency 1156system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64938.640113 # average overall mshr miss latency 1157system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70376.088911 # average overall mshr miss latency 1158system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70206.183635 # average overall mshr miss latency 1159system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64938.640113 # average overall mshr miss latency 1160system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70376.088911 # average overall mshr miss latency 1161system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 84447.491861 # average overall mshr miss latency 1162system.cpu.l2cache.overall_avg_mshr_miss_latency::total 79334.229787 # average overall mshr miss latency 1163system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1164system.cpu.toL2Bus.trans_dist::ReadReq 7206354 # Transaction distribution 1165system.cpu.toL2Bus.trans_dist::ReadResp 7206353 # Transaction distribution 1166system.cpu.toL2Bus.trans_dist::Writeback 735673 # Transaction distribution 1167system.cpu.toL2Bus.trans_dist::HardPFReq 248887 # Transaction distribution 1168system.cpu.toL2Bus.trans_dist::UpgradeReq 19 # Transaction distribution 1169system.cpu.toL2Bus.trans_dist::UpgradeResp 19 # Transaction distribution 1170system.cpu.toL2Bus.trans_dist::ReadExReq 720846 # Transaction distribution 1171system.cpu.toL2Bus.trans_dist::ReadExResp 720846 # Transaction distribution 1172system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 10340989 # Packet count per connected master and slave (bytes) 1173system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6249103 # Packet count per connected master and slave (bytes) 1174system.cpu.toL2Bus.pkt_count::total 16590092 # Packet count per connected master and slave (bytes) 1175system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 330911040 # Cumulative packet size per connected master and slave (bytes) 1176system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 223511616 # Cumulative packet size per connected master and slave (bytes) 1177system.cpu.toL2Bus.pkt_size::total 554422656 # Cumulative packet size per connected master and slave (bytes) 1178system.cpu.toL2Bus.snoops 248905 # Total snoops (count) 1179system.cpu.toL2Bus.snoop_fanout::samples 8911779 # Request fanout histogram 1180system.cpu.toL2Bus.snoop_fanout::mean 1.027928 # Request fanout histogram 1181system.cpu.toL2Bus.snoop_fanout::stdev 0.164766 # Request fanout histogram 1182system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1183system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1184system.cpu.toL2Bus.snoop_fanout::1 8662892 97.21% 97.21% # Request fanout histogram 1185system.cpu.toL2Bus.snoop_fanout::2 248887 2.79% 100.00% # Request fanout histogram 1186system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1187system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 1188system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 1189system.cpu.toL2Bus.snoop_fanout::total 8911779 # Request fanout histogram 1190system.cpu.toL2Bus.reqLayer0.occupancy 5067119000 # Layer occupancy (ticks) 1191system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) 1192system.cpu.toL2Bus.respLayer0.occupancy 7756292749 # Layer occupancy (ticks) 1193system.cpu.toL2Bus.respLayer0.utilization 1.9 # Layer utilization (%) 1194system.cpu.toL2Bus.respLayer1.occupancy 4138723116 # Layer occupancy (ticks) 1195system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) 1196system.membus.trans_dist::ReadReq 314058 # Transaction distribution 1197system.membus.trans_dist::ReadResp 314058 # Transaction distribution 1198system.membus.trans_dist::Writeback 66342 # Transaction distribution 1199system.membus.trans_dist::UpgradeReq 19 # Transaction distribution 1200system.membus.trans_dist::UpgradeResp 19 # Transaction distribution 1201system.membus.trans_dist::ReadExReq 1398 # Transaction distribution 1202system.membus.trans_dist::ReadExResp 1398 # Transaction distribution 1203system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 697292 # Packet count per connected master and slave (bytes) 1204system.membus.pkt_count::total 697292 # Packet count per connected master and slave (bytes) 1205system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 24435072 # Cumulative packet size per connected master and slave (bytes) 1206system.membus.pkt_size::total 24435072 # Cumulative packet size per connected master and slave (bytes) 1207system.membus.snoops 0 # Total snoops (count) 1208system.membus.snoop_fanout::samples 381817 # Request fanout histogram 1209system.membus.snoop_fanout::mean 0 # Request fanout histogram 1210system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1211system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1212system.membus.snoop_fanout::0 381817 100.00% 100.00% # Request fanout histogram 1213system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 1214system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1215system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1216system.membus.snoop_fanout::max_value 0 # Request fanout histogram 1217system.membus.snoop_fanout::total 381817 # Request fanout histogram 1218system.membus.reqLayer0.occupancy 746606366 # Layer occupancy (ticks) 1219system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) 1220system.membus.respLayer1.occupancy 1648197495 # Layer occupancy (ticks) 1221system.membus.respLayer1.utilization 0.4 # Layer utilization (%) 1222 1223---------- End Simulation Statistics ---------- 1224