stats.txt revision 10352:5f1f92bf76ee
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.297198 # Number of seconds simulated 4sim_ticks 297198275500 # Number of ticks simulated 5final_tick 297198275500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 98901 # Simulator instruction rate (inst/s) 8host_op_rate 121761 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 45880544 # Simulator tick rate (ticks/s) 10host_mem_usage 261988 # Number of bytes of host memory used 11host_seconds 6477.65 # Real time elapsed on the host 12sim_insts 640649298 # Number of instructions simulated 13sim_ops 788724957 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 150208 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 18436864 # Number of bytes read from this memory 18system.physmem.bytes_read::total 18587072 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 150208 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 150208 # Number of instructions bytes read from this memory 21system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory 22system.physmem.bytes_written::total 4230272 # Number of bytes written to this memory 23system.physmem.num_reads::cpu.inst 2347 # Number of read requests responded to by this memory 24system.physmem.num_reads::cpu.data 288076 # Number of read requests responded to by this memory 25system.physmem.num_reads::total 290423 # Number of read requests responded to by this memory 26system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory 27system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory 28system.physmem.bw_read::cpu.inst 505413 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::cpu.data 62035569 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::total 62540982 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_inst_read::cpu.inst 505413 # Instruction read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::total 505413 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_write::writebacks 14233838 # Write bandwidth from this memory (bytes/s) 34system.physmem.bw_write::total 14233838 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_total::writebacks 14233838 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::cpu.inst 505413 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.data 62035569 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::total 76774820 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.readReqs 290424 # Number of read requests accepted 40system.physmem.writeReqs 66098 # Number of write requests accepted 41system.physmem.readBursts 290424 # Number of DRAM read bursts, including those serviced by the write queue 42system.physmem.writeBursts 66098 # Number of DRAM write bursts, including those merged in the write queue 43system.physmem.bytesReadDRAM 18565376 # Total number of bytes read from DRAM 44system.physmem.bytesReadWrQ 21760 # Total number of bytes read from write queue 45system.physmem.bytesWritten 4228224 # Total number of bytes written to DRAM 46system.physmem.bytesReadSys 18587136 # Total read bytes from the system interface side 47system.physmem.bytesWrittenSys 4230272 # Total written bytes from the system interface side 48system.physmem.servicedByWrQ 340 # Number of DRAM read bursts serviced by the write queue 49system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 50system.physmem.neitherReadNorWriteReqs 2334 # Number of requests that are neither read nor write 51system.physmem.perBankRdBursts::0 18318 # Per bank write bursts 52system.physmem.perBankRdBursts::1 18131 # Per bank write bursts 53system.physmem.perBankRdBursts::2 18196 # Per bank write bursts 54system.physmem.perBankRdBursts::3 18163 # Per bank write bursts 55system.physmem.perBankRdBursts::4 18256 # Per bank write bursts 56system.physmem.perBankRdBursts::5 18279 # Per bank write bursts 57system.physmem.perBankRdBursts::6 18091 # Per bank write bursts 58system.physmem.perBankRdBursts::7 17906 # Per bank write bursts 59system.physmem.perBankRdBursts::8 17946 # Per bank write bursts 60system.physmem.perBankRdBursts::9 17953 # Per bank write bursts 61system.physmem.perBankRdBursts::10 18007 # Per bank write bursts 62system.physmem.perBankRdBursts::11 18104 # Per bank write bursts 63system.physmem.perBankRdBursts::12 18147 # Per bank write bursts 64system.physmem.perBankRdBursts::13 18252 # Per bank write bursts 65system.physmem.perBankRdBursts::14 18085 # Per bank write bursts 66system.physmem.perBankRdBursts::15 18250 # Per bank write bursts 67system.physmem.perBankWrBursts::0 4173 # Per bank write bursts 68system.physmem.perBankWrBursts::1 4100 # Per bank write bursts 69system.physmem.perBankWrBursts::2 4137 # Per bank write bursts 70system.physmem.perBankWrBursts::3 4146 # Per bank write bursts 71system.physmem.perBankWrBursts::4 4224 # Per bank write bursts 72system.physmem.perBankWrBursts::5 4224 # Per bank write bursts 73system.physmem.perBankWrBursts::6 4170 # Per bank write bursts 74system.physmem.perBankWrBursts::7 4094 # Per bank write bursts 75system.physmem.perBankWrBursts::8 4094 # Per bank write bursts 76system.physmem.perBankWrBursts::9 4091 # Per bank write bursts 77system.physmem.perBankWrBursts::10 4093 # Per bank write bursts 78system.physmem.perBankWrBursts::11 4095 # Per bank write bursts 79system.physmem.perBankWrBursts::12 4096 # Per bank write bursts 80system.physmem.perBankWrBursts::13 4094 # Per bank write bursts 81system.physmem.perBankWrBursts::14 4096 # Per bank write bursts 82system.physmem.perBankWrBursts::15 4139 # Per bank write bursts 83system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 84system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 85system.physmem.totGap 297198223500 # Total gap between requests 86system.physmem.readPktSize::0 0 # Read request sizes (log2) 87system.physmem.readPktSize::1 0 # Read request sizes (log2) 88system.physmem.readPktSize::2 0 # Read request sizes (log2) 89system.physmem.readPktSize::3 0 # Read request sizes (log2) 90system.physmem.readPktSize::4 0 # Read request sizes (log2) 91system.physmem.readPktSize::5 0 # Read request sizes (log2) 92system.physmem.readPktSize::6 290424 # Read request sizes (log2) 93system.physmem.writePktSize::0 0 # Write request sizes (log2) 94system.physmem.writePktSize::1 0 # Write request sizes (log2) 95system.physmem.writePktSize::2 0 # Write request sizes (log2) 96system.physmem.writePktSize::3 0 # Write request sizes (log2) 97system.physmem.writePktSize::4 0 # Write request sizes (log2) 98system.physmem.writePktSize::5 0 # Write request sizes (log2) 99system.physmem.writePktSize::6 66098 # Write request sizes (log2) 100system.physmem.rdQLenPdf::0 235690 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::1 49717 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::2 4573 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::3 81 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::4 20 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 132system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 133system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 134system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::15 960 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::16 960 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::17 2419 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::18 4037 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::19 4096 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::20 4031 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::21 4034 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::22 4057 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::23 4045 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::24 4603 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::25 4179 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::26 4050 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::27 4477 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::28 4017 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::29 4022 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::30 4018 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::31 4048 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::32 4030 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 196system.physmem.bytesPerActivate::samples 106390 # Bytes accessed per row activation 197system.physmem.bytesPerActivate::mean 214.227653 # Bytes accessed per row activation 198system.physmem.bytesPerActivate::gmean 137.234885 # Bytes accessed per row activation 199system.physmem.bytesPerActivate::stdev 270.519636 # Bytes accessed per row activation 200system.physmem.bytesPerActivate::0-127 42398 39.85% 39.85% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::128-255 42939 40.36% 80.21% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::256-383 9834 9.24% 89.45% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::384-511 319 0.30% 89.75% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::512-639 247 0.23% 89.99% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::640-767 237 0.22% 90.21% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::768-895 324 0.30% 90.51% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::896-1023 1664 1.56% 92.08% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::1024-1151 8428 7.92% 100.00% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::total 106390 # Bytes accessed per row activation 210system.physmem.rdPerTurnAround::samples 4009 # Reads before turning the bus around for writes 211system.physmem.rdPerTurnAround::mean 48.488651 # Reads before turning the bus around for writes 212system.physmem.rdPerTurnAround::gmean 36.041584 # Reads before turning the bus around for writes 213system.physmem.rdPerTurnAround::stdev 505.320352 # Reads before turning the bus around for writes 214system.physmem.rdPerTurnAround::0-1023 4006 99.93% 99.93% # Reads before turning the bus around for writes 215system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.95% # Reads before turning the bus around for writes 216system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes 217system.physmem.rdPerTurnAround::31744-32767 1 0.02% 100.00% # Reads before turning the bus around for writes 218system.physmem.rdPerTurnAround::total 4009 # Reads before turning the bus around for writes 219system.physmem.wrPerTurnAround::samples 4009 # Writes before turning the bus around for reads 220system.physmem.wrPerTurnAround::mean 16.479421 # Writes before turning the bus around for reads 221system.physmem.wrPerTurnAround::gmean 16.458127 # Writes before turning the bus around for reads 222system.physmem.wrPerTurnAround::stdev 0.855088 # Writes before turning the bus around for reads 223system.physmem.wrPerTurnAround::16 3049 76.05% 76.05% # Writes before turning the bus around for reads 224system.physmem.wrPerTurnAround::17 1 0.02% 76.08% # Writes before turning the bus around for reads 225system.physmem.wrPerTurnAround::18 956 23.85% 99.93% # Writes before turning the bus around for reads 226system.physmem.wrPerTurnAround::19 3 0.07% 100.00% # Writes before turning the bus around for reads 227system.physmem.wrPerTurnAround::total 4009 # Writes before turning the bus around for reads 228system.physmem.totQLat 3531270750 # Total ticks spent queuing 229system.physmem.totMemAccLat 8970345750 # Total ticks spent from burst creation until serviced by the DRAM 230system.physmem.totBusLat 1450420000 # Total ticks spent in databus transfers 231system.physmem.avgQLat 12173.27 # Average queueing delay per DRAM burst 232system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 233system.physmem.avgMemAccLat 30923.27 # Average memory access latency per DRAM burst 234system.physmem.avgRdBW 62.47 # Average DRAM read bandwidth in MiByte/s 235system.physmem.avgWrBW 14.23 # Average achieved write bandwidth in MiByte/s 236system.physmem.avgRdBWSys 62.54 # Average system read bandwidth in MiByte/s 237system.physmem.avgWrBWSys 14.23 # Average system write bandwidth in MiByte/s 238system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 239system.physmem.busUtil 0.60 # Data bus utilization in percentage 240system.physmem.busUtilRead 0.49 # Data bus utilization in percentage for reads 241system.physmem.busUtilWrite 0.11 # Data bus utilization in percentage for writes 242system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing 243system.physmem.avgWrQLen 28.82 # Average write queue length when enqueuing 244system.physmem.readRowHits 199840 # Number of row buffer hits during reads 245system.physmem.writeRowHits 49907 # Number of row buffer hits during writes 246system.physmem.readRowHitRate 68.89 # Row buffer hit rate for reads 247system.physmem.writeRowHitRate 75.50 # Row buffer hit rate for writes 248system.physmem.avgGap 833604.16 # Average gap between requests 249system.physmem.pageHitRate 70.12 # Row buffer hit rate, read and write combined 250system.physmem.memoryStateTime::IDLE 84430805250 # Time in different power states 251system.physmem.memoryStateTime::REF 9923940000 # Time in different power states 252system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states 253system.physmem.memoryStateTime::ACT 202838904750 # Time in different power states 254system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states 255system.membus.throughput 76774820 # Throughput (bytes/s) 256system.membus.trans_dist::ReadReq 224345 # Transaction distribution 257system.membus.trans_dist::ReadResp 224344 # Transaction distribution 258system.membus.trans_dist::Writeback 66098 # Transaction distribution 259system.membus.trans_dist::UpgradeReq 2334 # Transaction distribution 260system.membus.trans_dist::UpgradeResp 2334 # Transaction distribution 261system.membus.trans_dist::ReadExReq 66079 # Transaction distribution 262system.membus.trans_dist::ReadExResp 66079 # Transaction distribution 263system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 651613 # Packet count per connected master and slave (bytes) 264system.membus.pkt_count::total 651613 # Packet count per connected master and slave (bytes) 265system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22817344 # Cumulative packet size per connected master and slave (bytes) 266system.membus.tot_pkt_size::total 22817344 # Cumulative packet size per connected master and slave (bytes) 267system.membus.data_through_bus 22817344 # Total data (bytes) 268system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 269system.membus.reqLayer0.occupancy 1003041500 # Layer occupancy (ticks) 270system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) 271system.membus.respLayer1.occupancy 2737822416 # Layer occupancy (ticks) 272system.membus.respLayer1.utilization 0.9 # Layer utilization (%) 273system.cpu_clk_domain.clock 500 # Clock period in ticks 274system.cpu.branchPred.lookups 271863224 # Number of BP lookups 275system.cpu.branchPred.condPredicted 178425431 # Number of conditional branches predicted 276system.cpu.branchPred.condIncorrect 15415799 # Number of conditional branches incorrect 277system.cpu.branchPred.BTBLookups 186524109 # Number of BTB lookups 278system.cpu.branchPred.BTBHits 146250524 # Number of BTB hits 279system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 280system.cpu.branchPred.BTBHitPct 78.408376 # BTB Hit Percentage 281system.cpu.branchPred.usedRAS 34625446 # Number of times the RAS was used to get a target. 282system.cpu.branchPred.RASInCorrect 1929978 # Number of incorrect RAS predictions. 283system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 284system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 285system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 286system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 287system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 288system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 289system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 290system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 291system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 292system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 293system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 294system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 295system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 296system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 297system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 298system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 299system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 300system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 301system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 302system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 303system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 304system.cpu.dtb.inst_hits 0 # ITB inst hits 305system.cpu.dtb.inst_misses 0 # ITB inst misses 306system.cpu.dtb.read_hits 0 # DTB read hits 307system.cpu.dtb.read_misses 0 # DTB read misses 308system.cpu.dtb.write_hits 0 # DTB write hits 309system.cpu.dtb.write_misses 0 # DTB write misses 310system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 311system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 312system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 313system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 314system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 315system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 316system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 317system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 318system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 319system.cpu.dtb.read_accesses 0 # DTB read accesses 320system.cpu.dtb.write_accesses 0 # DTB write accesses 321system.cpu.dtb.inst_accesses 0 # ITB inst accesses 322system.cpu.dtb.hits 0 # DTB hits 323system.cpu.dtb.misses 0 # DTB misses 324system.cpu.dtb.accesses 0 # DTB accesses 325system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 326system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 327system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 328system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 329system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 330system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 331system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 332system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 333system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 334system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 335system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 336system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 337system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 338system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 339system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 340system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 341system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 342system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 343system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 344system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 345system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 346system.cpu.itb.inst_hits 0 # ITB inst hits 347system.cpu.itb.inst_misses 0 # ITB inst misses 348system.cpu.itb.read_hits 0 # DTB read hits 349system.cpu.itb.read_misses 0 # DTB read misses 350system.cpu.itb.write_hits 0 # DTB write hits 351system.cpu.itb.write_misses 0 # DTB write misses 352system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 353system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 354system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 355system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 356system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 357system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 358system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 359system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 360system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 361system.cpu.itb.read_accesses 0 # DTB read accesses 362system.cpu.itb.write_accesses 0 # DTB write accesses 363system.cpu.itb.inst_accesses 0 # ITB inst accesses 364system.cpu.itb.hits 0 # DTB hits 365system.cpu.itb.misses 0 # DTB misses 366system.cpu.itb.accesses 0 # DTB accesses 367system.cpu.workload.num_syscalls 673 # Number of system calls 368system.cpu.numCycles 594396552 # number of cpu cycles simulated 369system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 370system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 371system.cpu.fetch.icacheStallCycles 217387549 # Number of cycles fetch is stalled on an Icache miss 372system.cpu.fetch.Insts 1367579713 # Number of instructions fetch has processed 373system.cpu.fetch.Branches 271863224 # Number of branches that fetch encountered 374system.cpu.fetch.predictedBranches 180875970 # Number of branches that fetch has predicted taken 375system.cpu.fetch.Cycles 338099313 # Number of cycles fetch has run and was not squashing or blocked 376system.cpu.fetch.SquashCycles 30904558 # Number of cycles fetch has spent squashing 377system.cpu.fetch.MiscStallCycles 628206 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 378system.cpu.fetch.PendingTrapStallCycles 6076291 # Number of stall cycles due to pending traps 379system.cpu.fetch.IcacheWaitRetryStallCycles 107 # Number of stall cycles due to full MSHR 380system.cpu.fetch.CacheLines 207850438 # Number of cache lines fetched 381system.cpu.fetch.IcacheSquashes 5507154 # Number of outstanding Icache misses that were squashed 382system.cpu.fetch.rateDist::samples 577643745 # Number of instructions fetched each cycle (Total) 383system.cpu.fetch.rateDist::mean 2.955013 # Number of instructions fetched each cycle (Total) 384system.cpu.fetch.rateDist::stdev 3.177882 # Number of instructions fetched each cycle (Total) 385system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 386system.cpu.fetch.rateDist::0 246926096 42.75% 42.75% # Number of instructions fetched each cycle (Total) 387system.cpu.fetch.rateDist::1 22334065 3.87% 46.61% # Number of instructions fetched each cycle (Total) 388system.cpu.fetch.rateDist::2 58641984 10.15% 56.77% # Number of instructions fetched each cycle (Total) 389system.cpu.fetch.rateDist::3 13805206 2.39% 59.16% # Number of instructions fetched each cycle (Total) 390system.cpu.fetch.rateDist::4 49967679 8.65% 67.81% # Number of instructions fetched each cycle (Total) 391system.cpu.fetch.rateDist::5 26102781 4.52% 72.32% # Number of instructions fetched each cycle (Total) 392system.cpu.fetch.rateDist::6 32011884 5.54% 77.87% # Number of instructions fetched each cycle (Total) 393system.cpu.fetch.rateDist::7 19377139 3.35% 81.22% # Number of instructions fetched each cycle (Total) 394system.cpu.fetch.rateDist::8 108476911 18.78% 100.00% # Number of instructions fetched each cycle (Total) 395system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 396system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 397system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 398system.cpu.fetch.rateDist::total 577643745 # Number of instructions fetched each cycle (Total) 399system.cpu.fetch.branchRate 0.457377 # Number of branch fetches per cycle 400system.cpu.fetch.rate 2.300787 # Number of inst fetches per cycle 401system.cpu.decode.IdleCycles 170543616 # Number of cycles decode is idle 402system.cpu.decode.BlockedCycles 112383913 # Number of cycles decode is blocked 403system.cpu.decode.RunCycles 256390493 # Number of cycles decode is running 404system.cpu.decode.UnblockCycles 22882666 # Number of cycles decode is unblocking 405system.cpu.decode.SquashCycles 15443057 # Number of cycles decode is squashing 406system.cpu.decode.BranchResolved 30474424 # Number of times decode resolved a branch 407system.cpu.decode.BranchMispred 9349 # Number of times decode detected a branch misprediction 408system.cpu.decode.DecodedInsts 1602087744 # Number of instructions handled by decode 409system.cpu.decode.SquashedInsts 25664 # Number of squashed instructions handled by decode 410system.cpu.rename.SquashCycles 15443057 # Number of cycles rename is squashing 411system.cpu.rename.IdleCycles 180102309 # Number of cycles rename is idle 412system.cpu.rename.BlockCycles 80879107 # Number of cycles rename is blocking 413system.cpu.rename.serializeStallCycles 304937 # count of cycles rename stalled for serializing inst 414system.cpu.rename.RunCycles 269061579 # Number of cycles rename is running 415system.cpu.rename.UnblockCycles 31852756 # Number of cycles rename is unblocking 416system.cpu.rename.RenamedInsts 1553633601 # Number of instructions processed by rename 417system.cpu.rename.ROBFullEvents 27722 # Number of times rename has blocked due to ROB full 418system.cpu.rename.IQFullEvents 3084329 # Number of times rename has blocked due to IQ full 419system.cpu.rename.LQFullEvents 23262068 # Number of times rename has blocked due to LQ full 420system.cpu.rename.SQFullEvents 5400130 # Number of times rename has blocked due to SQ full 421system.cpu.rename.RenamedOperands 1588085164 # Number of destination operands rename has renamed 422system.cpu.rename.RenameLookups 7592228001 # Number of register rename lookups that rename has made 423system.cpu.rename.int_rename_lookups 1750427089 # Number of integer rename lookups 424system.cpu.rename.fp_rename_lookups 56767331 # Number of floating rename lookups 425system.cpu.rename.CommittedMaps 874778230 # Number of HB maps that are committed 426system.cpu.rename.UndoneMaps 713306934 # Number of HB maps that are undone due to squashing 427system.cpu.rename.serializingInsts 13108 # count of serializing insts renamed 428system.cpu.rename.tempSerializingInsts 10964 # count of temporary serializing insts renamed 429system.cpu.rename.skidInsts 53001201 # count of insts added to the skid buffer 430system.cpu.memDep0.insertedLoads 494421032 # Number of loads inserted to the mem dependence unit. 431system.cpu.memDep0.insertedStores 283375622 # Number of stores inserted to the mem dependence unit. 432system.cpu.memDep0.conflictingLoads 38186333 # Number of conflicting loads. 433system.cpu.memDep0.conflictingStores 81232307 # Number of conflicting stores. 434system.cpu.iq.iqInstsAdded 1474584555 # Number of instructions added to the IQ (excludes non-spec) 435system.cpu.iq.iqNonSpecInstsAdded 16256 # Number of non-speculative instructions added to the IQ 436system.cpu.iq.iqInstsIssued 1149612413 # Number of instructions issued 437system.cpu.iq.iqSquashedInstsIssued 2320605 # Number of squashed instructions issued 438system.cpu.iq.iqSquashedInstsExamined 685767226 # Number of squashed instructions iterated over during squash; mainly for profiling 439system.cpu.iq.iqSquashedOperandsExamined 1987453954 # Number of squashed operands that are examined and possibly removed from graph 440system.cpu.iq.iqSquashedNonSpecRemoved 4102 # Number of squashed non-spec instructions that were removed 441system.cpu.iq.issued_per_cycle::samples 577643745 # Number of insts issued each cycle 442system.cpu.iq.issued_per_cycle::mean 1.990175 # Number of insts issued each cycle 443system.cpu.iq.issued_per_cycle::stdev 1.969584 # Number of insts issued each cycle 444system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 445system.cpu.iq.issued_per_cycle::0 197611085 34.21% 34.21% # Number of insts issued each cycle 446system.cpu.iq.issued_per_cycle::1 85639840 14.83% 49.04% # Number of insts issued each cycle 447system.cpu.iq.issued_per_cycle::2 74707514 12.93% 61.97% # Number of insts issued each cycle 448system.cpu.iq.issued_per_cycle::3 82105787 14.21% 76.18% # Number of insts issued each cycle 449system.cpu.iq.issued_per_cycle::4 66954970 11.59% 87.77% # Number of insts issued each cycle 450system.cpu.iq.issued_per_cycle::5 40972938 7.09% 94.87% # Number of insts issued each cycle 451system.cpu.iq.issued_per_cycle::6 18446421 3.19% 98.06% # Number of insts issued each cycle 452system.cpu.iq.issued_per_cycle::7 4764432 0.82% 98.88% # Number of insts issued each cycle 453system.cpu.iq.issued_per_cycle::8 6440758 1.12% 100.00% # Number of insts issued each cycle 454system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 455system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 456system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 457system.cpu.iq.issued_per_cycle::total 577643745 # Number of insts issued each cycle 458system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 459system.cpu.iq.fu_full::IntAlu 853039 1.90% 1.90% # attempts to use FU when none available 460system.cpu.iq.fu_full::IntMult 10574 0.02% 1.92% # attempts to use FU when none available 461system.cpu.iq.fu_full::IntDiv 0 0.00% 1.92% # attempts to use FU when none available 462system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.92% # attempts to use FU when none available 463system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.92% # attempts to use FU when none available 464system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.92% # attempts to use FU when none available 465system.cpu.iq.fu_full::FloatMult 0 0.00% 1.92% # attempts to use FU when none available 466system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.92% # attempts to use FU when none available 467system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.92% # attempts to use FU when none available 468system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.92% # attempts to use FU when none available 469system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.92% # attempts to use FU when none available 470system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.92% # attempts to use FU when none available 471system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.92% # attempts to use FU when none available 472system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.92% # attempts to use FU when none available 473system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.92% # attempts to use FU when none available 474system.cpu.iq.fu_full::SimdMult 0 0.00% 1.92% # attempts to use FU when none available 475system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.92% # attempts to use FU when none available 476system.cpu.iq.fu_full::SimdShift 0 0.00% 1.92% # attempts to use FU when none available 477system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.92% # attempts to use FU when none available 478system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.92% # attempts to use FU when none available 479system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.92% # attempts to use FU when none available 480system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.92% # attempts to use FU when none available 481system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.92% # attempts to use FU when none available 482system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.92% # attempts to use FU when none available 483system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.92% # attempts to use FU when none available 484system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.92% # attempts to use FU when none available 485system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.92% # attempts to use FU when none available 486system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.92% # attempts to use FU when none available 487system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.92% # attempts to use FU when none available 488system.cpu.iq.fu_full::MemRead 27015778 60.17% 62.09% # attempts to use FU when none available 489system.cpu.iq.fu_full::MemWrite 17022674 37.91% 100.00% # attempts to use FU when none available 490system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 491system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 492system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 493system.cpu.iq.FU_type_0::IntAlu 506618209 44.07% 44.07% # Type of FU issued 494system.cpu.iq.FU_type_0::IntMult 5850863 0.51% 44.58% # Type of FU issued 495system.cpu.iq.FU_type_0::IntDiv 0 0.00% 44.58% # Type of FU issued 496system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 44.58% # Type of FU issued 497system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 44.58% # Type of FU issued 498system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 44.58% # Type of FU issued 499system.cpu.iq.FU_type_0::FloatMult 0 0.00% 44.58% # Type of FU issued 500system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 44.58% # Type of FU issued 501system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 44.58% # Type of FU issued 502system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 44.58% # Type of FU issued 503system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 44.58% # Type of FU issued 504system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 44.58% # Type of FU issued 505system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 44.58% # Type of FU issued 506system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 44.58% # Type of FU issued 507system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 44.58% # Type of FU issued 508system.cpu.iq.FU_type_0::SimdMult 0 0.00% 44.58% # Type of FU issued 509system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 44.58% # Type of FU issued 510system.cpu.iq.FU_type_0::SimdShift 0 0.00% 44.58% # Type of FU issued 511system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 44.58% # Type of FU issued 512system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 44.58% # Type of FU issued 513system.cpu.iq.FU_type_0::SimdFloatAdd 1274977 0.11% 44.69% # Type of FU issued 514system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 44.69% # Type of FU issued 515system.cpu.iq.FU_type_0::SimdFloatCmp 3188014 0.28% 44.97% # Type of FU issued 516system.cpu.iq.FU_type_0::SimdFloatCvt 2550893 0.22% 45.19% # Type of FU issued 517system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 45.19% # Type of FU issued 518system.cpu.iq.FU_type_0::SimdFloatMisc 11539273 1.00% 46.19% # Type of FU issued 519system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 46.19% # Type of FU issued 520system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 46.19% # Type of FU issued 521system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 46.19% # Type of FU issued 522system.cpu.iq.FU_type_0::MemRead 402298542 34.99% 81.19% # Type of FU issued 523system.cpu.iq.FU_type_0::MemWrite 216291642 18.81% 100.00% # Type of FU issued 524system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 525system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 526system.cpu.iq.FU_type_0::total 1149612413 # Type of FU issued 527system.cpu.iq.rate 1.934083 # Inst issue rate 528system.cpu.iq.fu_busy_cnt 44902065 # FU busy when requested 529system.cpu.iq.fu_busy_rate 0.039058 # FU busy rate (busy events/executed inst) 530system.cpu.iq.int_inst_queue_reads 2861318586 # Number of integer instruction queue reads 531system.cpu.iq.int_inst_queue_writes 2106127825 # Number of integer instruction queue writes 532system.cpu.iq.int_inst_queue_wakeup_accesses 1031796042 # Number of integer instruction queue wakeup accesses 533system.cpu.iq.fp_inst_queue_reads 62772655 # Number of floating instruction queue reads 534system.cpu.iq.fp_inst_queue_writes 54292666 # Number of floating instruction queue writes 535system.cpu.iq.fp_inst_queue_wakeup_accesses 30270248 # Number of floating instruction queue wakeup accesses 536system.cpu.iq.int_alu_accesses 1162493023 # Number of integer alu accesses 537system.cpu.iq.fp_alu_accesses 32021455 # Number of floating point alu accesses 538system.cpu.iew.lsq.thread0.forwLoads 23570591 # Number of loads that had data forwarded from stores 539system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 540system.cpu.iew.lsq.thread0.squashedLoads 242180094 # Number of loads squashed 541system.cpu.iew.lsq.thread0.ignoredResponses 1210 # Number of memory responses ignored because the instruction is squashed 542system.cpu.iew.lsq.thread0.memOrderViolation 685580 # Number of memory ordering violations 543system.cpu.iew.lsq.thread0.squashedStores 154395126 # Number of stores squashed 544system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 545system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 546system.cpu.iew.lsq.thread0.rescheduledLoads 29018041 # Number of loads that were rescheduled 547system.cpu.iew.lsq.thread0.cacheBlocked 192 # Number of times an access to memory failed due to the cache being blocked 548system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 549system.cpu.iew.iewSquashCycles 15443057 # Number of cycles IEW is squashing 550system.cpu.iew.iewBlockCycles 78194989 # Number of cycles IEW is blocking 551system.cpu.iew.iewUnblockCycles 1280631 # Number of cycles IEW is unblocking 552system.cpu.iew.iewDispatchedInsts 1475233939 # Number of instructions dispatched to IQ 553system.cpu.iew.iewDispSquashedInsts 214769 # Number of squashed instructions skipped by dispatch 554system.cpu.iew.iewDispLoadInsts 494421032 # Number of dispatched load instructions 555system.cpu.iew.iewDispStoreInsts 283375622 # Number of dispatched store instructions 556system.cpu.iew.iewDispNonSpecInsts 10516 # Number of dispatched non-speculative instructions 557system.cpu.iew.iewIQFullEvents 630754 # Number of times the IQ has become full, causing a stall 558system.cpu.iew.iewLSQFullEvents 23941 # Number of times the LSQ has become full, causing a stall 559system.cpu.iew.memOrderViolationEvents 685580 # Number of memory order violations 560system.cpu.iew.predictedTakenIncorrect 16670086 # Number of branches that were predicted taken incorrectly 561system.cpu.iew.predictedNotTakenIncorrect 506202 # Number of branches that were predicted not taken incorrectly 562system.cpu.iew.branchMispredicts 17176288 # Number of branch mispredicts detected at execute 563system.cpu.iew.iewExecutedInsts 1116354859 # Number of executed instructions 564system.cpu.iew.iewExecLoadInsts 386341523 # Number of load instructions executed 565system.cpu.iew.iewExecSquashedInsts 33257554 # Number of squashed instructions skipped in execute 566system.cpu.iew.exec_swp 0 # number of swp insts executed 567system.cpu.iew.exec_nop 633128 # number of nop insts executed 568system.cpu.iew.exec_refs 593821006 # number of memory reference insts executed 569system.cpu.iew.exec_branches 162537737 # Number of branches executed 570system.cpu.iew.exec_stores 207479483 # Number of stores executed 571system.cpu.iew.exec_rate 1.878131 # Inst execution rate 572system.cpu.iew.wb_sent 1074811517 # cumulative count of insts sent to commit 573system.cpu.iew.wb_count 1062066290 # cumulative count of insts written-back 574system.cpu.iew.wb_producers 606518919 # num instructions producing a value 575system.cpu.iew.wb_consumers 1092664472 # num instructions consuming a value 576system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 577system.cpu.iew.wb_rate 1.786798 # insts written-back per cycle 578system.cpu.iew.wb_fanout 0.555082 # average fanout of values written-back 579system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 580system.cpu.commit.commitSquashedInsts 686508704 # The number of squashed insts skipped by commit 581system.cpu.commit.commitNonSpecStalls 12154 # The number of times commit has been forced to stall to communicate backwards 582system.cpu.commit.branchMispredicts 15406577 # The number of times a branch was mispredicted 583system.cpu.commit.committed_per_cycle::samples 485351634 # Number of insts commited each cycle 584system.cpu.commit.committed_per_cycle::mean 1.625069 # Number of insts commited each cycle 585system.cpu.commit.committed_per_cycle::stdev 2.327523 # Number of insts commited each cycle 586system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 587system.cpu.commit.committed_per_cycle::0 210489753 43.37% 43.37% # Number of insts commited each cycle 588system.cpu.commit.committed_per_cycle::1 125850152 25.93% 69.30% # Number of insts commited each cycle 589system.cpu.commit.committed_per_cycle::2 47800480 9.85% 79.15% # Number of insts commited each cycle 590system.cpu.commit.committed_per_cycle::3 20690881 4.26% 83.41% # Number of insts commited each cycle 591system.cpu.commit.committed_per_cycle::4 22810841 4.70% 88.11% # Number of insts commited each cycle 592system.cpu.commit.committed_per_cycle::5 8150144 1.68% 89.79% # Number of insts commited each cycle 593system.cpu.commit.committed_per_cycle::6 8105919 1.67% 91.46% # Number of insts commited each cycle 594system.cpu.commit.committed_per_cycle::7 7050996 1.45% 92.91% # Number of insts commited each cycle 595system.cpu.commit.committed_per_cycle::8 34402468 7.09% 100.00% # Number of insts commited each cycle 596system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 597system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 598system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 599system.cpu.commit.committed_per_cycle::total 485351634 # Number of insts commited each cycle 600system.cpu.commit.committedInsts 640654410 # Number of instructions committed 601system.cpu.commit.committedOps 788730069 # Number of ops (including micro ops) committed 602system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 603system.cpu.commit.refs 381221434 # Number of memory references committed 604system.cpu.commit.loads 252240938 # Number of loads committed 605system.cpu.commit.membars 5740 # Number of memory barriers committed 606system.cpu.commit.branches 137364859 # Number of branches committed 607system.cpu.commit.fp_insts 24239771 # Number of committed floating point instructions. 608system.cpu.commit.int_insts 682251399 # Number of committed integer instructions. 609system.cpu.commit.function_calls 19275340 # Number of function calls committed. 610system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 611system.cpu.commit.op_class_0::IntAlu 385756793 48.91% 48.91% # Class of committed instruction 612system.cpu.commit.op_class_0::IntMult 5173441 0.66% 49.56% # Class of committed instruction 613system.cpu.commit.op_class_0::IntDiv 0 0.00% 49.56% # Class of committed instruction 614system.cpu.commit.op_class_0::FloatAdd 0 0.00% 49.56% # Class of committed instruction 615system.cpu.commit.op_class_0::FloatCmp 0 0.00% 49.56% # Class of committed instruction 616system.cpu.commit.op_class_0::FloatCvt 0 0.00% 49.56% # Class of committed instruction 617system.cpu.commit.op_class_0::FloatMult 0 0.00% 49.56% # Class of committed instruction 618system.cpu.commit.op_class_0::FloatDiv 0 0.00% 49.56% # Class of committed instruction 619system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 49.56% # Class of committed instruction 620system.cpu.commit.op_class_0::SimdAdd 0 0.00% 49.56% # Class of committed instruction 621system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 49.56% # Class of committed instruction 622system.cpu.commit.op_class_0::SimdAlu 0 0.00% 49.56% # Class of committed instruction 623system.cpu.commit.op_class_0::SimdCmp 0 0.00% 49.56% # Class of committed instruction 624system.cpu.commit.op_class_0::SimdCvt 0 0.00% 49.56% # Class of committed instruction 625system.cpu.commit.op_class_0::SimdMisc 0 0.00% 49.56% # Class of committed instruction 626system.cpu.commit.op_class_0::SimdMult 0 0.00% 49.56% # Class of committed instruction 627system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 49.56% # Class of committed instruction 628system.cpu.commit.op_class_0::SimdShift 0 0.00% 49.56% # Class of committed instruction 629system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 49.56% # Class of committed instruction 630system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 49.56% # Class of committed instruction 631system.cpu.commit.op_class_0::SimdFloatAdd 637528 0.08% 49.65% # Class of committed instruction 632system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 49.65% # Class of committed instruction 633system.cpu.commit.op_class_0::SimdFloatCmp 3187668 0.40% 50.05% # Class of committed instruction 634system.cpu.commit.op_class_0::SimdFloatCvt 2550131 0.32% 50.37% # Class of committed instruction 635system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 50.37% # Class of committed instruction 636system.cpu.commit.op_class_0::SimdFloatMisc 10203074 1.29% 51.67% # Class of committed instruction 637system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 51.67% # Class of committed instruction 638system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 51.67% # Class of committed instruction 639system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 51.67% # Class of committed instruction 640system.cpu.commit.op_class_0::MemRead 252240938 31.98% 83.65% # Class of committed instruction 641system.cpu.commit.op_class_0::MemWrite 128980496 16.35% 100.00% # Class of committed instruction 642system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 643system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 644system.cpu.commit.op_class_0::total 788730069 # Class of committed instruction 645system.cpu.commit.bw_lim_events 34402468 # number cycles where commit BW limit reached 646system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 647system.cpu.rob.rob_reads 1926179188 # The number of ROB reads 648system.cpu.rob.rob_writes 3042778169 # The number of ROB writes 649system.cpu.timesIdled 159779 # Number of times that the entire CPU went into an idle state and unscheduled itself 650system.cpu.idleCycles 16752807 # Total number of cycles that the CPU has spent unscheduled due to idling 651system.cpu.committedInsts 640649298 # Number of Instructions Simulated 652system.cpu.committedOps 788724957 # Number of Ops (including micro ops) Simulated 653system.cpu.cpi 0.927803 # CPI: Cycles Per Instruction 654system.cpu.cpi_total 0.927803 # CPI: Total CPI of All Threads 655system.cpu.ipc 1.077815 # IPC: Instructions Per Cycle 656system.cpu.ipc_total 1.077815 # IPC: Total IPC of All Threads 657system.cpu.int_regfile_reads 1132703521 # number of integer regfile reads 658system.cpu.int_regfile_writes 646986163 # number of integer regfile writes 659system.cpu.fp_regfile_reads 37276202 # number of floating regfile reads 660system.cpu.fp_regfile_writes 27223952 # number of floating regfile writes 661system.cpu.cc_regfile_reads 4371075707 # number of cc regfile reads 662system.cpu.cc_regfile_writes 413227106 # number of cc regfile writes 663system.cpu.misc_regfile_reads 814254354 # number of misc regfile reads 664system.cpu.misc_regfile_writes 6386808 # number of misc regfile writes 665system.cpu.toL2Bus.throughput 191669699 # Throughput (bytes/s) 666system.cpu.toL2Bus.trans_dist::ReadReq 729385 # Transaction distribution 667system.cpu.toL2Bus.trans_dist::ReadResp 729383 # Transaction distribution 668system.cpu.toL2Bus.trans_dist::Writeback 91367 # Transaction distribution 669system.cpu.toL2Bus.trans_dist::UpgradeReq 2337 # Transaction distribution 670system.cpu.toL2Bus.trans_dist::UpgradeResp 2337 # Transaction distribution 671system.cpu.toL2Bus.trans_dist::ReadExReq 69311 # Transaction distribution 672system.cpu.toL2Bus.trans_dist::ReadExResp 69311 # Transaction distribution 673system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 26757 # Packet count per connected master and slave (bytes) 674system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1664338 # Packet count per connected master and slave (bytes) 675system.cpu.toL2Bus.pkt_count::total 1691095 # Packet count per connected master and slave (bytes) 676system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 781440 # Cumulative packet size per connected master and slave (bytes) 677system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 56032960 # Cumulative packet size per connected master and slave (bytes) 678system.cpu.toL2Bus.tot_pkt_size::total 56814400 # Cumulative packet size per connected master and slave (bytes) 679system.cpu.toL2Bus.data_through_bus 56814400 # Total data (bytes) 680system.cpu.toL2Bus.snoop_data_through_bus 149504 # Total snoop data (bytes) 681system.cpu.toL2Bus.reqLayer0.occupancy 537567000 # Layer occupancy (ticks) 682system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) 683system.cpu.toL2Bus.respLayer0.occupancy 22218748 # Layer occupancy (ticks) 684system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 685system.cpu.toL2Bus.respLayer1.occupancy 1220548813 # Layer occupancy (ticks) 686system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) 687system.cpu.icache.tags.replacements 10545 # number of replacements 688system.cpu.icache.tags.tagsinuse 1626.781544 # Cycle average of tags in use 689system.cpu.icache.tags.total_refs 207828971 # Total number of references to valid blocks. 690system.cpu.icache.tags.sampled_refs 12209 # Sample count of references to valid blocks. 691system.cpu.icache.tags.avg_refs 17022.603899 # Average number of references to valid blocks. 692system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 693system.cpu.icache.tags.occ_blocks::cpu.inst 1626.781544 # Average occupied blocks per requestor 694system.cpu.icache.tags.occ_percent::cpu.inst 0.794327 # Average percentage of cache occupancy 695system.cpu.icache.tags.occ_percent::total 0.794327 # Average percentage of cache occupancy 696system.cpu.icache.tags.occ_task_id_blocks::1024 1664 # Occupied blocks per task id 697system.cpu.icache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id 698system.cpu.icache.tags.age_task_id_blocks_1024::1 67 # Occupied blocks per task id 699system.cpu.icache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id 700system.cpu.icache.tags.age_task_id_blocks_1024::4 1549 # Occupied blocks per task id 701system.cpu.icache.tags.occ_task_id_percent::1024 0.812500 # Percentage of cache occupancy per task id 702system.cpu.icache.tags.tag_accesses 415715422 # Number of tag accesses 703system.cpu.icache.tags.data_accesses 415715422 # Number of data accesses 704system.cpu.icache.ReadReq_hits::cpu.inst 207833630 # number of ReadReq hits 705system.cpu.icache.ReadReq_hits::total 207833630 # number of ReadReq hits 706system.cpu.icache.demand_hits::cpu.inst 207833630 # number of demand (read+write) hits 707system.cpu.icache.demand_hits::total 207833630 # number of demand (read+write) hits 708system.cpu.icache.overall_hits::cpu.inst 207833630 # number of overall hits 709system.cpu.icache.overall_hits::total 207833630 # number of overall hits 710system.cpu.icache.ReadReq_misses::cpu.inst 16808 # number of ReadReq misses 711system.cpu.icache.ReadReq_misses::total 16808 # number of ReadReq misses 712system.cpu.icache.demand_misses::cpu.inst 16808 # number of demand (read+write) misses 713system.cpu.icache.demand_misses::total 16808 # number of demand (read+write) misses 714system.cpu.icache.overall_misses::cpu.inst 16808 # number of overall misses 715system.cpu.icache.overall_misses::total 16808 # number of overall misses 716system.cpu.icache.ReadReq_miss_latency::cpu.inst 373718245 # number of ReadReq miss cycles 717system.cpu.icache.ReadReq_miss_latency::total 373718245 # number of ReadReq miss cycles 718system.cpu.icache.demand_miss_latency::cpu.inst 373718245 # number of demand (read+write) miss cycles 719system.cpu.icache.demand_miss_latency::total 373718245 # number of demand (read+write) miss cycles 720system.cpu.icache.overall_miss_latency::cpu.inst 373718245 # number of overall miss cycles 721system.cpu.icache.overall_miss_latency::total 373718245 # number of overall miss cycles 722system.cpu.icache.ReadReq_accesses::cpu.inst 207850438 # number of ReadReq accesses(hits+misses) 723system.cpu.icache.ReadReq_accesses::total 207850438 # number of ReadReq accesses(hits+misses) 724system.cpu.icache.demand_accesses::cpu.inst 207850438 # number of demand (read+write) accesses 725system.cpu.icache.demand_accesses::total 207850438 # number of demand (read+write) accesses 726system.cpu.icache.overall_accesses::cpu.inst 207850438 # number of overall (read+write) accesses 727system.cpu.icache.overall_accesses::total 207850438 # number of overall (read+write) accesses 728system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000081 # miss rate for ReadReq accesses 729system.cpu.icache.ReadReq_miss_rate::total 0.000081 # miss rate for ReadReq accesses 730system.cpu.icache.demand_miss_rate::cpu.inst 0.000081 # miss rate for demand accesses 731system.cpu.icache.demand_miss_rate::total 0.000081 # miss rate for demand accesses 732system.cpu.icache.overall_miss_rate::cpu.inst 0.000081 # miss rate for overall accesses 733system.cpu.icache.overall_miss_rate::total 0.000081 # miss rate for overall accesses 734system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22234.545752 # average ReadReq miss latency 735system.cpu.icache.ReadReq_avg_miss_latency::total 22234.545752 # average ReadReq miss latency 736system.cpu.icache.demand_avg_miss_latency::cpu.inst 22234.545752 # average overall miss latency 737system.cpu.icache.demand_avg_miss_latency::total 22234.545752 # average overall miss latency 738system.cpu.icache.overall_avg_miss_latency::cpu.inst 22234.545752 # average overall miss latency 739system.cpu.icache.overall_avg_miss_latency::total 22234.545752 # average overall miss latency 740system.cpu.icache.blocked_cycles::no_mshrs 1690 # number of cycles access was blocked 741system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 742system.cpu.icache.blocked::no_mshrs 26 # number of cycles access was blocked 743system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 744system.cpu.icache.avg_blocked_cycles::no_mshrs 65 # average number of cycles each access was blocked 745system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 746system.cpu.icache.fast_writes 0 # number of fast writes performed 747system.cpu.icache.cache_copies 0 # number of cache copies performed 748system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2261 # number of ReadReq MSHR hits 749system.cpu.icache.ReadReq_mshr_hits::total 2261 # number of ReadReq MSHR hits 750system.cpu.icache.demand_mshr_hits::cpu.inst 2261 # number of demand (read+write) MSHR hits 751system.cpu.icache.demand_mshr_hits::total 2261 # number of demand (read+write) MSHR hits 752system.cpu.icache.overall_mshr_hits::cpu.inst 2261 # number of overall MSHR hits 753system.cpu.icache.overall_mshr_hits::total 2261 # number of overall MSHR hits 754system.cpu.icache.ReadReq_mshr_misses::cpu.inst 14547 # number of ReadReq MSHR misses 755system.cpu.icache.ReadReq_mshr_misses::total 14547 # number of ReadReq MSHR misses 756system.cpu.icache.demand_mshr_misses::cpu.inst 14547 # number of demand (read+write) MSHR misses 757system.cpu.icache.demand_mshr_misses::total 14547 # number of demand (read+write) MSHR misses 758system.cpu.icache.overall_mshr_misses::cpu.inst 14547 # number of overall MSHR misses 759system.cpu.icache.overall_mshr_misses::total 14547 # number of overall MSHR misses 760system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 287782750 # number of ReadReq MSHR miss cycles 761system.cpu.icache.ReadReq_mshr_miss_latency::total 287782750 # number of ReadReq MSHR miss cycles 762system.cpu.icache.demand_mshr_miss_latency::cpu.inst 287782750 # number of demand (read+write) MSHR miss cycles 763system.cpu.icache.demand_mshr_miss_latency::total 287782750 # number of demand (read+write) MSHR miss cycles 764system.cpu.icache.overall_mshr_miss_latency::cpu.inst 287782750 # number of overall MSHR miss cycles 765system.cpu.icache.overall_mshr_miss_latency::total 287782750 # number of overall MSHR miss cycles 766system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000070 # mshr miss rate for ReadReq accesses 767system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000070 # mshr miss rate for ReadReq accesses 768system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000070 # mshr miss rate for demand accesses 769system.cpu.icache.demand_mshr_miss_rate::total 0.000070 # mshr miss rate for demand accesses 770system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000070 # mshr miss rate for overall accesses 771system.cpu.icache.overall_mshr_miss_rate::total 0.000070 # mshr miss rate for overall accesses 772system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19782.962123 # average ReadReq mshr miss latency 773system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19782.962123 # average ReadReq mshr miss latency 774system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19782.962123 # average overall mshr miss latency 775system.cpu.icache.demand_avg_mshr_miss_latency::total 19782.962123 # average overall mshr miss latency 776system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19782.962123 # average overall mshr miss latency 777system.cpu.icache.overall_avg_mshr_miss_latency::total 19782.962123 # average overall mshr miss latency 778system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 779system.cpu.l2cache.tags.replacements 257640 # number of replacements 780system.cpu.l2cache.tags.tagsinuse 32630.586328 # Cycle average of tags in use 781system.cpu.l2cache.tags.total_refs 527670 # Total number of references to valid blocks. 782system.cpu.l2cache.tags.sampled_refs 290385 # Sample count of references to valid blocks. 783system.cpu.l2cache.tags.avg_refs 1.817139 # Average number of references to valid blocks. 784system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 785system.cpu.l2cache.tags.occ_blocks::writebacks 2747.858581 # Average occupied blocks per requestor 786system.cpu.l2cache.tags.occ_blocks::cpu.inst 68.601052 # Average occupied blocks per requestor 787system.cpu.l2cache.tags.occ_blocks::cpu.data 29814.126695 # Average occupied blocks per requestor 788system.cpu.l2cache.tags.occ_percent::writebacks 0.083858 # Average percentage of cache occupancy 789system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002094 # Average percentage of cache occupancy 790system.cpu.l2cache.tags.occ_percent::cpu.data 0.909855 # Average percentage of cache occupancy 791system.cpu.l2cache.tags.occ_percent::total 0.995806 # Average percentage of cache occupancy 792system.cpu.l2cache.tags.occ_task_id_blocks::1024 32745 # Occupied blocks per task id 793system.cpu.l2cache.tags.age_task_id_blocks_1024::0 87 # Occupied blocks per task id 794system.cpu.l2cache.tags.age_task_id_blocks_1024::1 153 # Occupied blocks per task id 795system.cpu.l2cache.tags.age_task_id_blocks_1024::2 496 # Occupied blocks per task id 796system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4949 # Occupied blocks per task id 797system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27060 # Occupied blocks per task id 798system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999298 # Percentage of cache occupancy per task id 799system.cpu.l2cache.tags.tag_accesses 7480211 # Number of tag accesses 800system.cpu.l2cache.tags.data_accesses 7480211 # Number of data accesses 801system.cpu.l2cache.ReadReq_hits::cpu.inst 9862 # number of ReadReq hits 802system.cpu.l2cache.ReadReq_hits::cpu.data 492819 # number of ReadReq hits 803system.cpu.l2cache.ReadReq_hits::total 502681 # number of ReadReq hits 804system.cpu.l2cache.Writeback_hits::writebacks 91367 # number of Writeback hits 805system.cpu.l2cache.Writeback_hits::total 91367 # number of Writeback hits 806system.cpu.l2cache.UpgradeReq_hits::cpu.data 3 # number of UpgradeReq hits 807system.cpu.l2cache.UpgradeReq_hits::total 3 # number of UpgradeReq hits 808system.cpu.l2cache.ReadExReq_hits::cpu.data 3232 # number of ReadExReq hits 809system.cpu.l2cache.ReadExReq_hits::total 3232 # number of ReadExReq hits 810system.cpu.l2cache.demand_hits::cpu.inst 9862 # number of demand (read+write) hits 811system.cpu.l2cache.demand_hits::cpu.data 496051 # number of demand (read+write) hits 812system.cpu.l2cache.demand_hits::total 505913 # number of demand (read+write) hits 813system.cpu.l2cache.overall_hits::cpu.inst 9862 # number of overall hits 814system.cpu.l2cache.overall_hits::cpu.data 496051 # number of overall hits 815system.cpu.l2cache.overall_hits::total 505913 # number of overall hits 816system.cpu.l2cache.ReadReq_misses::cpu.inst 2349 # number of ReadReq misses 817system.cpu.l2cache.ReadReq_misses::cpu.data 222019 # number of ReadReq misses 818system.cpu.l2cache.ReadReq_misses::total 224368 # number of ReadReq misses 819system.cpu.l2cache.UpgradeReq_misses::cpu.data 2334 # number of UpgradeReq misses 820system.cpu.l2cache.UpgradeReq_misses::total 2334 # number of UpgradeReq misses 821system.cpu.l2cache.ReadExReq_misses::cpu.data 66079 # number of ReadExReq misses 822system.cpu.l2cache.ReadExReq_misses::total 66079 # number of ReadExReq misses 823system.cpu.l2cache.demand_misses::cpu.inst 2349 # number of demand (read+write) misses 824system.cpu.l2cache.demand_misses::cpu.data 288098 # number of demand (read+write) misses 825system.cpu.l2cache.demand_misses::total 290447 # number of demand (read+write) misses 826system.cpu.l2cache.overall_misses::cpu.inst 2349 # number of overall misses 827system.cpu.l2cache.overall_misses::cpu.data 288098 # number of overall misses 828system.cpu.l2cache.overall_misses::total 290447 # number of overall misses 829system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 172220250 # number of ReadReq miss cycles 830system.cpu.l2cache.ReadReq_miss_latency::cpu.data 16196026750 # number of ReadReq miss cycles 831system.cpu.l2cache.ReadReq_miss_latency::total 16368247000 # number of ReadReq miss cycles 832system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5137976250 # number of ReadExReq miss cycles 833system.cpu.l2cache.ReadExReq_miss_latency::total 5137976250 # number of ReadExReq miss cycles 834system.cpu.l2cache.demand_miss_latency::cpu.inst 172220250 # number of demand (read+write) miss cycles 835system.cpu.l2cache.demand_miss_latency::cpu.data 21334003000 # number of demand (read+write) miss cycles 836system.cpu.l2cache.demand_miss_latency::total 21506223250 # number of demand (read+write) miss cycles 837system.cpu.l2cache.overall_miss_latency::cpu.inst 172220250 # number of overall miss cycles 838system.cpu.l2cache.overall_miss_latency::cpu.data 21334003000 # number of overall miss cycles 839system.cpu.l2cache.overall_miss_latency::total 21506223250 # number of overall miss cycles 840system.cpu.l2cache.ReadReq_accesses::cpu.inst 12211 # number of ReadReq accesses(hits+misses) 841system.cpu.l2cache.ReadReq_accesses::cpu.data 714838 # number of ReadReq accesses(hits+misses) 842system.cpu.l2cache.ReadReq_accesses::total 727049 # number of ReadReq accesses(hits+misses) 843system.cpu.l2cache.Writeback_accesses::writebacks 91367 # number of Writeback accesses(hits+misses) 844system.cpu.l2cache.Writeback_accesses::total 91367 # number of Writeback accesses(hits+misses) 845system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2337 # number of UpgradeReq accesses(hits+misses) 846system.cpu.l2cache.UpgradeReq_accesses::total 2337 # number of UpgradeReq accesses(hits+misses) 847system.cpu.l2cache.ReadExReq_accesses::cpu.data 69311 # number of ReadExReq accesses(hits+misses) 848system.cpu.l2cache.ReadExReq_accesses::total 69311 # number of ReadExReq accesses(hits+misses) 849system.cpu.l2cache.demand_accesses::cpu.inst 12211 # number of demand (read+write) accesses 850system.cpu.l2cache.demand_accesses::cpu.data 784149 # number of demand (read+write) accesses 851system.cpu.l2cache.demand_accesses::total 796360 # number of demand (read+write) accesses 852system.cpu.l2cache.overall_accesses::cpu.inst 12211 # number of overall (read+write) accesses 853system.cpu.l2cache.overall_accesses::cpu.data 784149 # number of overall (read+write) accesses 854system.cpu.l2cache.overall_accesses::total 796360 # number of overall (read+write) accesses 855system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.192368 # miss rate for ReadReq accesses 856system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.310586 # miss rate for ReadReq accesses 857system.cpu.l2cache.ReadReq_miss_rate::total 0.308601 # miss rate for ReadReq accesses 858system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.998716 # miss rate for UpgradeReq accesses 859system.cpu.l2cache.UpgradeReq_miss_rate::total 0.998716 # miss rate for UpgradeReq accesses 860system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.953370 # miss rate for ReadExReq accesses 861system.cpu.l2cache.ReadExReq_miss_rate::total 0.953370 # miss rate for ReadExReq accesses 862system.cpu.l2cache.demand_miss_rate::cpu.inst 0.192368 # miss rate for demand accesses 863system.cpu.l2cache.demand_miss_rate::cpu.data 0.367402 # miss rate for demand accesses 864system.cpu.l2cache.demand_miss_rate::total 0.364718 # miss rate for demand accesses 865system.cpu.l2cache.overall_miss_rate::cpu.inst 0.192368 # miss rate for overall accesses 866system.cpu.l2cache.overall_miss_rate::cpu.data 0.367402 # miss rate for overall accesses 867system.cpu.l2cache.overall_miss_rate::total 0.364718 # miss rate for overall accesses 868system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73316.411239 # average ReadReq miss latency 869system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 72948.832082 # average ReadReq miss latency 870system.cpu.l2cache.ReadReq_avg_miss_latency::total 72952.680418 # average ReadReq miss latency 871system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77755.054556 # average ReadExReq miss latency 872system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77755.054556 # average ReadExReq miss latency 873system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73316.411239 # average overall miss latency 874system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74051.201327 # average overall miss latency 875system.cpu.l2cache.demand_avg_miss_latency::total 74045.258687 # average overall miss latency 876system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73316.411239 # average overall miss latency 877system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74051.201327 # average overall miss latency 878system.cpu.l2cache.overall_avg_miss_latency::total 74045.258687 # average overall miss latency 879system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 880system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 881system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 882system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 883system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 884system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 885system.cpu.l2cache.fast_writes 0 # number of fast writes performed 886system.cpu.l2cache.cache_copies 0 # number of cache copies performed 887system.cpu.l2cache.writebacks::writebacks 66098 # number of writebacks 888system.cpu.l2cache.writebacks::total 66098 # number of writebacks 889system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits 890system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 21 # number of ReadReq MSHR hits 891system.cpu.l2cache.ReadReq_mshr_hits::total 23 # number of ReadReq MSHR hits 892system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits 893system.cpu.l2cache.demand_mshr_hits::cpu.data 21 # number of demand (read+write) MSHR hits 894system.cpu.l2cache.demand_mshr_hits::total 23 # number of demand (read+write) MSHR hits 895system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits 896system.cpu.l2cache.overall_mshr_hits::cpu.data 21 # number of overall MSHR hits 897system.cpu.l2cache.overall_mshr_hits::total 23 # number of overall MSHR hits 898system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2347 # number of ReadReq MSHR misses 899system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 221998 # number of ReadReq MSHR misses 900system.cpu.l2cache.ReadReq_mshr_misses::total 224345 # number of ReadReq MSHR misses 901system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2334 # number of UpgradeReq MSHR misses 902system.cpu.l2cache.UpgradeReq_mshr_misses::total 2334 # number of UpgradeReq MSHR misses 903system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66079 # number of ReadExReq MSHR misses 904system.cpu.l2cache.ReadExReq_mshr_misses::total 66079 # number of ReadExReq MSHR misses 905system.cpu.l2cache.demand_mshr_misses::cpu.inst 2347 # number of demand (read+write) MSHR misses 906system.cpu.l2cache.demand_mshr_misses::cpu.data 288077 # number of demand (read+write) MSHR misses 907system.cpu.l2cache.demand_mshr_misses::total 290424 # number of demand (read+write) MSHR misses 908system.cpu.l2cache.overall_mshr_misses::cpu.inst 2347 # number of overall MSHR misses 909system.cpu.l2cache.overall_mshr_misses::cpu.data 288077 # number of overall MSHR misses 910system.cpu.l2cache.overall_mshr_misses::total 290424 # number of overall MSHR misses 911system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 142668750 # number of ReadReq MSHR miss cycles 912system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 13415878250 # number of ReadReq MSHR miss cycles 913system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13558547000 # number of ReadReq MSHR miss cycles 914system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 23342334 # number of UpgradeReq MSHR miss cycles 915system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 23342334 # number of UpgradeReq MSHR miss cycles 916system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4297620250 # number of ReadExReq MSHR miss cycles 917system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4297620250 # number of ReadExReq MSHR miss cycles 918system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 142668750 # number of demand (read+write) MSHR miss cycles 919system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 17713498500 # number of demand (read+write) MSHR miss cycles 920system.cpu.l2cache.demand_mshr_miss_latency::total 17856167250 # number of demand (read+write) MSHR miss cycles 921system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 142668750 # number of overall MSHR miss cycles 922system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 17713498500 # number of overall MSHR miss cycles 923system.cpu.l2cache.overall_mshr_miss_latency::total 17856167250 # number of overall MSHR miss cycles 924system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.192204 # mshr miss rate for ReadReq accesses 925system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.310557 # mshr miss rate for ReadReq accesses 926system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.308569 # mshr miss rate for ReadReq accesses 927system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.998716 # mshr miss rate for UpgradeReq accesses 928system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.998716 # mshr miss rate for UpgradeReq accesses 929system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.953370 # mshr miss rate for ReadExReq accesses 930system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.953370 # mshr miss rate for ReadExReq accesses 931system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.192204 # mshr miss rate for demand accesses 932system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.367375 # mshr miss rate for demand accesses 933system.cpu.l2cache.demand_mshr_miss_rate::total 0.364689 # mshr miss rate for demand accesses 934system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.192204 # mshr miss rate for overall accesses 935system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.367375 # mshr miss rate for overall accesses 936system.cpu.l2cache.overall_mshr_miss_rate::total 0.364689 # mshr miss rate for overall accesses 937system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60787.707712 # average ReadReq mshr miss latency 938system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60432.428445 # average ReadReq mshr miss latency 939system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60436.145223 # average ReadReq mshr miss latency 940system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency 941system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency 942system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65037.610285 # average ReadExReq mshr miss latency 943system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65037.610285 # average ReadExReq mshr miss latency 944system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60787.707712 # average overall mshr miss latency 945system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61488.763421 # average overall mshr miss latency 946system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61483.097988 # average overall mshr miss latency 947system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60787.707712 # average overall mshr miss latency 948system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61488.763421 # average overall mshr miss latency 949system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61483.097988 # average overall mshr miss latency 950system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 951system.cpu.dcache.tags.replacements 780052 # number of replacements 952system.cpu.dcache.tags.tagsinuse 4092.850454 # Cycle average of tags in use 953system.cpu.dcache.tags.total_refs 456274938 # Total number of references to valid blocks. 954system.cpu.dcache.tags.sampled_refs 784148 # Sample count of references to valid blocks. 955system.cpu.dcache.tags.avg_refs 581.873496 # Average number of references to valid blocks. 956system.cpu.dcache.tags.warmup_cycle 340792000 # Cycle when the warmup percentage was hit. 957system.cpu.dcache.tags.occ_blocks::cpu.data 4092.850454 # Average occupied blocks per requestor 958system.cpu.dcache.tags.occ_percent::cpu.data 0.999231 # Average percentage of cache occupancy 959system.cpu.dcache.tags.occ_percent::total 0.999231 # Average percentage of cache occupancy 960system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 961system.cpu.dcache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id 962system.cpu.dcache.tags.age_task_id_blocks_1024::1 258 # Occupied blocks per task id 963system.cpu.dcache.tags.age_task_id_blocks_1024::2 976 # Occupied blocks per task id 964system.cpu.dcache.tags.age_task_id_blocks_1024::3 2364 # Occupied blocks per task id 965system.cpu.dcache.tags.age_task_id_blocks_1024::4 451 # Occupied blocks per task id 966system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 967system.cpu.dcache.tags.tag_accesses 918547346 # Number of tag accesses 968system.cpu.dcache.tags.data_accesses 918547346 # Number of data accesses 969system.cpu.dcache.ReadReq_hits::cpu.data 328318489 # number of ReadReq hits 970system.cpu.dcache.ReadReq_hits::total 328318489 # number of ReadReq hits 971system.cpu.dcache.WriteReq_hits::cpu.data 127934774 # number of WriteReq hits 972system.cpu.dcache.WriteReq_hits::total 127934774 # number of WriteReq hits 973system.cpu.dcache.SoftPFReq_hits::cpu.data 3905 # number of SoftPFReq hits 974system.cpu.dcache.SoftPFReq_hits::total 3905 # number of SoftPFReq hits 975system.cpu.dcache.LoadLockedReq_hits::cpu.data 5745 # number of LoadLockedReq hits 976system.cpu.dcache.LoadLockedReq_hits::total 5745 # number of LoadLockedReq hits 977system.cpu.dcache.StoreCondReq_hits::cpu.data 5739 # number of StoreCondReq hits 978system.cpu.dcache.StoreCondReq_hits::total 5739 # number of StoreCondReq hits 979system.cpu.dcache.demand_hits::cpu.data 456253263 # number of demand (read+write) hits 980system.cpu.dcache.demand_hits::total 456253263 # number of demand (read+write) hits 981system.cpu.dcache.overall_hits::cpu.data 456257168 # number of overall hits 982system.cpu.dcache.overall_hits::total 456257168 # number of overall hits 983system.cpu.dcache.ReadReq_misses::cpu.data 1596085 # number of ReadReq misses 984system.cpu.dcache.ReadReq_misses::total 1596085 # number of ReadReq misses 985system.cpu.dcache.WriteReq_misses::cpu.data 1016703 # number of WriteReq misses 986system.cpu.dcache.WriteReq_misses::total 1016703 # number of WriteReq misses 987system.cpu.dcache.SoftPFReq_misses::cpu.data 156 # number of SoftPFReq misses 988system.cpu.dcache.SoftPFReq_misses::total 156 # number of SoftPFReq misses 989system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses 990system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses 991system.cpu.dcache.demand_misses::cpu.data 2612788 # number of demand (read+write) misses 992system.cpu.dcache.demand_misses::total 2612788 # number of demand (read+write) misses 993system.cpu.dcache.overall_misses::cpu.data 2612944 # number of overall misses 994system.cpu.dcache.overall_misses::total 2612944 # number of overall misses 995system.cpu.dcache.ReadReq_miss_latency::cpu.data 65672832321 # number of ReadReq miss cycles 996system.cpu.dcache.ReadReq_miss_latency::total 65672832321 # number of ReadReq miss cycles 997system.cpu.dcache.WriteReq_miss_latency::cpu.data 69021730126 # number of WriteReq miss cycles 998system.cpu.dcache.WriteReq_miss_latency::total 69021730126 # number of WriteReq miss cycles 999system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 224500 # number of LoadLockedReq miss cycles 1000system.cpu.dcache.LoadLockedReq_miss_latency::total 224500 # number of LoadLockedReq miss cycles 1001system.cpu.dcache.demand_miss_latency::cpu.data 134694562447 # number of demand (read+write) miss cycles 1002system.cpu.dcache.demand_miss_latency::total 134694562447 # number of demand (read+write) miss cycles 1003system.cpu.dcache.overall_miss_latency::cpu.data 134694562447 # number of overall miss cycles 1004system.cpu.dcache.overall_miss_latency::total 134694562447 # number of overall miss cycles 1005system.cpu.dcache.ReadReq_accesses::cpu.data 329914574 # number of ReadReq accesses(hits+misses) 1006system.cpu.dcache.ReadReq_accesses::total 329914574 # number of ReadReq accesses(hits+misses) 1007system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses) 1008system.cpu.dcache.WriteReq_accesses::total 128951477 # number of WriteReq accesses(hits+misses) 1009system.cpu.dcache.SoftPFReq_accesses::cpu.data 4061 # number of SoftPFReq accesses(hits+misses) 1010system.cpu.dcache.SoftPFReq_accesses::total 4061 # number of SoftPFReq accesses(hits+misses) 1011system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5748 # number of LoadLockedReq accesses(hits+misses) 1012system.cpu.dcache.LoadLockedReq_accesses::total 5748 # number of LoadLockedReq accesses(hits+misses) 1013system.cpu.dcache.StoreCondReq_accesses::cpu.data 5739 # number of StoreCondReq accesses(hits+misses) 1014system.cpu.dcache.StoreCondReq_accesses::total 5739 # number of StoreCondReq accesses(hits+misses) 1015system.cpu.dcache.demand_accesses::cpu.data 458866051 # number of demand (read+write) accesses 1016system.cpu.dcache.demand_accesses::total 458866051 # number of demand (read+write) accesses 1017system.cpu.dcache.overall_accesses::cpu.data 458870112 # number of overall (read+write) accesses 1018system.cpu.dcache.overall_accesses::total 458870112 # number of overall (read+write) accesses 1019system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004838 # miss rate for ReadReq accesses 1020system.cpu.dcache.ReadReq_miss_rate::total 0.004838 # miss rate for ReadReq accesses 1021system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.007884 # miss rate for WriteReq accesses 1022system.cpu.dcache.WriteReq_miss_rate::total 0.007884 # miss rate for WriteReq accesses 1023system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.038414 # miss rate for SoftPFReq accesses 1024system.cpu.dcache.SoftPFReq_miss_rate::total 0.038414 # miss rate for SoftPFReq accesses 1025system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000522 # miss rate for LoadLockedReq accesses 1026system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000522 # miss rate for LoadLockedReq accesses 1027system.cpu.dcache.demand_miss_rate::cpu.data 0.005694 # miss rate for demand accesses 1028system.cpu.dcache.demand_miss_rate::total 0.005694 # miss rate for demand accesses 1029system.cpu.dcache.overall_miss_rate::cpu.data 0.005694 # miss rate for overall accesses 1030system.cpu.dcache.overall_miss_rate::total 0.005694 # miss rate for overall accesses 1031system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 41146.199808 # average ReadReq miss latency 1032system.cpu.dcache.ReadReq_avg_miss_latency::total 41146.199808 # average ReadReq miss latency 1033system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 67887.800199 # average WriteReq miss latency 1034system.cpu.dcache.WriteReq_avg_miss_latency::total 67887.800199 # average WriteReq miss latency 1035system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 74833.333333 # average LoadLockedReq miss latency 1036system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 74833.333333 # average LoadLockedReq miss latency 1037system.cpu.dcache.demand_avg_miss_latency::cpu.data 51552.044195 # average overall miss latency 1038system.cpu.dcache.demand_avg_miss_latency::total 51552.044195 # average overall miss latency 1039system.cpu.dcache.overall_avg_miss_latency::cpu.data 51548.966395 # average overall miss latency 1040system.cpu.dcache.overall_avg_miss_latency::total 51548.966395 # average overall miss latency 1041system.cpu.dcache.blocked_cycles::no_mshrs 3326 # number of cycles access was blocked 1042system.cpu.dcache.blocked_cycles::no_targets 660 # number of cycles access was blocked 1043system.cpu.dcache.blocked::no_mshrs 72 # number of cycles access was blocked 1044system.cpu.dcache.blocked::no_targets 8 # number of cycles access was blocked 1045system.cpu.dcache.avg_blocked_cycles::no_mshrs 46.194444 # average number of cycles each access was blocked 1046system.cpu.dcache.avg_blocked_cycles::no_targets 82.500000 # average number of cycles each access was blocked 1047system.cpu.dcache.fast_writes 0 # number of fast writes performed 1048system.cpu.dcache.cache_copies 0 # number of cache copies performed 1049system.cpu.dcache.writebacks::writebacks 91367 # number of writebacks 1050system.cpu.dcache.writebacks::total 91367 # number of writebacks 1051system.cpu.dcache.ReadReq_mshr_hits::cpu.data 881385 # number of ReadReq MSHR hits 1052system.cpu.dcache.ReadReq_mshr_hits::total 881385 # number of ReadReq MSHR hits 1053system.cpu.dcache.WriteReq_mshr_hits::cpu.data 945064 # number of WriteReq MSHR hits 1054system.cpu.dcache.WriteReq_mshr_hits::total 945064 # number of WriteReq MSHR hits 1055system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits 1056system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits 1057system.cpu.dcache.demand_mshr_hits::cpu.data 1826449 # number of demand (read+write) MSHR hits 1058system.cpu.dcache.demand_mshr_hits::total 1826449 # number of demand (read+write) MSHR hits 1059system.cpu.dcache.overall_mshr_hits::cpu.data 1826449 # number of overall MSHR hits 1060system.cpu.dcache.overall_mshr_hits::total 1826449 # number of overall MSHR hits 1061system.cpu.dcache.ReadReq_mshr_misses::cpu.data 714700 # number of ReadReq MSHR misses 1062system.cpu.dcache.ReadReq_mshr_misses::total 714700 # number of ReadReq MSHR misses 1063system.cpu.dcache.WriteReq_mshr_misses::cpu.data 71639 # number of WriteReq MSHR misses 1064system.cpu.dcache.WriteReq_mshr_misses::total 71639 # number of WriteReq MSHR misses 1065system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 147 # number of SoftPFReq MSHR misses 1066system.cpu.dcache.SoftPFReq_mshr_misses::total 147 # number of SoftPFReq MSHR misses 1067system.cpu.dcache.demand_mshr_misses::cpu.data 786339 # number of demand (read+write) MSHR misses 1068system.cpu.dcache.demand_mshr_misses::total 786339 # number of demand (read+write) MSHR misses 1069system.cpu.dcache.overall_mshr_misses::cpu.data 786486 # number of overall MSHR misses 1070system.cpu.dcache.overall_mshr_misses::total 786486 # number of overall MSHR misses 1071system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21837733771 # number of ReadReq MSHR miss cycles 1072system.cpu.dcache.ReadReq_mshr_miss_latency::total 21837733771 # number of ReadReq MSHR miss cycles 1073system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5293200916 # number of WriteReq MSHR miss cycles 1074system.cpu.dcache.WriteReq_mshr_miss_latency::total 5293200916 # number of WriteReq MSHR miss cycles 1075system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 2189000 # number of SoftPFReq MSHR miss cycles 1076system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 2189000 # number of SoftPFReq MSHR miss cycles 1077system.cpu.dcache.demand_mshr_miss_latency::cpu.data 27130934687 # number of demand (read+write) MSHR miss cycles 1078system.cpu.dcache.demand_mshr_miss_latency::total 27130934687 # number of demand (read+write) MSHR miss cycles 1079system.cpu.dcache.overall_mshr_miss_latency::cpu.data 27133123687 # number of overall MSHR miss cycles 1080system.cpu.dcache.overall_mshr_miss_latency::total 27133123687 # number of overall MSHR miss cycles 1081system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002166 # mshr miss rate for ReadReq accesses 1082system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002166 # mshr miss rate for ReadReq accesses 1083system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000556 # mshr miss rate for WriteReq accesses 1084system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000556 # mshr miss rate for WriteReq accesses 1085system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.036198 # mshr miss rate for SoftPFReq accesses 1086system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.036198 # mshr miss rate for SoftPFReq accesses 1087system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001714 # mshr miss rate for demand accesses 1088system.cpu.dcache.demand_mshr_miss_rate::total 0.001714 # mshr miss rate for demand accesses 1089system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001714 # mshr miss rate for overall accesses 1090system.cpu.dcache.overall_mshr_miss_rate::total 0.001714 # mshr miss rate for overall accesses 1091system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 30555.105318 # average ReadReq mshr miss latency 1092system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30555.105318 # average ReadReq mshr miss latency 1093system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73887.141306 # average WriteReq mshr miss latency 1094system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73887.141306 # average WriteReq mshr miss latency 1095system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 14891.156463 # average SoftPFReq mshr miss latency 1096system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 14891.156463 # average SoftPFReq mshr miss latency 1097system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34502.847610 # average overall mshr miss latency 1098system.cpu.dcache.demand_avg_mshr_miss_latency::total 34502.847610 # average overall mshr miss latency 1099system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34499.182041 # average overall mshr miss latency 1100system.cpu.dcache.overall_avg_mshr_miss_latency::total 34499.182041 # average overall mshr miss latency 1101system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1102 1103---------- End Simulation Statistics ---------- 1104