stats.txt revision 10220:9eab5efc02e8
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.628792 # Number of seconds simulated 4sim_ticks 628791732500 # Number of ticks simulated 5final_tick 628791732500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 86286 # Simulator instruction rate (inst/s) 8host_op_rate 117510 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 39191918 # Simulator tick rate (ticks/s) 10host_mem_usage 321468 # Number of bytes of host memory used 11host_seconds 16043.91 # Real time elapsed on the host 12sim_insts 1384370590 # Number of instructions simulated 13sim_ops 1885325342 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 154944 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 30242560 # Number of bytes read from this memory 18system.physmem.bytes_read::total 30397504 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 154944 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 154944 # Number of instructions bytes read from this memory 21system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory 22system.physmem.bytes_written::total 4230272 # Number of bytes written to this memory 23system.physmem.num_reads::cpu.inst 2421 # Number of read requests responded to by this memory 24system.physmem.num_reads::cpu.data 472540 # Number of read requests responded to by this memory 25system.physmem.num_reads::total 474961 # Number of read requests responded to by this memory 26system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory 27system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory 28system.physmem.bw_read::cpu.inst 246415 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::cpu.data 48096307 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::total 48342722 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_inst_read::cpu.inst 246415 # Instruction read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::total 246415 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_write::writebacks 6727620 # Write bandwidth from this memory (bytes/s) 34system.physmem.bw_write::total 6727620 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_total::writebacks 6727620 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::cpu.inst 246415 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.data 48096307 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::total 55070342 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.readReqs 474962 # Number of read requests accepted 40system.physmem.writeReqs 66098 # Number of write requests accepted 41system.physmem.readBursts 474962 # Number of DRAM read bursts, including those serviced by the write queue 42system.physmem.writeBursts 66098 # Number of DRAM write bursts, including those merged in the write queue 43system.physmem.bytesReadDRAM 30374848 # Total number of bytes read from DRAM 44system.physmem.bytesReadWrQ 22720 # Total number of bytes read from write queue 45system.physmem.bytesWritten 4229184 # Total number of bytes written to DRAM 46system.physmem.bytesReadSys 30397568 # Total read bytes from the system interface side 47system.physmem.bytesWrittenSys 4230272 # Total written bytes from the system interface side 48system.physmem.servicedByWrQ 355 # Number of DRAM read bursts serviced by the write queue 49system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 50system.physmem.neitherReadNorWriteReqs 4292 # Number of requests that are neither read nor write 51system.physmem.perBankRdBursts::0 29853 # Per bank write bursts 52system.physmem.perBankRdBursts::1 29663 # Per bank write bursts 53system.physmem.perBankRdBursts::2 29734 # Per bank write bursts 54system.physmem.perBankRdBursts::3 29691 # Per bank write bursts 55system.physmem.perBankRdBursts::4 29781 # Per bank write bursts 56system.physmem.perBankRdBursts::5 29812 # Per bank write bursts 57system.physmem.perBankRdBursts::6 29626 # Per bank write bursts 58system.physmem.perBankRdBursts::7 29426 # Per bank write bursts 59system.physmem.perBankRdBursts::8 29463 # Per bank write bursts 60system.physmem.perBankRdBursts::9 29476 # Per bank write bursts 61system.physmem.perBankRdBursts::10 29540 # Per bank write bursts 62system.physmem.perBankRdBursts::11 29638 # Per bank write bursts 63system.physmem.perBankRdBursts::12 29686 # Per bank write bursts 64system.physmem.perBankRdBursts::13 29802 # Per bank write bursts 65system.physmem.perBankRdBursts::14 29621 # Per bank write bursts 66system.physmem.perBankRdBursts::15 29795 # Per bank write bursts 67system.physmem.perBankWrBursts::0 4173 # Per bank write bursts 68system.physmem.perBankWrBursts::1 4102 # Per bank write bursts 69system.physmem.perBankWrBursts::2 4137 # Per bank write bursts 70system.physmem.perBankWrBursts::3 4146 # Per bank write bursts 71system.physmem.perBankWrBursts::4 4225 # Per bank write bursts 72system.physmem.perBankWrBursts::5 4224 # Per bank write bursts 73system.physmem.perBankWrBursts::6 4171 # Per bank write bursts 74system.physmem.perBankWrBursts::7 4094 # Per bank write bursts 75system.physmem.perBankWrBursts::8 4096 # Per bank write bursts 76system.physmem.perBankWrBursts::9 4093 # Per bank write bursts 77system.physmem.perBankWrBursts::10 4094 # Per bank write bursts 78system.physmem.perBankWrBursts::11 4097 # Per bank write bursts 79system.physmem.perBankWrBursts::12 4098 # Per bank write bursts 80system.physmem.perBankWrBursts::13 4096 # Per bank write bursts 81system.physmem.perBankWrBursts::14 4096 # Per bank write bursts 82system.physmem.perBankWrBursts::15 4139 # Per bank write bursts 83system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 84system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 85system.physmem.totGap 628791712500 # Total gap between requests 86system.physmem.readPktSize::0 0 # Read request sizes (log2) 87system.physmem.readPktSize::1 0 # Read request sizes (log2) 88system.physmem.readPktSize::2 0 # Read request sizes (log2) 89system.physmem.readPktSize::3 0 # Read request sizes (log2) 90system.physmem.readPktSize::4 0 # Read request sizes (log2) 91system.physmem.readPktSize::5 0 # Read request sizes (log2) 92system.physmem.readPktSize::6 474962 # Read request sizes (log2) 93system.physmem.writePktSize::0 0 # Write request sizes (log2) 94system.physmem.writePktSize::1 0 # Write request sizes (log2) 95system.physmem.writePktSize::2 0 # Write request sizes (log2) 96system.physmem.writePktSize::3 0 # Write request sizes (log2) 97system.physmem.writePktSize::4 0 # Write request sizes (log2) 98system.physmem.writePktSize::5 0 # Write request sizes (log2) 99system.physmem.writePktSize::6 66098 # Write request sizes (log2) 100system.physmem.rdQLenPdf::0 407661 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::1 66594 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::2 276 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::3 58 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::4 15 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 132system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 133system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 134system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::15 981 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::16 983 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::17 3990 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::18 4006 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::19 4008 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::20 4009 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::21 4008 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::22 4007 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::23 4007 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::24 4016 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::25 4008 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::26 4009 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::27 4011 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::28 4008 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::29 4008 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::30 4008 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::31 4007 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::32 4009 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 196system.physmem.bytesPerActivate::samples 194074 # Bytes accessed per row activation 197system.physmem.bytesPerActivate::mean 178.290755 # Bytes accessed per row activation 198system.physmem.bytesPerActivate::gmean 128.832062 # Bytes accessed per row activation 199system.physmem.bytesPerActivate::stdev 207.398992 # Bytes accessed per row activation 200system.physmem.bytesPerActivate::0-127 73771 38.01% 38.01% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::128-255 88634 45.67% 83.68% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::256-383 20233 10.43% 94.11% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::384-511 463 0.24% 94.35% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::512-639 411 0.21% 94.56% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::640-767 515 0.27% 94.82% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::768-895 585 0.30% 95.12% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::896-1023 564 0.29% 95.42% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::1024-1151 8898 4.58% 100.00% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::total 194074 # Bytes accessed per row activation 210system.physmem.rdPerTurnAround::samples 4007 # Reads before turning the bus around for writes 211system.physmem.rdPerTurnAround::mean 48.655603 # Reads before turning the bus around for writes 212system.physmem.rdPerTurnAround::gmean 36.114528 # Reads before turning the bus around for writes 213system.physmem.rdPerTurnAround::stdev 505.912792 # Reads before turning the bus around for writes 214system.physmem.rdPerTurnAround::0-1023 4004 99.93% 99.93% # Reads before turning the bus around for writes 215system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.95% # Reads before turning the bus around for writes 216system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes 217system.physmem.rdPerTurnAround::31744-32767 1 0.02% 100.00% # Reads before turning the bus around for writes 218system.physmem.rdPerTurnAround::total 4007 # Reads before turning the bus around for writes 219system.physmem.wrPerTurnAround::samples 4007 # Writes before turning the bus around for reads 220system.physmem.wrPerTurnAround::mean 16.491390 # Writes before turning the bus around for reads 221system.physmem.wrPerTurnAround::gmean 16.469672 # Writes before turning the bus around for reads 222system.physmem.wrPerTurnAround::stdev 0.863565 # Writes before turning the bus around for reads 223system.physmem.wrPerTurnAround::16 3025 75.49% 75.49% # Writes before turning the bus around for reads 224system.physmem.wrPerTurnAround::17 1 0.02% 75.52% # Writes before turning the bus around for reads 225system.physmem.wrPerTurnAround::18 975 24.33% 99.85% # Writes before turning the bus around for reads 226system.physmem.wrPerTurnAround::19 6 0.15% 100.00% # Writes before turning the bus around for reads 227system.physmem.wrPerTurnAround::total 4007 # Writes before turning the bus around for reads 228system.physmem.totQLat 5771153000 # Total ticks spent queuing 229system.physmem.totMemAccLat 14670034250 # Total ticks spent from burst creation until serviced by the DRAM 230system.physmem.totBusLat 2373035000 # Total ticks spent in databus transfers 231system.physmem.avgQLat 12159.86 # Average queueing delay per DRAM burst 232system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 233system.physmem.avgMemAccLat 30909.86 # Average memory access latency per DRAM burst 234system.physmem.avgRdBW 48.31 # Average DRAM read bandwidth in MiByte/s 235system.physmem.avgWrBW 6.73 # Average achieved write bandwidth in MiByte/s 236system.physmem.avgRdBWSys 48.34 # Average system read bandwidth in MiByte/s 237system.physmem.avgWrBWSys 6.73 # Average system write bandwidth in MiByte/s 238system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 239system.physmem.busUtil 0.43 # Data bus utilization in percentage 240system.physmem.busUtilRead 0.38 # Data bus utilization in percentage for reads 241system.physmem.busUtilWrite 0.05 # Data bus utilization in percentage for writes 242system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing 243system.physmem.avgWrQLen 18.42 # Average write queue length when enqueuing 244system.physmem.readRowHits 296657 # Number of row buffer hits during reads 245system.physmem.writeRowHits 49944 # Number of row buffer hits during writes 246system.physmem.readRowHitRate 62.51 # Row buffer hit rate for reads 247system.physmem.writeRowHitRate 75.56 # Row buffer hit rate for writes 248system.physmem.avgGap 1162147.84 # Average gap between requests 249system.physmem.pageHitRate 64.10 # Row buffer hit rate, read and write combined 250system.physmem.memoryStateTime::IDLE 162139876750 # Time in different power states 251system.physmem.memoryStateTime::REF 20996560000 # Time in different power states 252system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states 253system.physmem.memoryStateTime::ACT 445650242000 # Time in different power states 254system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states 255system.membus.throughput 55070241 # Throughput (bytes/s) 256system.membus.trans_dist::ReadReq 408884 # Transaction distribution 257system.membus.trans_dist::ReadResp 408882 # Transaction distribution 258system.membus.trans_dist::Writeback 66098 # Transaction distribution 259system.membus.trans_dist::UpgradeReq 4292 # Transaction distribution 260system.membus.trans_dist::UpgradeResp 4292 # Transaction distribution 261system.membus.trans_dist::ReadExReq 66078 # Transaction distribution 262system.membus.trans_dist::ReadExResp 66078 # Transaction distribution 263system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1024604 # Packet count per connected master and slave (bytes) 264system.membus.pkt_count::total 1024604 # Packet count per connected master and slave (bytes) 265system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 34627712 # Cumulative packet size per connected master and slave (bytes) 266system.membus.tot_pkt_size::total 34627712 # Cumulative packet size per connected master and slave (bytes) 267system.membus.data_through_bus 34627712 # Total data (bytes) 268system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 269system.membus.reqLayer0.occupancy 1214449500 # Layer occupancy (ticks) 270system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) 271system.membus.respLayer1.occupancy 4441072458 # Layer occupancy (ticks) 272system.membus.respLayer1.utilization 0.7 # Layer utilization (%) 273system.cpu_clk_domain.clock 500 # Clock period in ticks 274system.cpu.branchPred.lookups 439434227 # Number of BP lookups 275system.cpu.branchPred.condPredicted 352242826 # Number of conditional branches predicted 276system.cpu.branchPred.condIncorrect 30627071 # Number of conditional branches incorrect 277system.cpu.branchPred.BTBLookups 250632586 # Number of BTB lookups 278system.cpu.branchPred.BTBHits 230940186 # Number of BTB hits 279system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 280system.cpu.branchPred.BTBHitPct 92.142921 # BTB Hit Percentage 281system.cpu.branchPred.usedRAS 52229993 # Number of times the RAS was used to get a target. 282system.cpu.branchPred.RASInCorrect 2805540 # Number of incorrect RAS predictions. 283system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 284system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 285system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 286system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 287system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 288system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 289system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 290system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 291system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 292system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 293system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 294system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 295system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 296system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 297system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 298system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 299system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 300system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 301system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 302system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 303system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 304system.cpu.dtb.inst_hits 0 # ITB inst hits 305system.cpu.dtb.inst_misses 0 # ITB inst misses 306system.cpu.dtb.read_hits 0 # DTB read hits 307system.cpu.dtb.read_misses 0 # DTB read misses 308system.cpu.dtb.write_hits 0 # DTB write hits 309system.cpu.dtb.write_misses 0 # DTB write misses 310system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 311system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 312system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 313system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 314system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 315system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 316system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 317system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 318system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 319system.cpu.dtb.read_accesses 0 # DTB read accesses 320system.cpu.dtb.write_accesses 0 # DTB write accesses 321system.cpu.dtb.inst_accesses 0 # ITB inst accesses 322system.cpu.dtb.hits 0 # DTB hits 323system.cpu.dtb.misses 0 # DTB misses 324system.cpu.dtb.accesses 0 # DTB accesses 325system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 326system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 327system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 328system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 329system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 330system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 331system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 332system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 333system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 334system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 335system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 336system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 337system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 338system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 339system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 340system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 341system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 342system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 343system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 344system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 345system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 346system.cpu.itb.inst_hits 0 # ITB inst hits 347system.cpu.itb.inst_misses 0 # ITB inst misses 348system.cpu.itb.read_hits 0 # DTB read hits 349system.cpu.itb.read_misses 0 # DTB read misses 350system.cpu.itb.write_hits 0 # DTB write hits 351system.cpu.itb.write_misses 0 # DTB write misses 352system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 353system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 354system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 355system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 356system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 357system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 358system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 359system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 360system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 361system.cpu.itb.read_accesses 0 # DTB read accesses 362system.cpu.itb.write_accesses 0 # DTB write accesses 363system.cpu.itb.inst_accesses 0 # ITB inst accesses 364system.cpu.itb.hits 0 # DTB hits 365system.cpu.itb.misses 0 # DTB misses 366system.cpu.itb.accesses 0 # DTB accesses 367system.cpu.workload.num_syscalls 1411 # Number of system calls 368system.cpu.numCycles 1257583466 # number of cpu cycles simulated 369system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 370system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 371system.cpu.fetch.icacheStallCycles 355252330 # Number of cycles fetch is stalled on an Icache miss 372system.cpu.fetch.Insts 2281557009 # Number of instructions fetch has processed 373system.cpu.fetch.Branches 439434227 # Number of branches that fetch encountered 374system.cpu.fetch.predictedBranches 283170179 # Number of branches that fetch has predicted taken 375system.cpu.fetch.Cycles 601713503 # Number of cycles fetch has run and was not squashing or blocked 376system.cpu.fetch.SquashCycles 156847289 # Number of cycles fetch has spent squashing 377system.cpu.fetch.BlockedCycles 133155767 # Number of cycles fetch has spent blocked 378system.cpu.fetch.MiscStallCycles 595 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 379system.cpu.fetch.PendingTrapStallCycles 11076 # Number of stall cycles due to pending traps 380system.cpu.fetch.IcacheWaitRetryStallCycles 125 # Number of stall cycles due to full MSHR 381system.cpu.fetch.CacheLines 335955320 # Number of cache lines fetched 382system.cpu.fetch.IcacheSquashes 11758504 # Number of outstanding Icache misses that were squashed 383system.cpu.fetch.rateDist::samples 1216301526 # Number of instructions fetched each cycle (Total) 384system.cpu.fetch.rateDist::mean 2.576674 # Number of instructions fetched each cycle (Total) 385system.cpu.fetch.rateDist::stdev 3.174492 # Number of instructions fetched each cycle (Total) 386system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 387system.cpu.fetch.rateDist::0 614632846 50.53% 50.53% # Number of instructions fetched each cycle (Total) 388system.cpu.fetch.rateDist::1 42470987 3.49% 54.02% # Number of instructions fetched each cycle (Total) 389system.cpu.fetch.rateDist::2 96126752 7.90% 61.93% # Number of instructions fetched each cycle (Total) 390system.cpu.fetch.rateDist::3 57281313 4.71% 66.64% # Number of instructions fetched each cycle (Total) 391system.cpu.fetch.rateDist::4 72527941 5.96% 72.60% # Number of instructions fetched each cycle (Total) 392system.cpu.fetch.rateDist::5 45003441 3.70% 76.30% # Number of instructions fetched each cycle (Total) 393system.cpu.fetch.rateDist::6 31089370 2.56% 78.86% # Number of instructions fetched each cycle (Total) 394system.cpu.fetch.rateDist::7 31572340 2.60% 81.45% # Number of instructions fetched each cycle (Total) 395system.cpu.fetch.rateDist::8 225596536 18.55% 100.00% # Number of instructions fetched each cycle (Total) 396system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 397system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 398system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 399system.cpu.fetch.rateDist::total 1216301526 # Number of instructions fetched each cycle (Total) 400system.cpu.fetch.branchRate 0.349427 # Number of branch fetches per cycle 401system.cpu.fetch.rate 1.814239 # Number of inst fetches per cycle 402system.cpu.decode.IdleCycles 405937331 # Number of cycles decode is idle 403system.cpu.decode.BlockedCycles 105620938 # Number of cycles decode is blocked 404system.cpu.decode.RunCycles 561845304 # Number of cycles decode is running 405system.cpu.decode.UnblockCycles 16741500 # Number of cycles decode is unblocking 406system.cpu.decode.SquashCycles 126156453 # Number of cycles decode is squashing 407system.cpu.decode.BranchResolved 44653834 # Number of times decode resolved a branch 408system.cpu.decode.BranchMispred 11972 # Number of times decode detected a branch misprediction 409system.cpu.decode.DecodedInsts 3026383079 # Number of instructions handled by decode 410system.cpu.decode.SquashedInsts 27573 # Number of squashed instructions handled by decode 411system.cpu.rename.SquashCycles 126156453 # Number of cycles rename is squashing 412system.cpu.rename.IdleCycles 441649817 # Number of cycles rename is idle 413system.cpu.rename.BlockCycles 37679339 # Number of cycles rename is blocking 414system.cpu.rename.serializeStallCycles 449718 # count of cycles rename stalled for serializing inst 415system.cpu.rename.RunCycles 540872152 # Number of cycles rename is running 416system.cpu.rename.UnblockCycles 69494047 # Number of cycles rename is unblocking 417system.cpu.rename.RenamedInsts 2944559238 # Number of instructions processed by rename 418system.cpu.rename.ROBFullEvents 81 # Number of times rename has blocked due to ROB full 419system.cpu.rename.IQFullEvents 4802711 # Number of times rename has blocked due to IQ full 420system.cpu.rename.LSQFullEvents 54195204 # Number of times rename has blocked due to LSQ full 421system.cpu.rename.FullRegisterEvents 788 # Number of times there has been no free registers 422system.cpu.rename.RenamedOperands 2928884357 # Number of destination operands rename has renamed 423system.cpu.rename.RenameLookups 14250328437 # Number of register rename lookups that rename has made 424system.cpu.rename.int_rename_lookups 12163279231 # Number of integer rename lookups 425system.cpu.rename.fp_rename_lookups 83987601 # Number of floating rename lookups 426system.cpu.rename.CommittedMaps 1993140090 # Number of HB maps that are committed 427system.cpu.rename.UndoneMaps 935744267 # Number of HB maps that are undone due to squashing 428system.cpu.rename.serializingInsts 20476 # count of serializing insts renamed 429system.cpu.rename.tempSerializingInsts 17997 # count of temporary serializing insts renamed 430system.cpu.rename.skidInsts 177752072 # count of insts added to the skid buffer 431system.cpu.memDep0.insertedLoads 970380112 # Number of loads inserted to the mem dependence unit. 432system.cpu.memDep0.insertedStores 488270478 # Number of stores inserted to the mem dependence unit. 433system.cpu.memDep0.conflictingLoads 36212412 # Number of conflicting loads. 434system.cpu.memDep0.conflictingStores 40741930 # Number of conflicting stores. 435system.cpu.iq.iqInstsAdded 2792865970 # Number of instructions added to the IQ (excludes non-spec) 436system.cpu.iq.iqNonSpecInstsAdded 27850 # Number of non-speculative instructions added to the IQ 437system.cpu.iq.iqInstsIssued 2433397099 # Number of instructions issued 438system.cpu.iq.iqSquashedInstsIssued 13404605 # Number of squashed instructions issued 439system.cpu.iq.iqSquashedInstsExamined 895018158 # Number of squashed instructions iterated over during squash; mainly for profiling 440system.cpu.iq.iqSquashedOperandsExamined 2348989049 # Number of squashed operands that are examined and possibly removed from graph 441system.cpu.iq.iqSquashedNonSpecRemoved 6466 # Number of squashed non-spec instructions that were removed 442system.cpu.iq.issued_per_cycle::samples 1216301526 # Number of insts issued each cycle 443system.cpu.iq.issued_per_cycle::mean 2.000653 # Number of insts issued each cycle 444system.cpu.iq.issued_per_cycle::stdev 1.872636 # Number of insts issued each cycle 445system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 446system.cpu.iq.issued_per_cycle::0 380324245 31.27% 31.27% # Number of insts issued each cycle 447system.cpu.iq.issued_per_cycle::1 183454055 15.08% 46.35% # Number of insts issued each cycle 448system.cpu.iq.issued_per_cycle::2 204117167 16.78% 63.13% # Number of insts issued each cycle 449system.cpu.iq.issued_per_cycle::3 169768830 13.96% 77.09% # Number of insts issued each cycle 450system.cpu.iq.issued_per_cycle::4 132683622 10.91% 88.00% # Number of insts issued each cycle 451system.cpu.iq.issued_per_cycle::5 92575300 7.61% 95.61% # Number of insts issued each cycle 452system.cpu.iq.issued_per_cycle::6 37909888 3.12% 98.73% # Number of insts issued each cycle 453system.cpu.iq.issued_per_cycle::7 12415448 1.02% 99.75% # Number of insts issued each cycle 454system.cpu.iq.issued_per_cycle::8 3052971 0.25% 100.00% # Number of insts issued each cycle 455system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 456system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 457system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 458system.cpu.iq.issued_per_cycle::total 1216301526 # Number of insts issued each cycle 459system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 460system.cpu.iq.fu_full::IntAlu 714605 0.81% 0.81% # attempts to use FU when none available 461system.cpu.iq.fu_full::IntMult 24383 0.03% 0.84% # attempts to use FU when none available 462system.cpu.iq.fu_full::IntDiv 0 0.00% 0.84% # attempts to use FU when none available 463system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.84% # attempts to use FU when none available 464system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.84% # attempts to use FU when none available 465system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.84% # attempts to use FU when none available 466system.cpu.iq.fu_full::FloatMult 0 0.00% 0.84% # attempts to use FU when none available 467system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.84% # attempts to use FU when none available 468system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.84% # attempts to use FU when none available 469system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.84% # attempts to use FU when none available 470system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.84% # attempts to use FU when none available 471system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.84% # attempts to use FU when none available 472system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.84% # attempts to use FU when none available 473system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.84% # attempts to use FU when none available 474system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.84% # attempts to use FU when none available 475system.cpu.iq.fu_full::SimdMult 0 0.00% 0.84% # attempts to use FU when none available 476system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.84% # attempts to use FU when none available 477system.cpu.iq.fu_full::SimdShift 0 0.00% 0.84% # attempts to use FU when none available 478system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.84% # attempts to use FU when none available 479system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.84% # attempts to use FU when none available 480system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.84% # attempts to use FU when none available 481system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.84% # attempts to use FU when none available 482system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.84% # attempts to use FU when none available 483system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.84% # attempts to use FU when none available 484system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.84% # attempts to use FU when none available 485system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.84% # attempts to use FU when none available 486system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.84% # attempts to use FU when none available 487system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.84% # attempts to use FU when none available 488system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.84% # attempts to use FU when none available 489system.cpu.iq.fu_full::MemRead 55145870 62.89% 63.73% # attempts to use FU when none available 490system.cpu.iq.fu_full::MemWrite 31799244 36.27% 100.00% # attempts to use FU when none available 491system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 492system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 493system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 494system.cpu.iq.FU_type_0::IntAlu 1104322039 45.38% 45.38% # Type of FU issued 495system.cpu.iq.FU_type_0::IntMult 11223967 0.46% 45.84% # Type of FU issued 496system.cpu.iq.FU_type_0::IntDiv 0 0.00% 45.84% # Type of FU issued 497system.cpu.iq.FU_type_0::FloatAdd 3 0.00% 45.84% # Type of FU issued 498system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 45.84% # Type of FU issued 499system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 45.84% # Type of FU issued 500system.cpu.iq.FU_type_0::FloatMult 0 0.00% 45.84% # Type of FU issued 501system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 45.84% # Type of FU issued 502system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 45.84% # Type of FU issued 503system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 45.84% # Type of FU issued 504system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 45.84% # Type of FU issued 505system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 45.84% # Type of FU issued 506system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 45.84% # Type of FU issued 507system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 45.84% # Type of FU issued 508system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 45.84% # Type of FU issued 509system.cpu.iq.FU_type_0::SimdMult 0 0.00% 45.84% # Type of FU issued 510system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 45.84% # Type of FU issued 511system.cpu.iq.FU_type_0::SimdShift 0 0.00% 45.84% # Type of FU issued 512system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 45.84% # Type of FU issued 513system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 45.84% # Type of FU issued 514system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.06% 45.90% # Type of FU issued 515system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 45.90% # Type of FU issued 516system.cpu.iq.FU_type_0::SimdFloatCmp 6876477 0.28% 46.18% # Type of FU issued 517system.cpu.iq.FU_type_0::SimdFloatCvt 5502004 0.23% 46.41% # Type of FU issued 518system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 46.41% # Type of FU issued 519system.cpu.iq.FU_type_0::SimdFloatMisc 23392771 0.96% 47.37% # Type of FU issued 520system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.37% # Type of FU issued 521system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.37% # Type of FU issued 522system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.37% # Type of FU issued 523system.cpu.iq.FU_type_0::MemRead 838298218 34.45% 81.82% # Type of FU issued 524system.cpu.iq.FU_type_0::MemWrite 442406331 18.18% 100.00% # Type of FU issued 525system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 526system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 527system.cpu.iq.FU_type_0::total 2433397099 # Type of FU issued 528system.cpu.iq.rate 1.934979 # Inst issue rate 529system.cpu.iq.fu_busy_cnt 87684102 # FU busy when requested 530system.cpu.iq.fu_busy_rate 0.036034 # FU busy rate (busy events/executed inst) 531system.cpu.iq.int_inst_queue_reads 6061689588 # Number of integer instruction queue reads 532system.cpu.iq.int_inst_queue_writes 3605336566 # Number of integer instruction queue writes 533system.cpu.iq.int_inst_queue_wakeup_accesses 2248845458 # Number of integer instruction queue wakeup accesses 534system.cpu.iq.fp_inst_queue_reads 122494843 # Number of floating instruction queue reads 535system.cpu.iq.fp_inst_queue_writes 82642602 # Number of floating instruction queue writes 536system.cpu.iq.fp_inst_queue_wakeup_accesses 56425705 # Number of floating instruction queue wakeup accesses 537system.cpu.iq.int_alu_accesses 2457771318 # Number of integer alu accesses 538system.cpu.iq.fp_alu_accesses 63309883 # Number of floating point alu accesses 539system.cpu.iew.lsq.thread0.forwLoads 84349734 # Number of loads that had data forwarded from stores 540system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 541system.cpu.iew.lsq.thread0.squashedLoads 338992931 # Number of loads squashed 542system.cpu.iew.lsq.thread0.ignoredResponses 10163 # Number of memory responses ignored because the instruction is squashed 543system.cpu.iew.lsq.thread0.memOrderViolation 1428185 # Number of memory ordering violations 544system.cpu.iew.lsq.thread0.squashedStores 211275181 # Number of stores squashed 545system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 546system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 547system.cpu.iew.lsq.thread0.rescheduledLoads 5 # Number of loads that were rescheduled 548system.cpu.iew.lsq.thread0.cacheBlocked 448 # Number of times an access to memory failed due to the cache being blocked 549system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 550system.cpu.iew.iewSquashCycles 126156453 # Number of cycles IEW is squashing 551system.cpu.iew.iewBlockCycles 15953141 # Number of cycles IEW is blocking 552system.cpu.iew.iewUnblockCycles 1561672 # Number of cycles IEW is unblocking 553system.cpu.iew.iewDispatchedInsts 2792906296 # Number of instructions dispatched to IQ 554system.cpu.iew.iewDispSquashedInsts 1415032 # Number of squashed instructions skipped by dispatch 555system.cpu.iew.iewDispLoadInsts 970380112 # Number of dispatched load instructions 556system.cpu.iew.iewDispStoreInsts 488270478 # Number of dispatched store instructions 557system.cpu.iew.iewDispNonSpecInsts 17864 # Number of dispatched non-speculative instructions 558system.cpu.iew.iewIQFullEvents 1555530 # Number of times the IQ has become full, causing a stall 559system.cpu.iew.iewLSQFullEvents 2527 # Number of times the LSQ has become full, causing a stall 560system.cpu.iew.memOrderViolationEvents 1428185 # Number of memory order violations 561system.cpu.iew.predictedTakenIncorrect 32514856 # Number of branches that were predicted taken incorrectly 562system.cpu.iew.predictedNotTakenIncorrect 1483129 # Number of branches that were predicted not taken incorrectly 563system.cpu.iew.branchMispredicts 33997985 # Number of branch mispredicts detected at execute 564system.cpu.iew.iewExecutedInsts 2358061254 # Number of executed instructions 565system.cpu.iew.iewExecLoadInsts 792590559 # Number of load instructions executed 566system.cpu.iew.iewExecSquashedInsts 75335845 # Number of squashed instructions skipped in execute 567system.cpu.iew.exec_swp 0 # number of swp insts executed 568system.cpu.iew.exec_nop 12476 # number of nop insts executed 569system.cpu.iew.exec_refs 1216220468 # number of memory reference insts executed 570system.cpu.iew.exec_branches 319843836 # Number of branches executed 571system.cpu.iew.exec_stores 423629909 # Number of stores executed 572system.cpu.iew.exec_rate 1.875073 # Inst execution rate 573system.cpu.iew.wb_sent 2330961284 # cumulative count of insts sent to commit 574system.cpu.iew.wb_count 2305271163 # cumulative count of insts written-back 575system.cpu.iew.wb_producers 1347649196 # num instructions producing a value 576system.cpu.iew.wb_consumers 2523801543 # num instructions consuming a value 577system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 578system.cpu.iew.wb_rate 1.833096 # insts written-back per cycle 579system.cpu.iew.wb_fanout 0.533976 # average fanout of values written-back 580system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 581system.cpu.commit.commitSquashedInsts 907570051 # The number of squashed insts skipped by commit 582system.cpu.commit.commitNonSpecStalls 21384 # The number of times commit has been forced to stall to communicate backwards 583system.cpu.commit.branchMispredicts 30615394 # The number of times a branch was mispredicted 584system.cpu.commit.committed_per_cycle::samples 1090145073 # Number of insts commited each cycle 585system.cpu.commit.committed_per_cycle::mean 1.729436 # Number of insts commited each cycle 586system.cpu.commit.committed_per_cycle::stdev 2.397108 # Number of insts commited each cycle 587system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 588system.cpu.commit.committed_per_cycle::0 449857024 41.27% 41.27% # Number of insts commited each cycle 589system.cpu.commit.committed_per_cycle::1 288588820 26.47% 67.74% # Number of insts commited each cycle 590system.cpu.commit.committed_per_cycle::2 95106380 8.72% 76.46% # Number of insts commited each cycle 591system.cpu.commit.committed_per_cycle::3 70218402 6.44% 82.90% # Number of insts commited each cycle 592system.cpu.commit.committed_per_cycle::4 46473981 4.26% 87.17% # Number of insts commited each cycle 593system.cpu.commit.committed_per_cycle::5 22183134 2.03% 89.20% # Number of insts commited each cycle 594system.cpu.commit.committed_per_cycle::6 15845043 1.45% 90.66% # Number of insts commited each cycle 595system.cpu.commit.committed_per_cycle::7 10980592 1.01% 91.66% # Number of insts commited each cycle 596system.cpu.commit.committed_per_cycle::8 90891697 8.34% 100.00% # Number of insts commited each cycle 597system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 598system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 599system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 600system.cpu.commit.committed_per_cycle::total 1090145073 # Number of insts commited each cycle 601system.cpu.commit.committedInsts 1384381606 # Number of instructions committed 602system.cpu.commit.committedOps 1885336358 # Number of ops (including micro ops) committed 603system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 604system.cpu.commit.refs 908382478 # Number of memory references committed 605system.cpu.commit.loads 631387181 # Number of loads committed 606system.cpu.commit.membars 9986 # Number of memory barriers committed 607system.cpu.commit.branches 298259106 # Number of branches committed 608system.cpu.commit.fp_insts 52289415 # Number of committed floating point instructions. 609system.cpu.commit.int_insts 1653698867 # Number of committed integer instructions. 610system.cpu.commit.function_calls 41577833 # Number of function calls committed. 611system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 612system.cpu.commit.op_class_0::IntAlu 930022484 49.33% 49.33% # Class of committed instruction 613system.cpu.commit.op_class_0::IntMult 11168279 0.59% 49.92% # Class of committed instruction 614system.cpu.commit.op_class_0::IntDiv 0 0.00% 49.92% # Class of committed instruction 615system.cpu.commit.op_class_0::FloatAdd 0 0.00% 49.92% # Class of committed instruction 616system.cpu.commit.op_class_0::FloatCmp 0 0.00% 49.92% # Class of committed instruction 617system.cpu.commit.op_class_0::FloatCvt 0 0.00% 49.92% # Class of committed instruction 618system.cpu.commit.op_class_0::FloatMult 0 0.00% 49.92% # Class of committed instruction 619system.cpu.commit.op_class_0::FloatDiv 0 0.00% 49.92% # Class of committed instruction 620system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 49.92% # Class of committed instruction 621system.cpu.commit.op_class_0::SimdAdd 0 0.00% 49.92% # Class of committed instruction 622system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 49.92% # Class of committed instruction 623system.cpu.commit.op_class_0::SimdAlu 0 0.00% 49.92% # Class of committed instruction 624system.cpu.commit.op_class_0::SimdCmp 0 0.00% 49.92% # Class of committed instruction 625system.cpu.commit.op_class_0::SimdCvt 0 0.00% 49.92% # Class of committed instruction 626system.cpu.commit.op_class_0::SimdMisc 0 0.00% 49.92% # Class of committed instruction 627system.cpu.commit.op_class_0::SimdMult 0 0.00% 49.92% # Class of committed instruction 628system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 49.92% # Class of committed instruction 629system.cpu.commit.op_class_0::SimdShift 0 0.00% 49.92% # Class of committed instruction 630system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 49.92% # Class of committed instruction 631system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 49.92% # Class of committed instruction 632system.cpu.commit.op_class_0::SimdFloatAdd 1375288 0.07% 49.99% # Class of committed instruction 633system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 49.99% # Class of committed instruction 634system.cpu.commit.op_class_0::SimdFloatCmp 6876469 0.36% 50.36% # Class of committed instruction 635system.cpu.commit.op_class_0::SimdFloatCvt 5501172 0.29% 50.65% # Class of committed instruction 636system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 50.65% # Class of committed instruction 637system.cpu.commit.op_class_0::SimdFloatMisc 22010188 1.17% 51.82% # Class of committed instruction 638system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 51.82% # Class of committed instruction 639system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 51.82% # Class of committed instruction 640system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 51.82% # Class of committed instruction 641system.cpu.commit.op_class_0::MemRead 631387181 33.49% 85.31% # Class of committed instruction 642system.cpu.commit.op_class_0::MemWrite 276995297 14.69% 100.00% # Class of committed instruction 643system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 644system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 645system.cpu.commit.op_class_0::total 1885336358 # Class of committed instruction 646system.cpu.commit.bw_lim_events 90891697 # number cycles where commit BW limit reached 647system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 648system.cpu.rob.rob_reads 3792141440 # The number of ROB reads 649system.cpu.rob.rob_writes 5711980108 # The number of ROB writes 650system.cpu.timesIdled 352856 # Number of times that the entire CPU went into an idle state and unscheduled itself 651system.cpu.idleCycles 41281940 # Total number of cycles that the CPU has spent unscheduled due to idling 652system.cpu.committedInsts 1384370590 # Number of Instructions Simulated 653system.cpu.committedOps 1885325342 # Number of Ops (including micro ops) Simulated 654system.cpu.committedInsts_total 1384370590 # Number of Instructions Simulated 655system.cpu.cpi 0.908415 # CPI: Cycles Per Instruction 656system.cpu.cpi_total 0.908415 # CPI: Total CPI of All Threads 657system.cpu.ipc 1.100818 # IPC: Instructions Per Cycle 658system.cpu.ipc_total 1.100818 # IPC: Total IPC of All Threads 659system.cpu.int_regfile_reads 11756762903 # number of integer regfile reads 660system.cpu.int_regfile_writes 2218718479 # number of integer regfile writes 661system.cpu.fp_regfile_reads 68795802 # number of floating regfile reads 662system.cpu.fp_regfile_writes 49537143 # number of floating regfile writes 663system.cpu.misc_regfile_reads 1677857394 # number of misc regfile reads 664system.cpu.misc_regfile_writes 13772902 # number of misc regfile writes 665system.cpu.toL2Bus.throughput 169149196 # Throughput (bytes/s) 666system.cpu.toL2Bus.trans_dist::ReadReq 1493034 # Transaction distribution 667system.cpu.toL2Bus.trans_dist::ReadResp 1493032 # Transaction distribution 668system.cpu.toL2Bus.trans_dist::Writeback 96318 # Transaction distribution 669system.cpu.toL2Bus.trans_dist::UpgradeReq 4295 # Transaction distribution 670system.cpu.toL2Bus.trans_dist::UpgradeResp 4295 # Transaction distribution 671system.cpu.toL2Bus.trans_dist::ReadExReq 72519 # Transaction distribution 672system.cpu.toL2Bus.trans_dist::ReadExResp 72519 # Transaction distribution 673system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 52723 # Packet count per connected master and slave (bytes) 674system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3178995 # Packet count per connected master and slave (bytes) 675system.cpu.toL2Bus.pkt_count::total 3231718 # Packet count per connected master and slave (bytes) 676system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1549696 # Cumulative packet size per connected master and slave (bytes) 677system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 104535104 # Cumulative packet size per connected master and slave (bytes) 678system.cpu.toL2Bus.tot_pkt_size::total 106084800 # Cumulative packet size per connected master and slave (bytes) 679system.cpu.toL2Bus.data_through_bus 106084800 # Total data (bytes) 680system.cpu.toL2Bus.snoop_data_through_bus 274816 # Total snoop data (bytes) 681system.cpu.toL2Bus.reqLayer0.occupancy 929401499 # Layer occupancy (ticks) 682system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 683system.cpu.toL2Bus.respLayer0.occupancy 43182746 # Layer occupancy (ticks) 684system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 685system.cpu.toL2Bus.respLayer1.occupancy 2371256268 # Layer occupancy (ticks) 686system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) 687system.cpu.icache.tags.replacements 22529 # number of replacements 688system.cpu.icache.tags.tagsinuse 1644.627190 # Cycle average of tags in use 689system.cpu.icache.tags.total_refs 335917634 # Total number of references to valid blocks. 690system.cpu.icache.tags.sampled_refs 24213 # Sample count of references to valid blocks. 691system.cpu.icache.tags.avg_refs 13873.441292 # Average number of references to valid blocks. 692system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 693system.cpu.icache.tags.occ_blocks::cpu.inst 1644.627190 # Average occupied blocks per requestor 694system.cpu.icache.tags.occ_percent::cpu.inst 0.803041 # Average percentage of cache occupancy 695system.cpu.icache.tags.occ_percent::total 0.803041 # Average percentage of cache occupancy 696system.cpu.icache.tags.occ_task_id_blocks::1024 1684 # Occupied blocks per task id 697system.cpu.icache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id 698system.cpu.icache.tags.age_task_id_blocks_1024::1 62 # Occupied blocks per task id 699system.cpu.icache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id 700system.cpu.icache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id 701system.cpu.icache.tags.age_task_id_blocks_1024::4 1552 # Occupied blocks per task id 702system.cpu.icache.tags.occ_task_id_percent::1024 0.822266 # Percentage of cache occupancy per task id 703system.cpu.icache.tags.tag_accesses 671939144 # Number of tag accesses 704system.cpu.icache.tags.data_accesses 671939144 # Number of data accesses 705system.cpu.icache.ReadReq_hits::cpu.inst 335924107 # number of ReadReq hits 706system.cpu.icache.ReadReq_hits::total 335924107 # number of ReadReq hits 707system.cpu.icache.demand_hits::cpu.inst 335924107 # number of demand (read+write) hits 708system.cpu.icache.demand_hits::total 335924107 # number of demand (read+write) hits 709system.cpu.icache.overall_hits::cpu.inst 335924107 # number of overall hits 710system.cpu.icache.overall_hits::total 335924107 # number of overall hits 711system.cpu.icache.ReadReq_misses::cpu.inst 31211 # number of ReadReq misses 712system.cpu.icache.ReadReq_misses::total 31211 # number of ReadReq misses 713system.cpu.icache.demand_misses::cpu.inst 31211 # number of demand (read+write) misses 714system.cpu.icache.demand_misses::total 31211 # number of demand (read+write) misses 715system.cpu.icache.overall_misses::cpu.inst 31211 # number of overall misses 716system.cpu.icache.overall_misses::total 31211 # number of overall misses 717system.cpu.icache.ReadReq_miss_latency::cpu.inst 530208992 # number of ReadReq miss cycles 718system.cpu.icache.ReadReq_miss_latency::total 530208992 # number of ReadReq miss cycles 719system.cpu.icache.demand_miss_latency::cpu.inst 530208992 # number of demand (read+write) miss cycles 720system.cpu.icache.demand_miss_latency::total 530208992 # number of demand (read+write) miss cycles 721system.cpu.icache.overall_miss_latency::cpu.inst 530208992 # number of overall miss cycles 722system.cpu.icache.overall_miss_latency::total 530208992 # number of overall miss cycles 723system.cpu.icache.ReadReq_accesses::cpu.inst 335955318 # number of ReadReq accesses(hits+misses) 724system.cpu.icache.ReadReq_accesses::total 335955318 # number of ReadReq accesses(hits+misses) 725system.cpu.icache.demand_accesses::cpu.inst 335955318 # number of demand (read+write) accesses 726system.cpu.icache.demand_accesses::total 335955318 # number of demand (read+write) accesses 727system.cpu.icache.overall_accesses::cpu.inst 335955318 # number of overall (read+write) accesses 728system.cpu.icache.overall_accesses::total 335955318 # number of overall (read+write) accesses 729system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000093 # miss rate for ReadReq accesses 730system.cpu.icache.ReadReq_miss_rate::total 0.000093 # miss rate for ReadReq accesses 731system.cpu.icache.demand_miss_rate::cpu.inst 0.000093 # miss rate for demand accesses 732system.cpu.icache.demand_miss_rate::total 0.000093 # miss rate for demand accesses 733system.cpu.icache.overall_miss_rate::cpu.inst 0.000093 # miss rate for overall accesses 734system.cpu.icache.overall_miss_rate::total 0.000093 # miss rate for overall accesses 735system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16987.888629 # average ReadReq miss latency 736system.cpu.icache.ReadReq_avg_miss_latency::total 16987.888629 # average ReadReq miss latency 737system.cpu.icache.demand_avg_miss_latency::cpu.inst 16987.888629 # average overall miss latency 738system.cpu.icache.demand_avg_miss_latency::total 16987.888629 # average overall miss latency 739system.cpu.icache.overall_avg_miss_latency::cpu.inst 16987.888629 # average overall miss latency 740system.cpu.icache.overall_avg_miss_latency::total 16987.888629 # average overall miss latency 741system.cpu.icache.blocked_cycles::no_mshrs 1881 # number of cycles access was blocked 742system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 743system.cpu.icache.blocked::no_mshrs 32 # number of cycles access was blocked 744system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 745system.cpu.icache.avg_blocked_cycles::no_mshrs 58.781250 # average number of cycles each access was blocked 746system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 747system.cpu.icache.fast_writes 0 # number of fast writes performed 748system.cpu.icache.cache_copies 0 # number of cache copies performed 749system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2702 # number of ReadReq MSHR hits 750system.cpu.icache.ReadReq_mshr_hits::total 2702 # number of ReadReq MSHR hits 751system.cpu.icache.demand_mshr_hits::cpu.inst 2702 # number of demand (read+write) MSHR hits 752system.cpu.icache.demand_mshr_hits::total 2702 # number of demand (read+write) MSHR hits 753system.cpu.icache.overall_mshr_hits::cpu.inst 2702 # number of overall MSHR hits 754system.cpu.icache.overall_mshr_hits::total 2702 # number of overall MSHR hits 755system.cpu.icache.ReadReq_mshr_misses::cpu.inst 28509 # number of ReadReq MSHR misses 756system.cpu.icache.ReadReq_mshr_misses::total 28509 # number of ReadReq MSHR misses 757system.cpu.icache.demand_mshr_misses::cpu.inst 28509 # number of demand (read+write) MSHR misses 758system.cpu.icache.demand_mshr_misses::total 28509 # number of demand (read+write) MSHR misses 759system.cpu.icache.overall_mshr_misses::cpu.inst 28509 # number of overall MSHR misses 760system.cpu.icache.overall_mshr_misses::total 28509 # number of overall MSHR misses 761system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 424344751 # number of ReadReq MSHR miss cycles 762system.cpu.icache.ReadReq_mshr_miss_latency::total 424344751 # number of ReadReq MSHR miss cycles 763system.cpu.icache.demand_mshr_miss_latency::cpu.inst 424344751 # number of demand (read+write) MSHR miss cycles 764system.cpu.icache.demand_mshr_miss_latency::total 424344751 # number of demand (read+write) MSHR miss cycles 765system.cpu.icache.overall_mshr_miss_latency::cpu.inst 424344751 # number of overall MSHR miss cycles 766system.cpu.icache.overall_mshr_miss_latency::total 424344751 # number of overall MSHR miss cycles 767system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000085 # mshr miss rate for ReadReq accesses 768system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000085 # mshr miss rate for ReadReq accesses 769system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000085 # mshr miss rate for demand accesses 770system.cpu.icache.demand_mshr_miss_rate::total 0.000085 # mshr miss rate for demand accesses 771system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000085 # mshr miss rate for overall accesses 772system.cpu.icache.overall_mshr_miss_rate::total 0.000085 # mshr miss rate for overall accesses 773system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14884.589112 # average ReadReq mshr miss latency 774system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14884.589112 # average ReadReq mshr miss latency 775system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14884.589112 # average overall mshr miss latency 776system.cpu.icache.demand_avg_mshr_miss_latency::total 14884.589112 # average overall mshr miss latency 777system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14884.589112 # average overall mshr miss latency 778system.cpu.icache.overall_avg_mshr_miss_latency::total 14884.589112 # average overall mshr miss latency 779system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 780system.cpu.l2cache.tags.replacements 442179 # number of replacements 781system.cpu.l2cache.tags.tagsinuse 32677.883650 # Cycle average of tags in use 782system.cpu.l2cache.tags.total_refs 1109649 # Total number of references to valid blocks. 783system.cpu.l2cache.tags.sampled_refs 474925 # Sample count of references to valid blocks. 784system.cpu.l2cache.tags.avg_refs 2.336472 # Average number of references to valid blocks. 785system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 786system.cpu.l2cache.tags.occ_blocks::writebacks 1317.007846 # Average occupied blocks per requestor 787system.cpu.l2cache.tags.occ_blocks::cpu.inst 51.079905 # Average occupied blocks per requestor 788system.cpu.l2cache.tags.occ_blocks::cpu.data 31309.795899 # Average occupied blocks per requestor 789system.cpu.l2cache.tags.occ_percent::writebacks 0.040192 # Average percentage of cache occupancy 790system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001559 # Average percentage of cache occupancy 791system.cpu.l2cache.tags.occ_percent::cpu.data 0.955499 # Average percentage of cache occupancy 792system.cpu.l2cache.tags.occ_percent::total 0.997250 # Average percentage of cache occupancy 793system.cpu.l2cache.tags.occ_task_id_blocks::1024 32746 # Occupied blocks per task id 794system.cpu.l2cache.tags.age_task_id_blocks_1024::0 100 # Occupied blocks per task id 795system.cpu.l2cache.tags.age_task_id_blocks_1024::1 149 # Occupied blocks per task id 796system.cpu.l2cache.tags.age_task_id_blocks_1024::2 509 # Occupied blocks per task id 797system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5033 # Occupied blocks per task id 798system.cpu.l2cache.tags.age_task_id_blocks_1024::4 26955 # Occupied blocks per task id 799system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999329 # Percentage of cache occupancy per task id 800system.cpu.l2cache.tags.tag_accesses 13842423 # Number of tag accesses 801system.cpu.l2cache.tags.data_accesses 13842423 # Number of data accesses 802system.cpu.l2cache.ReadReq_hits::cpu.inst 21791 # number of ReadReq hits 803system.cpu.l2cache.ReadReq_hits::cpu.data 1058039 # number of ReadReq hits 804system.cpu.l2cache.ReadReq_hits::total 1079830 # number of ReadReq hits 805system.cpu.l2cache.Writeback_hits::writebacks 96318 # number of Writeback hits 806system.cpu.l2cache.Writeback_hits::total 96318 # number of Writeback hits 807system.cpu.l2cache.UpgradeReq_hits::cpu.data 3 # number of UpgradeReq hits 808system.cpu.l2cache.UpgradeReq_hits::total 3 # number of UpgradeReq hits 809system.cpu.l2cache.ReadExReq_hits::cpu.data 6441 # number of ReadExReq hits 810system.cpu.l2cache.ReadExReq_hits::total 6441 # number of ReadExReq hits 811system.cpu.l2cache.demand_hits::cpu.inst 21791 # number of demand (read+write) hits 812system.cpu.l2cache.demand_hits::cpu.data 1064480 # number of demand (read+write) hits 813system.cpu.l2cache.demand_hits::total 1086271 # number of demand (read+write) hits 814system.cpu.l2cache.overall_hits::cpu.inst 21791 # number of overall hits 815system.cpu.l2cache.overall_hits::cpu.data 1064480 # number of overall hits 816system.cpu.l2cache.overall_hits::total 1086271 # number of overall hits 817system.cpu.l2cache.ReadReq_misses::cpu.inst 2424 # number of ReadReq misses 818system.cpu.l2cache.ReadReq_misses::cpu.data 406486 # number of ReadReq misses 819system.cpu.l2cache.ReadReq_misses::total 408910 # number of ReadReq misses 820system.cpu.l2cache.UpgradeReq_misses::cpu.data 4292 # number of UpgradeReq misses 821system.cpu.l2cache.UpgradeReq_misses::total 4292 # number of UpgradeReq misses 822system.cpu.l2cache.ReadExReq_misses::cpu.data 66078 # number of ReadExReq misses 823system.cpu.l2cache.ReadExReq_misses::total 66078 # number of ReadExReq misses 824system.cpu.l2cache.demand_misses::cpu.inst 2424 # number of demand (read+write) misses 825system.cpu.l2cache.demand_misses::cpu.data 472564 # number of demand (read+write) misses 826system.cpu.l2cache.demand_misses::total 474988 # number of demand (read+write) misses 827system.cpu.l2cache.overall_misses::cpu.inst 2424 # number of overall misses 828system.cpu.l2cache.overall_misses::cpu.data 472564 # number of overall misses 829system.cpu.l2cache.overall_misses::total 474988 # number of overall misses 830system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 173590500 # number of ReadReq miss cycles 831system.cpu.l2cache.ReadReq_miss_latency::cpu.data 30155031750 # number of ReadReq miss cycles 832system.cpu.l2cache.ReadReq_miss_latency::total 30328622250 # number of ReadReq miss cycles 833system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4756999500 # number of ReadExReq miss cycles 834system.cpu.l2cache.ReadExReq_miss_latency::total 4756999500 # number of ReadExReq miss cycles 835system.cpu.l2cache.demand_miss_latency::cpu.inst 173590500 # number of demand (read+write) miss cycles 836system.cpu.l2cache.demand_miss_latency::cpu.data 34912031250 # number of demand (read+write) miss cycles 837system.cpu.l2cache.demand_miss_latency::total 35085621750 # number of demand (read+write) miss cycles 838system.cpu.l2cache.overall_miss_latency::cpu.inst 173590500 # number of overall miss cycles 839system.cpu.l2cache.overall_miss_latency::cpu.data 34912031250 # number of overall miss cycles 840system.cpu.l2cache.overall_miss_latency::total 35085621750 # number of overall miss cycles 841system.cpu.l2cache.ReadReq_accesses::cpu.inst 24215 # number of ReadReq accesses(hits+misses) 842system.cpu.l2cache.ReadReq_accesses::cpu.data 1464525 # number of ReadReq accesses(hits+misses) 843system.cpu.l2cache.ReadReq_accesses::total 1488740 # number of ReadReq accesses(hits+misses) 844system.cpu.l2cache.Writeback_accesses::writebacks 96318 # number of Writeback accesses(hits+misses) 845system.cpu.l2cache.Writeback_accesses::total 96318 # number of Writeback accesses(hits+misses) 846system.cpu.l2cache.UpgradeReq_accesses::cpu.data 4295 # number of UpgradeReq accesses(hits+misses) 847system.cpu.l2cache.UpgradeReq_accesses::total 4295 # number of UpgradeReq accesses(hits+misses) 848system.cpu.l2cache.ReadExReq_accesses::cpu.data 72519 # number of ReadExReq accesses(hits+misses) 849system.cpu.l2cache.ReadExReq_accesses::total 72519 # number of ReadExReq accesses(hits+misses) 850system.cpu.l2cache.demand_accesses::cpu.inst 24215 # number of demand (read+write) accesses 851system.cpu.l2cache.demand_accesses::cpu.data 1537044 # number of demand (read+write) accesses 852system.cpu.l2cache.demand_accesses::total 1561259 # number of demand (read+write) accesses 853system.cpu.l2cache.overall_accesses::cpu.inst 24215 # number of overall (read+write) accesses 854system.cpu.l2cache.overall_accesses::cpu.data 1537044 # number of overall (read+write) accesses 855system.cpu.l2cache.overall_accesses::total 1561259 # number of overall (read+write) accesses 856system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.100103 # miss rate for ReadReq accesses 857system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.277555 # miss rate for ReadReq accesses 858system.cpu.l2cache.ReadReq_miss_rate::total 0.274669 # miss rate for ReadReq accesses 859system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.999302 # miss rate for UpgradeReq accesses 860system.cpu.l2cache.UpgradeReq_miss_rate::total 0.999302 # miss rate for UpgradeReq accesses 861system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.911182 # miss rate for ReadExReq accesses 862system.cpu.l2cache.ReadExReq_miss_rate::total 0.911182 # miss rate for ReadExReq accesses 863system.cpu.l2cache.demand_miss_rate::cpu.inst 0.100103 # miss rate for demand accesses 864system.cpu.l2cache.demand_miss_rate::cpu.data 0.307450 # miss rate for demand accesses 865system.cpu.l2cache.demand_miss_rate::total 0.304234 # miss rate for demand accesses 866system.cpu.l2cache.overall_miss_rate::cpu.inst 0.100103 # miss rate for overall accesses 867system.cpu.l2cache.overall_miss_rate::cpu.data 0.307450 # miss rate for overall accesses 868system.cpu.l2cache.overall_miss_rate::total 0.304234 # miss rate for overall accesses 869system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71613.242574 # average ReadReq miss latency 870system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 74184.674872 # average ReadReq miss latency 871system.cpu.l2cache.ReadReq_avg_miss_latency::total 74169.431538 # average ReadReq miss latency 872system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71990.670117 # average ReadExReq miss latency 873system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71990.670117 # average ReadExReq miss latency 874system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71613.242574 # average overall miss latency 875system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73877.890085 # average overall miss latency 876system.cpu.l2cache.demand_avg_miss_latency::total 73866.332939 # average overall miss latency 877system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71613.242574 # average overall miss latency 878system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73877.890085 # average overall miss latency 879system.cpu.l2cache.overall_avg_miss_latency::total 73866.332939 # average overall miss latency 880system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 881system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 882system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 883system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 884system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 885system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 886system.cpu.l2cache.fast_writes 0 # number of fast writes performed 887system.cpu.l2cache.cache_copies 0 # number of cache copies performed 888system.cpu.l2cache.writebacks::writebacks 66098 # number of writebacks 889system.cpu.l2cache.writebacks::total 66098 # number of writebacks 890system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits 891system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 24 # number of ReadReq MSHR hits 892system.cpu.l2cache.ReadReq_mshr_hits::total 26 # number of ReadReq MSHR hits 893system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits 894system.cpu.l2cache.demand_mshr_hits::cpu.data 24 # number of demand (read+write) MSHR hits 895system.cpu.l2cache.demand_mshr_hits::total 26 # number of demand (read+write) MSHR hits 896system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits 897system.cpu.l2cache.overall_mshr_hits::cpu.data 24 # number of overall MSHR hits 898system.cpu.l2cache.overall_mshr_hits::total 26 # number of overall MSHR hits 899system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2422 # number of ReadReq MSHR misses 900system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 406462 # number of ReadReq MSHR misses 901system.cpu.l2cache.ReadReq_mshr_misses::total 408884 # number of ReadReq MSHR misses 902system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 4292 # number of UpgradeReq MSHR misses 903system.cpu.l2cache.UpgradeReq_mshr_misses::total 4292 # number of UpgradeReq MSHR misses 904system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66078 # number of ReadExReq MSHR misses 905system.cpu.l2cache.ReadExReq_mshr_misses::total 66078 # number of ReadExReq MSHR misses 906system.cpu.l2cache.demand_mshr_misses::cpu.inst 2422 # number of demand (read+write) MSHR misses 907system.cpu.l2cache.demand_mshr_misses::cpu.data 472540 # number of demand (read+write) MSHR misses 908system.cpu.l2cache.demand_mshr_misses::total 474962 # number of demand (read+write) MSHR misses 909system.cpu.l2cache.overall_mshr_misses::cpu.inst 2422 # number of overall MSHR misses 910system.cpu.l2cache.overall_mshr_misses::cpu.data 472540 # number of overall MSHR misses 911system.cpu.l2cache.overall_mshr_misses::total 474962 # number of overall MSHR misses 912system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 143052750 # number of ReadReq MSHR miss cycles 913system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 25094264500 # number of ReadReq MSHR miss cycles 914system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25237317250 # number of ReadReq MSHR miss cycles 915system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 42924292 # number of UpgradeReq MSHR miss cycles 916system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 42924292 # number of UpgradeReq MSHR miss cycles 917system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3924413500 # number of ReadExReq MSHR miss cycles 918system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3924413500 # number of ReadExReq MSHR miss cycles 919system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 143052750 # number of demand (read+write) MSHR miss cycles 920system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 29018678000 # number of demand (read+write) MSHR miss cycles 921system.cpu.l2cache.demand_mshr_miss_latency::total 29161730750 # number of demand (read+write) MSHR miss cycles 922system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 143052750 # number of overall MSHR miss cycles 923system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 29018678000 # number of overall MSHR miss cycles 924system.cpu.l2cache.overall_mshr_miss_latency::total 29161730750 # number of overall MSHR miss cycles 925system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.100021 # mshr miss rate for ReadReq accesses 926system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.277538 # mshr miss rate for ReadReq accesses 927system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.274651 # mshr miss rate for ReadReq accesses 928system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.999302 # mshr miss rate for UpgradeReq accesses 929system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.999302 # mshr miss rate for UpgradeReq accesses 930system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.911182 # mshr miss rate for ReadExReq accesses 931system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.911182 # mshr miss rate for ReadExReq accesses 932system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.100021 # mshr miss rate for demand accesses 933system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.307434 # mshr miss rate for demand accesses 934system.cpu.l2cache.demand_mshr_miss_rate::total 0.304217 # mshr miss rate for demand accesses 935system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.100021 # mshr miss rate for overall accesses 936system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.307434 # mshr miss rate for overall accesses 937system.cpu.l2cache.overall_mshr_miss_rate::total 0.304217 # mshr miss rate for overall accesses 938system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59063.893476 # average ReadReq mshr miss latency 939system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 61738.279347 # average ReadReq mshr miss latency 940system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61722.437782 # average ReadReq mshr miss latency 941system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency 942system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency 943system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59390.621690 # average ReadExReq mshr miss latency 944system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59390.621690 # average ReadExReq mshr miss latency 945system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59063.893476 # average overall mshr miss latency 946system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61409.992805 # average overall mshr miss latency 947system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61398.029211 # average overall mshr miss latency 948system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59063.893476 # average overall mshr miss latency 949system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61409.992805 # average overall mshr miss latency 950system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61398.029211 # average overall mshr miss latency 951system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 952system.cpu.dcache.tags.replacements 1532947 # number of replacements 953system.cpu.dcache.tags.tagsinuse 4094.376885 # Cycle average of tags in use 954system.cpu.dcache.tags.total_refs 969983510 # Total number of references to valid blocks. 955system.cpu.dcache.tags.sampled_refs 1537043 # Sample count of references to valid blocks. 956system.cpu.dcache.tags.avg_refs 631.071161 # Average number of references to valid blocks. 957system.cpu.dcache.tags.warmup_cycle 400583250 # Cycle when the warmup percentage was hit. 958system.cpu.dcache.tags.occ_blocks::cpu.data 4094.376885 # Average occupied blocks per requestor 959system.cpu.dcache.tags.occ_percent::cpu.data 0.999604 # Average percentage of cache occupancy 960system.cpu.dcache.tags.occ_percent::total 0.999604 # Average percentage of cache occupancy 961system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 962system.cpu.dcache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id 963system.cpu.dcache.tags.age_task_id_blocks_1024::1 263 # Occupied blocks per task id 964system.cpu.dcache.tags.age_task_id_blocks_1024::2 978 # Occupied blocks per task id 965system.cpu.dcache.tags.age_task_id_blocks_1024::3 2415 # Occupied blocks per task id 966system.cpu.dcache.tags.age_task_id_blocks_1024::4 394 # Occupied blocks per task id 967system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 968system.cpu.dcache.tags.tag_accesses 1947074947 # Number of tag accesses 969system.cpu.dcache.tags.data_accesses 1947074947 # Number of data accesses 970system.cpu.dcache.ReadReq_hits::cpu.data 693859178 # number of ReadReq hits 971system.cpu.dcache.ReadReq_hits::total 693859178 # number of ReadReq hits 972system.cpu.dcache.WriteReq_hits::cpu.data 276090749 # number of WriteReq hits 973system.cpu.dcache.WriteReq_hits::total 276090749 # number of WriteReq hits 974system.cpu.dcache.LoadLockedReq_hits::cpu.data 10001 # number of LoadLockedReq hits 975system.cpu.dcache.LoadLockedReq_hits::total 10001 # number of LoadLockedReq hits 976system.cpu.dcache.StoreCondReq_hits::cpu.data 9985 # number of StoreCondReq hits 977system.cpu.dcache.StoreCondReq_hits::total 9985 # number of StoreCondReq hits 978system.cpu.dcache.demand_hits::cpu.data 969949927 # number of demand (read+write) hits 979system.cpu.dcache.demand_hits::total 969949927 # number of demand (read+write) hits 980system.cpu.dcache.overall_hits::cpu.data 969949927 # number of overall hits 981system.cpu.dcache.overall_hits::total 969949927 # number of overall hits 982system.cpu.dcache.ReadReq_misses::cpu.data 1954107 # number of ReadReq misses 983system.cpu.dcache.ReadReq_misses::total 1954107 # number of ReadReq misses 984system.cpu.dcache.WriteReq_misses::cpu.data 844929 # number of WriteReq misses 985system.cpu.dcache.WriteReq_misses::total 844929 # number of WriteReq misses 986system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses 987system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses 988system.cpu.dcache.demand_misses::cpu.data 2799036 # number of demand (read+write) misses 989system.cpu.dcache.demand_misses::total 2799036 # number of demand (read+write) misses 990system.cpu.dcache.overall_misses::cpu.data 2799036 # number of overall misses 991system.cpu.dcache.overall_misses::total 2799036 # number of overall misses 992system.cpu.dcache.ReadReq_miss_latency::cpu.data 79576585056 # number of ReadReq miss cycles 993system.cpu.dcache.ReadReq_miss_latency::total 79576585056 # number of ReadReq miss cycles 994system.cpu.dcache.WriteReq_miss_latency::cpu.data 58758638704 # number of WriteReq miss cycles 995system.cpu.dcache.WriteReq_miss_latency::total 58758638704 # number of WriteReq miss cycles 996system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 210750 # number of LoadLockedReq miss cycles 997system.cpu.dcache.LoadLockedReq_miss_latency::total 210750 # number of LoadLockedReq miss cycles 998system.cpu.dcache.demand_miss_latency::cpu.data 138335223760 # number of demand (read+write) miss cycles 999system.cpu.dcache.demand_miss_latency::total 138335223760 # number of demand (read+write) miss cycles 1000system.cpu.dcache.overall_miss_latency::cpu.data 138335223760 # number of overall miss cycles 1001system.cpu.dcache.overall_miss_latency::total 138335223760 # number of overall miss cycles 1002system.cpu.dcache.ReadReq_accesses::cpu.data 695813285 # number of ReadReq accesses(hits+misses) 1003system.cpu.dcache.ReadReq_accesses::total 695813285 # number of ReadReq accesses(hits+misses) 1004system.cpu.dcache.WriteReq_accesses::cpu.data 276935678 # number of WriteReq accesses(hits+misses) 1005system.cpu.dcache.WriteReq_accesses::total 276935678 # number of WriteReq accesses(hits+misses) 1006system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10004 # number of LoadLockedReq accesses(hits+misses) 1007system.cpu.dcache.LoadLockedReq_accesses::total 10004 # number of LoadLockedReq accesses(hits+misses) 1008system.cpu.dcache.StoreCondReq_accesses::cpu.data 9985 # number of StoreCondReq accesses(hits+misses) 1009system.cpu.dcache.StoreCondReq_accesses::total 9985 # number of StoreCondReq accesses(hits+misses) 1010system.cpu.dcache.demand_accesses::cpu.data 972748963 # number of demand (read+write) accesses 1011system.cpu.dcache.demand_accesses::total 972748963 # number of demand (read+write) accesses 1012system.cpu.dcache.overall_accesses::cpu.data 972748963 # number of overall (read+write) accesses 1013system.cpu.dcache.overall_accesses::total 972748963 # number of overall (read+write) accesses 1014system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002808 # miss rate for ReadReq accesses 1015system.cpu.dcache.ReadReq_miss_rate::total 0.002808 # miss rate for ReadReq accesses 1016system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003051 # miss rate for WriteReq accesses 1017system.cpu.dcache.WriteReq_miss_rate::total 0.003051 # miss rate for WriteReq accesses 1018system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000300 # miss rate for LoadLockedReq accesses 1019system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000300 # miss rate for LoadLockedReq accesses 1020system.cpu.dcache.demand_miss_rate::cpu.data 0.002877 # miss rate for demand accesses 1021system.cpu.dcache.demand_miss_rate::total 0.002877 # miss rate for demand accesses 1022system.cpu.dcache.overall_miss_rate::cpu.data 0.002877 # miss rate for overall accesses 1023system.cpu.dcache.overall_miss_rate::total 0.002877 # miss rate for overall accesses 1024system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40722.736808 # average ReadReq miss latency 1025system.cpu.dcache.ReadReq_avg_miss_latency::total 40722.736808 # average ReadReq miss latency 1026system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69542.693770 # average WriteReq miss latency 1027system.cpu.dcache.WriteReq_avg_miss_latency::total 69542.693770 # average WriteReq miss latency 1028system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 70250 # average LoadLockedReq miss latency 1029system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 70250 # average LoadLockedReq miss latency 1030system.cpu.dcache.demand_avg_miss_latency::cpu.data 49422.452502 # average overall miss latency 1031system.cpu.dcache.demand_avg_miss_latency::total 49422.452502 # average overall miss latency 1032system.cpu.dcache.overall_avg_miss_latency::cpu.data 49422.452502 # average overall miss latency 1033system.cpu.dcache.overall_avg_miss_latency::total 49422.452502 # average overall miss latency 1034system.cpu.dcache.blocked_cycles::no_mshrs 2414 # number of cycles access was blocked 1035system.cpu.dcache.blocked_cycles::no_targets 988 # number of cycles access was blocked 1036system.cpu.dcache.blocked::no_mshrs 54 # number of cycles access was blocked 1037system.cpu.dcache.blocked::no_targets 92 # number of cycles access was blocked 1038system.cpu.dcache.avg_blocked_cycles::no_mshrs 44.703704 # average number of cycles each access was blocked 1039system.cpu.dcache.avg_blocked_cycles::no_targets 10.739130 # average number of cycles each access was blocked 1040system.cpu.dcache.fast_writes 0 # number of fast writes performed 1041system.cpu.dcache.cache_copies 0 # number of cache copies performed 1042system.cpu.dcache.writebacks::writebacks 96318 # number of writebacks 1043system.cpu.dcache.writebacks::total 96318 # number of writebacks 1044system.cpu.dcache.ReadReq_mshr_hits::cpu.data 489582 # number of ReadReq MSHR hits 1045system.cpu.dcache.ReadReq_mshr_hits::total 489582 # number of ReadReq MSHR hits 1046system.cpu.dcache.WriteReq_mshr_hits::cpu.data 768115 # number of WriteReq MSHR hits 1047system.cpu.dcache.WriteReq_mshr_hits::total 768115 # number of WriteReq MSHR hits 1048system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits 1049system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits 1050system.cpu.dcache.demand_mshr_hits::cpu.data 1257697 # number of demand (read+write) MSHR hits 1051system.cpu.dcache.demand_mshr_hits::total 1257697 # number of demand (read+write) MSHR hits 1052system.cpu.dcache.overall_mshr_hits::cpu.data 1257697 # number of overall MSHR hits 1053system.cpu.dcache.overall_mshr_hits::total 1257697 # number of overall MSHR hits 1054system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1464525 # number of ReadReq MSHR misses 1055system.cpu.dcache.ReadReq_mshr_misses::total 1464525 # number of ReadReq MSHR misses 1056system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76814 # number of WriteReq MSHR misses 1057system.cpu.dcache.WriteReq_mshr_misses::total 76814 # number of WriteReq MSHR misses 1058system.cpu.dcache.demand_mshr_misses::cpu.data 1541339 # number of demand (read+write) MSHR misses 1059system.cpu.dcache.demand_mshr_misses::total 1541339 # number of demand (read+write) MSHR misses 1060system.cpu.dcache.overall_mshr_misses::cpu.data 1541339 # number of overall MSHR misses 1061system.cpu.dcache.overall_mshr_misses::total 1541339 # number of overall MSHR misses 1062system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 42200288024 # number of ReadReq MSHR miss cycles 1063system.cpu.dcache.ReadReq_mshr_miss_latency::total 42200288024 # number of ReadReq MSHR miss cycles 1064system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4993959708 # number of WriteReq MSHR miss cycles 1065system.cpu.dcache.WriteReq_mshr_miss_latency::total 4993959708 # number of WriteReq MSHR miss cycles 1066system.cpu.dcache.demand_mshr_miss_latency::cpu.data 47194247732 # number of demand (read+write) MSHR miss cycles 1067system.cpu.dcache.demand_mshr_miss_latency::total 47194247732 # number of demand (read+write) MSHR miss cycles 1068system.cpu.dcache.overall_mshr_miss_latency::cpu.data 47194247732 # number of overall MSHR miss cycles 1069system.cpu.dcache.overall_mshr_miss_latency::total 47194247732 # number of overall MSHR miss cycles 1070system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002105 # mshr miss rate for ReadReq accesses 1071system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002105 # mshr miss rate for ReadReq accesses 1072system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000277 # mshr miss rate for WriteReq accesses 1073system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000277 # mshr miss rate for WriteReq accesses 1074system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001585 # mshr miss rate for demand accesses 1075system.cpu.dcache.demand_mshr_miss_rate::total 0.001585 # mshr miss rate for demand accesses 1076system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001585 # mshr miss rate for overall accesses 1077system.cpu.dcache.overall_mshr_miss_rate::total 0.001585 # mshr miss rate for overall accesses 1078system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 28815.000102 # average ReadReq mshr miss latency 1079system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 28815.000102 # average ReadReq mshr miss latency 1080system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 65013.665582 # average WriteReq mshr miss latency 1081system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 65013.665582 # average WriteReq mshr miss latency 1082system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30618.992793 # average overall mshr miss latency 1083system.cpu.dcache.demand_avg_mshr_miss_latency::total 30618.992793 # average overall mshr miss latency 1084system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30618.992793 # average overall mshr miss latency 1085system.cpu.dcache.overall_avg_mshr_miss_latency::total 30618.992793 # average overall mshr miss latency 1086system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1087 1088---------- End Simulation Statistics ---------- 1089