stats.txt revision 10148:4574d5882066
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.629657 # Number of seconds simulated 4sim_ticks 629657386500 # Number of ticks simulated 5final_tick 629657386500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 85982 # Simulator instruction rate (inst/s) 8host_op_rate 117096 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 39107572 # Simulator tick rate (ticks/s) 10host_mem_usage 322024 # Number of bytes of host memory used 11host_seconds 16100.65 # Real time elapsed on the host 12sim_insts 1384370590 # Number of instructions simulated 13sim_ops 1885325342 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 155392 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 30242880 # Number of bytes read from this memory 18system.physmem.bytes_read::total 30398272 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 155392 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 155392 # Number of instructions bytes read from this memory 21system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory 22system.physmem.bytes_written::total 4230272 # Number of bytes written to this memory 23system.physmem.num_reads::cpu.inst 2428 # Number of read requests responded to by this memory 24system.physmem.num_reads::cpu.data 472545 # Number of read requests responded to by this memory 25system.physmem.num_reads::total 474973 # Number of read requests responded to by this memory 26system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory 27system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory 28system.physmem.bw_read::cpu.inst 246788 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::cpu.data 48030692 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::total 48277480 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_inst_read::cpu.inst 246788 # Instruction read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::total 246788 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_write::writebacks 6718371 # Write bandwidth from this memory (bytes/s) 34system.physmem.bw_write::total 6718371 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_total::writebacks 6718371 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::cpu.inst 246788 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.data 48030692 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::total 54995851 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.readReqs 474973 # Number of read requests accepted 40system.physmem.writeReqs 66098 # Number of write requests accepted 41system.physmem.readBursts 474973 # Number of DRAM read bursts, including those serviced by the write queue 42system.physmem.writeBursts 66098 # Number of DRAM write bursts, including those merged in the write queue 43system.physmem.bytesReadDRAM 30370688 # Total number of bytes read from DRAM 44system.physmem.bytesReadWrQ 27584 # Total number of bytes read from write queue 45system.physmem.bytesWritten 4228672 # Total number of bytes written to DRAM 46system.physmem.bytesReadSys 30398272 # Total read bytes from the system interface side 47system.physmem.bytesWrittenSys 4230272 # Total written bytes from the system interface side 48system.physmem.servicedByWrQ 431 # Number of DRAM read bursts serviced by the write queue 49system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 50system.physmem.neitherReadNorWriteReqs 4296 # Number of requests that are neither read nor write 51system.physmem.perBankRdBursts::0 29858 # Per bank write bursts 52system.physmem.perBankRdBursts::1 29659 # Per bank write bursts 53system.physmem.perBankRdBursts::2 29728 # Per bank write bursts 54system.physmem.perBankRdBursts::3 29690 # Per bank write bursts 55system.physmem.perBankRdBursts::4 29781 # Per bank write bursts 56system.physmem.perBankRdBursts::5 29808 # Per bank write bursts 57system.physmem.perBankRdBursts::6 29619 # Per bank write bursts 58system.physmem.perBankRdBursts::7 29428 # Per bank write bursts 59system.physmem.perBankRdBursts::8 29461 # Per bank write bursts 60system.physmem.perBankRdBursts::9 29473 # Per bank write bursts 61system.physmem.perBankRdBursts::10 29524 # Per bank write bursts 62system.physmem.perBankRdBursts::11 29641 # Per bank write bursts 63system.physmem.perBankRdBursts::12 29683 # Per bank write bursts 64system.physmem.perBankRdBursts::13 29785 # Per bank write bursts 65system.physmem.perBankRdBursts::14 29611 # Per bank write bursts 66system.physmem.perBankRdBursts::15 29793 # Per bank write bursts 67system.physmem.perBankWrBursts::0 4174 # Per bank write bursts 68system.physmem.perBankWrBursts::1 4100 # Per bank write bursts 69system.physmem.perBankWrBursts::2 4137 # Per bank write bursts 70system.physmem.perBankWrBursts::3 4146 # Per bank write bursts 71system.physmem.perBankWrBursts::4 4223 # Per bank write bursts 72system.physmem.perBankWrBursts::5 4223 # Per bank write bursts 73system.physmem.perBankWrBursts::6 4171 # Per bank write bursts 74system.physmem.perBankWrBursts::7 4094 # Per bank write bursts 75system.physmem.perBankWrBursts::8 4094 # Per bank write bursts 76system.physmem.perBankWrBursts::9 4093 # Per bank write bursts 77system.physmem.perBankWrBursts::10 4093 # Per bank write bursts 78system.physmem.perBankWrBursts::11 4097 # Per bank write bursts 79system.physmem.perBankWrBursts::12 4098 # Per bank write bursts 80system.physmem.perBankWrBursts::13 4094 # Per bank write bursts 81system.physmem.perBankWrBursts::14 4096 # Per bank write bursts 82system.physmem.perBankWrBursts::15 4140 # Per bank write bursts 83system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 84system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 85system.physmem.totGap 629657309500 # Total gap between requests 86system.physmem.readPktSize::0 0 # Read request sizes (log2) 87system.physmem.readPktSize::1 0 # Read request sizes (log2) 88system.physmem.readPktSize::2 0 # Read request sizes (log2) 89system.physmem.readPktSize::3 0 # Read request sizes (log2) 90system.physmem.readPktSize::4 0 # Read request sizes (log2) 91system.physmem.readPktSize::5 0 # Read request sizes (log2) 92system.physmem.readPktSize::6 474973 # Read request sizes (log2) 93system.physmem.writePktSize::0 0 # Write request sizes (log2) 94system.physmem.writePktSize::1 0 # Write request sizes (log2) 95system.physmem.writePktSize::2 0 # Write request sizes (log2) 96system.physmem.writePktSize::3 0 # Write request sizes (log2) 97system.physmem.writePktSize::4 0 # Write request sizes (log2) 98system.physmem.writePktSize::5 0 # Write request sizes (log2) 99system.physmem.writePktSize::6 66098 # Write request sizes (log2) 100system.physmem.rdQLenPdf::0 407581 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::1 66607 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::2 273 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::3 61 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::4 18 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 132system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 133system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 134system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::15 941 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::16 941 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::17 965 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::18 3991 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::19 3992 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::20 3994 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::21 3993 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::22 4172 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::23 4867 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::24 4005 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::25 5495 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::26 4100 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::27 4045 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::28 4370 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::29 4016 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::30 3998 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::31 4000 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::32 3993 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::33 196 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::34 3 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::35 3 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::36 1 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::37 1 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::38 1 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 196system.physmem.bytesPerActivate::samples 28167 # Bytes accessed per row activation 197system.physmem.bytesPerActivate::mean 403.324742 # Bytes accessed per row activation 198system.physmem.bytesPerActivate::gmean 187.656646 # Bytes accessed per row activation 199system.physmem.bytesPerActivate::stdev 439.024801 # Bytes accessed per row activation 200system.physmem.bytesPerActivate::0-127 14746 52.35% 52.35% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::128-255 2789 9.90% 62.25% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::256-383 571 2.03% 64.28% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::384-511 164 0.58% 64.86% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::512-639 93 0.33% 65.19% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::640-767 524 1.86% 67.05% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::768-895 314 1.11% 68.17% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::896-1023 86 0.31% 68.47% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::1024-1151 8880 31.53% 100.00% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::total 28167 # Bytes accessed per row activation 210system.physmem.rdPerTurnAround::samples 3992 # Reads before turning the bus around for writes 211system.physmem.rdPerTurnAround::mean 48.707415 # Reads before turning the bus around for writes 212system.physmem.rdPerTurnAround::gmean 36.187766 # Reads before turning the bus around for writes 213system.physmem.rdPerTurnAround::stdev 506.851977 # Reads before turning the bus around for writes 214system.physmem.rdPerTurnAround::0-1023 3989 99.92% 99.92% # Reads before turning the bus around for writes 215system.physmem.rdPerTurnAround::1024-2047 1 0.03% 99.95% # Reads before turning the bus around for writes 216system.physmem.rdPerTurnAround::2048-3071 1 0.03% 99.97% # Reads before turning the bus around for writes 217system.physmem.rdPerTurnAround::31744-32767 1 0.03% 100.00% # Reads before turning the bus around for writes 218system.physmem.rdPerTurnAround::total 3992 # Reads before turning the bus around for writes 219system.physmem.wrPerTurnAround::samples 3992 # Writes before turning the bus around for reads 220system.physmem.wrPerTurnAround::mean 16.551353 # Writes before turning the bus around for reads 221system.physmem.wrPerTurnAround::gmean 16.521439 # Writes before turning the bus around for reads 222system.physmem.wrPerTurnAround::stdev 1.024563 # Writes before turning the bus around for reads 223system.physmem.wrPerTurnAround::16 3052 76.45% 76.45% # Writes before turning the bus around for reads 224system.physmem.wrPerTurnAround::18 627 15.71% 92.16% # Writes before turning the bus around for reads 225system.physmem.wrPerTurnAround::19 310 7.77% 99.92% # Writes before turning the bus around for reads 226system.physmem.wrPerTurnAround::20 1 0.03% 99.95% # Writes before turning the bus around for reads 227system.physmem.wrPerTurnAround::21 1 0.03% 99.97% # Writes before turning the bus around for reads 228system.physmem.wrPerTurnAround::24 1 0.03% 100.00% # Writes before turning the bus around for reads 229system.physmem.wrPerTurnAround::total 3992 # Writes before turning the bus around for reads 230system.physmem.totQLat 3604221250 # Total ticks spent queuing 231system.physmem.totMemAccLat 15074013750 # Total ticks spent from burst creation until serviced by the DRAM 232system.physmem.totBusLat 2372710000 # Total ticks spent in databus transfers 233system.physmem.totBankLat 9097082500 # Total ticks spent accessing banks 234system.physmem.avgQLat 7595.16 # Average queueing delay per DRAM burst 235system.physmem.avgBankLat 19170.24 # Average bank access latency per DRAM burst 236system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 237system.physmem.avgMemAccLat 31765.39 # Average memory access latency per DRAM burst 238system.physmem.avgRdBW 48.23 # Average DRAM read bandwidth in MiByte/s 239system.physmem.avgWrBW 6.72 # Average achieved write bandwidth in MiByte/s 240system.physmem.avgRdBWSys 48.28 # Average system read bandwidth in MiByte/s 241system.physmem.avgWrBWSys 6.72 # Average system write bandwidth in MiByte/s 242system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 243system.physmem.busUtil 0.43 # Data bus utilization in percentage 244system.physmem.busUtilRead 0.38 # Data bus utilization in percentage for reads 245system.physmem.busUtilWrite 0.05 # Data bus utilization in percentage for writes 246system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing 247system.physmem.avgWrQLen 24.85 # Average write queue length when enqueuing 248system.physmem.readRowHits 295971 # Number of row buffer hits during reads 249system.physmem.writeRowHits 49954 # Number of row buffer hits during writes 250system.physmem.readRowHitRate 62.37 # Row buffer hit rate for reads 251system.physmem.writeRowHitRate 75.58 # Row buffer hit rate for writes 252system.physmem.avgGap 1163724.00 # Average gap between requests 253system.physmem.pageHitRate 63.98 # Row buffer hit rate, read and write combined 254system.physmem.prechargeAllPercent 24.27 # Percentage of time for which DRAM has all the banks in precharge state 255system.membus.throughput 54995851 # Throughput (bytes/s) 256system.membus.trans_dist::ReadReq 408896 # Transaction distribution 257system.membus.trans_dist::ReadResp 408896 # Transaction distribution 258system.membus.trans_dist::Writeback 66098 # Transaction distribution 259system.membus.trans_dist::UpgradeReq 4296 # Transaction distribution 260system.membus.trans_dist::UpgradeResp 4296 # Transaction distribution 261system.membus.trans_dist::ReadExReq 66077 # Transaction distribution 262system.membus.trans_dist::ReadExResp 66077 # Transaction distribution 263system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1024636 # Packet count per connected master and slave (bytes) 264system.membus.pkt_count::total 1024636 # Packet count per connected master and slave (bytes) 265system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 34628544 # Cumulative packet size per connected master and slave (bytes) 266system.membus.tot_pkt_size::total 34628544 # Cumulative packet size per connected master and slave (bytes) 267system.membus.data_through_bus 34628544 # Total data (bytes) 268system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 269system.membus.reqLayer0.occupancy 1215525500 # Layer occupancy (ticks) 270system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) 271system.membus.respLayer1.occupancy 4444359954 # Layer occupancy (ticks) 272system.membus.respLayer1.utilization 0.7 # Layer utilization (%) 273system.cpu_clk_domain.clock 500 # Clock period in ticks 274system.cpu.branchPred.lookups 438199522 # Number of BP lookups 275system.cpu.branchPred.condPredicted 350949441 # Number of conditional branches predicted 276system.cpu.branchPred.condIncorrect 30620410 # Number of conditional branches incorrect 277system.cpu.branchPred.BTBLookups 248742563 # Number of BTB lookups 278system.cpu.branchPred.BTBHits 229772650 # Number of BTB hits 279system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 280system.cpu.branchPred.BTBHitPct 92.373676 # BTB Hit Percentage 281system.cpu.branchPred.usedRAS 52962534 # Number of times the RAS was used to get a target. 282system.cpu.branchPred.RASInCorrect 2805242 # Number of incorrect RAS predictions. 283system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 284system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 285system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 286system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 287system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 288system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 289system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 290system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 291system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 292system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 293system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 294system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 295system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 296system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 297system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 298system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 299system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 300system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 301system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 302system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 303system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 304system.cpu.dtb.inst_hits 0 # ITB inst hits 305system.cpu.dtb.inst_misses 0 # ITB inst misses 306system.cpu.dtb.read_hits 0 # DTB read hits 307system.cpu.dtb.read_misses 0 # DTB read misses 308system.cpu.dtb.write_hits 0 # DTB write hits 309system.cpu.dtb.write_misses 0 # DTB write misses 310system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 311system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 312system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 313system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 314system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 315system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 316system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 317system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 318system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 319system.cpu.dtb.read_accesses 0 # DTB read accesses 320system.cpu.dtb.write_accesses 0 # DTB write accesses 321system.cpu.dtb.inst_accesses 0 # ITB inst accesses 322system.cpu.dtb.hits 0 # DTB hits 323system.cpu.dtb.misses 0 # DTB misses 324system.cpu.dtb.accesses 0 # DTB accesses 325system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 326system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 327system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 328system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 329system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 330system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 331system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 332system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 333system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 334system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 335system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 336system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 337system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 338system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 339system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 340system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 341system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 342system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 343system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 344system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 345system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 346system.cpu.itb.inst_hits 0 # ITB inst hits 347system.cpu.itb.inst_misses 0 # ITB inst misses 348system.cpu.itb.read_hits 0 # DTB read hits 349system.cpu.itb.read_misses 0 # DTB read misses 350system.cpu.itb.write_hits 0 # DTB write hits 351system.cpu.itb.write_misses 0 # DTB write misses 352system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 353system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 354system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 355system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 356system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 357system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 358system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 359system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 360system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 361system.cpu.itb.read_accesses 0 # DTB read accesses 362system.cpu.itb.write_accesses 0 # DTB write accesses 363system.cpu.itb.inst_accesses 0 # ITB inst accesses 364system.cpu.itb.hits 0 # DTB hits 365system.cpu.itb.misses 0 # DTB misses 366system.cpu.itb.accesses 0 # DTB accesses 367system.cpu.workload.num_syscalls 1411 # Number of system calls 368system.cpu.numCycles 1259314774 # number of cpu cycles simulated 369system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 370system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 371system.cpu.fetch.icacheStallCycles 354212583 # Number of cycles fetch is stalled on an Icache miss 372system.cpu.fetch.Insts 2278943291 # Number of instructions fetch has processed 373system.cpu.fetch.Branches 438199522 # Number of branches that fetch encountered 374system.cpu.fetch.predictedBranches 282735184 # Number of branches that fetch has predicted taken 375system.cpu.fetch.Cycles 601285341 # Number of cycles fetch has run and was not squashing or blocked 376system.cpu.fetch.SquashCycles 157201665 # Number of cycles fetch has spent squashing 377system.cpu.fetch.BlockedCycles 134990206 # Number of cycles fetch has spent blocked 378system.cpu.fetch.MiscStallCycles 592 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 379system.cpu.fetch.PendingTrapStallCycles 11080 # Number of stall cycles due to pending traps 380system.cpu.fetch.IcacheWaitRetryStallCycles 114 # Number of stall cycles due to full MSHR 381system.cpu.fetch.CacheLines 334803997 # Number of cache lines fetched 382system.cpu.fetch.IcacheSquashes 11648696 # Number of outstanding Icache misses that were squashed 383system.cpu.fetch.rateDist::samples 1217029612 # Number of instructions fetched each cycle (Total) 384system.cpu.fetch.rateDist::mean 2.574413 # Number of instructions fetched each cycle (Total) 385system.cpu.fetch.rateDist::stdev 3.174582 # Number of instructions fetched each cycle (Total) 386system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 387system.cpu.fetch.rateDist::0 615789102 50.60% 50.60% # Number of instructions fetched each cycle (Total) 388system.cpu.fetch.rateDist::1 42212896 3.47% 54.07% # Number of instructions fetched each cycle (Total) 389system.cpu.fetch.rateDist::2 95956201 7.88% 61.95% # Number of instructions fetched each cycle (Total) 390system.cpu.fetch.rateDist::3 57716133 4.74% 66.69% # Number of instructions fetched each cycle (Total) 391system.cpu.fetch.rateDist::4 72254915 5.94% 72.63% # Number of instructions fetched each cycle (Total) 392system.cpu.fetch.rateDist::5 44707595 3.67% 76.30% # Number of instructions fetched each cycle (Total) 393system.cpu.fetch.rateDist::6 31168110 2.56% 78.86% # Number of instructions fetched each cycle (Total) 394system.cpu.fetch.rateDist::7 31500430 2.59% 81.45% # Number of instructions fetched each cycle (Total) 395system.cpu.fetch.rateDist::8 225724230 18.55% 100.00% # Number of instructions fetched each cycle (Total) 396system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 397system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 398system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 399system.cpu.fetch.rateDist::total 1217029612 # Number of instructions fetched each cycle (Total) 400system.cpu.fetch.branchRate 0.347967 # Number of branch fetches per cycle 401system.cpu.fetch.rate 1.809669 # Number of inst fetches per cycle 402system.cpu.decode.IdleCycles 405265267 # Number of cycles decode is idle 403system.cpu.decode.BlockedCycles 107157501 # Number of cycles decode is blocked 404system.cpu.decode.RunCycles 560735859 # Number of cycles decode is running 405system.cpu.decode.UnblockCycles 17352207 # Number of cycles decode is unblocking 406system.cpu.decode.SquashCycles 126518778 # Number of cycles decode is squashing 407system.cpu.decode.BranchResolved 44627065 # Number of times decode resolved a branch 408system.cpu.decode.BranchMispred 11198 # Number of times decode detected a branch misprediction 409system.cpu.decode.DecodedInsts 3022541715 # Number of instructions handled by decode 410system.cpu.decode.SquashedInsts 25538 # Number of squashed instructions handled by decode 411system.cpu.rename.SquashCycles 126518778 # Number of cycles rename is squashing 412system.cpu.rename.IdleCycles 441244328 # Number of cycles rename is idle 413system.cpu.rename.BlockCycles 38456610 # Number of cycles rename is blocking 414system.cpu.rename.serializeStallCycles 454301 # count of cycles rename stalled for serializing inst 415system.cpu.rename.RunCycles 539911121 # Number of cycles rename is running 416system.cpu.rename.UnblockCycles 70444474 # Number of cycles rename is unblocking 417system.cpu.rename.RenamedInsts 2941731616 # Number of instructions processed by rename 418system.cpu.rename.ROBFullEvents 86 # Number of times rename has blocked due to ROB full 419system.cpu.rename.IQFullEvents 4811465 # Number of times rename has blocked due to IQ full 420system.cpu.rename.LSQFullEvents 54362751 # Number of times rename has blocked due to LSQ full 421system.cpu.rename.FullRegisterEvents 733 # Number of times there has been no free registers 422system.cpu.rename.RenamedOperands 2929353177 # Number of destination operands rename has renamed 423system.cpu.rename.RenameLookups 14237214542 # Number of register rename lookups that rename has made 424system.cpu.rename.int_rename_lookups 12151315514 # Number of integer rename lookups 425system.cpu.rename.fp_rename_lookups 83979009 # Number of floating rename lookups 426system.cpu.rename.CommittedMaps 1993140090 # Number of HB maps that are committed 427system.cpu.rename.UndoneMaps 936213087 # Number of HB maps that are undone due to squashing 428system.cpu.rename.serializingInsts 20203 # count of serializing insts renamed 429system.cpu.rename.tempSerializingInsts 17724 # count of temporary serializing insts renamed 430system.cpu.rename.skidInsts 179723252 # count of insts added to the skid buffer 431system.cpu.memDep0.insertedLoads 971631963 # Number of loads inserted to the mem dependence unit. 432system.cpu.memDep0.insertedStores 486198822 # Number of stores inserted to the mem dependence unit. 433system.cpu.memDep0.conflictingLoads 36723664 # Number of conflicting loads. 434system.cpu.memDep0.conflictingStores 38677099 # Number of conflicting stores. 435system.cpu.iq.iqInstsAdded 2793016392 # Number of instructions added to the IQ (excludes non-spec) 436system.cpu.iq.iqNonSpecInstsAdded 27622 # Number of non-speculative instructions added to the IQ 437system.cpu.iq.iqInstsIssued 2435260833 # Number of instructions issued 438system.cpu.iq.iqSquashedInstsIssued 13305109 # Number of squashed instructions issued 439system.cpu.iq.iqSquashedInstsExamined 895166670 # Number of squashed instructions iterated over during squash; mainly for profiling 440system.cpu.iq.iqSquashedOperandsExamined 2343525890 # Number of squashed operands that are examined and possibly removed from graph 441system.cpu.iq.iqSquashedNonSpecRemoved 6238 # Number of squashed non-spec instructions that were removed 442system.cpu.iq.issued_per_cycle::samples 1217029612 # Number of insts issued each cycle 443system.cpu.iq.issued_per_cycle::mean 2.000987 # Number of insts issued each cycle 444system.cpu.iq.issued_per_cycle::stdev 1.873461 # Number of insts issued each cycle 445system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 446system.cpu.iq.issued_per_cycle::0 381057421 31.31% 31.31% # Number of insts issued each cycle 447system.cpu.iq.issued_per_cycle::1 183026992 15.04% 46.35% # Number of insts issued each cycle 448system.cpu.iq.issued_per_cycle::2 204041316 16.77% 63.11% # Number of insts issued each cycle 449system.cpu.iq.issued_per_cycle::3 169676462 13.94% 77.06% # Number of insts issued each cycle 450system.cpu.iq.issued_per_cycle::4 132865899 10.92% 87.97% # Number of insts issued each cycle 451system.cpu.iq.issued_per_cycle::5 92968001 7.64% 95.61% # Number of insts issued each cycle 452system.cpu.iq.issued_per_cycle::6 37978061 3.12% 98.73% # Number of insts issued each cycle 453system.cpu.iq.issued_per_cycle::7 12373824 1.02% 99.75% # Number of insts issued each cycle 454system.cpu.iq.issued_per_cycle::8 3041636 0.25% 100.00% # Number of insts issued each cycle 455system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 456system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 457system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 458system.cpu.iq.issued_per_cycle::total 1217029612 # Number of insts issued each cycle 459system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 460system.cpu.iq.fu_full::IntAlu 714935 0.82% 0.82% # attempts to use FU when none available 461system.cpu.iq.fu_full::IntMult 24383 0.03% 0.84% # attempts to use FU when none available 462system.cpu.iq.fu_full::IntDiv 0 0.00% 0.84% # attempts to use FU when none available 463system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.84% # attempts to use FU when none available 464system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.84% # attempts to use FU when none available 465system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.84% # attempts to use FU when none available 466system.cpu.iq.fu_full::FloatMult 0 0.00% 0.84% # attempts to use FU when none available 467system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.84% # attempts to use FU when none available 468system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.84% # attempts to use FU when none available 469system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.84% # attempts to use FU when none available 470system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.84% # attempts to use FU when none available 471system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.84% # attempts to use FU when none available 472system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.84% # attempts to use FU when none available 473system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.84% # attempts to use FU when none available 474system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.84% # attempts to use FU when none available 475system.cpu.iq.fu_full::SimdMult 0 0.00% 0.84% # attempts to use FU when none available 476system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.84% # attempts to use FU when none available 477system.cpu.iq.fu_full::SimdShift 0 0.00% 0.84% # attempts to use FU when none available 478system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.84% # attempts to use FU when none available 479system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.84% # attempts to use FU when none available 480system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.84% # attempts to use FU when none available 481system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.84% # attempts to use FU when none available 482system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.84% # attempts to use FU when none available 483system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.84% # attempts to use FU when none available 484system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.84% # attempts to use FU when none available 485system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.84% # attempts to use FU when none available 486system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.84% # attempts to use FU when none available 487system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.84% # attempts to use FU when none available 488system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.84% # attempts to use FU when none available 489system.cpu.iq.fu_full::MemRead 55166828 62.92% 63.77% # attempts to use FU when none available 490system.cpu.iq.fu_full::MemWrite 31766374 36.23% 100.00% # attempts to use FU when none available 491system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 492system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 493system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 494system.cpu.iq.FU_type_0::IntAlu 1104417509 45.35% 45.35% # Type of FU issued 495system.cpu.iq.FU_type_0::IntMult 11223990 0.46% 45.81% # Type of FU issued 496system.cpu.iq.FU_type_0::IntDiv 0 0.00% 45.81% # Type of FU issued 497system.cpu.iq.FU_type_0::FloatAdd 3 0.00% 45.81% # Type of FU issued 498system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 45.81% # Type of FU issued 499system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 45.81% # Type of FU issued 500system.cpu.iq.FU_type_0::FloatMult 0 0.00% 45.81% # Type of FU issued 501system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 45.81% # Type of FU issued 502system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 45.81% # Type of FU issued 503system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 45.81% # Type of FU issued 504system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 45.81% # Type of FU issued 505system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 45.81% # Type of FU issued 506system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 45.81% # Type of FU issued 507system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 45.81% # Type of FU issued 508system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 45.81% # Type of FU issued 509system.cpu.iq.FU_type_0::SimdMult 0 0.00% 45.81% # Type of FU issued 510system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 45.81% # Type of FU issued 511system.cpu.iq.FU_type_0::SimdShift 0 0.00% 45.81% # Type of FU issued 512system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 45.81% # Type of FU issued 513system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 45.81% # Type of FU issued 514system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.06% 45.87% # Type of FU issued 515system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 45.87% # Type of FU issued 516system.cpu.iq.FU_type_0::SimdFloatCmp 6876473 0.28% 46.15% # Type of FU issued 517system.cpu.iq.FU_type_0::SimdFloatCvt 5501794 0.23% 46.38% # Type of FU issued 518system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 46.38% # Type of FU issued 519system.cpu.iq.FU_type_0::SimdFloatMisc 23394204 0.96% 47.34% # Type of FU issued 520system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.34% # Type of FU issued 521system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.34% # Type of FU issued 522system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.34% # Type of FU issued 523system.cpu.iq.FU_type_0::MemRead 839996872 34.49% 81.83% # Type of FU issued 524system.cpu.iq.FU_type_0::MemWrite 442474698 18.17% 100.00% # Type of FU issued 525system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 526system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 527system.cpu.iq.FU_type_0::total 2435260833 # Type of FU issued 528system.cpu.iq.rate 1.933798 # Inst issue rate 529system.cpu.iq.fu_busy_cnt 87672520 # FU busy when requested 530system.cpu.iq.fu_busy_rate 0.036001 # FU busy rate (busy events/executed inst) 531system.cpu.iq.int_inst_queue_reads 6066045738 # Number of integer instruction queue reads 532system.cpu.iq.int_inst_queue_writes 3605651148 # Number of integer instruction queue writes 533system.cpu.iq.int_inst_queue_wakeup_accesses 2250091074 # Number of integer instruction queue wakeup accesses 534system.cpu.iq.fp_inst_queue_reads 122483169 # Number of floating instruction queue reads 535system.cpu.iq.fp_inst_queue_writes 82625914 # Number of floating instruction queue writes 536system.cpu.iq.fp_inst_queue_wakeup_accesses 56426435 # Number of floating instruction queue wakeup accesses 537system.cpu.iq.int_alu_accesses 2459629474 # Number of integer alu accesses 538system.cpu.iq.fp_alu_accesses 63303879 # Number of floating point alu accesses 539system.cpu.iew.lsq.thread0.forwLoads 84463938 # Number of loads that had data forwarded from stores 540system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 541system.cpu.iew.lsq.thread0.squashedLoads 340244782 # Number of loads squashed 542system.cpu.iew.lsq.thread0.ignoredResponses 10257 # Number of memory responses ignored because the instruction is squashed 543system.cpu.iew.lsq.thread0.memOrderViolation 1430041 # Number of memory ordering violations 544system.cpu.iew.lsq.thread0.squashedStores 209203525 # Number of stores squashed 545system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 546system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 547system.cpu.iew.lsq.thread0.rescheduledLoads 5 # Number of loads that were rescheduled 548system.cpu.iew.lsq.thread0.cacheBlocked 356 # Number of times an access to memory failed due to the cache being blocked 549system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 550system.cpu.iew.iewSquashCycles 126518778 # Number of cycles IEW is squashing 551system.cpu.iew.iewBlockCycles 16487163 # Number of cycles IEW is blocking 552system.cpu.iew.iewUnblockCycles 1561706 # Number of cycles IEW is unblocking 553system.cpu.iew.iewDispatchedInsts 2793056470 # Number of instructions dispatched to IQ 554system.cpu.iew.iewDispSquashedInsts 1389243 # Number of squashed instructions skipped by dispatch 555system.cpu.iew.iewDispLoadInsts 971631963 # Number of dispatched load instructions 556system.cpu.iew.iewDispStoreInsts 486198822 # Number of dispatched store instructions 557system.cpu.iew.iewDispNonSpecInsts 17636 # Number of dispatched non-speculative instructions 558system.cpu.iew.iewIQFullEvents 1558036 # Number of times the IQ has become full, causing a stall 559system.cpu.iew.iewLSQFullEvents 2522 # Number of times the LSQ has become full, causing a stall 560system.cpu.iew.memOrderViolationEvents 1430041 # Number of memory order violations 561system.cpu.iew.predictedTakenIncorrect 32401956 # Number of branches that were predicted taken incorrectly 562system.cpu.iew.predictedNotTakenIncorrect 1516006 # Number of branches that were predicted not taken incorrectly 563system.cpu.iew.branchMispredicts 33917962 # Number of branch mispredicts detected at execute 564system.cpu.iew.iewExecutedInsts 2359922616 # Number of executed instructions 565system.cpu.iew.iewExecLoadInsts 794093704 # Number of load instructions executed 566system.cpu.iew.iewExecSquashedInsts 75338217 # Number of squashed instructions skipped in execute 567system.cpu.iew.exec_swp 0 # number of swp insts executed 568system.cpu.iew.exec_nop 12456 # number of nop insts executed 569system.cpu.iew.exec_refs 1217365234 # number of memory reference insts executed 570system.cpu.iew.exec_branches 319562430 # Number of branches executed 571system.cpu.iew.exec_stores 423271530 # Number of stores executed 572system.cpu.iew.exec_rate 1.873974 # Inst execution rate 573system.cpu.iew.wb_sent 2332280723 # cumulative count of insts sent to commit 574system.cpu.iew.wb_count 2306517509 # cumulative count of insts written-back 575system.cpu.iew.wb_producers 1349120960 # num instructions producing a value 576system.cpu.iew.wb_consumers 2527351065 # num instructions consuming a value 577system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 578system.cpu.iew.wb_rate 1.831566 # insts written-back per cycle 579system.cpu.iew.wb_fanout 0.533808 # average fanout of values written-back 580system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 581system.cpu.commit.commitSquashedInsts 907720231 # The number of squashed insts skipped by commit 582system.cpu.commit.commitNonSpecStalls 21384 # The number of times commit has been forced to stall to communicate backwards 583system.cpu.commit.branchMispredicts 30609492 # The number of times a branch was mispredicted 584system.cpu.commit.committed_per_cycle::samples 1090510834 # Number of insts commited each cycle 585system.cpu.commit.committed_per_cycle::mean 1.728856 # Number of insts commited each cycle 586system.cpu.commit.committed_per_cycle::stdev 2.396955 # Number of insts commited each cycle 587system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 588system.cpu.commit.committed_per_cycle::0 450229589 41.29% 41.29% # Number of insts commited each cycle 589system.cpu.commit.committed_per_cycle::1 288600221 26.46% 67.75% # Number of insts commited each cycle 590system.cpu.commit.committed_per_cycle::2 95089363 8.72% 76.47% # Number of insts commited each cycle 591system.cpu.commit.committed_per_cycle::3 70207190 6.44% 82.91% # Number of insts commited each cycle 592system.cpu.commit.committed_per_cycle::4 46482431 4.26% 87.17% # Number of insts commited each cycle 593system.cpu.commit.committed_per_cycle::5 22180112 2.03% 89.20% # Number of insts commited each cycle 594system.cpu.commit.committed_per_cycle::6 15844912 1.45% 90.66% # Number of insts commited each cycle 595system.cpu.commit.committed_per_cycle::7 10980043 1.01% 91.66% # Number of insts commited each cycle 596system.cpu.commit.committed_per_cycle::8 90896973 8.34% 100.00% # Number of insts commited each cycle 597system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 598system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 599system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 600system.cpu.commit.committed_per_cycle::total 1090510834 # Number of insts commited each cycle 601system.cpu.commit.committedInsts 1384381606 # Number of instructions committed 602system.cpu.commit.committedOps 1885336358 # Number of ops (including micro ops) committed 603system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 604system.cpu.commit.refs 908382478 # Number of memory references committed 605system.cpu.commit.loads 631387181 # Number of loads committed 606system.cpu.commit.membars 9986 # Number of memory barriers committed 607system.cpu.commit.branches 298259106 # Number of branches committed 608system.cpu.commit.fp_insts 52289415 # Number of committed floating point instructions. 609system.cpu.commit.int_insts 1653698867 # Number of committed integer instructions. 610system.cpu.commit.function_calls 41577833 # Number of function calls committed. 611system.cpu.commit.bw_lim_events 90896973 # number cycles where commit BW limit reached 612system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 613system.cpu.rob.rob_reads 3792652105 # The number of ROB reads 614system.cpu.rob.rob_writes 5712643141 # The number of ROB writes 615system.cpu.timesIdled 352993 # Number of times that the entire CPU went into an idle state and unscheduled itself 616system.cpu.idleCycles 42285162 # Total number of cycles that the CPU has spent unscheduled due to idling 617system.cpu.committedInsts 1384370590 # Number of Instructions Simulated 618system.cpu.committedOps 1885325342 # Number of Ops (including micro ops) Simulated 619system.cpu.committedInsts_total 1384370590 # Number of Instructions Simulated 620system.cpu.cpi 0.909666 # CPI: Cycles Per Instruction 621system.cpu.cpi_total 0.909666 # CPI: Total CPI of All Threads 622system.cpu.ipc 1.099305 # IPC: Instructions Per Cycle 623system.cpu.ipc_total 1.099305 # IPC: Total IPC of All Threads 624system.cpu.int_regfile_reads 11767299799 # number of integer regfile reads 625system.cpu.int_regfile_writes 2220455487 # number of integer regfile writes 626system.cpu.fp_regfile_reads 68795103 # number of floating regfile reads 627system.cpu.fp_regfile_writes 49537962 # number of floating regfile writes 628system.cpu.misc_regfile_reads 1678438007 # number of misc regfile reads 629system.cpu.misc_regfile_writes 13772902 # number of misc regfile writes 630system.cpu.toL2Bus.throughput 168942873 # Throughput (bytes/s) 631system.cpu.toL2Bus.trans_dist::ReadReq 1493289 # Transaction distribution 632system.cpu.toL2Bus.trans_dist::ReadResp 1493289 # Transaction distribution 633system.cpu.toL2Bus.trans_dist::Writeback 96321 # Transaction distribution 634system.cpu.toL2Bus.trans_dist::UpgradeReq 4299 # Transaction distribution 635system.cpu.toL2Bus.trans_dist::UpgradeResp 4299 # Transaction distribution 636system.cpu.toL2Bus.trans_dist::ReadExReq 72517 # Transaction distribution 637system.cpu.toL2Bus.trans_dist::ReadExResp 72517 # Transaction distribution 638system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 53208 # Packet count per connected master and slave (bytes) 639system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3179025 # Packet count per connected master and slave (bytes) 640system.cpu.toL2Bus.pkt_count::total 3232233 # Packet count per connected master and slave (bytes) 641system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1565120 # Cumulative packet size per connected master and slave (bytes) 642system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 104535936 # Cumulative packet size per connected master and slave (bytes) 643system.cpu.toL2Bus.tot_pkt_size::total 106101056 # Cumulative packet size per connected master and slave (bytes) 644system.cpu.toL2Bus.data_through_bus 106101056 # Total data (bytes) 645system.cpu.toL2Bus.snoop_data_through_bus 275072 # Total snoop data (bytes) 646system.cpu.toL2Bus.reqLayer0.occupancy 929534000 # Layer occupancy (ticks) 647system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 648system.cpu.toL2Bus.respLayer0.occupancy 43545495 # Layer occupancy (ticks) 649system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 650system.cpu.toL2Bus.respLayer1.occupancy 2368755772 # Layer occupancy (ticks) 651system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) 652system.cpu.icache.tags.replacements 22771 # number of replacements 653system.cpu.icache.tags.tagsinuse 1640.597248 # Cycle average of tags in use 654system.cpu.icache.tags.total_refs 334768394 # Total number of references to valid blocks. 655system.cpu.icache.tags.sampled_refs 24455 # Sample count of references to valid blocks. 656system.cpu.icache.tags.avg_refs 13689.159436 # Average number of references to valid blocks. 657system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 658system.cpu.icache.tags.occ_blocks::cpu.inst 1640.597248 # Average occupied blocks per requestor 659system.cpu.icache.tags.occ_percent::cpu.inst 0.801073 # Average percentage of cache occupancy 660system.cpu.icache.tags.occ_percent::total 0.801073 # Average percentage of cache occupancy 661system.cpu.icache.tags.occ_task_id_blocks::1024 1684 # Occupied blocks per task id 662system.cpu.icache.tags.age_task_id_blocks_1024::0 68 # Occupied blocks per task id 663system.cpu.icache.tags.age_task_id_blocks_1024::1 66 # Occupied blocks per task id 664system.cpu.icache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id 665system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id 666system.cpu.icache.tags.age_task_id_blocks_1024::4 1545 # Occupied blocks per task id 667system.cpu.icache.tags.occ_task_id_percent::1024 0.822266 # Percentage of cache occupancy per task id 668system.cpu.icache.tags.tag_accesses 669636743 # Number of tag accesses 669system.cpu.icache.tags.data_accesses 669636743 # Number of data accesses 670system.cpu.icache.ReadReq_hits::cpu.inst 334772400 # number of ReadReq hits 671system.cpu.icache.ReadReq_hits::total 334772400 # number of ReadReq hits 672system.cpu.icache.demand_hits::cpu.inst 334772400 # number of demand (read+write) hits 673system.cpu.icache.demand_hits::total 334772400 # number of demand (read+write) hits 674system.cpu.icache.overall_hits::cpu.inst 334772400 # number of overall hits 675system.cpu.icache.overall_hits::total 334772400 # number of overall hits 676system.cpu.icache.ReadReq_misses::cpu.inst 31595 # number of ReadReq misses 677system.cpu.icache.ReadReq_misses::total 31595 # number of ReadReq misses 678system.cpu.icache.demand_misses::cpu.inst 31595 # number of demand (read+write) misses 679system.cpu.icache.demand_misses::total 31595 # number of demand (read+write) misses 680system.cpu.icache.overall_misses::cpu.inst 31595 # number of overall misses 681system.cpu.icache.overall_misses::total 31595 # number of overall misses 682system.cpu.icache.ReadReq_miss_latency::cpu.inst 539866742 # number of ReadReq miss cycles 683system.cpu.icache.ReadReq_miss_latency::total 539866742 # number of ReadReq miss cycles 684system.cpu.icache.demand_miss_latency::cpu.inst 539866742 # number of demand (read+write) miss cycles 685system.cpu.icache.demand_miss_latency::total 539866742 # number of demand (read+write) miss cycles 686system.cpu.icache.overall_miss_latency::cpu.inst 539866742 # number of overall miss cycles 687system.cpu.icache.overall_miss_latency::total 539866742 # number of overall miss cycles 688system.cpu.icache.ReadReq_accesses::cpu.inst 334803995 # number of ReadReq accesses(hits+misses) 689system.cpu.icache.ReadReq_accesses::total 334803995 # number of ReadReq accesses(hits+misses) 690system.cpu.icache.demand_accesses::cpu.inst 334803995 # number of demand (read+write) accesses 691system.cpu.icache.demand_accesses::total 334803995 # number of demand (read+write) accesses 692system.cpu.icache.overall_accesses::cpu.inst 334803995 # number of overall (read+write) accesses 693system.cpu.icache.overall_accesses::total 334803995 # number of overall (read+write) accesses 694system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000094 # miss rate for ReadReq accesses 695system.cpu.icache.ReadReq_miss_rate::total 0.000094 # miss rate for ReadReq accesses 696system.cpu.icache.demand_miss_rate::cpu.inst 0.000094 # miss rate for demand accesses 697system.cpu.icache.demand_miss_rate::total 0.000094 # miss rate for demand accesses 698system.cpu.icache.overall_miss_rate::cpu.inst 0.000094 # miss rate for overall accesses 699system.cpu.icache.overall_miss_rate::total 0.000094 # miss rate for overall accesses 700system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17087.094224 # average ReadReq miss latency 701system.cpu.icache.ReadReq_avg_miss_latency::total 17087.094224 # average ReadReq miss latency 702system.cpu.icache.demand_avg_miss_latency::cpu.inst 17087.094224 # average overall miss latency 703system.cpu.icache.demand_avg_miss_latency::total 17087.094224 # average overall miss latency 704system.cpu.icache.overall_avg_miss_latency::cpu.inst 17087.094224 # average overall miss latency 705system.cpu.icache.overall_avg_miss_latency::total 17087.094224 # average overall miss latency 706system.cpu.icache.blocked_cycles::no_mshrs 1720 # number of cycles access was blocked 707system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 708system.cpu.icache.blocked::no_mshrs 34 # number of cycles access was blocked 709system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 710system.cpu.icache.avg_blocked_cycles::no_mshrs 50.588235 # average number of cycles each access was blocked 711system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 712system.cpu.icache.fast_writes 0 # number of fast writes performed 713system.cpu.icache.cache_copies 0 # number of cache copies performed 714system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2842 # number of ReadReq MSHR hits 715system.cpu.icache.ReadReq_mshr_hits::total 2842 # number of ReadReq MSHR hits 716system.cpu.icache.demand_mshr_hits::cpu.inst 2842 # number of demand (read+write) MSHR hits 717system.cpu.icache.demand_mshr_hits::total 2842 # number of demand (read+write) MSHR hits 718system.cpu.icache.overall_mshr_hits::cpu.inst 2842 # number of overall MSHR hits 719system.cpu.icache.overall_mshr_hits::total 2842 # number of overall MSHR hits 720system.cpu.icache.ReadReq_mshr_misses::cpu.inst 28753 # number of ReadReq MSHR misses 721system.cpu.icache.ReadReq_mshr_misses::total 28753 # number of ReadReq MSHR misses 722system.cpu.icache.demand_mshr_misses::cpu.inst 28753 # number of demand (read+write) MSHR misses 723system.cpu.icache.demand_mshr_misses::total 28753 # number of demand (read+write) MSHR misses 724system.cpu.icache.overall_mshr_misses::cpu.inst 28753 # number of overall MSHR misses 725system.cpu.icache.overall_mshr_misses::total 28753 # number of overall MSHR misses 726system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 429678502 # number of ReadReq MSHR miss cycles 727system.cpu.icache.ReadReq_mshr_miss_latency::total 429678502 # number of ReadReq MSHR miss cycles 728system.cpu.icache.demand_mshr_miss_latency::cpu.inst 429678502 # number of demand (read+write) MSHR miss cycles 729system.cpu.icache.demand_mshr_miss_latency::total 429678502 # number of demand (read+write) MSHR miss cycles 730system.cpu.icache.overall_mshr_miss_latency::cpu.inst 429678502 # number of overall MSHR miss cycles 731system.cpu.icache.overall_mshr_miss_latency::total 429678502 # number of overall MSHR miss cycles 732system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000086 # mshr miss rate for ReadReq accesses 733system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000086 # mshr miss rate for ReadReq accesses 734system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000086 # mshr miss rate for demand accesses 735system.cpu.icache.demand_mshr_miss_rate::total 0.000086 # mshr miss rate for demand accesses 736system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000086 # mshr miss rate for overall accesses 737system.cpu.icache.overall_mshr_miss_rate::total 0.000086 # mshr miss rate for overall accesses 738system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14943.779849 # average ReadReq mshr miss latency 739system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14943.779849 # average ReadReq mshr miss latency 740system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14943.779849 # average overall mshr miss latency 741system.cpu.icache.demand_avg_mshr_miss_latency::total 14943.779849 # average overall mshr miss latency 742system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14943.779849 # average overall mshr miss latency 743system.cpu.icache.overall_avg_mshr_miss_latency::total 14943.779849 # average overall mshr miss latency 744system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 745system.cpu.l2cache.tags.replacements 442191 # number of replacements 746system.cpu.l2cache.tags.tagsinuse 32677.338993 # Cycle average of tags in use 747system.cpu.l2cache.tags.total_refs 1109910 # Total number of references to valid blocks. 748system.cpu.l2cache.tags.sampled_refs 474938 # Sample count of references to valid blocks. 749system.cpu.l2cache.tags.avg_refs 2.336958 # Average number of references to valid blocks. 750system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 751system.cpu.l2cache.tags.occ_blocks::writebacks 1321.185121 # Average occupied blocks per requestor 752system.cpu.l2cache.tags.occ_blocks::cpu.inst 50.537350 # Average occupied blocks per requestor 753system.cpu.l2cache.tags.occ_blocks::cpu.data 31305.616521 # Average occupied blocks per requestor 754system.cpu.l2cache.tags.occ_percent::writebacks 0.040319 # Average percentage of cache occupancy 755system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001542 # Average percentage of cache occupancy 756system.cpu.l2cache.tags.occ_percent::cpu.data 0.955372 # Average percentage of cache occupancy 757system.cpu.l2cache.tags.occ_percent::total 0.997233 # Average percentage of cache occupancy 758system.cpu.l2cache.tags.occ_task_id_blocks::1024 32747 # Occupied blocks per task id 759system.cpu.l2cache.tags.age_task_id_blocks_1024::0 106 # Occupied blocks per task id 760system.cpu.l2cache.tags.age_task_id_blocks_1024::1 154 # Occupied blocks per task id 761system.cpu.l2cache.tags.age_task_id_blocks_1024::2 505 # Occupied blocks per task id 762system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5025 # Occupied blocks per task id 763system.cpu.l2cache.tags.age_task_id_blocks_1024::4 26957 # Occupied blocks per task id 764system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999359 # Percentage of cache occupancy per task id 765system.cpu.l2cache.tags.tag_accesses 13844482 # Number of tag accesses 766system.cpu.l2cache.tags.data_accesses 13844482 # Number of data accesses 767system.cpu.l2cache.ReadReq_hits::cpu.inst 22025 # number of ReadReq hits 768system.cpu.l2cache.ReadReq_hits::cpu.data 1058044 # number of ReadReq hits 769system.cpu.l2cache.ReadReq_hits::total 1080069 # number of ReadReq hits 770system.cpu.l2cache.Writeback_hits::writebacks 96321 # number of Writeback hits 771system.cpu.l2cache.Writeback_hits::total 96321 # number of Writeback hits 772system.cpu.l2cache.UpgradeReq_hits::cpu.data 3 # number of UpgradeReq hits 773system.cpu.l2cache.UpgradeReq_hits::total 3 # number of UpgradeReq hits 774system.cpu.l2cache.ReadExReq_hits::cpu.data 6440 # number of ReadExReq hits 775system.cpu.l2cache.ReadExReq_hits::total 6440 # number of ReadExReq hits 776system.cpu.l2cache.demand_hits::cpu.inst 22025 # number of demand (read+write) hits 777system.cpu.l2cache.demand_hits::cpu.data 1064484 # number of demand (read+write) hits 778system.cpu.l2cache.demand_hits::total 1086509 # number of demand (read+write) hits 779system.cpu.l2cache.overall_hits::cpu.inst 22025 # number of overall hits 780system.cpu.l2cache.overall_hits::cpu.data 1064484 # number of overall hits 781system.cpu.l2cache.overall_hits::total 1086509 # number of overall hits 782system.cpu.l2cache.ReadReq_misses::cpu.inst 2430 # number of ReadReq misses 783system.cpu.l2cache.ReadReq_misses::cpu.data 406492 # number of ReadReq misses 784system.cpu.l2cache.ReadReq_misses::total 408922 # number of ReadReq misses 785system.cpu.l2cache.UpgradeReq_misses::cpu.data 4296 # number of UpgradeReq misses 786system.cpu.l2cache.UpgradeReq_misses::total 4296 # number of UpgradeReq misses 787system.cpu.l2cache.ReadExReq_misses::cpu.data 66077 # number of ReadExReq misses 788system.cpu.l2cache.ReadExReq_misses::total 66077 # number of ReadExReq misses 789system.cpu.l2cache.demand_misses::cpu.inst 2430 # number of demand (read+write) misses 790system.cpu.l2cache.demand_misses::cpu.data 472569 # number of demand (read+write) misses 791system.cpu.l2cache.demand_misses::total 474999 # number of demand (read+write) misses 792system.cpu.l2cache.overall_misses::cpu.inst 2430 # number of overall misses 793system.cpu.l2cache.overall_misses::cpu.data 472569 # number of overall misses 794system.cpu.l2cache.overall_misses::total 474999 # number of overall misses 795system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 176338750 # number of ReadReq miss cycles 796system.cpu.l2cache.ReadReq_miss_latency::cpu.data 30866203500 # number of ReadReq miss cycles 797system.cpu.l2cache.ReadReq_miss_latency::total 31042542250 # number of ReadReq miss cycles 798system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4447510000 # number of ReadExReq miss cycles 799system.cpu.l2cache.ReadExReq_miss_latency::total 4447510000 # number of ReadExReq miss cycles 800system.cpu.l2cache.demand_miss_latency::cpu.inst 176338750 # number of demand (read+write) miss cycles 801system.cpu.l2cache.demand_miss_latency::cpu.data 35313713500 # number of demand (read+write) miss cycles 802system.cpu.l2cache.demand_miss_latency::total 35490052250 # number of demand (read+write) miss cycles 803system.cpu.l2cache.overall_miss_latency::cpu.inst 176338750 # number of overall miss cycles 804system.cpu.l2cache.overall_miss_latency::cpu.data 35313713500 # number of overall miss cycles 805system.cpu.l2cache.overall_miss_latency::total 35490052250 # number of overall miss cycles 806system.cpu.l2cache.ReadReq_accesses::cpu.inst 24455 # number of ReadReq accesses(hits+misses) 807system.cpu.l2cache.ReadReq_accesses::cpu.data 1464536 # number of ReadReq accesses(hits+misses) 808system.cpu.l2cache.ReadReq_accesses::total 1488991 # number of ReadReq accesses(hits+misses) 809system.cpu.l2cache.Writeback_accesses::writebacks 96321 # number of Writeback accesses(hits+misses) 810system.cpu.l2cache.Writeback_accesses::total 96321 # number of Writeback accesses(hits+misses) 811system.cpu.l2cache.UpgradeReq_accesses::cpu.data 4299 # number of UpgradeReq accesses(hits+misses) 812system.cpu.l2cache.UpgradeReq_accesses::total 4299 # number of UpgradeReq accesses(hits+misses) 813system.cpu.l2cache.ReadExReq_accesses::cpu.data 72517 # number of ReadExReq accesses(hits+misses) 814system.cpu.l2cache.ReadExReq_accesses::total 72517 # number of ReadExReq accesses(hits+misses) 815system.cpu.l2cache.demand_accesses::cpu.inst 24455 # number of demand (read+write) accesses 816system.cpu.l2cache.demand_accesses::cpu.data 1537053 # number of demand (read+write) accesses 817system.cpu.l2cache.demand_accesses::total 1561508 # number of demand (read+write) accesses 818system.cpu.l2cache.overall_accesses::cpu.inst 24455 # number of overall (read+write) accesses 819system.cpu.l2cache.overall_accesses::cpu.data 1537053 # number of overall (read+write) accesses 820system.cpu.l2cache.overall_accesses::total 1561508 # number of overall (read+write) accesses 821system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.099366 # miss rate for ReadReq accesses 822system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.277557 # miss rate for ReadReq accesses 823system.cpu.l2cache.ReadReq_miss_rate::total 0.274630 # miss rate for ReadReq accesses 824system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.999302 # miss rate for UpgradeReq accesses 825system.cpu.l2cache.UpgradeReq_miss_rate::total 0.999302 # miss rate for UpgradeReq accesses 826system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.911193 # miss rate for ReadExReq accesses 827system.cpu.l2cache.ReadExReq_miss_rate::total 0.911193 # miss rate for ReadExReq accesses 828system.cpu.l2cache.demand_miss_rate::cpu.inst 0.099366 # miss rate for demand accesses 829system.cpu.l2cache.demand_miss_rate::cpu.data 0.307451 # miss rate for demand accesses 830system.cpu.l2cache.demand_miss_rate::total 0.304192 # miss rate for demand accesses 831system.cpu.l2cache.overall_miss_rate::cpu.inst 0.099366 # miss rate for overall accesses 832system.cpu.l2cache.overall_miss_rate::cpu.data 0.307451 # miss rate for overall accesses 833system.cpu.l2cache.overall_miss_rate::total 0.304192 # miss rate for overall accesses 834system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72567.386831 # average ReadReq miss latency 835system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75933.114305 # average ReadReq miss latency 836system.cpu.l2cache.ReadReq_avg_miss_latency::total 75913.113626 # average ReadReq miss latency 837system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 67307.989164 # average ReadExReq miss latency 838system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67307.989164 # average ReadExReq miss latency 839system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72567.386831 # average overall miss latency 840system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74727.105460 # average overall miss latency 841system.cpu.l2cache.demand_avg_miss_latency::total 74716.056771 # average overall miss latency 842system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72567.386831 # average overall miss latency 843system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74727.105460 # average overall miss latency 844system.cpu.l2cache.overall_avg_miss_latency::total 74716.056771 # average overall miss latency 845system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 846system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 847system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 848system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 849system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 850system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 851system.cpu.l2cache.fast_writes 0 # number of fast writes performed 852system.cpu.l2cache.cache_copies 0 # number of cache copies performed 853system.cpu.l2cache.writebacks::writebacks 66098 # number of writebacks 854system.cpu.l2cache.writebacks::total 66098 # number of writebacks 855system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits 856system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 24 # number of ReadReq MSHR hits 857system.cpu.l2cache.ReadReq_mshr_hits::total 26 # number of ReadReq MSHR hits 858system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits 859system.cpu.l2cache.demand_mshr_hits::cpu.data 24 # number of demand (read+write) MSHR hits 860system.cpu.l2cache.demand_mshr_hits::total 26 # number of demand (read+write) MSHR hits 861system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits 862system.cpu.l2cache.overall_mshr_hits::cpu.data 24 # number of overall MSHR hits 863system.cpu.l2cache.overall_mshr_hits::total 26 # number of overall MSHR hits 864system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2428 # number of ReadReq MSHR misses 865system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 406468 # number of ReadReq MSHR misses 866system.cpu.l2cache.ReadReq_mshr_misses::total 408896 # number of ReadReq MSHR misses 867system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 4296 # number of UpgradeReq MSHR misses 868system.cpu.l2cache.UpgradeReq_mshr_misses::total 4296 # number of UpgradeReq MSHR misses 869system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66077 # number of ReadExReq MSHR misses 870system.cpu.l2cache.ReadExReq_mshr_misses::total 66077 # number of ReadExReq MSHR misses 871system.cpu.l2cache.demand_mshr_misses::cpu.inst 2428 # number of demand (read+write) MSHR misses 872system.cpu.l2cache.demand_mshr_misses::cpu.data 472545 # number of demand (read+write) MSHR misses 873system.cpu.l2cache.demand_mshr_misses::total 474973 # number of demand (read+write) MSHR misses 874system.cpu.l2cache.overall_mshr_misses::cpu.inst 2428 # number of overall MSHR misses 875system.cpu.l2cache.overall_mshr_misses::cpu.data 472545 # number of overall MSHR misses 876system.cpu.l2cache.overall_mshr_misses::total 474973 # number of overall MSHR misses 877system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 145726000 # number of ReadReq MSHR miss cycles 878system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 25804582750 # number of ReadReq MSHR miss cycles 879system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25950308750 # number of ReadReq MSHR miss cycles 880system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 42964296 # number of UpgradeReq MSHR miss cycles 881system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 42964296 # number of UpgradeReq MSHR miss cycles 882system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3615056500 # number of ReadExReq MSHR miss cycles 883system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3615056500 # number of ReadExReq MSHR miss cycles 884system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 145726000 # number of demand (read+write) MSHR miss cycles 885system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 29419639250 # number of demand (read+write) MSHR miss cycles 886system.cpu.l2cache.demand_mshr_miss_latency::total 29565365250 # number of demand (read+write) MSHR miss cycles 887system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 145726000 # number of overall MSHR miss cycles 888system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 29419639250 # number of overall MSHR miss cycles 889system.cpu.l2cache.overall_mshr_miss_latency::total 29565365250 # number of overall MSHR miss cycles 890system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.099284 # mshr miss rate for ReadReq accesses 891system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.277540 # mshr miss rate for ReadReq accesses 892system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.274613 # mshr miss rate for ReadReq accesses 893system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.999302 # mshr miss rate for UpgradeReq accesses 894system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.999302 # mshr miss rate for UpgradeReq accesses 895system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.911193 # mshr miss rate for ReadExReq accesses 896system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.911193 # mshr miss rate for ReadExReq accesses 897system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.099284 # mshr miss rate for demand accesses 898system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.307436 # mshr miss rate for demand accesses 899system.cpu.l2cache.demand_mshr_miss_rate::total 0.304176 # mshr miss rate for demand accesses 900system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.099284 # mshr miss rate for overall accesses 901system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.307436 # mshr miss rate for overall accesses 902system.cpu.l2cache.overall_mshr_miss_rate::total 0.304176 # mshr miss rate for overall accesses 903system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60018.945634 # average ReadReq mshr miss latency 904system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63484.905946 # average ReadReq mshr miss latency 905system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63464.325281 # average ReadReq mshr miss latency 906system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency 907system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency 908system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54709.755286 # average ReadExReq mshr miss latency 909system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54709.755286 # average ReadExReq mshr miss latency 910system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60018.945634 # average overall mshr miss latency 911system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62257.857453 # average overall mshr miss latency 912system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62246.412428 # average overall mshr miss latency 913system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60018.945634 # average overall mshr miss latency 914system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62257.857453 # average overall mshr miss latency 915system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62246.412428 # average overall mshr miss latency 916system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 917system.cpu.dcache.tags.replacements 1532957 # number of replacements 918system.cpu.dcache.tags.tagsinuse 4094.373897 # Cycle average of tags in use 919system.cpu.dcache.tags.total_refs 971355471 # Total number of references to valid blocks. 920system.cpu.dcache.tags.sampled_refs 1537053 # Sample count of references to valid blocks. 921system.cpu.dcache.tags.avg_refs 631.959647 # Average number of references to valid blocks. 922system.cpu.dcache.tags.warmup_cycle 402104250 # Cycle when the warmup percentage was hit. 923system.cpu.dcache.tags.occ_blocks::cpu.data 4094.373897 # Average occupied blocks per requestor 924system.cpu.dcache.tags.occ_percent::cpu.data 0.999603 # Average percentage of cache occupancy 925system.cpu.dcache.tags.occ_percent::total 0.999603 # Average percentage of cache occupancy 926system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 927system.cpu.dcache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id 928system.cpu.dcache.tags.age_task_id_blocks_1024::1 265 # Occupied blocks per task id 929system.cpu.dcache.tags.age_task_id_blocks_1024::2 973 # Occupied blocks per task id 930system.cpu.dcache.tags.age_task_id_blocks_1024::3 2410 # Occupied blocks per task id 931system.cpu.dcache.tags.age_task_id_blocks_1024::4 400 # Occupied blocks per task id 932system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 933system.cpu.dcache.tags.tag_accesses 1949798453 # Number of tag accesses 934system.cpu.dcache.tags.data_accesses 1949798453 # Number of data accesses 935system.cpu.dcache.ReadReq_hits::cpu.data 695221170 # number of ReadReq hits 936system.cpu.dcache.ReadReq_hits::total 695221170 # number of ReadReq hits 937system.cpu.dcache.WriteReq_hits::cpu.data 276100593 # number of WriteReq hits 938system.cpu.dcache.WriteReq_hits::total 276100593 # number of WriteReq hits 939system.cpu.dcache.LoadLockedReq_hits::cpu.data 10000 # number of LoadLockedReq hits 940system.cpu.dcache.LoadLockedReq_hits::total 10000 # number of LoadLockedReq hits 941system.cpu.dcache.StoreCondReq_hits::cpu.data 9985 # number of StoreCondReq hits 942system.cpu.dcache.StoreCondReq_hits::total 9985 # number of StoreCondReq hits 943system.cpu.dcache.demand_hits::cpu.data 971321763 # number of demand (read+write) hits 944system.cpu.dcache.demand_hits::total 971321763 # number of demand (read+write) hits 945system.cpu.dcache.overall_hits::cpu.data 971321763 # number of overall hits 946system.cpu.dcache.overall_hits::total 971321763 # number of overall hits 947system.cpu.dcache.ReadReq_misses::cpu.data 1953864 # number of ReadReq misses 948system.cpu.dcache.ReadReq_misses::total 1953864 # number of ReadReq misses 949system.cpu.dcache.WriteReq_misses::cpu.data 835085 # number of WriteReq misses 950system.cpu.dcache.WriteReq_misses::total 835085 # number of WriteReq misses 951system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses 952system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses 953system.cpu.dcache.demand_misses::cpu.data 2788949 # number of demand (read+write) misses 954system.cpu.dcache.demand_misses::total 2788949 # number of demand (read+write) misses 955system.cpu.dcache.overall_misses::cpu.data 2788949 # number of overall misses 956system.cpu.dcache.overall_misses::total 2788949 # number of overall misses 957system.cpu.dcache.ReadReq_miss_latency::cpu.data 82025897599 # number of ReadReq miss cycles 958system.cpu.dcache.ReadReq_miss_latency::total 82025897599 # number of ReadReq miss cycles 959system.cpu.dcache.WriteReq_miss_latency::cpu.data 54715114042 # number of WriteReq miss cycles 960system.cpu.dcache.WriteReq_miss_latency::total 54715114042 # number of WriteReq miss cycles 961system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 225000 # number of LoadLockedReq miss cycles 962system.cpu.dcache.LoadLockedReq_miss_latency::total 225000 # number of LoadLockedReq miss cycles 963system.cpu.dcache.demand_miss_latency::cpu.data 136741011641 # number of demand (read+write) miss cycles 964system.cpu.dcache.demand_miss_latency::total 136741011641 # number of demand (read+write) miss cycles 965system.cpu.dcache.overall_miss_latency::cpu.data 136741011641 # number of overall miss cycles 966system.cpu.dcache.overall_miss_latency::total 136741011641 # number of overall miss cycles 967system.cpu.dcache.ReadReq_accesses::cpu.data 697175034 # number of ReadReq accesses(hits+misses) 968system.cpu.dcache.ReadReq_accesses::total 697175034 # number of ReadReq accesses(hits+misses) 969system.cpu.dcache.WriteReq_accesses::cpu.data 276935678 # number of WriteReq accesses(hits+misses) 970system.cpu.dcache.WriteReq_accesses::total 276935678 # number of WriteReq accesses(hits+misses) 971system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10003 # number of LoadLockedReq accesses(hits+misses) 972system.cpu.dcache.LoadLockedReq_accesses::total 10003 # number of LoadLockedReq accesses(hits+misses) 973system.cpu.dcache.StoreCondReq_accesses::cpu.data 9985 # number of StoreCondReq accesses(hits+misses) 974system.cpu.dcache.StoreCondReq_accesses::total 9985 # number of StoreCondReq accesses(hits+misses) 975system.cpu.dcache.demand_accesses::cpu.data 974110712 # number of demand (read+write) accesses 976system.cpu.dcache.demand_accesses::total 974110712 # number of demand (read+write) accesses 977system.cpu.dcache.overall_accesses::cpu.data 974110712 # number of overall (read+write) accesses 978system.cpu.dcache.overall_accesses::total 974110712 # number of overall (read+write) accesses 979system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002803 # miss rate for ReadReq accesses 980system.cpu.dcache.ReadReq_miss_rate::total 0.002803 # miss rate for ReadReq accesses 981system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003015 # miss rate for WriteReq accesses 982system.cpu.dcache.WriteReq_miss_rate::total 0.003015 # miss rate for WriteReq accesses 983system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000300 # miss rate for LoadLockedReq accesses 984system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000300 # miss rate for LoadLockedReq accesses 985system.cpu.dcache.demand_miss_rate::cpu.data 0.002863 # miss rate for demand accesses 986system.cpu.dcache.demand_miss_rate::total 0.002863 # miss rate for demand accesses 987system.cpu.dcache.overall_miss_rate::cpu.data 0.002863 # miss rate for overall accesses 988system.cpu.dcache.overall_miss_rate::total 0.002863 # miss rate for overall accesses 989system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 41981.375162 # average ReadReq miss latency 990system.cpu.dcache.ReadReq_avg_miss_latency::total 41981.375162 # average ReadReq miss latency 991system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65520.412942 # average WriteReq miss latency 992system.cpu.dcache.WriteReq_avg_miss_latency::total 65520.412942 # average WriteReq miss latency 993system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 75000 # average LoadLockedReq miss latency 994system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 75000 # average LoadLockedReq miss latency 995system.cpu.dcache.demand_avg_miss_latency::cpu.data 49029.584851 # average overall miss latency 996system.cpu.dcache.demand_avg_miss_latency::total 49029.584851 # average overall miss latency 997system.cpu.dcache.overall_avg_miss_latency::cpu.data 49029.584851 # average overall miss latency 998system.cpu.dcache.overall_avg_miss_latency::total 49029.584851 # average overall miss latency 999system.cpu.dcache.blocked_cycles::no_mshrs 2327 # number of cycles access was blocked 1000system.cpu.dcache.blocked_cycles::no_targets 933 # number of cycles access was blocked 1001system.cpu.dcache.blocked::no_mshrs 51 # number of cycles access was blocked 1002system.cpu.dcache.blocked::no_targets 89 # number of cycles access was blocked 1003system.cpu.dcache.avg_blocked_cycles::no_mshrs 45.627451 # average number of cycles each access was blocked 1004system.cpu.dcache.avg_blocked_cycles::no_targets 10.483146 # average number of cycles each access was blocked 1005system.cpu.dcache.fast_writes 0 # number of fast writes performed 1006system.cpu.dcache.cache_copies 0 # number of cache copies performed 1007system.cpu.dcache.writebacks::writebacks 96321 # number of writebacks 1008system.cpu.dcache.writebacks::total 96321 # number of writebacks 1009system.cpu.dcache.ReadReq_mshr_hits::cpu.data 489326 # number of ReadReq MSHR hits 1010system.cpu.dcache.ReadReq_mshr_hits::total 489326 # number of ReadReq MSHR hits 1011system.cpu.dcache.WriteReq_mshr_hits::cpu.data 758271 # number of WriteReq MSHR hits 1012system.cpu.dcache.WriteReq_mshr_hits::total 758271 # number of WriteReq MSHR hits 1013system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits 1014system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits 1015system.cpu.dcache.demand_mshr_hits::cpu.data 1247597 # number of demand (read+write) MSHR hits 1016system.cpu.dcache.demand_mshr_hits::total 1247597 # number of demand (read+write) MSHR hits 1017system.cpu.dcache.overall_mshr_hits::cpu.data 1247597 # number of overall MSHR hits 1018system.cpu.dcache.overall_mshr_hits::total 1247597 # number of overall MSHR hits 1019system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1464538 # number of ReadReq MSHR misses 1020system.cpu.dcache.ReadReq_mshr_misses::total 1464538 # number of ReadReq MSHR misses 1021system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76814 # number of WriteReq MSHR misses 1022system.cpu.dcache.WriteReq_mshr_misses::total 76814 # number of WriteReq MSHR misses 1023system.cpu.dcache.demand_mshr_misses::cpu.data 1541352 # number of demand (read+write) MSHR misses 1024system.cpu.dcache.demand_mshr_misses::total 1541352 # number of demand (read+write) MSHR misses 1025system.cpu.dcache.overall_mshr_misses::cpu.data 1541352 # number of overall MSHR misses 1026system.cpu.dcache.overall_mshr_misses::total 1541352 # number of overall MSHR misses 1027system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 42911632024 # number of ReadReq MSHR miss cycles 1028system.cpu.dcache.ReadReq_mshr_miss_latency::total 42911632024 # number of ReadReq MSHR miss cycles 1029system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4684436204 # number of WriteReq MSHR miss cycles 1030system.cpu.dcache.WriteReq_mshr_miss_latency::total 4684436204 # number of WriteReq MSHR miss cycles 1031system.cpu.dcache.demand_mshr_miss_latency::cpu.data 47596068228 # number of demand (read+write) MSHR miss cycles 1032system.cpu.dcache.demand_mshr_miss_latency::total 47596068228 # number of demand (read+write) MSHR miss cycles 1033system.cpu.dcache.overall_mshr_miss_latency::cpu.data 47596068228 # number of overall MSHR miss cycles 1034system.cpu.dcache.overall_mshr_miss_latency::total 47596068228 # number of overall MSHR miss cycles 1035system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002101 # mshr miss rate for ReadReq accesses 1036system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002101 # mshr miss rate for ReadReq accesses 1037system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000277 # mshr miss rate for WriteReq accesses 1038system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000277 # mshr miss rate for WriteReq accesses 1039system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001582 # mshr miss rate for demand accesses 1040system.cpu.dcache.demand_mshr_miss_rate::total 0.001582 # mshr miss rate for demand accesses 1041system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001582 # mshr miss rate for overall accesses 1042system.cpu.dcache.overall_mshr_miss_rate::total 0.001582 # mshr miss rate for overall accesses 1043system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29300.456543 # average ReadReq mshr miss latency 1044system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29300.456543 # average ReadReq mshr miss latency 1045system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 60984.146171 # average WriteReq mshr miss latency 1046system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 60984.146171 # average WriteReq mshr miss latency 1047system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30879.428079 # average overall mshr miss latency 1048system.cpu.dcache.demand_avg_mshr_miss_latency::total 30879.428079 # average overall mshr miss latency 1049system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30879.428079 # average overall mshr miss latency 1050system.cpu.dcache.overall_avg_mshr_miss_latency::total 30879.428079 # average overall mshr miss latency 1051system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1052 1053---------- End Simulation Statistics ---------- 1054