stats.txt revision 11507
111507SCurtis.Dunham@arm.com 211507SCurtis.Dunham@arm.com---------- Begin Simulation Statistics ---------- 311507SCurtis.Dunham@arm.comsim_seconds 0.326731 # Number of seconds simulated 411507SCurtis.Dunham@arm.comsim_ticks 326731324000 # Number of ticks simulated 511507SCurtis.Dunham@arm.comfinal_tick 326731324000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 611507SCurtis.Dunham@arm.comsim_freq 1000000000000 # Frequency of simulated ticks 711507SCurtis.Dunham@arm.comhost_inst_rate 120212 # Simulator instruction rate (inst/s) 811507SCurtis.Dunham@arm.comhost_op_rate 147997 # Simulator op (including micro ops) rate (op/s) 911507SCurtis.Dunham@arm.comhost_tick_rate 61308199 # Simulator tick rate (ticks/s) 1011507SCurtis.Dunham@arm.comhost_mem_usage 272964 # Number of bytes of host memory used 1111507SCurtis.Dunham@arm.comhost_seconds 5329.33 # Real time elapsed on the host 1211507SCurtis.Dunham@arm.comsim_insts 640649299 # Number of instructions simulated 1311507SCurtis.Dunham@arm.comsim_ops 788724958 # Number of ops (including micro ops) simulated 1411507SCurtis.Dunham@arm.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1511507SCurtis.Dunham@arm.comsystem.clk_domain.clock 1000 # Clock period in ticks 1611507SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu.inst 227072 # Number of bytes read from this memory 1711507SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu.data 47957824 # Number of bytes read from this memory 1811507SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu.l2cache.prefetcher 12822400 # Number of bytes read from this memory 1911507SCurtis.Dunham@arm.comsystem.physmem.bytes_read::total 61007296 # Number of bytes read from this memory 2011507SCurtis.Dunham@arm.comsystem.physmem.bytes_inst_read::cpu.inst 227072 # Number of instructions bytes read from this memory 2111507SCurtis.Dunham@arm.comsystem.physmem.bytes_inst_read::total 227072 # Number of instructions bytes read from this memory 2211507SCurtis.Dunham@arm.comsystem.physmem.bytes_written::writebacks 4245376 # Number of bytes written to this memory 2311507SCurtis.Dunham@arm.comsystem.physmem.bytes_written::total 4245376 # Number of bytes written to this memory 2411507SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu.inst 3548 # Number of read requests responded to by this memory 2511507SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu.data 749341 # Number of read requests responded to by this memory 2611507SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu.l2cache.prefetcher 200350 # Number of read requests responded to by this memory 2711507SCurtis.Dunham@arm.comsystem.physmem.num_reads::total 953239 # Number of read requests responded to by this memory 2811507SCurtis.Dunham@arm.comsystem.physmem.num_writes::writebacks 66334 # Number of write requests responded to by this memory 2911507SCurtis.Dunham@arm.comsystem.physmem.num_writes::total 66334 # Number of write requests responded to by this memory 3011507SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu.inst 694981 # Total read bandwidth from this memory (bytes/s) 3111507SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu.data 146780613 # Total read bandwidth from this memory (bytes/s) 3211507SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu.l2cache.prefetcher 39244477 # Total read bandwidth from this memory (bytes/s) 3311507SCurtis.Dunham@arm.comsystem.physmem.bw_read::total 186720071 # Total read bandwidth from this memory (bytes/s) 3411507SCurtis.Dunham@arm.comsystem.physmem.bw_inst_read::cpu.inst 694981 # Instruction read bandwidth from this memory (bytes/s) 3511507SCurtis.Dunham@arm.comsystem.physmem.bw_inst_read::total 694981 # Instruction read bandwidth from this memory (bytes/s) 3611507SCurtis.Dunham@arm.comsystem.physmem.bw_write::writebacks 12993477 # Write bandwidth from this memory (bytes/s) 3711507SCurtis.Dunham@arm.comsystem.physmem.bw_write::total 12993477 # Write bandwidth from this memory (bytes/s) 3811507SCurtis.Dunham@arm.comsystem.physmem.bw_total::writebacks 12993477 # Total bandwidth to/from this memory (bytes/s) 3911507SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu.inst 694981 # Total bandwidth to/from this memory (bytes/s) 4011507SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu.data 146780613 # Total bandwidth to/from this memory (bytes/s) 4111507SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu.l2cache.prefetcher 39244477 # Total bandwidth to/from this memory (bytes/s) 4211507SCurtis.Dunham@arm.comsystem.physmem.bw_total::total 199713548 # Total bandwidth to/from this memory (bytes/s) 4311507SCurtis.Dunham@arm.comsystem.physmem.readReqs 953240 # Number of read requests accepted 4411507SCurtis.Dunham@arm.comsystem.physmem.writeReqs 66334 # Number of write requests accepted 4511507SCurtis.Dunham@arm.comsystem.physmem.readBursts 953240 # Number of DRAM read bursts, including those serviced by the write queue 4611507SCurtis.Dunham@arm.comsystem.physmem.writeBursts 66334 # Number of DRAM write bursts, including those merged in the write queue 4711507SCurtis.Dunham@arm.comsystem.physmem.bytesReadDRAM 60987072 # Total number of bytes read from DRAM 4811507SCurtis.Dunham@arm.comsystem.physmem.bytesReadWrQ 20288 # Total number of bytes read from write queue 4911507SCurtis.Dunham@arm.comsystem.physmem.bytesWritten 4240192 # Total number of bytes written to DRAM 5011507SCurtis.Dunham@arm.comsystem.physmem.bytesReadSys 61007360 # Total read bytes from the system interface side 5111507SCurtis.Dunham@arm.comsystem.physmem.bytesWrittenSys 4245376 # Total written bytes from the system interface side 5211507SCurtis.Dunham@arm.comsystem.physmem.servicedByWrQ 317 # Number of DRAM read bursts serviced by the write queue 5311507SCurtis.Dunham@arm.comsystem.physmem.mergedWrBursts 64 # Number of DRAM write bursts merged with an existing one 5411507SCurtis.Dunham@arm.comsystem.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 5511507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::0 19685 # Per bank write bursts 5611507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::1 19287 # Per bank write bursts 5711507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::2 657567 # Per bank write bursts 5811507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::3 20052 # Per bank write bursts 5911507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::4 19480 # Per bank write bursts 6011507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::5 20770 # Per bank write bursts 6111507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::6 19386 # Per bank write bursts 6211507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::7 19760 # Per bank write bursts 6311507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::8 19321 # Per bank write bursts 6411507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::9 19768 # Per bank write bursts 6511507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::10 19303 # Per bank write bursts 6611507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::11 19444 # Per bank write bursts 6711507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::12 19433 # Per bank write bursts 6811507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::13 20871 # Per bank write bursts 6911507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::14 19269 # Per bank write bursts 7011507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::15 19527 # Per bank write bursts 7111507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::0 4288 # Per bank write bursts 7211507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::1 4110 # Per bank write bursts 7311507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::2 4140 # Per bank write bursts 7411507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::3 4154 # Per bank write bursts 7511507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::4 4242 # Per bank write bursts 7611507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::5 4232 # Per bank write bursts 7711507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::6 4174 # Per bank write bursts 7811507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::7 4096 # Per bank write bursts 7911507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::8 4095 # Per bank write bursts 8011507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::9 4095 # Per bank write bursts 8111507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::10 4095 # Per bank write bursts 8211507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::11 4097 # Per bank write bursts 8311507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::12 4098 # Per bank write bursts 8411507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::13 4095 # Per bank write bursts 8511507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::14 4096 # Per bank write bursts 8611507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::15 4146 # Per bank write bursts 8711507SCurtis.Dunham@arm.comsystem.physmem.numRdRetry 0 # Number of times read queue was full causing retry 8811507SCurtis.Dunham@arm.comsystem.physmem.numWrRetry 0 # Number of times write queue was full causing retry 8911507SCurtis.Dunham@arm.comsystem.physmem.totGap 326731313500 # Total gap between requests 9011507SCurtis.Dunham@arm.comsystem.physmem.readPktSize::0 0 # Read request sizes (log2) 9111507SCurtis.Dunham@arm.comsystem.physmem.readPktSize::1 0 # Read request sizes (log2) 9211507SCurtis.Dunham@arm.comsystem.physmem.readPktSize::2 0 # Read request sizes (log2) 9311507SCurtis.Dunham@arm.comsystem.physmem.readPktSize::3 0 # Read request sizes (log2) 9411507SCurtis.Dunham@arm.comsystem.physmem.readPktSize::4 0 # Read request sizes (log2) 9511507SCurtis.Dunham@arm.comsystem.physmem.readPktSize::5 0 # Read request sizes (log2) 9611507SCurtis.Dunham@arm.comsystem.physmem.readPktSize::6 953240 # Read request sizes (log2) 9711507SCurtis.Dunham@arm.comsystem.physmem.writePktSize::0 0 # Write request sizes (log2) 9811507SCurtis.Dunham@arm.comsystem.physmem.writePktSize::1 0 # Write request sizes (log2) 9911507SCurtis.Dunham@arm.comsystem.physmem.writePktSize::2 0 # Write request sizes (log2) 10011507SCurtis.Dunham@arm.comsystem.physmem.writePktSize::3 0 # Write request sizes (log2) 10111507SCurtis.Dunham@arm.comsystem.physmem.writePktSize::4 0 # Write request sizes (log2) 10211507SCurtis.Dunham@arm.comsystem.physmem.writePktSize::5 0 # Write request sizes (log2) 10311507SCurtis.Dunham@arm.comsystem.physmem.writePktSize::6 66334 # Write request sizes (log2) 10411507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::0 759877 # What read queue length does an incoming req see 10511507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::1 120823 # What read queue length does an incoming req see 10611507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::2 14314 # What read queue length does an incoming req see 10711507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::3 6736 # What read queue length does an incoming req see 10811507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::4 6450 # What read queue length does an incoming req see 10911507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::5 7728 # What read queue length does an incoming req see 11011507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::6 8758 # What read queue length does an incoming req see 11111507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::7 9260 # What read queue length does an incoming req see 11211507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::8 8005 # What read queue length does an incoming req see 11311507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::9 3769 # What read queue length does an incoming req see 11411507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::10 2825 # What read queue length does an incoming req see 11511507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::11 2023 # What read queue length does an incoming req see 11611507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::12 1473 # What read queue length does an incoming req see 11711507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::13 882 # What read queue length does an incoming req see 11811507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 11911507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 12011507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 12111507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 12211507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 12311507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 12411507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 12511507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 12611507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 12711507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 12811507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 12911507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 13011507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 13111507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 13211507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 13311507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 13411507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 13511507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 13611507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 13711507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 13811507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 13911507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 14011507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 14111507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 14211507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 14311507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 14411507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 14511507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 14611507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 14711507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 14811507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 14911507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 15011507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 15111507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::15 576 # What write queue length does an incoming req see 15211507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::16 601 # What write queue length does an incoming req see 15311507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::17 1013 # What write queue length does an incoming req see 15411507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::18 1770 # What write queue length does an incoming req see 15511507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::19 2625 # What write queue length does an incoming req see 15611507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::20 3363 # What write queue length does an incoming req see 15711507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::21 3862 # What write queue length does an incoming req see 15811507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::22 4189 # What write queue length does an incoming req see 15911507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::23 4478 # What write queue length does an incoming req see 16011507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::24 4705 # What write queue length does an incoming req see 16111507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::25 4914 # What write queue length does an incoming req see 16211507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::26 5084 # What write queue length does an incoming req see 16311507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::27 5227 # What write queue length does an incoming req see 16411507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::28 5048 # What write queue length does an incoming req see 16511507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::29 4894 # What write queue length does an incoming req see 16611507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::30 4176 # What write queue length does an incoming req see 16711507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::31 4054 # What write queue length does an incoming req see 16811507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::32 4028 # What write queue length does an incoming req see 16911507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::33 114 # What write queue length does an incoming req see 17011507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::34 102 # What write queue length does an incoming req see 17111507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::35 85 # What write queue length does an incoming req see 17211507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::36 81 # What write queue length does an incoming req see 17311507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::37 85 # What write queue length does an incoming req see 17411507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::38 81 # What write queue length does an incoming req see 17511507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::39 80 # What write queue length does an incoming req see 17611507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::40 97 # What write queue length does an incoming req see 17711507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::41 86 # What write queue length does an incoming req see 17811507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::42 82 # What write queue length does an incoming req see 17911507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::43 75 # What write queue length does an incoming req see 18011507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::44 71 # What write queue length does an incoming req see 18111507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::45 72 # What write queue length does an incoming req see 18211507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::46 71 # What write queue length does an incoming req see 18311507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::47 64 # What write queue length does an incoming req see 18411507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::48 66 # What write queue length does an incoming req see 18511507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::49 58 # What write queue length does an incoming req see 18611507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::50 65 # What write queue length does an incoming req see 18711507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::51 53 # What write queue length does an incoming req see 18811507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::52 52 # What write queue length does an incoming req see 18911507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::53 44 # What write queue length does an incoming req see 19011507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::54 42 # What write queue length does an incoming req see 19111507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::55 19 # What write queue length does an incoming req see 19211507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::56 3 # What write queue length does an incoming req see 19311507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 19411507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 19511507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 19611507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 19711507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 19811507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 19911507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 20011507SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::samples 187141 # Bytes accessed per row activation 20111507SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::mean 348.533437 # Bytes accessed per row activation 20211507SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::gmean 199.264052 # Bytes accessed per row activation 20311507SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::stdev 368.938471 # Bytes accessed per row activation 20411507SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::0-127 57976 30.98% 30.98% # Bytes accessed per row activation 20511507SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::128-255 60329 32.24% 63.22% # Bytes accessed per row activation 20611507SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::256-383 15964 8.53% 71.75% # Bytes accessed per row activation 20711507SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::384-511 2811 1.50% 73.25% # Bytes accessed per row activation 20811507SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::512-639 2834 1.51% 74.76% # Bytes accessed per row activation 20911507SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::640-767 2850 1.52% 76.29% # Bytes accessed per row activation 21011507SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::768-895 2680 1.43% 77.72% # Bytes accessed per row activation 21111507SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::896-1023 20043 10.71% 88.43% # Bytes accessed per row activation 21211507SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::1024-1151 21654 11.57% 100.00% # Bytes accessed per row activation 21311507SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::total 187141 # Bytes accessed per row activation 21411507SCurtis.Dunham@arm.comsystem.physmem.rdPerTurnAround::samples 4039 # Reads before turning the bus around for writes 21511507SCurtis.Dunham@arm.comsystem.physmem.rdPerTurnAround::mean 232.424858 # Reads before turning the bus around for writes 21611507SCurtis.Dunham@arm.comsystem.physmem.rdPerTurnAround::gmean 40.579593 # Reads before turning the bus around for writes 21711507SCurtis.Dunham@arm.comsystem.physmem.rdPerTurnAround::stdev 3031.486386 # Reads before turning the bus around for writes 21811507SCurtis.Dunham@arm.comsystem.physmem.rdPerTurnAround::0-4095 4013 99.36% 99.36% # Reads before turning the bus around for writes 21911507SCurtis.Dunham@arm.comsystem.physmem.rdPerTurnAround::4096-8191 12 0.30% 99.65% # Reads before turning the bus around for writes 22011507SCurtis.Dunham@arm.comsystem.physmem.rdPerTurnAround::8192-12287 1 0.02% 99.68% # Reads before turning the bus around for writes 22111507SCurtis.Dunham@arm.comsystem.physmem.rdPerTurnAround::12288-16383 4 0.10% 99.78% # Reads before turning the bus around for writes 22211507SCurtis.Dunham@arm.comsystem.physmem.rdPerTurnAround::16384-20479 4 0.10% 99.88% # Reads before turning the bus around for writes 22311507SCurtis.Dunham@arm.comsystem.physmem.rdPerTurnAround::24576-28671 1 0.02% 99.90% # Reads before turning the bus around for writes 22411507SCurtis.Dunham@arm.comsystem.physmem.rdPerTurnAround::53248-57343 1 0.02% 99.93% # Reads before turning the bus around for writes 22511507SCurtis.Dunham@arm.comsystem.physmem.rdPerTurnAround::57344-61439 1 0.02% 99.95% # Reads before turning the bus around for writes 22611507SCurtis.Dunham@arm.comsystem.physmem.rdPerTurnAround::106496-110591 1 0.02% 99.98% # Reads before turning the bus around for writes 22711507SCurtis.Dunham@arm.comsystem.physmem.rdPerTurnAround::118784-122879 1 0.02% 100.00% # Reads before turning the bus around for writes 22811507SCurtis.Dunham@arm.comsystem.physmem.rdPerTurnAround::total 4039 # Reads before turning the bus around for writes 22911507SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::samples 4039 # Writes before turning the bus around for reads 23011507SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::mean 16.403318 # Writes before turning the bus around for reads 23111507SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::gmean 16.369585 # Writes before turning the bus around for reads 23211507SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::stdev 1.145225 # Writes before turning the bus around for reads 23311507SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::16 3419 84.65% 84.65% # Writes before turning the bus around for reads 23411507SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::17 15 0.37% 85.02% # Writes before turning the bus around for reads 23511507SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::18 455 11.27% 96.29% # Writes before turning the bus around for reads 23611507SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::19 68 1.68% 97.97% # Writes before turning the bus around for reads 23711507SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::20 26 0.64% 98.61% # Writes before turning the bus around for reads 23811507SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::21 15 0.37% 98.98% # Writes before turning the bus around for reads 23911507SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::22 15 0.37% 99.36% # Writes before turning the bus around for reads 24011507SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::23 7 0.17% 99.53% # Writes before turning the bus around for reads 24111507SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::24 9 0.22% 99.75% # Writes before turning the bus around for reads 24211507SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::25 4 0.10% 99.85% # Writes before turning the bus around for reads 24311507SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::27 3 0.07% 99.93% # Writes before turning the bus around for reads 24411507SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::28 1 0.02% 99.95% # Writes before turning the bus around for reads 24511507SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::29 1 0.02% 99.98% # Writes before turning the bus around for reads 24611507SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::32 1 0.02% 100.00% # Writes before turning the bus around for reads 24711507SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::total 4039 # Writes before turning the bus around for reads 24811507SCurtis.Dunham@arm.comsystem.physmem.totQLat 12733277648 # Total ticks spent queuing 24911507SCurtis.Dunham@arm.comsystem.physmem.totMemAccLat 30600583898 # Total ticks spent from burst creation until serviced by the DRAM 25011507SCurtis.Dunham@arm.comsystem.physmem.totBusLat 4764615000 # Total ticks spent in databus transfers 25111507SCurtis.Dunham@arm.comsystem.physmem.avgQLat 13362.34 # Average queueing delay per DRAM burst 25211507SCurtis.Dunham@arm.comsystem.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 25311507SCurtis.Dunham@arm.comsystem.physmem.avgMemAccLat 32112.34 # Average memory access latency per DRAM burst 25411507SCurtis.Dunham@arm.comsystem.physmem.avgRdBW 186.66 # Average DRAM read bandwidth in MiByte/s 25511507SCurtis.Dunham@arm.comsystem.physmem.avgWrBW 12.98 # Average achieved write bandwidth in MiByte/s 25611507SCurtis.Dunham@arm.comsystem.physmem.avgRdBWSys 186.72 # Average system read bandwidth in MiByte/s 25711507SCurtis.Dunham@arm.comsystem.physmem.avgWrBWSys 12.99 # Average system write bandwidth in MiByte/s 25811507SCurtis.Dunham@arm.comsystem.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 25911507SCurtis.Dunham@arm.comsystem.physmem.busUtil 1.56 # Data bus utilization in percentage 26011507SCurtis.Dunham@arm.comsystem.physmem.busUtilRead 1.46 # Data bus utilization in percentage for reads 26111507SCurtis.Dunham@arm.comsystem.physmem.busUtilWrite 0.10 # Data bus utilization in percentage for writes 26211507SCurtis.Dunham@arm.comsystem.physmem.avgRdQLen 1.09 # Average read queue length when enqueuing 26311507SCurtis.Dunham@arm.comsystem.physmem.avgWrQLen 25.20 # Average write queue length when enqueuing 26411507SCurtis.Dunham@arm.comsystem.physmem.readRowHits 805882 # Number of row buffer hits during reads 26511507SCurtis.Dunham@arm.comsystem.physmem.writeRowHits 26140 # Number of row buffer hits during writes 26611507SCurtis.Dunham@arm.comsystem.physmem.readRowHitRate 84.57 # Row buffer hit rate for reads 26711507SCurtis.Dunham@arm.comsystem.physmem.writeRowHitRate 39.44 # Row buffer hit rate for writes 26811507SCurtis.Dunham@arm.comsystem.physmem.avgGap 320458.66 # Average gap between requests 26911507SCurtis.Dunham@arm.comsystem.physmem.pageHitRate 81.64 # Row buffer hit rate, read and write combined 27011507SCurtis.Dunham@arm.comsystem.physmem_0.actEnergy 905544360 # Energy for activate commands per rank (pJ) 27111507SCurtis.Dunham@arm.comsystem.physmem_0.preEnergy 494096625 # Energy for precharge commands per rank (pJ) 27211507SCurtis.Dunham@arm.comsystem.physmem_0.readEnergy 6208534800 # Energy for read commands per rank (pJ) 27311507SCurtis.Dunham@arm.comsystem.physmem_0.writeEnergy 216665280 # Energy for write commands per rank (pJ) 27411507SCurtis.Dunham@arm.comsystem.physmem_0.refreshEnergy 21340194720 # Energy for refresh commands per rank (pJ) 27511507SCurtis.Dunham@arm.comsystem.physmem_0.actBackEnergy 220053154905 # Energy for active background per rank (pJ) 27611507SCurtis.Dunham@arm.comsystem.physmem_0.preBackEnergy 3007065000 # Energy for precharge background per rank (pJ) 27711507SCurtis.Dunham@arm.comsystem.physmem_0.totalEnergy 252225255690 # Total energy per rank (pJ) 27811507SCurtis.Dunham@arm.comsystem.physmem_0.averagePower 771.975754 # Core power per rank (mW) 27911507SCurtis.Dunham@arm.comsystem.physmem_0.memoryStateTime::IDLE 3732596290 # Time in different power states 28011507SCurtis.Dunham@arm.comsystem.physmem_0.memoryStateTime::REF 10910120000 # Time in different power states 28111507SCurtis.Dunham@arm.comsystem.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 28211507SCurtis.Dunham@arm.comsystem.physmem_0.memoryStateTime::ACT 312084210210 # Time in different power states 28311507SCurtis.Dunham@arm.comsystem.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 28411507SCurtis.Dunham@arm.comsystem.physmem_1.actEnergy 509143320 # Energy for activate commands per rank (pJ) 28511507SCurtis.Dunham@arm.comsystem.physmem_1.preEnergy 277806375 # Energy for precharge commands per rank (pJ) 28611507SCurtis.Dunham@arm.comsystem.physmem_1.readEnergy 1223765400 # Energy for read commands per rank (pJ) 28711507SCurtis.Dunham@arm.comsystem.physmem_1.writeEnergy 212654160 # Energy for write commands per rank (pJ) 28811507SCurtis.Dunham@arm.comsystem.physmem_1.refreshEnergy 21340194720 # Energy for refresh commands per rank (pJ) 28911507SCurtis.Dunham@arm.comsystem.physmem_1.actBackEnergy 86358123315 # Energy for active background per rank (pJ) 29011507SCurtis.Dunham@arm.comsystem.physmem_1.preBackEnergy 120283389750 # Energy for precharge background per rank (pJ) 29111507SCurtis.Dunham@arm.comsystem.physmem_1.totalEnergy 230205077040 # Total energy per rank (pJ) 29211507SCurtis.Dunham@arm.comsystem.physmem_1.averagePower 704.579541 # Core power per rank (mW) 29311507SCurtis.Dunham@arm.comsystem.physmem_1.memoryStateTime::IDLE 199538723813 # Time in different power states 29411507SCurtis.Dunham@arm.comsystem.physmem_1.memoryStateTime::REF 10910120000 # Time in different power states 29511507SCurtis.Dunham@arm.comsystem.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 29611507SCurtis.Dunham@arm.comsystem.physmem_1.memoryStateTime::ACT 116279470187 # Time in different power states 29711507SCurtis.Dunham@arm.comsystem.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 29811507SCurtis.Dunham@arm.comsystem.cpu.branchPred.lookups 174663372 # Number of BP lookups 29911507SCurtis.Dunham@arm.comsystem.cpu.branchPred.condPredicted 119116658 # Number of conditional branches predicted 30011507SCurtis.Dunham@arm.comsystem.cpu.branchPred.condIncorrect 4015834 # Number of conditional branches incorrect 30111507SCurtis.Dunham@arm.comsystem.cpu.branchPred.BTBLookups 96720842 # Number of BTB lookups 30211507SCurtis.Dunham@arm.comsystem.cpu.branchPred.BTBHits 67756635 # Number of BTB hits 30311507SCurtis.Dunham@arm.comsystem.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 30411507SCurtis.Dunham@arm.comsystem.cpu.branchPred.BTBHitPct 70.053810 # BTB Hit Percentage 30511507SCurtis.Dunham@arm.comsystem.cpu.branchPred.usedRAS 18785000 # Number of times the RAS was used to get a target. 30611507SCurtis.Dunham@arm.comsystem.cpu.branchPred.RASInCorrect 1299597 # Number of incorrect RAS predictions. 30711507SCurtis.Dunham@arm.comsystem.cpu.branchPred.indirectLookups 16716087 # Number of indirect predictor lookups. 30811507SCurtis.Dunham@arm.comsystem.cpu.branchPred.indirectHits 16701520 # Number of indirect target hits. 30911507SCurtis.Dunham@arm.comsystem.cpu.branchPred.indirectMisses 14567 # Number of indirect misses. 31011507SCurtis.Dunham@arm.comsystem.cpu.branchPredindirectMispredicted 1279491 # Number of mispredicted indirect branches. 31111507SCurtis.Dunham@arm.comsystem.cpu_clk_domain.clock 500 # Clock period in ticks 31211507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 31311507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 31411507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 31511507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 31611507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 31711507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 31811507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 31911507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 32011507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 32111507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 32211507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 32311507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 32411507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 32511507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 32611507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 32711507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 32811507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 32911507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 33011507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 33111507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 33211507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 33311507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 33411507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 33511507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 33611507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 33711507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 33811507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 33911507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 34011507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 34111507SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walks 0 # Table walker walks requested 34211507SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 34311507SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 34411507SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 34511507SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 34611507SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 34711507SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 34811507SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 34911507SCurtis.Dunham@arm.comsystem.cpu.dtb.inst_hits 0 # ITB inst hits 35011507SCurtis.Dunham@arm.comsystem.cpu.dtb.inst_misses 0 # ITB inst misses 35111507SCurtis.Dunham@arm.comsystem.cpu.dtb.read_hits 0 # DTB read hits 35211507SCurtis.Dunham@arm.comsystem.cpu.dtb.read_misses 0 # DTB read misses 35311507SCurtis.Dunham@arm.comsystem.cpu.dtb.write_hits 0 # DTB write hits 35411507SCurtis.Dunham@arm.comsystem.cpu.dtb.write_misses 0 # DTB write misses 35511507SCurtis.Dunham@arm.comsystem.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 35611507SCurtis.Dunham@arm.comsystem.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 35711507SCurtis.Dunham@arm.comsystem.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 35811507SCurtis.Dunham@arm.comsystem.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 35911507SCurtis.Dunham@arm.comsystem.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 36011507SCurtis.Dunham@arm.comsystem.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 36111507SCurtis.Dunham@arm.comsystem.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 36211507SCurtis.Dunham@arm.comsystem.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 36311507SCurtis.Dunham@arm.comsystem.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 36411507SCurtis.Dunham@arm.comsystem.cpu.dtb.read_accesses 0 # DTB read accesses 36511507SCurtis.Dunham@arm.comsystem.cpu.dtb.write_accesses 0 # DTB write accesses 36611507SCurtis.Dunham@arm.comsystem.cpu.dtb.inst_accesses 0 # ITB inst accesses 36711507SCurtis.Dunham@arm.comsystem.cpu.dtb.hits 0 # DTB hits 36811507SCurtis.Dunham@arm.comsystem.cpu.dtb.misses 0 # DTB misses 36911507SCurtis.Dunham@arm.comsystem.cpu.dtb.accesses 0 # DTB accesses 37011507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 37111507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 37211507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 37311507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 37411507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 37511507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 37611507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 37711507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 37811507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 37911507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 38011507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 38111507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 38211507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 38311507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 38411507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 38511507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 38611507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 38711507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 38811507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 38911507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 39011507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 39111507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 39211507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 39311507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 39411507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 39511507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 39611507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 39711507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 39811507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 39911507SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walks 0 # Table walker walks requested 40011507SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 40111507SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 40211507SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 40311507SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 40411507SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 40511507SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 40611507SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 40711507SCurtis.Dunham@arm.comsystem.cpu.itb.inst_hits 0 # ITB inst hits 40811507SCurtis.Dunham@arm.comsystem.cpu.itb.inst_misses 0 # ITB inst misses 40911507SCurtis.Dunham@arm.comsystem.cpu.itb.read_hits 0 # DTB read hits 41011507SCurtis.Dunham@arm.comsystem.cpu.itb.read_misses 0 # DTB read misses 41111507SCurtis.Dunham@arm.comsystem.cpu.itb.write_hits 0 # DTB write hits 41211507SCurtis.Dunham@arm.comsystem.cpu.itb.write_misses 0 # DTB write misses 41311507SCurtis.Dunham@arm.comsystem.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 41411507SCurtis.Dunham@arm.comsystem.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 41511507SCurtis.Dunham@arm.comsystem.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 41611507SCurtis.Dunham@arm.comsystem.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 41711507SCurtis.Dunham@arm.comsystem.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 41811507SCurtis.Dunham@arm.comsystem.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 41911507SCurtis.Dunham@arm.comsystem.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 42011507SCurtis.Dunham@arm.comsystem.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 42111507SCurtis.Dunham@arm.comsystem.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 42211507SCurtis.Dunham@arm.comsystem.cpu.itb.read_accesses 0 # DTB read accesses 42311507SCurtis.Dunham@arm.comsystem.cpu.itb.write_accesses 0 # DTB write accesses 42411507SCurtis.Dunham@arm.comsystem.cpu.itb.inst_accesses 0 # ITB inst accesses 42511507SCurtis.Dunham@arm.comsystem.cpu.itb.hits 0 # DTB hits 42611507SCurtis.Dunham@arm.comsystem.cpu.itb.misses 0 # DTB misses 42711507SCurtis.Dunham@arm.comsystem.cpu.itb.accesses 0 # DTB accesses 42811507SCurtis.Dunham@arm.comsystem.cpu.workload.num_syscalls 673 # Number of system calls 42911507SCurtis.Dunham@arm.comsystem.cpu.numCycles 653462649 # number of cpu cycles simulated 43011507SCurtis.Dunham@arm.comsystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 43111507SCurtis.Dunham@arm.comsystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 43211507SCurtis.Dunham@arm.comsystem.cpu.fetch.icacheStallCycles 34330546 # Number of cycles fetch is stalled on an Icache miss 43311507SCurtis.Dunham@arm.comsystem.cpu.fetch.Insts 824287133 # Number of instructions fetch has processed 43411507SCurtis.Dunham@arm.comsystem.cpu.fetch.Branches 174663372 # Number of branches that fetch encountered 43511507SCurtis.Dunham@arm.comsystem.cpu.fetch.predictedBranches 103243155 # Number of branches that fetch has predicted taken 43611507SCurtis.Dunham@arm.comsystem.cpu.fetch.Cycles 614749504 # Number of cycles fetch has run and was not squashing or blocked 43711507SCurtis.Dunham@arm.comsystem.cpu.fetch.SquashCycles 8068361 # Number of cycles fetch has spent squashing 43811507SCurtis.Dunham@arm.comsystem.cpu.fetch.MiscStallCycles 2074 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 43911507SCurtis.Dunham@arm.comsystem.cpu.fetch.PendingTrapStallCycles 17 # Number of stall cycles due to pending traps 44011507SCurtis.Dunham@arm.comsystem.cpu.fetch.IcacheWaitRetryStallCycles 3172 # Number of stall cycles due to full MSHR 44111507SCurtis.Dunham@arm.comsystem.cpu.fetch.CacheLines 247743048 # Number of cache lines fetched 44211507SCurtis.Dunham@arm.comsystem.cpu.fetch.IcacheSquashes 12728 # Number of outstanding Icache misses that were squashed 44311507SCurtis.Dunham@arm.comsystem.cpu.fetch.rateDist::samples 653119493 # Number of instructions fetched each cycle (Total) 44411507SCurtis.Dunham@arm.comsystem.cpu.fetch.rateDist::mean 1.556506 # Number of instructions fetched each cycle (Total) 44511507SCurtis.Dunham@arm.comsystem.cpu.fetch.rateDist::stdev 1.252668 # Number of instructions fetched each cycle (Total) 44611507SCurtis.Dunham@arm.comsystem.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 44711507SCurtis.Dunham@arm.comsystem.cpu.fetch.rateDist::0 191049151 29.25% 29.25% # Number of instructions fetched each cycle (Total) 44811507SCurtis.Dunham@arm.comsystem.cpu.fetch.rateDist::1 148339787 22.71% 51.96% # Number of instructions fetched each cycle (Total) 44911507SCurtis.Dunham@arm.comsystem.cpu.fetch.rateDist::2 72947000 11.17% 63.13% # Number of instructions fetched each cycle (Total) 45011507SCurtis.Dunham@arm.comsystem.cpu.fetch.rateDist::3 240783555 36.87% 100.00% # Number of instructions fetched each cycle (Total) 45111507SCurtis.Dunham@arm.comsystem.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 45211507SCurtis.Dunham@arm.comsystem.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 45311507SCurtis.Dunham@arm.comsystem.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) 45411507SCurtis.Dunham@arm.comsystem.cpu.fetch.rateDist::total 653119493 # Number of instructions fetched each cycle (Total) 45511507SCurtis.Dunham@arm.comsystem.cpu.fetch.branchRate 0.267289 # Number of branch fetches per cycle 45611507SCurtis.Dunham@arm.comsystem.cpu.fetch.rate 1.261414 # Number of inst fetches per cycle 45711507SCurtis.Dunham@arm.comsystem.cpu.decode.IdleCycles 75090408 # Number of cycles decode is idle 45811507SCurtis.Dunham@arm.comsystem.cpu.decode.BlockedCycles 234264663 # Number of cycles decode is blocked 45911507SCurtis.Dunham@arm.comsystem.cpu.decode.RunCycles 277765642 # Number of cycles decode is running 46011507SCurtis.Dunham@arm.comsystem.cpu.decode.UnblockCycles 61977614 # Number of cycles decode is unblocking 46111507SCurtis.Dunham@arm.comsystem.cpu.decode.SquashCycles 4021166 # Number of cycles decode is squashing 46211507SCurtis.Dunham@arm.comsystem.cpu.decode.BranchResolved 20809487 # Number of times decode resolved a branch 46311507SCurtis.Dunham@arm.comsystem.cpu.decode.BranchMispred 13114 # Number of times decode detected a branch misprediction 46411507SCurtis.Dunham@arm.comsystem.cpu.decode.DecodedInsts 924578192 # Number of instructions handled by decode 46511507SCurtis.Dunham@arm.comsystem.cpu.decode.SquashedInsts 11804661 # Number of squashed instructions handled by decode 46611507SCurtis.Dunham@arm.comsystem.cpu.rename.SquashCycles 4021166 # Number of cycles rename is squashing 46711507SCurtis.Dunham@arm.comsystem.cpu.rename.IdleCycles 118033326 # Number of cycles rename is idle 46811507SCurtis.Dunham@arm.comsystem.cpu.rename.BlockCycles 133536652 # Number of cycles rename is blocking 46911507SCurtis.Dunham@arm.comsystem.cpu.rename.serializeStallCycles 207511 # count of cycles rename stalled for serializing inst 47011507SCurtis.Dunham@arm.comsystem.cpu.rename.RunCycles 294559211 # Number of cycles rename is running 47111507SCurtis.Dunham@arm.comsystem.cpu.rename.UnblockCycles 102761627 # Number of cycles rename is unblocking 47211507SCurtis.Dunham@arm.comsystem.cpu.rename.RenamedInsts 906540244 # Number of instructions processed by rename 47311507SCurtis.Dunham@arm.comsystem.cpu.rename.SquashedInsts 6891569 # Number of squashed instructions processed by rename 47411507SCurtis.Dunham@arm.comsystem.cpu.rename.ROBFullEvents 27986936 # Number of times rename has blocked due to ROB full 47511507SCurtis.Dunham@arm.comsystem.cpu.rename.IQFullEvents 2218724 # Number of times rename has blocked due to IQ full 47611507SCurtis.Dunham@arm.comsystem.cpu.rename.LQFullEvents 49336465 # Number of times rename has blocked due to LQ full 47711507SCurtis.Dunham@arm.comsystem.cpu.rename.SQFullEvents 494906 # Number of times rename has blocked due to SQ full 47811507SCurtis.Dunham@arm.comsystem.cpu.rename.RenamedOperands 980929615 # Number of destination operands rename has renamed 47911507SCurtis.Dunham@arm.comsystem.cpu.rename.RenameLookups 4376071754 # Number of register rename lookups that rename has made 48011507SCurtis.Dunham@arm.comsystem.cpu.rename.int_rename_lookups 1001832293 # Number of integer rename lookups 48111507SCurtis.Dunham@arm.comsystem.cpu.rename.fp_rename_lookups 34457071 # Number of floating rename lookups 48211507SCurtis.Dunham@arm.comsystem.cpu.rename.CommittedMaps 874778230 # Number of HB maps that are committed 48311507SCurtis.Dunham@arm.comsystem.cpu.rename.UndoneMaps 106151385 # Number of HB maps that are undone due to squashing 48411507SCurtis.Dunham@arm.comsystem.cpu.rename.serializingInsts 6850 # count of serializing insts renamed 48511507SCurtis.Dunham@arm.comsystem.cpu.rename.tempSerializingInsts 6837 # count of temporary serializing insts renamed 48611507SCurtis.Dunham@arm.comsystem.cpu.rename.skidInsts 138811891 # count of insts added to the skid buffer 48711507SCurtis.Dunham@arm.comsystem.cpu.memDep0.insertedLoads 271881167 # Number of loads inserted to the mem dependence unit. 48811507SCurtis.Dunham@arm.comsystem.cpu.memDep0.insertedStores 160584857 # Number of stores inserted to the mem dependence unit. 48911507SCurtis.Dunham@arm.comsystem.cpu.memDep0.conflictingLoads 6164108 # Number of conflicting loads. 49011507SCurtis.Dunham@arm.comsystem.cpu.memDep0.conflictingStores 12154940 # Number of conflicting stores. 49111507SCurtis.Dunham@arm.comsystem.cpu.iq.iqInstsAdded 899826382 # Number of instructions added to the IQ (excludes non-spec) 49211507SCurtis.Dunham@arm.comsystem.cpu.iq.iqNonSpecInstsAdded 12579 # Number of non-speculative instructions added to the IQ 49311507SCurtis.Dunham@arm.comsystem.cpu.iq.iqInstsIssued 860025252 # Number of instructions issued 49411507SCurtis.Dunham@arm.comsystem.cpu.iq.iqSquashedInstsIssued 9216952 # Number of squashed instructions issued 49511507SCurtis.Dunham@arm.comsystem.cpu.iq.iqSquashedInstsExamined 111114003 # Number of squashed instructions iterated over during squash; mainly for profiling 49611507SCurtis.Dunham@arm.comsystem.cpu.iq.iqSquashedOperandsExamined 248251839 # Number of squashed operands that are examined and possibly removed from graph 49711507SCurtis.Dunham@arm.comsystem.cpu.iq.iqSquashedNonSpecRemoved 425 # Number of squashed non-spec instructions that were removed 49811507SCurtis.Dunham@arm.comsystem.cpu.iq.issued_per_cycle::samples 653119493 # Number of insts issued each cycle 49911507SCurtis.Dunham@arm.comsystem.cpu.iq.issued_per_cycle::mean 1.316796 # Number of insts issued each cycle 50011507SCurtis.Dunham@arm.comsystem.cpu.iq.issued_per_cycle::stdev 1.093773 # Number of insts issued each cycle 50111507SCurtis.Dunham@arm.comsystem.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 50211507SCurtis.Dunham@arm.comsystem.cpu.iq.issued_per_cycle::0 190460700 29.16% 29.16% # Number of insts issued each cycle 50311507SCurtis.Dunham@arm.comsystem.cpu.iq.issued_per_cycle::1 182404327 27.93% 57.09% # Number of insts issued each cycle 50411507SCurtis.Dunham@arm.comsystem.cpu.iq.issued_per_cycle::2 175564310 26.88% 83.97% # Number of insts issued each cycle 50511507SCurtis.Dunham@arm.comsystem.cpu.iq.issued_per_cycle::3 92270630 14.13% 98.10% # Number of insts issued each cycle 50611507SCurtis.Dunham@arm.comsystem.cpu.iq.issued_per_cycle::4 12417215 1.90% 100.00% # Number of insts issued each cycle 50711507SCurtis.Dunham@arm.comsystem.cpu.iq.issued_per_cycle::5 2311 0.00% 100.00% # Number of insts issued each cycle 50811507SCurtis.Dunham@arm.comsystem.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 50911507SCurtis.Dunham@arm.comsystem.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 51011507SCurtis.Dunham@arm.comsystem.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 51111507SCurtis.Dunham@arm.comsystem.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 51211507SCurtis.Dunham@arm.comsystem.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 51311507SCurtis.Dunham@arm.comsystem.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle 51411507SCurtis.Dunham@arm.comsystem.cpu.iq.issued_per_cycle::total 653119493 # Number of insts issued each cycle 51511507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 51611507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::IntAlu 66606660 24.62% 24.62% # attempts to use FU when none available 51711507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::IntMult 18142 0.01% 24.63% # attempts to use FU when none available 51811507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::IntDiv 0 0.00% 24.63% # attempts to use FU when none available 51911507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::FloatAdd 0 0.00% 24.63% # attempts to use FU when none available 52011507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::FloatCmp 0 0.00% 24.63% # attempts to use FU when none available 52111507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::FloatCvt 0 0.00% 24.63% # attempts to use FU when none available 52211507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::FloatMult 0 0.00% 24.63% # attempts to use FU when none available 52311507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::FloatDiv 0 0.00% 24.63% # attempts to use FU when none available 52411507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::FloatSqrt 0 0.00% 24.63% # attempts to use FU when none available 52511507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdAdd 0 0.00% 24.63% # attempts to use FU when none available 52611507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdAddAcc 0 0.00% 24.63% # attempts to use FU when none available 52711507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdAlu 0 0.00% 24.63% # attempts to use FU when none available 52811507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdCmp 0 0.00% 24.63% # attempts to use FU when none available 52911507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdCvt 0 0.00% 24.63% # attempts to use FU when none available 53011507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdMisc 0 0.00% 24.63% # attempts to use FU when none available 53111507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdMult 0 0.00% 24.63% # attempts to use FU when none available 53211507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdMultAcc 0 0.00% 24.63% # attempts to use FU when none available 53311507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdShift 0 0.00% 24.63% # attempts to use FU when none available 53411507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 24.63% # attempts to use FU when none available 53511507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdSqrt 0 0.00% 24.63% # attempts to use FU when none available 53611507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 24.63% # attempts to use FU when none available 53711507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 24.63% # attempts to use FU when none available 53811507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 24.63% # attempts to use FU when none available 53911507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdFloatCvt 636889 0.24% 24.87% # attempts to use FU when none available 54011507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 24.87% # attempts to use FU when none available 54111507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 24.87% # attempts to use FU when none available 54211507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdFloatMult 0 0.00% 24.87% # attempts to use FU when none available 54311507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 24.87% # attempts to use FU when none available 54411507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 24.87% # attempts to use FU when none available 54511507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::MemRead 134118538 49.58% 74.45% # attempts to use FU when none available 54611507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::MemWrite 69109914 25.55% 100.00% # attempts to use FU when none available 54711507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 54811507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 54911507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 55011507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::IntAlu 413086253 48.03% 48.03% # Type of FU issued 55111507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::IntMult 5187655 0.60% 48.64% # Type of FU issued 55211507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::IntDiv 0 0.00% 48.64% # Type of FU issued 55311507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::FloatAdd 0 0.00% 48.64% # Type of FU issued 55411507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::FloatCmp 0 0.00% 48.64% # Type of FU issued 55511507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::FloatCvt 0 0.00% 48.64% # Type of FU issued 55611507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::FloatMult 0 0.00% 48.64% # Type of FU issued 55711507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::FloatDiv 0 0.00% 48.64% # Type of FU issued 55811507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 48.64% # Type of FU issued 55911507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdAdd 0 0.00% 48.64% # Type of FU issued 56011507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 48.64% # Type of FU issued 56111507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdAlu 0 0.00% 48.64% # Type of FU issued 56211507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdCmp 0 0.00% 48.64% # Type of FU issued 56311507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdCvt 0 0.00% 48.64% # Type of FU issued 56411507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdMisc 0 0.00% 48.64% # Type of FU issued 56511507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdMult 0 0.00% 48.64% # Type of FU issued 56611507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 48.64% # Type of FU issued 56711507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdShift 0 0.00% 48.64% # Type of FU issued 56811507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.64% # Type of FU issued 56911507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 48.64% # Type of FU issued 57011507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdFloatAdd 637528 0.07% 48.71% # Type of FU issued 57111507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.71% # Type of FU issued 57211507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdFloatCmp 3187674 0.37% 49.08% # Type of FU issued 57311507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdFloatCvt 2550149 0.30% 49.38% # Type of FU issued 57411507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.38% # Type of FU issued 57511507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMisc 11478193 1.33% 50.71% # Type of FU issued 57611507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 50.71% # Type of FU issued 57711507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 50.71% # Type of FU issued 57811507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 50.71% # Type of FU issued 57911507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::MemRead 266665790 31.01% 81.72% # Type of FU issued 58011507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::MemWrite 157232010 18.28% 100.00% # Type of FU issued 58111507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 58211507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 58311507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::total 860025252 # Type of FU issued 58411507SCurtis.Dunham@arm.comsystem.cpu.iq.rate 1.316105 # Inst issue rate 58511507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_busy_cnt 270490143 # FU busy when requested 58611507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_busy_rate 0.314514 # FU busy rate (busy events/executed inst) 58711507SCurtis.Dunham@arm.comsystem.cpu.iq.int_inst_queue_reads 2595335329 # Number of integer instruction queue reads 58811507SCurtis.Dunham@arm.comsystem.cpu.iq.int_inst_queue_writes 980330228 # Number of integer instruction queue writes 58911507SCurtis.Dunham@arm.comsystem.cpu.iq.int_inst_queue_wakeup_accesses 820077465 # Number of integer instruction queue wakeup accesses 59011507SCurtis.Dunham@arm.comsystem.cpu.iq.fp_inst_queue_reads 57541763 # Number of floating instruction queue reads 59111507SCurtis.Dunham@arm.comsystem.cpu.iq.fp_inst_queue_writes 30641547 # Number of floating instruction queue writes 59211507SCurtis.Dunham@arm.comsystem.cpu.iq.fp_inst_queue_wakeup_accesses 24878664 # Number of floating instruction queue wakeup accesses 59311507SCurtis.Dunham@arm.comsystem.cpu.iq.int_alu_accesses 1098495276 # Number of integer alu accesses 59411507SCurtis.Dunham@arm.comsystem.cpu.iq.fp_alu_accesses 32020119 # Number of floating point alu accesses 59511507SCurtis.Dunham@arm.comsystem.cpu.iew.lsq.thread0.forwLoads 13987051 # Number of loads that had data forwarded from stores 59611507SCurtis.Dunham@arm.comsystem.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 59711507SCurtis.Dunham@arm.comsystem.cpu.iew.lsq.thread0.squashedLoads 19640229 # Number of loads squashed 59811507SCurtis.Dunham@arm.comsystem.cpu.iew.lsq.thread0.ignoredResponses 121 # Number of memory responses ignored because the instruction is squashed 59911507SCurtis.Dunham@arm.comsystem.cpu.iew.lsq.thread0.memOrderViolation 18814 # Number of memory ordering violations 60011507SCurtis.Dunham@arm.comsystem.cpu.iew.lsq.thread0.squashedStores 31604361 # Number of stores squashed 60111507SCurtis.Dunham@arm.comsystem.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 60211507SCurtis.Dunham@arm.comsystem.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 60311507SCurtis.Dunham@arm.comsystem.cpu.iew.lsq.thread0.rescheduledLoads 1918936 # Number of loads that were rescheduled 60411507SCurtis.Dunham@arm.comsystem.cpu.iew.lsq.thread0.cacheBlocked 18556 # Number of times an access to memory failed due to the cache being blocked 60511507SCurtis.Dunham@arm.comsystem.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 60611507SCurtis.Dunham@arm.comsystem.cpu.iew.iewSquashCycles 4021166 # Number of cycles IEW is squashing 60711507SCurtis.Dunham@arm.comsystem.cpu.iew.iewBlockCycles 10589336 # Number of cycles IEW is blocking 60811507SCurtis.Dunham@arm.comsystem.cpu.iew.iewUnblockCycles 14351 # Number of cycles IEW is unblocking 60911507SCurtis.Dunham@arm.comsystem.cpu.iew.iewDispatchedInsts 899849213 # Number of instructions dispatched to IQ 61011507SCurtis.Dunham@arm.comsystem.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch 61111507SCurtis.Dunham@arm.comsystem.cpu.iew.iewDispLoadInsts 271881167 # Number of dispatched load instructions 61211507SCurtis.Dunham@arm.comsystem.cpu.iew.iewDispStoreInsts 160584857 # Number of dispatched store instructions 61311507SCurtis.Dunham@arm.comsystem.cpu.iew.iewDispNonSpecInsts 6839 # Number of dispatched non-speculative instructions 61411507SCurtis.Dunham@arm.comsystem.cpu.iew.iewIQFullEvents 943 # Number of times the IQ has become full, causing a stall 61511507SCurtis.Dunham@arm.comsystem.cpu.iew.iewLSQFullEvents 11501 # Number of times the LSQ has become full, causing a stall 61611507SCurtis.Dunham@arm.comsystem.cpu.iew.memOrderViolationEvents 18814 # Number of memory order violations 61711507SCurtis.Dunham@arm.comsystem.cpu.iew.predictedTakenIncorrect 3295227 # Number of branches that were predicted taken incorrectly 61811507SCurtis.Dunham@arm.comsystem.cpu.iew.predictedNotTakenIncorrect 3290376 # Number of branches that were predicted not taken incorrectly 61911507SCurtis.Dunham@arm.comsystem.cpu.iew.branchMispredicts 6585603 # Number of branch mispredicts detected at execute 62011507SCurtis.Dunham@arm.comsystem.cpu.iew.iewExecutedInsts 850170088 # Number of executed instructions 62111507SCurtis.Dunham@arm.comsystem.cpu.iew.iewExecLoadInsts 263374256 # Number of load instructions executed 62211507SCurtis.Dunham@arm.comsystem.cpu.iew.iewExecSquashedInsts 9855164 # Number of squashed instructions skipped in execute 62311507SCurtis.Dunham@arm.comsystem.cpu.iew.exec_swp 0 # number of swp insts executed 62411507SCurtis.Dunham@arm.comsystem.cpu.iew.exec_nop 10252 # number of nop insts executed 62511507SCurtis.Dunham@arm.comsystem.cpu.iew.exec_refs 416063199 # number of memory reference insts executed 62611507SCurtis.Dunham@arm.comsystem.cpu.iew.exec_branches 143379422 # Number of branches executed 62711507SCurtis.Dunham@arm.comsystem.cpu.iew.exec_stores 152688943 # Number of stores executed 62811507SCurtis.Dunham@arm.comsystem.cpu.iew.exec_rate 1.301023 # Inst execution rate 62911507SCurtis.Dunham@arm.comsystem.cpu.iew.wb_sent 846292107 # cumulative count of insts sent to commit 63011507SCurtis.Dunham@arm.comsystem.cpu.iew.wb_count 844956129 # cumulative count of insts written-back 63111507SCurtis.Dunham@arm.comsystem.cpu.iew.wb_producers 487338276 # num instructions producing a value 63211507SCurtis.Dunham@arm.comsystem.cpu.iew.wb_consumers 808096579 # num instructions consuming a value 63311507SCurtis.Dunham@arm.comsystem.cpu.iew.wb_rate 1.293044 # insts written-back per cycle 63411507SCurtis.Dunham@arm.comsystem.cpu.iew.wb_fanout 0.603069 # average fanout of values written-back 63511507SCurtis.Dunham@arm.comsystem.cpu.commit.commitSquashedInsts 103168329 # The number of squashed insts skipped by commit 63611507SCurtis.Dunham@arm.comsystem.cpu.commit.commitNonSpecStalls 12154 # The number of times commit has been forced to stall to communicate backwards 63711507SCurtis.Dunham@arm.comsystem.cpu.commit.branchMispredicts 4002820 # The number of times a branch was mispredicted 63811507SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::samples 638538795 # Number of insts commited each cycle 63911507SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::mean 1.235211 # Number of insts commited each cycle 64011507SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::stdev 2.072799 # Number of insts commited each cycle 64111507SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 64211507SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::0 348204518 54.53% 54.53% # Number of insts commited each cycle 64311507SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::1 137237104 21.49% 76.02% # Number of insts commited each cycle 64411507SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::2 51340026 8.04% 84.06% # Number of insts commited each cycle 64511507SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::3 28219441 4.42% 88.48% # Number of insts commited each cycle 64611507SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::4 14379877 2.25% 90.74% # Number of insts commited each cycle 64711507SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::5 14774087 2.31% 93.05% # Number of insts commited each cycle 64811507SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::6 7871873 1.23% 94.28% # Number of insts commited each cycle 64911507SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::7 6561542 1.03% 95.31% # Number of insts commited each cycle 65011507SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::8 29950327 4.69% 100.00% # Number of insts commited each cycle 65111507SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 65211507SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 65311507SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 65411507SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::total 638538795 # Number of insts commited each cycle 65511507SCurtis.Dunham@arm.comsystem.cpu.commit.committedInsts 640654411 # Number of instructions committed 65611507SCurtis.Dunham@arm.comsystem.cpu.commit.committedOps 788730070 # Number of ops (including micro ops) committed 65711507SCurtis.Dunham@arm.comsystem.cpu.commit.swp_count 0 # Number of s/w prefetches committed 65811507SCurtis.Dunham@arm.comsystem.cpu.commit.refs 381221434 # Number of memory references committed 65911507SCurtis.Dunham@arm.comsystem.cpu.commit.loads 252240938 # Number of loads committed 66011507SCurtis.Dunham@arm.comsystem.cpu.commit.membars 5740 # Number of memory barriers committed 66111507SCurtis.Dunham@arm.comsystem.cpu.commit.branches 137364860 # Number of branches committed 66211507SCurtis.Dunham@arm.comsystem.cpu.commit.fp_insts 24239771 # Number of committed floating point instructions. 66311507SCurtis.Dunham@arm.comsystem.cpu.commit.int_insts 682251399 # Number of committed integer instructions. 66411507SCurtis.Dunham@arm.comsystem.cpu.commit.function_calls 19275340 # Number of function calls committed. 66511507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 66611507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::IntAlu 385756794 48.91% 48.91% # Class of committed instruction 66711507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::IntMult 5173441 0.66% 49.56% # Class of committed instruction 66811507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::IntDiv 0 0.00% 49.56% # Class of committed instruction 66911507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::FloatAdd 0 0.00% 49.56% # Class of committed instruction 67011507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::FloatCmp 0 0.00% 49.56% # Class of committed instruction 67111507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::FloatCvt 0 0.00% 49.56% # Class of committed instruction 67211507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::FloatMult 0 0.00% 49.56% # Class of committed instruction 67311507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::FloatDiv 0 0.00% 49.56% # Class of committed instruction 67411507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::FloatSqrt 0 0.00% 49.56% # Class of committed instruction 67511507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::SimdAdd 0 0.00% 49.56% # Class of committed instruction 67611507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 49.56% # Class of committed instruction 67711507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::SimdAlu 0 0.00% 49.56% # Class of committed instruction 67811507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::SimdCmp 0 0.00% 49.56% # Class of committed instruction 67911507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::SimdCvt 0 0.00% 49.56% # Class of committed instruction 68011507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::SimdMisc 0 0.00% 49.56% # Class of committed instruction 68111507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::SimdMult 0 0.00% 49.56% # Class of committed instruction 68211507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 49.56% # Class of committed instruction 68311507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::SimdShift 0 0.00% 49.56% # Class of committed instruction 68411507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 49.56% # Class of committed instruction 68511507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::SimdSqrt 0 0.00% 49.56% # Class of committed instruction 68611507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::SimdFloatAdd 637528 0.08% 49.65% # Class of committed instruction 68711507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 49.65% # Class of committed instruction 68811507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::SimdFloatCmp 3187668 0.40% 50.05% # Class of committed instruction 68911507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::SimdFloatCvt 2550131 0.32% 50.37% # Class of committed instruction 69011507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 50.37% # Class of committed instruction 69111507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::SimdFloatMisc 10203074 1.29% 51.67% # Class of committed instruction 69211507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 51.67% # Class of committed instruction 69311507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 51.67% # Class of committed instruction 69411507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 51.67% # Class of committed instruction 69511507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::MemRead 252240938 31.98% 83.65% # Class of committed instruction 69611507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::MemWrite 128980496 16.35% 100.00% # Class of committed instruction 69711507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 69811507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 69911507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::total 788730070 # Class of committed instruction 70011507SCurtis.Dunham@arm.comsystem.cpu.commit.bw_lim_events 29950327 # number cycles where commit BW limit reached 70111507SCurtis.Dunham@arm.comsystem.cpu.rob.rob_reads 1500478116 # The number of ROB reads 70211507SCurtis.Dunham@arm.comsystem.cpu.rob.rob_writes 1798380886 # The number of ROB writes 70311507SCurtis.Dunham@arm.comsystem.cpu.timesIdled 9234 # Number of times that the entire CPU went into an idle state and unscheduled itself 70411507SCurtis.Dunham@arm.comsystem.cpu.idleCycles 343156 # Total number of cycles that the CPU has spent unscheduled due to idling 70511507SCurtis.Dunham@arm.comsystem.cpu.committedInsts 640649299 # Number of Instructions Simulated 70611507SCurtis.Dunham@arm.comsystem.cpu.committedOps 788724958 # Number of Ops (including micro ops) Simulated 70711507SCurtis.Dunham@arm.comsystem.cpu.cpi 1.020001 # CPI: Cycles Per Instruction 70811507SCurtis.Dunham@arm.comsystem.cpu.cpi_total 1.020001 # CPI: Total CPI of All Threads 70911507SCurtis.Dunham@arm.comsystem.cpu.ipc 0.980392 # IPC: Instructions Per Cycle 71011507SCurtis.Dunham@arm.comsystem.cpu.ipc_total 0.980392 # IPC: Total IPC of All Threads 71111507SCurtis.Dunham@arm.comsystem.cpu.int_regfile_reads 868460109 # number of integer regfile reads 71211507SCurtis.Dunham@arm.comsystem.cpu.int_regfile_writes 500697086 # number of integer regfile writes 71311507SCurtis.Dunham@arm.comsystem.cpu.fp_regfile_reads 30616061 # number of floating regfile reads 71411507SCurtis.Dunham@arm.comsystem.cpu.fp_regfile_writes 22959483 # number of floating regfile writes 71511507SCurtis.Dunham@arm.comsystem.cpu.cc_regfile_reads 3322370942 # number of cc regfile reads 71611507SCurtis.Dunham@arm.comsystem.cpu.cc_regfile_writes 369203387 # number of cc regfile writes 71711507SCurtis.Dunham@arm.comsystem.cpu.misc_regfile_reads 632347849 # number of misc regfile reads 71811507SCurtis.Dunham@arm.comsystem.cpu.misc_regfile_writes 6386808 # number of misc regfile writes 71911507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.replacements 2756452 # number of replacements 72011507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.tagsinuse 511.912722 # Cycle average of tags in use 72111507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.total_refs 371048240 # Total number of references to valid blocks. 72211507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.sampled_refs 2756964 # Sample count of references to valid blocks. 72311507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.avg_refs 134.585813 # Average number of references to valid blocks. 72411507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.warmup_cycle 268220000 # Cycle when the warmup percentage was hit. 72511507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.occ_blocks::cpu.data 511.912722 # Average occupied blocks per requestor 72611507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.occ_percent::cpu.data 0.999830 # Average percentage of cache occupancy 72711507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.occ_percent::total 0.999830 # Average percentage of cache occupancy 72811507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 72911507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id 73011507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::1 252 # Occupied blocks per task id 73111507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::2 164 # Occupied blocks per task id 73211507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::4 56 # Occupied blocks per task id 73311507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 73411507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.tag_accesses 751744798 # Number of tag accesses 73511507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.data_accesses 751744798 # Number of data accesses 73611507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_hits::cpu.data 243125245 # number of ReadReq hits 73711507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_hits::total 243125245 # number of ReadReq hits 73811507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_hits::cpu.data 127906950 # number of WriteReq hits 73911507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_hits::total 127906950 # number of WriteReq hits 74011507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_hits::cpu.data 3157 # number of SoftPFReq hits 74111507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_hits::total 3157 # number of SoftPFReq hits 74211507SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_hits::cpu.data 5738 # number of LoadLockedReq hits 74311507SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_hits::total 5738 # number of LoadLockedReq hits 74411507SCurtis.Dunham@arm.comsystem.cpu.dcache.StoreCondReq_hits::cpu.data 5739 # number of StoreCondReq hits 74511507SCurtis.Dunham@arm.comsystem.cpu.dcache.StoreCondReq_hits::total 5739 # number of StoreCondReq hits 74611507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_hits::cpu.data 371032195 # number of demand (read+write) hits 74711507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_hits::total 371032195 # number of demand (read+write) hits 74811507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_hits::cpu.data 371035352 # number of overall hits 74911507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_hits::total 371035352 # number of overall hits 75011507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_misses::cpu.data 2401911 # number of ReadReq misses 75111507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_misses::total 2401911 # number of ReadReq misses 75211507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_misses::cpu.data 1044527 # number of WriteReq misses 75311507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_misses::total 1044527 # number of WriteReq misses 75411507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_misses::cpu.data 647 # number of SoftPFReq misses 75511507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_misses::total 647 # number of SoftPFReq misses 75611507SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses 75711507SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses 75811507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_misses::cpu.data 3446438 # number of demand (read+write) misses 75911507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_misses::total 3446438 # number of demand (read+write) misses 76011507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_misses::cpu.data 3447085 # number of overall misses 76111507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_misses::total 3447085 # number of overall misses 76211507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_miss_latency::cpu.data 68215511500 # number of ReadReq miss cycles 76311507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_miss_latency::total 68215511500 # number of ReadReq miss cycles 76411507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_miss_latency::cpu.data 10001211350 # number of WriteReq miss cycles 76511507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_miss_latency::total 10001211350 # number of WriteReq miss cycles 76611507SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 165500 # number of LoadLockedReq miss cycles 76711507SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_miss_latency::total 165500 # number of LoadLockedReq miss cycles 76811507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_miss_latency::cpu.data 78216722850 # number of demand (read+write) miss cycles 76911507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_miss_latency::total 78216722850 # number of demand (read+write) miss cycles 77011507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_miss_latency::cpu.data 78216722850 # number of overall miss cycles 77111507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_miss_latency::total 78216722850 # number of overall miss cycles 77211507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_accesses::cpu.data 245527156 # number of ReadReq accesses(hits+misses) 77311507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_accesses::total 245527156 # number of ReadReq accesses(hits+misses) 77411507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses) 77511507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_accesses::total 128951477 # number of WriteReq accesses(hits+misses) 77611507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_accesses::cpu.data 3804 # number of SoftPFReq accesses(hits+misses) 77711507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_accesses::total 3804 # number of SoftPFReq accesses(hits+misses) 77811507SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::cpu.data 5741 # number of LoadLockedReq accesses(hits+misses) 77911507SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::total 5741 # number of LoadLockedReq accesses(hits+misses) 78011507SCurtis.Dunham@arm.comsystem.cpu.dcache.StoreCondReq_accesses::cpu.data 5739 # number of StoreCondReq accesses(hits+misses) 78111507SCurtis.Dunham@arm.comsystem.cpu.dcache.StoreCondReq_accesses::total 5739 # number of StoreCondReq accesses(hits+misses) 78211507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_accesses::cpu.data 374478633 # number of demand (read+write) accesses 78311507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_accesses::total 374478633 # number of demand (read+write) accesses 78411507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_accesses::cpu.data 374482437 # number of overall (read+write) accesses 78511507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_accesses::total 374482437 # number of overall (read+write) accesses 78611507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009783 # miss rate for ReadReq accesses 78711507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_miss_rate::total 0.009783 # miss rate for ReadReq accesses 78811507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.008100 # miss rate for WriteReq accesses 78911507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_miss_rate::total 0.008100 # miss rate for WriteReq accesses 79011507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.170084 # miss rate for SoftPFReq accesses 79111507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_miss_rate::total 0.170084 # miss rate for SoftPFReq accesses 79211507SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000523 # miss rate for LoadLockedReq accesses 79311507SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_miss_rate::total 0.000523 # miss rate for LoadLockedReq accesses 79411507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_miss_rate::cpu.data 0.009203 # miss rate for demand accesses 79511507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_miss_rate::total 0.009203 # miss rate for demand accesses 79611507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_miss_rate::cpu.data 0.009205 # miss rate for overall accesses 79711507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_miss_rate::total 0.009205 # miss rate for overall accesses 79811507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28400.515881 # average ReadReq miss latency 79911507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::total 28400.515881 # average ReadReq miss latency 80011507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 9574.871066 # average WriteReq miss latency 80111507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::total 9574.871066 # average WriteReq miss latency 80211507SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 55166.666667 # average LoadLockedReq miss latency 80311507SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_avg_miss_latency::total 55166.666667 # average LoadLockedReq miss latency 80411507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_avg_miss_latency::cpu.data 22694.945579 # average overall miss latency 80511507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_avg_miss_latency::total 22694.945579 # average overall miss latency 80611507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_avg_miss_latency::cpu.data 22690.685855 # average overall miss latency 80711507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_avg_miss_latency::total 22690.685855 # average overall miss latency 80811507SCurtis.Dunham@arm.comsystem.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 80911507SCurtis.Dunham@arm.comsystem.cpu.dcache.blocked_cycles::no_targets 351776 # number of cycles access was blocked 81011507SCurtis.Dunham@arm.comsystem.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 81111507SCurtis.Dunham@arm.comsystem.cpu.dcache.blocked::no_targets 4812 # number of cycles access was blocked 81211507SCurtis.Dunham@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 81311507SCurtis.Dunham@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_targets 73.103907 # average number of cycles each access was blocked 81411507SCurtis.Dunham@arm.comsystem.cpu.dcache.writebacks::writebacks 2756452 # number of writebacks 81511507SCurtis.Dunham@arm.comsystem.cpu.dcache.writebacks::total 2756452 # number of writebacks 81611507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::cpu.data 366436 # number of ReadReq MSHR hits 81711507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::total 366436 # number of ReadReq MSHR hits 81811507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::cpu.data 323495 # number of WriteReq MSHR hits 81911507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::total 323495 # number of WriteReq MSHR hits 82011507SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits 82111507SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits 82211507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_hits::cpu.data 689931 # number of demand (read+write) MSHR hits 82311507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_hits::total 689931 # number of demand (read+write) MSHR hits 82411507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_hits::cpu.data 689931 # number of overall MSHR hits 82511507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_hits::total 689931 # number of overall MSHR hits 82611507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::cpu.data 2035475 # number of ReadReq MSHR misses 82711507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::total 2035475 # number of ReadReq MSHR misses 82811507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::cpu.data 721032 # number of WriteReq MSHR misses 82911507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::total 721032 # number of WriteReq MSHR misses 83011507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 642 # number of SoftPFReq MSHR misses 83111507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_mshr_misses::total 642 # number of SoftPFReq MSHR misses 83211507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_misses::cpu.data 2756507 # number of demand (read+write) MSHR misses 83311507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_misses::total 2756507 # number of demand (read+write) MSHR misses 83411507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_misses::cpu.data 2757149 # number of overall MSHR misses 83511507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_misses::total 2757149 # number of overall MSHR misses 83611507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 63009195000 # number of ReadReq MSHR miss cycles 83711507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::total 63009195000 # number of ReadReq MSHR miss cycles 83811507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5955069850 # number of WriteReq MSHR miss cycles 83911507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::total 5955069850 # number of WriteReq MSHR miss cycles 84011507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5660000 # number of SoftPFReq MSHR miss cycles 84111507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5660000 # number of SoftPFReq MSHR miss cycles 84211507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::cpu.data 68964264850 # number of demand (read+write) MSHR miss cycles 84311507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::total 68964264850 # number of demand (read+write) MSHR miss cycles 84411507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::cpu.data 68969924850 # number of overall MSHR miss cycles 84511507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::total 68969924850 # number of overall MSHR miss cycles 84611507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.008290 # mshr miss rate for ReadReq accesses 84711507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::total 0.008290 # mshr miss rate for ReadReq accesses 84811507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005591 # mshr miss rate for WriteReq accesses 84911507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005591 # mshr miss rate for WriteReq accesses 85011507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.168770 # mshr miss rate for SoftPFReq accesses 85111507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.168770 # mshr miss rate for SoftPFReq accesses 85211507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.007361 # mshr miss rate for demand accesses 85311507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::total 0.007361 # mshr miss rate for demand accesses 85411507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.007363 # mshr miss rate for overall accesses 85511507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::total 0.007363 # mshr miss rate for overall accesses 85611507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 30955.523895 # average ReadReq mshr miss latency 85711507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30955.523895 # average ReadReq mshr miss latency 85811507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8259.092315 # average WriteReq mshr miss latency 85911507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8259.092315 # average WriteReq mshr miss latency 86011507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 8816.199377 # average SoftPFReq mshr miss latency 86111507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 8816.199377 # average SoftPFReq mshr miss latency 86211507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25018.715661 # average overall mshr miss latency 86311507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::total 25018.715661 # average overall mshr miss latency 86411507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25014.942917 # average overall mshr miss latency 86511507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::total 25014.942917 # average overall mshr miss latency 86611507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.replacements 1979880 # number of replacements 86711507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.tagsinuse 510.626245 # Cycle average of tags in use 86811507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.total_refs 245759391 # Total number of references to valid blocks. 86911507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.sampled_refs 1980390 # Sample count of references to valid blocks. 87011507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.avg_refs 124.096461 # Average number of references to valid blocks. 87111507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.warmup_cycle 258109500 # Cycle when the warmup percentage was hit. 87211507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.occ_blocks::cpu.inst 510.626245 # Average occupied blocks per requestor 87311507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.occ_percent::cpu.inst 0.997317 # Average percentage of cache occupancy 87411507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.occ_percent::total 0.997317 # Average percentage of cache occupancy 87511507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id 87611507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id 87711507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::1 113 # Occupied blocks per task id 87811507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id 87911507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::4 333 # Occupied blocks per task id 88011507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id 88111507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.tag_accesses 497466609 # Number of tag accesses 88211507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.data_accesses 497466609 # Number of data accesses 88311507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_hits::cpu.inst 245759426 # number of ReadReq hits 88411507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_hits::total 245759426 # number of ReadReq hits 88511507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_hits::cpu.inst 245759426 # number of demand (read+write) hits 88611507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_hits::total 245759426 # number of demand (read+write) hits 88711507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_hits::cpu.inst 245759426 # number of overall hits 88811507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_hits::total 245759426 # number of overall hits 88911507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_misses::cpu.inst 1983591 # number of ReadReq misses 89011507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_misses::total 1983591 # number of ReadReq misses 89111507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_misses::cpu.inst 1983591 # number of demand (read+write) misses 89211507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_misses::total 1983591 # number of demand (read+write) misses 89311507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_misses::cpu.inst 1983591 # number of overall misses 89411507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_misses::total 1983591 # number of overall misses 89511507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_miss_latency::cpu.inst 16128682925 # number of ReadReq miss cycles 89611507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_miss_latency::total 16128682925 # number of ReadReq miss cycles 89711507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_miss_latency::cpu.inst 16128682925 # number of demand (read+write) miss cycles 89811507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_miss_latency::total 16128682925 # number of demand (read+write) miss cycles 89911507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_miss_latency::cpu.inst 16128682925 # number of overall miss cycles 90011507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_miss_latency::total 16128682925 # number of overall miss cycles 90111507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_accesses::cpu.inst 247743017 # number of ReadReq accesses(hits+misses) 90211507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_accesses::total 247743017 # number of ReadReq accesses(hits+misses) 90311507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_accesses::cpu.inst 247743017 # number of demand (read+write) accesses 90411507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_accesses::total 247743017 # number of demand (read+write) accesses 90511507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_accesses::cpu.inst 247743017 # number of overall (read+write) accesses 90611507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_accesses::total 247743017 # number of overall (read+write) accesses 90711507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.008007 # miss rate for ReadReq accesses 90811507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_miss_rate::total 0.008007 # miss rate for ReadReq accesses 90911507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_miss_rate::cpu.inst 0.008007 # miss rate for demand accesses 91011507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_miss_rate::total 0.008007 # miss rate for demand accesses 91111507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_miss_rate::cpu.inst 0.008007 # miss rate for overall accesses 91211507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_miss_rate::total 0.008007 # miss rate for overall accesses 91311507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8131.052684 # average ReadReq miss latency 91411507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::total 8131.052684 # average ReadReq miss latency 91511507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_avg_miss_latency::cpu.inst 8131.052684 # average overall miss latency 91611507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_avg_miss_latency::total 8131.052684 # average overall miss latency 91711507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_avg_miss_latency::cpu.inst 8131.052684 # average overall miss latency 91811507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_avg_miss_latency::total 8131.052684 # average overall miss latency 91911507SCurtis.Dunham@arm.comsystem.cpu.icache.blocked_cycles::no_mshrs 75472 # number of cycles access was blocked 92011507SCurtis.Dunham@arm.comsystem.cpu.icache.blocked_cycles::no_targets 75 # number of cycles access was blocked 92111507SCurtis.Dunham@arm.comsystem.cpu.icache.blocked::no_mshrs 2912 # number of cycles access was blocked 92211507SCurtis.Dunham@arm.comsystem.cpu.icache.blocked::no_targets 5 # number of cycles access was blocked 92311507SCurtis.Dunham@arm.comsystem.cpu.icache.avg_blocked_cycles::no_mshrs 25.917582 # average number of cycles each access was blocked 92411507SCurtis.Dunham@arm.comsystem.cpu.icache.avg_blocked_cycles::no_targets 15 # average number of cycles each access was blocked 92511507SCurtis.Dunham@arm.comsystem.cpu.icache.writebacks::writebacks 1979880 # number of writebacks 92611507SCurtis.Dunham@arm.comsystem.cpu.icache.writebacks::total 1979880 # number of writebacks 92711507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_hits::cpu.inst 3014 # number of ReadReq MSHR hits 92811507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_hits::total 3014 # number of ReadReq MSHR hits 92911507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_hits::cpu.inst 3014 # number of demand (read+write) MSHR hits 93011507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_hits::total 3014 # number of demand (read+write) MSHR hits 93111507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_hits::cpu.inst 3014 # number of overall MSHR hits 93211507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_hits::total 3014 # number of overall MSHR hits 93311507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_misses::cpu.inst 1980577 # number of ReadReq MSHR misses 93411507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_misses::total 1980577 # number of ReadReq MSHR misses 93511507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_misses::cpu.inst 1980577 # number of demand (read+write) MSHR misses 93611507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_misses::total 1980577 # number of demand (read+write) MSHR misses 93711507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_misses::cpu.inst 1980577 # number of overall MSHR misses 93811507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_misses::total 1980577 # number of overall MSHR misses 93911507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15098139938 # number of ReadReq MSHR miss cycles 94011507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::total 15098139938 # number of ReadReq MSHR miss cycles 94111507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_miss_latency::cpu.inst 15098139938 # number of demand (read+write) MSHR miss cycles 94211507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_miss_latency::total 15098139938 # number of demand (read+write) MSHR miss cycles 94311507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_miss_latency::cpu.inst 15098139938 # number of overall MSHR miss cycles 94411507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_miss_latency::total 15098139938 # number of overall MSHR miss cycles 94511507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.007994 # mshr miss rate for ReadReq accesses 94611507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::total 0.007994 # mshr miss rate for ReadReq accesses 94711507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.007994 # mshr miss rate for demand accesses 94811507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_miss_rate::total 0.007994 # mshr miss rate for demand accesses 94911507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.007994 # mshr miss rate for overall accesses 95011507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_miss_rate::total 0.007994 # mshr miss rate for overall accesses 95111507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 7623.101721 # average ReadReq mshr miss latency 95211507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::total 7623.101721 # average ReadReq mshr miss latency 95311507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 7623.101721 # average overall mshr miss latency 95411507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::total 7623.101721 # average overall mshr miss latency 95511507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 7623.101721 # average overall mshr miss latency 95611507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::total 7623.101721 # average overall mshr miss latency 95711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.prefetcher.num_hwpf_issued 1350865 # number of hwpf issued 95811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.prefetcher.pfIdentified 1355053 # number of prefetch candidates identified 95911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.prefetcher.pfBufferHit 3664 # number of redundant prefetches already in prefetch queue 96011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 96111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 96211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.prefetcher.pfSpanPage 4790051 # number of prefetches not generated due to page crossing 96311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.replacements 301370 # number of replacements 96411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.tagsinuse 16350.432681 # Cycle average of tags in use 96511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.total_refs 7222107 # Total number of references to valid blocks. 96611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.sampled_refs 317734 # Sample count of references to valid blocks. 96711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.avg_refs 22.730041 # Average number of references to valid blocks. 96811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.warmup_cycle 44242160500 # Cycle when the warmup percentage was hit. 96911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_blocks::writebacks 9843.702780 # Average occupied blocks per requestor 97011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 6506.729901 # Average occupied blocks per requestor 97111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_percent::writebacks 0.600812 # Average percentage of cache occupancy 97211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.397139 # Average percentage of cache occupancy 97311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_percent::total 0.997951 # Average percentage of cache occupancy 97411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_task_id_blocks::1022 6334 # Occupied blocks per task id 97511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_task_id_blocks::1024 10030 # Occupied blocks per task id 97611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1022::1 17 # Occupied blocks per task id 97711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1022::2 193 # Occupied blocks per task id 97811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1022::3 1704 # Occupied blocks per task id 97911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1022::4 4420 # Occupied blocks per task id 98011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id 98111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::1 146 # Occupied blocks per task id 98211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::2 303 # Occupied blocks per task id 98311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::3 2583 # Occupied blocks per task id 98411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::4 6932 # Occupied blocks per task id 98511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_task_id_percent::1022 0.386597 # Percentage of cache occupancy per task id 98611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_task_id_percent::1024 0.612183 # Percentage of cache occupancy per task id 98711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.tag_accesses 142338236 # Number of tag accesses 98811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.data_accesses 142338236 # Number of data accesses 98911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackDirty_hits::writebacks 736314 # number of WritebackDirty hits 99011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackDirty_hits::total 736314 # number of WritebackDirty hits 99111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackClean_hits::writebacks 3356496 # number of WritebackClean hits 99211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackClean_hits::total 3356496 # number of WritebackClean hits 99311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_hits::cpu.data 718501 # number of ReadExReq hits 99411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_hits::total 718501 # number of ReadExReq hits 99511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1976843 # number of ReadCleanReq hits 99611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_hits::total 1976843 # number of ReadCleanReq hits 99711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_hits::cpu.data 1287256 # number of ReadSharedReq hits 99811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_hits::total 1287256 # number of ReadSharedReq hits 99911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_hits::cpu.inst 1976843 # number of demand (read+write) hits 100011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_hits::cpu.data 2005757 # number of demand (read+write) hits 100111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_hits::total 3982600 # number of demand (read+write) hits 100211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_hits::cpu.inst 1976843 # number of overall hits 100311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_hits::cpu.data 2005757 # number of overall hits 100411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_hits::total 3982600 # number of overall hits 100511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.UpgradeReq_misses::cpu.data 185 # number of UpgradeReq misses 100611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.UpgradeReq_misses::total 185 # number of UpgradeReq misses 100711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_misses::cpu.data 2346 # number of ReadExReq misses 100811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_misses::total 2346 # number of ReadExReq misses 100911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3550 # number of ReadCleanReq misses 101011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_misses::total 3550 # number of ReadCleanReq misses 101111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_misses::cpu.data 748861 # number of ReadSharedReq misses 101211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_misses::total 748861 # number of ReadSharedReq misses 101311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_misses::cpu.inst 3550 # number of demand (read+write) misses 101411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_misses::cpu.data 751207 # number of demand (read+write) misses 101511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_misses::total 754757 # number of demand (read+write) misses 101611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_misses::cpu.inst 3550 # number of overall misses 101711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_misses::cpu.data 751207 # number of overall misses 101811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_misses::total 754757 # number of overall misses 101911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::cpu.data 195074000 # number of ReadExReq miss cycles 102011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::total 195074000 # number of ReadExReq miss cycles 102111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 261372000 # number of ReadCleanReq miss cycles 102211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_latency::total 261372000 # number of ReadCleanReq miss cycles 102311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 51585571000 # number of ReadSharedReq miss cycles 102411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_latency::total 51585571000 # number of ReadSharedReq miss cycles 102511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.inst 261372000 # number of demand (read+write) miss cycles 102611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.data 51780645000 # number of demand (read+write) miss cycles 102711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_miss_latency::total 52042017000 # number of demand (read+write) miss cycles 102811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.inst 261372000 # number of overall miss cycles 102911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.data 51780645000 # number of overall miss cycles 103011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_miss_latency::total 52042017000 # number of overall miss cycles 103111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackDirty_accesses::writebacks 736314 # number of WritebackDirty accesses(hits+misses) 103211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackDirty_accesses::total 736314 # number of WritebackDirty accesses(hits+misses) 103311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackClean_accesses::writebacks 3356496 # number of WritebackClean accesses(hits+misses) 103411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackClean_accesses::total 3356496 # number of WritebackClean accesses(hits+misses) 103511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.UpgradeReq_accesses::cpu.data 185 # number of UpgradeReq accesses(hits+misses) 103611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.UpgradeReq_accesses::total 185 # number of UpgradeReq accesses(hits+misses) 103711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_accesses::cpu.data 720847 # number of ReadExReq accesses(hits+misses) 103811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_accesses::total 720847 # number of ReadExReq accesses(hits+misses) 103911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1980393 # number of ReadCleanReq accesses(hits+misses) 104011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_accesses::total 1980393 # number of ReadCleanReq accesses(hits+misses) 104111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_accesses::cpu.data 2036117 # number of ReadSharedReq accesses(hits+misses) 104211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_accesses::total 2036117 # number of ReadSharedReq accesses(hits+misses) 104311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_accesses::cpu.inst 1980393 # number of demand (read+write) accesses 104411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_accesses::cpu.data 2756964 # number of demand (read+write) accesses 104511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_accesses::total 4737357 # number of demand (read+write) accesses 104611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_accesses::cpu.inst 1980393 # number of overall (read+write) accesses 104711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_accesses::cpu.data 2756964 # number of overall (read+write) accesses 104811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_accesses::total 4737357 # number of overall (read+write) accesses 104911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses 105011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses 105111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.003255 # miss rate for ReadExReq accesses 105211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::total 0.003255 # miss rate for ReadExReq accesses 105311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.001793 # miss rate for ReadCleanReq accesses 105411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_rate::total 0.001793 # miss rate for ReadCleanReq accesses 105511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.367789 # miss rate for ReadSharedReq accesses 105611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_rate::total 0.367789 # miss rate for ReadSharedReq accesses 105711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.001793 # miss rate for demand accesses 105811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.data 0.272476 # miss rate for demand accesses 105911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_miss_rate::total 0.159320 # miss rate for demand accesses 106011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.001793 # miss rate for overall accesses 106111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.data 0.272476 # miss rate for overall accesses 106211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_miss_rate::total 0.159320 # miss rate for overall accesses 106311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 83151.747656 # average ReadExReq miss latency 106411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::total 83151.747656 # average ReadExReq miss latency 106511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 73625.915493 # average ReadCleanReq miss latency 106611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 73625.915493 # average ReadCleanReq miss latency 106711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 68885.375257 # average ReadSharedReq miss latency 106811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 68885.375257 # average ReadSharedReq miss latency 106911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73625.915493 # average overall miss latency 107011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.data 68929.928768 # average overall miss latency 107111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::total 68952.016344 # average overall miss latency 107211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73625.915493 # average overall miss latency 107311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.data 68929.928768 # average overall miss latency 107411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::total 68952.016344 # average overall miss latency 107511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 107611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 107711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 107811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 107911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 108011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 108111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.unused_prefetches 2695 # number of HardPF blocks evicted w/o reference 108211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.writebacks::writebacks 66334 # number of writebacks 108311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.writebacks::total 66334 # number of writebacks 108411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 963 # number of ReadExReq MSHR hits 108511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_mshr_hits::total 963 # number of ReadExReq MSHR hits 108611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits 108711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits 108811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 903 # number of ReadSharedReq MSHR hits 108911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_hits::total 903 # number of ReadSharedReq MSHR hits 109011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits 109111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_hits::cpu.data 1866 # number of demand (read+write) MSHR hits 109211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_hits::total 1867 # number of demand (read+write) MSHR hits 109311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits 109411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_hits::cpu.data 1866 # number of overall MSHR hits 109511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_hits::total 1867 # number of overall MSHR hits 109611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 200438 # number of HardPFReq MSHR misses 109711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.HardPFReq_mshr_misses::total 200438 # number of HardPFReq MSHR misses 109811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 185 # number of UpgradeReq MSHR misses 109911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_misses::total 185 # number of UpgradeReq MSHR misses 110011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1383 # number of ReadExReq MSHR misses 110111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_mshr_misses::total 1383 # number of ReadExReq MSHR misses 110211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3549 # number of ReadCleanReq MSHR misses 110311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_misses::total 3549 # number of ReadCleanReq MSHR misses 110411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 747958 # number of ReadSharedReq MSHR misses 110511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_misses::total 747958 # number of ReadSharedReq MSHR misses 110611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.inst 3549 # number of demand (read+write) MSHR misses 110711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.data 749341 # number of demand (read+write) MSHR misses 110811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_misses::total 752890 # number of demand (read+write) MSHR misses 110911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.inst 3549 # number of overall MSHR misses 111011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.data 749341 # number of overall MSHR misses 111111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 200438 # number of overall MSHR misses 111211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_misses::total 953328 # number of overall MSHR misses 111311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 16667426112 # number of HardPFReq MSHR miss cycles 111411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.HardPFReq_mshr_miss_latency::total 16667426112 # number of HardPFReq MSHR miss cycles 111511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 2605000 # number of UpgradeReq MSHR miss cycles 111611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 2605000 # number of UpgradeReq MSHR miss cycles 111711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 137246500 # number of ReadExReq MSHR miss cycles 111811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::total 137246500 # number of ReadExReq MSHR miss cycles 111911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 240029500 # number of ReadCleanReq MSHR miss cycles 112011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 240029500 # number of ReadCleanReq MSHR miss cycles 112111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 47054888500 # number of ReadSharedReq MSHR miss cycles 112211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 47054888500 # number of ReadSharedReq MSHR miss cycles 112311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 240029500 # number of demand (read+write) MSHR miss cycles 112411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.data 47192135000 # number of demand (read+write) MSHR miss cycles 112511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::total 47432164500 # number of demand (read+write) MSHR miss cycles 112611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 240029500 # number of overall MSHR miss cycles 112711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.data 47192135000 # number of overall MSHR miss cycles 112811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 16667426112 # number of overall MSHR miss cycles 112911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::total 64099590612 # number of overall MSHR miss cycles 113011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 113111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 113211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses 113311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses 113411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001919 # mshr miss rate for ReadExReq accesses 113511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001919 # mshr miss rate for ReadExReq accesses 113611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.001792 # mshr miss rate for ReadCleanReq accesses 113711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.001792 # mshr miss rate for ReadCleanReq accesses 113811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.367345 # mshr miss rate for ReadSharedReq accesses 113911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.367345 # mshr miss rate for ReadSharedReq accesses 114011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.001792 # mshr miss rate for demand accesses 114111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.271799 # mshr miss rate for demand accesses 114211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::total 0.158926 # mshr miss rate for demand accesses 114311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.001792 # mshr miss rate for overall accesses 114411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.271799 # mshr miss rate for overall accesses 114511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses 114611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::total 0.201236 # mshr miss rate for overall accesses 114711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 83155.021064 # average HardPFReq mshr miss latency 114811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 83155.021064 # average HardPFReq mshr miss latency 114911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14081.081081 # average UpgradeReq mshr miss latency 115011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14081.081081 # average UpgradeReq mshr miss latency 115111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 99238.250181 # average ReadExReq mshr miss latency 115211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 99238.250181 # average ReadExReq mshr miss latency 115311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67632.995210 # average ReadCleanReq mshr miss latency 115411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67632.995210 # average ReadCleanReq mshr miss latency 115511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 62911.137390 # average ReadSharedReq mshr miss latency 115611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 62911.137390 # average ReadSharedReq mshr miss latency 115711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67632.995210 # average overall mshr miss latency 115811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62978.183497 # average overall mshr miss latency 115911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::total 63000.125516 # average overall mshr miss latency 116011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67632.995210 # average overall mshr miss latency 116111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62978.183497 # average overall mshr miss latency 116211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 83155.021064 # average overall mshr miss latency 116311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::total 67237.708965 # average overall mshr miss latency 116411507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_filter.tot_requests 9474058 # Total number of requests made to the snoop filter. 116511507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_single_requests 4736544 # Number of requests hitting in the snoop filter with a single holder of the requested data. 116611507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_multi_requests 643707 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 116711507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_filter.tot_snoops 759527 # Total number of snoops made to the snoop filter. 116811507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_single_snoops 116739 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 116911507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_multi_snoops 642788 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 117011507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::ReadResp 4016692 # Transaction distribution 117111507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::WritebackDirty 802648 # Transaction distribution 117211507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::WritebackClean 4000018 # Transaction distribution 117311507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::CleanEvict 986541 # Transaction distribution 117411507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::HardPFReq 243725 # Transaction distribution 117511507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::UpgradeReq 185 # Transaction distribution 117611507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::UpgradeResp 185 # Transaction distribution 117711507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExReq 720847 # Transaction distribution 117811507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExResp 720847 # Transaction distribution 117911507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::ReadCleanReq 1980577 # Transaction distribution 118011507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::ReadSharedReq 2036117 # Transaction distribution 118111507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5940848 # Packet count per connected master and slave (bytes) 118211507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8270750 # Packet count per connected master and slave (bytes) 118311507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pkt_count::total 14211598 # Packet count per connected master and slave (bytes) 118411507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 253457344 # Cumulative packet size per connected master and slave (bytes) 118511507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 352858624 # Cumulative packet size per connected master and slave (bytes) 118611507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pkt_size::total 606315968 # Cumulative packet size per connected master and slave (bytes) 118711507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoops 1296784 # Total snoops (count) 118811507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::samples 6034326 # Request fanout histogram 118911507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::mean 0.339099 # Request fanout histogram 119011507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::stdev 0.661177 # Request fanout histogram 119111507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 119211507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::0 4630880 76.74% 76.74% # Request fanout histogram 119311507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::1 760658 12.61% 89.35% # Request fanout histogram 119411507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::2 642788 10.65% 100.00% # Request fanout histogram 119511507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 119611507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 119711507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 119811507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::total 6034326 # Request fanout histogram 119911507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.reqLayer0.occupancy 9473361000 # Layer occupancy (ticks) 120011507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.reqLayer0.utilization 2.9 # Layer utilization (%) 120111507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.respLayer0.occupancy 2970865494 # Layer occupancy (ticks) 120211507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.respLayer0.utilization 0.9 # Layer utilization (%) 120311507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.respLayer1.occupancy 4135548979 # Layer occupancy (ticks) 120411507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) 120511507SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadResp 951856 # Transaction distribution 120611507SCurtis.Dunham@arm.comsystem.membus.trans_dist::WritebackDirty 66334 # Transaction distribution 120711507SCurtis.Dunham@arm.comsystem.membus.trans_dist::CleanEvict 227102 # Transaction distribution 120811507SCurtis.Dunham@arm.comsystem.membus.trans_dist::UpgradeReq 185 # Transaction distribution 120911507SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadExReq 1383 # Transaction distribution 121011507SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadExResp 1383 # Transaction distribution 121111507SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadSharedReq 951857 # Transaction distribution 121211507SCurtis.Dunham@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2200100 # Packet count per connected master and slave (bytes) 121311507SCurtis.Dunham@arm.comsystem.membus.pkt_count::total 2200100 # Packet count per connected master and slave (bytes) 121411507SCurtis.Dunham@arm.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 65252672 # Cumulative packet size per connected master and slave (bytes) 121511507SCurtis.Dunham@arm.comsystem.membus.pkt_size::total 65252672 # Cumulative packet size per connected master and slave (bytes) 121611507SCurtis.Dunham@arm.comsystem.membus.snoops 0 # Total snoops (count) 121711507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::samples 1246861 # Request fanout histogram 121811507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::mean 0 # Request fanout histogram 121911507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::stdev 0 # Request fanout histogram 122011507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 122111507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::0 1246861 100.00% 100.00% # Request fanout histogram 122211507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 122311507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 122411507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::min_value 0 # Request fanout histogram 122511507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::max_value 0 # Request fanout histogram 122611507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::total 1246861 # Request fanout histogram 122711507SCurtis.Dunham@arm.comsystem.membus.reqLayer0.occupancy 1754485252 # Layer occupancy (ticks) 122811507SCurtis.Dunham@arm.comsystem.membus.reqLayer0.utilization 0.5 # Layer utilization (%) 122911507SCurtis.Dunham@arm.comsystem.membus.respLayer1.occupancy 5014122383 # Layer occupancy (ticks) 123011507SCurtis.Dunham@arm.comsystem.membus.respLayer1.utilization 1.5 # Layer utilization (%) 123111507SCurtis.Dunham@arm.com 123211507SCurtis.Dunham@arm.com---------- End Simulation Statistics ---------- 1233