config.ini revision 11103:38f6188421e0
1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=System 13children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain 17eventq_index=0 18init_param=0 19kernel= 20kernel_addr_check=true 21load_addr_mask=1099511627775 22load_offset=0 23mem_mode=timing 24mem_ranges= 25memories=system.physmem 26mmap_using_noreserve=false 27num_work_ids=16 28readfile= 29symbolfile= 30work_begin_ckpt_count=0 31work_begin_cpu_id_exit=-1 32work_begin_exit_count=0 33work_cpus_ckpt_count=0 34work_end_ckpt_count=0 35work_end_exit_count=0 36work_item_id=-1 37system_port=system.membus.slave[0] 38 39[system.clk_domain] 40type=SrcClockDomain 41clock=1000 42domain_id=-1 43eventq_index=0 44init_perf_level=0 45voltage_domain=system.voltage_domain 46 47[system.cpu] 48type=DerivO3CPU 49children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload 50LFSTSize=1024 51LQEntries=16 52LSQCheckLoads=true 53LSQDepCheckShift=0 54SQEntries=16 55SSITSize=1024 56activity=0 57backComSize=5 58branchPred=system.cpu.branchPred 59cachePorts=200 60checker=Null 61clk_domain=system.cpu_clk_domain 62commitToDecodeDelay=1 63commitToFetchDelay=1 64commitToIEWDelay=1 65commitToRenameDelay=1 66commitWidth=8 67cpu_id=0 68decodeToFetchDelay=1 69decodeToRenameDelay=2 70decodeWidth=3 71dispatchWidth=6 72do_checkpoint_insts=true 73do_quiesce=true 74do_statistics_insts=true 75dstage2_mmu=system.cpu.dstage2_mmu 76dtb=system.cpu.dtb 77eventq_index=0 78fetchBufferSize=16 79fetchQueueSize=32 80fetchToDecodeDelay=3 81fetchTrapLatency=1 82fetchWidth=3 83forwardComSize=5 84fuPool=system.cpu.fuPool 85function_trace=false 86function_trace_start=0 87iewToCommitDelay=1 88iewToDecodeDelay=1 89iewToFetchDelay=1 90iewToRenameDelay=1 91interrupts=system.cpu.interrupts 92isa=system.cpu.isa 93issueToExecuteDelay=1 94issueWidth=8 95istage2_mmu=system.cpu.istage2_mmu 96itb=system.cpu.itb 97max_insts_all_threads=0 98max_insts_any_thread=0 99max_loads_all_threads=0 100max_loads_any_thread=0 101needsTSO=false 102numIQEntries=32 103numPhysCCRegs=640 104numPhysFloatRegs=192 105numPhysIntRegs=128 106numROBEntries=40 107numRobs=1 108numThreads=1 109profile=0 110progress_interval=0 111renameToDecodeDelay=1 112renameToFetchDelay=1 113renameToIEWDelay=1 114renameToROBDelay=1 115renameWidth=3 116simpoint_start_insts= 117smtCommitPolicy=RoundRobin 118smtFetchPolicy=SingleThread 119smtIQPolicy=Partitioned 120smtIQThreshold=100 121smtLSQPolicy=Partitioned 122smtLSQThreshold=100 123smtNumFetchingThreads=1 124smtROBPolicy=Partitioned 125smtROBThreshold=100 126socket_id=0 127squashWidth=8 128store_set_clear_period=250000 129switched_out=false 130system=system 131tracer=system.cpu.tracer 132trapLatency=13 133wbWidth=8 134workload=system.cpu.workload 135dcache_port=system.cpu.dcache.cpu_side 136icache_port=system.cpu.icache.cpu_side 137 138[system.cpu.branchPred] 139type=BiModeBP 140BTBEntries=2048 141BTBTagSize=18 142RASSize=16 143choiceCtrBits=2 144choicePredictorSize=8192 145eventq_index=0 146globalCtrBits=2 147globalPredictorSize=8192 148instShiftAmt=2 149numThreads=1 150 151[system.cpu.dcache] 152type=Cache 153children=tags 154addr_ranges=0:18446744073709551615 155assoc=2 156clk_domain=system.cpu_clk_domain 157demand_mshr_reserve=1 158eventq_index=0 159forward_snoops=true 160hit_latency=2 161is_read_only=false 162max_miss_count=0 163mshrs=6 164prefetch_on_access=false 165prefetcher=Null 166response_latency=2 167sequential_access=false 168size=32768 169system=system 170tags=system.cpu.dcache.tags 171tgts_per_mshr=8 172write_buffers=16 173cpu_side=system.cpu.dcache_port 174mem_side=system.cpu.toL2Bus.slave[1] 175 176[system.cpu.dcache.tags] 177type=LRU 178assoc=2 179block_size=64 180clk_domain=system.cpu_clk_domain 181eventq_index=0 182hit_latency=2 183sequential_access=false 184size=32768 185 186[system.cpu.dstage2_mmu] 187type=ArmStage2MMU 188children=stage2_tlb 189eventq_index=0 190stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb 191sys=system 192tlb=system.cpu.dtb 193 194[system.cpu.dstage2_mmu.stage2_tlb] 195type=ArmTLB 196children=walker 197eventq_index=0 198is_stage2=true 199size=32 200walker=system.cpu.dstage2_mmu.stage2_tlb.walker 201 202[system.cpu.dstage2_mmu.stage2_tlb.walker] 203type=ArmTableWalker 204clk_domain=system.cpu_clk_domain 205eventq_index=0 206is_stage2=true 207num_squash_per_cycle=2 208sys=system 209 210[system.cpu.dtb] 211type=ArmTLB 212children=walker 213eventq_index=0 214is_stage2=false 215size=64 216walker=system.cpu.dtb.walker 217 218[system.cpu.dtb.walker] 219type=ArmTableWalker 220clk_domain=system.cpu_clk_domain 221eventq_index=0 222is_stage2=false 223num_squash_per_cycle=2 224sys=system 225port=system.cpu.toL2Bus.slave[3] 226 227[system.cpu.fuPool] 228type=FUPool 229children=FUList0 FUList1 FUList2 FUList3 FUList4 230FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 231eventq_index=0 232 233[system.cpu.fuPool.FUList0] 234type=FUDesc 235children=opList 236count=2 237eventq_index=0 238opList=system.cpu.fuPool.FUList0.opList 239 240[system.cpu.fuPool.FUList0.opList] 241type=OpDesc 242eventq_index=0 243opClass=IntAlu 244opLat=1 245pipelined=true 246 247[system.cpu.fuPool.FUList1] 248type=FUDesc 249children=opList0 opList1 opList2 250count=1 251eventq_index=0 252opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 system.cpu.fuPool.FUList1.opList2 253 254[system.cpu.fuPool.FUList1.opList0] 255type=OpDesc 256eventq_index=0 257opClass=IntMult 258opLat=3 259pipelined=true 260 261[system.cpu.fuPool.FUList1.opList1] 262type=OpDesc 263eventq_index=0 264opClass=IntDiv 265opLat=12 266pipelined=false 267 268[system.cpu.fuPool.FUList1.opList2] 269type=OpDesc 270eventq_index=0 271opClass=IprAccess 272opLat=3 273pipelined=true 274 275[system.cpu.fuPool.FUList2] 276type=FUDesc 277children=opList 278count=1 279eventq_index=0 280opList=system.cpu.fuPool.FUList2.opList 281 282[system.cpu.fuPool.FUList2.opList] 283type=OpDesc 284eventq_index=0 285opClass=MemRead 286opLat=2 287pipelined=true 288 289[system.cpu.fuPool.FUList3] 290type=FUDesc 291children=opList 292count=1 293eventq_index=0 294opList=system.cpu.fuPool.FUList3.opList 295 296[system.cpu.fuPool.FUList3.opList] 297type=OpDesc 298eventq_index=0 299opClass=MemWrite 300opLat=2 301pipelined=true 302 303[system.cpu.fuPool.FUList4] 304type=FUDesc 305children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25 306count=2 307eventq_index=0 308opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 system.cpu.fuPool.FUList4.opList02 system.cpu.fuPool.FUList4.opList03 system.cpu.fuPool.FUList4.opList04 system.cpu.fuPool.FUList4.opList05 system.cpu.fuPool.FUList4.opList06 system.cpu.fuPool.FUList4.opList07 system.cpu.fuPool.FUList4.opList08 system.cpu.fuPool.FUList4.opList09 system.cpu.fuPool.FUList4.opList10 system.cpu.fuPool.FUList4.opList11 system.cpu.fuPool.FUList4.opList12 system.cpu.fuPool.FUList4.opList13 system.cpu.fuPool.FUList4.opList14 system.cpu.fuPool.FUList4.opList15 system.cpu.fuPool.FUList4.opList16 system.cpu.fuPool.FUList4.opList17 system.cpu.fuPool.FUList4.opList18 system.cpu.fuPool.FUList4.opList19 system.cpu.fuPool.FUList4.opList20 system.cpu.fuPool.FUList4.opList21 system.cpu.fuPool.FUList4.opList22 system.cpu.fuPool.FUList4.opList23 system.cpu.fuPool.FUList4.opList24 system.cpu.fuPool.FUList4.opList25 309 310[system.cpu.fuPool.FUList4.opList00] 311type=OpDesc 312eventq_index=0 313opClass=SimdAdd 314opLat=4 315pipelined=true 316 317[system.cpu.fuPool.FUList4.opList01] 318type=OpDesc 319eventq_index=0 320opClass=SimdAddAcc 321opLat=4 322pipelined=true 323 324[system.cpu.fuPool.FUList4.opList02] 325type=OpDesc 326eventq_index=0 327opClass=SimdAlu 328opLat=4 329pipelined=true 330 331[system.cpu.fuPool.FUList4.opList03] 332type=OpDesc 333eventq_index=0 334opClass=SimdCmp 335opLat=4 336pipelined=true 337 338[system.cpu.fuPool.FUList4.opList04] 339type=OpDesc 340eventq_index=0 341opClass=SimdCvt 342opLat=3 343pipelined=true 344 345[system.cpu.fuPool.FUList4.opList05] 346type=OpDesc 347eventq_index=0 348opClass=SimdMisc 349opLat=3 350pipelined=true 351 352[system.cpu.fuPool.FUList4.opList06] 353type=OpDesc 354eventq_index=0 355opClass=SimdMult 356opLat=5 357pipelined=true 358 359[system.cpu.fuPool.FUList4.opList07] 360type=OpDesc 361eventq_index=0 362opClass=SimdMultAcc 363opLat=5 364pipelined=true 365 366[system.cpu.fuPool.FUList4.opList08] 367type=OpDesc 368eventq_index=0 369opClass=SimdShift 370opLat=3 371pipelined=true 372 373[system.cpu.fuPool.FUList4.opList09] 374type=OpDesc 375eventq_index=0 376opClass=SimdShiftAcc 377opLat=3 378pipelined=true 379 380[system.cpu.fuPool.FUList4.opList10] 381type=OpDesc 382eventq_index=0 383opClass=SimdSqrt 384opLat=9 385pipelined=true 386 387[system.cpu.fuPool.FUList4.opList11] 388type=OpDesc 389eventq_index=0 390opClass=SimdFloatAdd 391opLat=5 392pipelined=true 393 394[system.cpu.fuPool.FUList4.opList12] 395type=OpDesc 396eventq_index=0 397opClass=SimdFloatAlu 398opLat=5 399pipelined=true 400 401[system.cpu.fuPool.FUList4.opList13] 402type=OpDesc 403eventq_index=0 404opClass=SimdFloatCmp 405opLat=3 406pipelined=true 407 408[system.cpu.fuPool.FUList4.opList14] 409type=OpDesc 410eventq_index=0 411opClass=SimdFloatCvt 412opLat=3 413pipelined=true 414 415[system.cpu.fuPool.FUList4.opList15] 416type=OpDesc 417eventq_index=0 418opClass=SimdFloatDiv 419opLat=3 420pipelined=true 421 422[system.cpu.fuPool.FUList4.opList16] 423type=OpDesc 424eventq_index=0 425opClass=SimdFloatMisc 426opLat=3 427pipelined=true 428 429[system.cpu.fuPool.FUList4.opList17] 430type=OpDesc 431eventq_index=0 432opClass=SimdFloatMult 433opLat=3 434pipelined=true 435 436[system.cpu.fuPool.FUList4.opList18] 437type=OpDesc 438eventq_index=0 439opClass=SimdFloatMultAcc 440opLat=1 441pipelined=true 442 443[system.cpu.fuPool.FUList4.opList19] 444type=OpDesc 445eventq_index=0 446opClass=SimdFloatSqrt 447opLat=9 448pipelined=true 449 450[system.cpu.fuPool.FUList4.opList20] 451type=OpDesc 452eventq_index=0 453opClass=FloatAdd 454opLat=5 455pipelined=true 456 457[system.cpu.fuPool.FUList4.opList21] 458type=OpDesc 459eventq_index=0 460opClass=FloatCmp 461opLat=5 462pipelined=true 463 464[system.cpu.fuPool.FUList4.opList22] 465type=OpDesc 466eventq_index=0 467opClass=FloatCvt 468opLat=5 469pipelined=true 470 471[system.cpu.fuPool.FUList4.opList23] 472type=OpDesc 473eventq_index=0 474opClass=FloatDiv 475opLat=9 476pipelined=false 477 478[system.cpu.fuPool.FUList4.opList24] 479type=OpDesc 480eventq_index=0 481opClass=FloatSqrt 482opLat=33 483pipelined=false 484 485[system.cpu.fuPool.FUList4.opList25] 486type=OpDesc 487eventq_index=0 488opClass=FloatMult 489opLat=4 490pipelined=true 491 492[system.cpu.icache] 493type=Cache 494children=tags 495addr_ranges=0:18446744073709551615 496assoc=2 497clk_domain=system.cpu_clk_domain 498demand_mshr_reserve=1 499eventq_index=0 500forward_snoops=false 501hit_latency=1 502is_read_only=true 503max_miss_count=0 504mshrs=2 505prefetch_on_access=false 506prefetcher=Null 507response_latency=1 508sequential_access=false 509size=32768 510system=system 511tags=system.cpu.icache.tags 512tgts_per_mshr=8 513write_buffers=8 514cpu_side=system.cpu.icache_port 515mem_side=system.cpu.toL2Bus.slave[0] 516 517[system.cpu.icache.tags] 518type=LRU 519assoc=2 520block_size=64 521clk_domain=system.cpu_clk_domain 522eventq_index=0 523hit_latency=1 524sequential_access=false 525size=32768 526 527[system.cpu.interrupts] 528type=ArmInterrupts 529eventq_index=0 530 531[system.cpu.isa] 532type=ArmISA 533eventq_index=0 534fpsid=1090793632 535id_aa64afr0_el1=0 536id_aa64afr1_el1=0 537id_aa64dfr0_el1=1052678 538id_aa64dfr1_el1=0 539id_aa64isar0_el1=0 540id_aa64isar1_el1=0 541id_aa64mmfr0_el1=15728642 542id_aa64mmfr1_el1=0 543id_aa64pfr0_el1=17 544id_aa64pfr1_el1=0 545id_isar0=34607377 546id_isar1=34677009 547id_isar2=555950401 548id_isar3=17899825 549id_isar4=268501314 550id_isar5=0 551id_mmfr0=270536963 552id_mmfr1=0 553id_mmfr2=19070976 554id_mmfr3=34611729 555id_pfr0=49 556id_pfr1=4113 557midr=1091551472 558pmu=Null 559system=system 560 561[system.cpu.istage2_mmu] 562type=ArmStage2MMU 563children=stage2_tlb 564eventq_index=0 565stage2_tlb=system.cpu.istage2_mmu.stage2_tlb 566sys=system 567tlb=system.cpu.itb 568 569[system.cpu.istage2_mmu.stage2_tlb] 570type=ArmTLB 571children=walker 572eventq_index=0 573is_stage2=true 574size=32 575walker=system.cpu.istage2_mmu.stage2_tlb.walker 576 577[system.cpu.istage2_mmu.stage2_tlb.walker] 578type=ArmTableWalker 579clk_domain=system.cpu_clk_domain 580eventq_index=0 581is_stage2=true 582num_squash_per_cycle=2 583sys=system 584 585[system.cpu.itb] 586type=ArmTLB 587children=walker 588eventq_index=0 589is_stage2=false 590size=64 591walker=system.cpu.itb.walker 592 593[system.cpu.itb.walker] 594type=ArmTableWalker 595clk_domain=system.cpu_clk_domain 596eventq_index=0 597is_stage2=false 598num_squash_per_cycle=2 599sys=system 600port=system.cpu.toL2Bus.slave[2] 601 602[system.cpu.l2cache] 603type=Cache 604children=prefetcher tags 605addr_ranges=0:18446744073709551615 606assoc=16 607clk_domain=system.cpu_clk_domain 608demand_mshr_reserve=1 609eventq_index=0 610forward_snoops=true 611hit_latency=12 612is_read_only=false 613max_miss_count=0 614mshrs=16 615prefetch_on_access=true 616prefetcher=system.cpu.l2cache.prefetcher 617response_latency=12 618sequential_access=false 619size=1048576 620system=system 621tags=system.cpu.l2cache.tags 622tgts_per_mshr=8 623write_buffers=8 624cpu_side=system.cpu.toL2Bus.master[0] 625mem_side=system.membus.slave[1] 626 627[system.cpu.l2cache.prefetcher] 628type=StridePrefetcher 629cache_snoop=false 630clk_domain=system.cpu_clk_domain 631degree=8 632eventq_index=0 633latency=1 634max_conf=7 635min_conf=0 636on_data=true 637on_inst=true 638on_miss=false 639on_read=true 640on_write=true 641queue_filter=true 642queue_size=32 643queue_squash=true 644start_conf=4 645sys=system 646table_assoc=4 647table_sets=16 648tag_prefetch=true 649thresh_conf=4 650use_master_id=true 651 652[system.cpu.l2cache.tags] 653type=RandomRepl 654assoc=16 655block_size=64 656clk_domain=system.cpu_clk_domain 657eventq_index=0 658hit_latency=12 659sequential_access=false 660size=1048576 661 662[system.cpu.toL2Bus] 663type=CoherentXBar 664clk_domain=system.cpu_clk_domain 665eventq_index=0 666forward_latency=0 667frontend_latency=1 668response_latency=1 669snoop_filter=Null 670snoop_response_latency=1 671system=system 672use_default_range=false 673width=32 674master=system.cpu.l2cache.cpu_side 675slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port 676 677[system.cpu.tracer] 678type=ExeTracer 679eventq_index=0 680 681[system.cpu.workload] 682type=LiveProcess 683cmd=perlbmk -I. -I lib mdred.makerand.pl 684cwd=build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing 685drivers= 686egid=100 687env= 688errout=cerr 689euid=100 690eventq_index=0 691executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/perlbmk 692gid=100 693input=cin 694kvmInSE=false 695max_stack_size=67108864 696output=cout 697pid=100 698ppid=99 699simpoint=0 700system=system 701uid=100 702useArchPT=false 703 704[system.cpu_clk_domain] 705type=SrcClockDomain 706clock=500 707domain_id=-1 708eventq_index=0 709init_perf_level=0 710voltage_domain=system.voltage_domain 711 712[system.dvfs_handler] 713type=DVFSHandler 714domains= 715enable=false 716eventq_index=0 717sys_clk_domain=system.clk_domain 718transition_latency=100000000 719 720[system.membus] 721type=CoherentXBar 722clk_domain=system.clk_domain 723eventq_index=0 724forward_latency=4 725frontend_latency=3 726response_latency=2 727snoop_filter=Null 728snoop_response_latency=4 729system=system 730use_default_range=false 731width=16 732master=system.physmem.port 733slave=system.system_port system.cpu.l2cache.mem_side 734 735[system.physmem] 736type=DRAMCtrl 737IDD0=0.075000 738IDD02=0.000000 739IDD2N=0.050000 740IDD2N2=0.000000 741IDD2P0=0.000000 742IDD2P02=0.000000 743IDD2P1=0.000000 744IDD2P12=0.000000 745IDD3N=0.057000 746IDD3N2=0.000000 747IDD3P0=0.000000 748IDD3P02=0.000000 749IDD3P1=0.000000 750IDD3P12=0.000000 751IDD4R=0.187000 752IDD4R2=0.000000 753IDD4W=0.165000 754IDD4W2=0.000000 755IDD5=0.220000 756IDD52=0.000000 757IDD6=0.000000 758IDD62=0.000000 759VDD=1.500000 760VDD2=0.000000 761activation_limit=4 762addr_mapping=RoRaBaCoCh 763bank_groups_per_rank=0 764banks_per_rank=8 765burst_length=8 766channels=1 767clk_domain=system.clk_domain 768conf_table_reported=true 769device_bus_width=8 770device_rowbuffer_size=1024 771device_size=536870912 772devices_per_rank=8 773dll=true 774eventq_index=0 775in_addr_map=true 776max_accesses_per_row=16 777mem_sched_policy=frfcfs 778min_writes_per_switch=16 779null=false 780page_policy=open_adaptive 781range=0:134217727 782ranks_per_channel=2 783read_buffer_size=32 784static_backend_latency=10000 785static_frontend_latency=10000 786tBURST=5000 787tCCD_L=0 788tCK=1250 789tCL=13750 790tCS=2500 791tRAS=35000 792tRCD=13750 793tREFI=7800000 794tRFC=260000 795tRP=13750 796tRRD=6000 797tRRD_L=0 798tRTP=7500 799tRTW=2500 800tWR=15000 801tWTR=7500 802tXAW=30000 803tXP=0 804tXPDLL=0 805tXS=0 806tXSDLL=0 807write_buffer_size=64 808write_high_thresh_perc=85 809write_low_thresh_perc=50 810port=system.membus.master[0] 811 812[system.voltage_domain] 813type=VoltageDomain 814eventq_index=0 815voltage=1.000000 816 817