config.ini revision 9265
17860SN/A[root]
27860SN/Atype=Root
37860SN/Achildren=system
48825Snilay@cs.wisc.edufull_system=false
57935SN/Atime_sync_enable=false
67935SN/Atime_sync_period=100000000000
77935SN/Atime_sync_spin_threshold=100000000
87860SN/A
97860SN/A[system]
107860SN/Atype=System
117860SN/Achildren=cpu membus physmem
128825Snilay@cs.wisc.eduboot_osflags=a
139265SAli.Saidi@ARM.comclock=1
148825Snilay@cs.wisc.eduinit_param=0
158825Snilay@cs.wisc.edukernel=
168825Snilay@cs.wisc.eduload_addr_mask=1099511627775
177860SN/Amem_mode=atomic
188464SN/Amemories=system.physmem
198721SN/Anum_work_ids=16
208825Snilay@cs.wisc.edureadfile=
218825Snilay@cs.wisc.edusymbolfile=
227935SN/Awork_begin_ckpt_count=0
237935SN/Awork_begin_cpu_id_exit=-1
247935SN/Awork_begin_exit_count=0
257935SN/Awork_cpus_ckpt_count=0
267935SN/Awork_end_ckpt_count=0
277935SN/Awork_end_exit_count=0
287935SN/Awork_item_id=-1
298893Ssaidi@eecs.umich.edusystem_port=system.membus.slave[0]
307860SN/A
317860SN/A[system.cpu]
327860SN/Atype=DerivO3CPU
338825Snilay@cs.wisc.educhildren=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
347860SN/ABTBEntries=4096
357860SN/ABTBTagSize=16
367860SN/ALFSTSize=1024
377860SN/ALQEntries=32
388210SN/ALSQCheckLoads=true
398210SN/ALSQDepCheckShift=4
407860SN/ARASSize=16
417860SN/ASQEntries=32
427860SN/ASSITSize=1024
437860SN/Aactivity=0
447860SN/AbackComSize=5
457860SN/AcachePorts=200
467860SN/Achecker=Null
477860SN/AchoiceCtrBits=2
487860SN/AchoicePredictorSize=8192
497860SN/Aclock=500
507860SN/AcommitToDecodeDelay=1
517860SN/AcommitToFetchDelay=1
527860SN/AcommitToIEWDelay=1
537860SN/AcommitToRenameDelay=1
547860SN/AcommitWidth=8
557860SN/Acpu_id=0
567860SN/AdecodeToFetchDelay=1
577860SN/AdecodeToRenameDelay=1
587860SN/AdecodeWidth=8
597860SN/Adefer_registration=false
607860SN/AdispatchWidth=8
617860SN/Ado_checkpoint_insts=true
628825Snilay@cs.wisc.edudo_quiesce=true
637860SN/Ado_statistics_insts=true
647860SN/Adtb=system.cpu.dtb
657860SN/AfetchToDecodeDelay=1
667860SN/AfetchTrapLatency=1
677860SN/AfetchWidth=8
687860SN/AforwardComSize=5
697860SN/AfuPool=system.cpu.fuPool
707860SN/Afunction_trace=false
717860SN/Afunction_trace_start=0
727860SN/AglobalCtrBits=2
737860SN/AglobalHistoryBits=13
747860SN/AglobalPredictorSize=8192
757860SN/AiewToCommitDelay=1
767860SN/AiewToDecodeDelay=1
777860SN/AiewToFetchDelay=1
787860SN/AiewToRenameDelay=1
797860SN/AinstShiftAmt=2
808825Snilay@cs.wisc.eduinterrupts=system.cpu.interrupts
817860SN/AissueToExecuteDelay=1
827860SN/AissueWidth=8
837860SN/Aitb=system.cpu.itb
847860SN/AlocalCtrBits=2
857860SN/AlocalHistoryBits=11
867860SN/AlocalHistoryTableSize=2048
877860SN/AlocalPredictorSize=2048
887860SN/Amax_insts_all_threads=0
897860SN/Amax_insts_any_thread=0
907860SN/Amax_loads_all_threads=0
917860SN/Amax_loads_any_thread=0
928825Snilay@cs.wisc.eduneedsTSO=false
937860SN/AnumIQEntries=64
947860SN/AnumPhysFloatRegs=256
957860SN/AnumPhysIntRegs=256
967860SN/AnumROBEntries=192
977860SN/AnumRobs=1
987860SN/AnumThreads=1
997860SN/ApredType=tournament
1008825Snilay@cs.wisc.eduprofile=0
1017860SN/Aprogress_interval=0
1027860SN/ArenameToDecodeDelay=1
1037860SN/ArenameToFetchDelay=1
1047860SN/ArenameToIEWDelay=2
1057860SN/ArenameToROBDelay=1
1067860SN/ArenameWidth=8
1077860SN/AsmtCommitPolicy=RoundRobin
1087860SN/AsmtFetchPolicy=SingleThread
1097860SN/AsmtIQPolicy=Partitioned
1107860SN/AsmtIQThreshold=100
1117860SN/AsmtLSQPolicy=Partitioned
1127860SN/AsmtLSQThreshold=100
1137860SN/AsmtNumFetchingThreads=1
1147860SN/AsmtROBPolicy=Partitioned
1157860SN/AsmtROBThreshold=100
1167860SN/AsquashWidth=8
1178521SN/Astore_set_clear_period=250000
1187860SN/Asystem=system
1197860SN/Atracer=system.cpu.tracer
1207860SN/AtrapLatency=13
1217860SN/AwbDepth=1
1227860SN/AwbWidth=8
1237860SN/Aworkload=system.cpu.workload
1247860SN/Adcache_port=system.cpu.dcache.cpu_side
1257860SN/Aicache_port=system.cpu.icache.cpu_side
1267860SN/A
1277860SN/A[system.cpu.dcache]
1287860SN/Atype=BaseCache
1298893Ssaidi@eecs.umich.eduaddr_ranges=0:18446744073709551615
1307860SN/Aassoc=2
1317860SN/Ablock_size=64
1329265SAli.Saidi@ARM.comclock=1
1337860SN/Aforward_snoops=true
1347860SN/Ahash_delay=1
1359265SAli.Saidi@ARM.comhit_latency=1000
1368150SN/Ais_top_level=true
1377860SN/Amax_miss_count=0
1387860SN/Amshrs=10
1397860SN/Aprefetch_on_access=false
1408835SAli.Saidi@ARM.comprefetcher=Null
1417860SN/AprioritizeRequests=false
1427860SN/Arepl=Null
1439265SAli.Saidi@ARM.comresponse_latency=1000
1447860SN/Asize=262144
1457860SN/Asubblock_size=0
1468835SAli.Saidi@ARM.comsystem=system
1477860SN/Atgts_per_mshr=20
1487860SN/Atrace_addr=0
1497860SN/Atwo_queue=false
1507860SN/Awrite_buffers=8
1517860SN/Acpu_side=system.cpu.dcache_port
1528893Ssaidi@eecs.umich.edumem_side=system.cpu.toL2Bus.slave[1]
1537860SN/A
1547860SN/A[system.cpu.dtb]
1557860SN/Atype=ArmTLB
1568825Snilay@cs.wisc.educhildren=walker
1577860SN/Asize=64
1588825Snilay@cs.wisc.eduwalker=system.cpu.dtb.walker
1598825Snilay@cs.wisc.edu
1608825Snilay@cs.wisc.edu[system.cpu.dtb.walker]
1618825Snilay@cs.wisc.edutype=ArmTableWalker
1629265SAli.Saidi@ARM.comclock=1
1639265SAli.Saidi@ARM.comnum_squash_per_cycle=2
1648825Snilay@cs.wisc.edusys=system
1658893Ssaidi@eecs.umich.eduport=system.cpu.toL2Bus.slave[3]
1667860SN/A
1677860SN/A[system.cpu.fuPool]
1687860SN/Atype=FUPool
1697860SN/Achildren=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
1707860SN/AFUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
1717860SN/A
1727860SN/A[system.cpu.fuPool.FUList0]
1737860SN/Atype=FUDesc
1747860SN/Achildren=opList
1757860SN/Acount=6
1767860SN/AopList=system.cpu.fuPool.FUList0.opList
1777860SN/A
1787860SN/A[system.cpu.fuPool.FUList0.opList]
1797860SN/Atype=OpDesc
1807860SN/AissueLat=1
1817860SN/AopClass=IntAlu
1827860SN/AopLat=1
1837860SN/A
1847860SN/A[system.cpu.fuPool.FUList1]
1857860SN/Atype=FUDesc
1867860SN/Achildren=opList0 opList1
1877860SN/Acount=2
1887860SN/AopList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
1897860SN/A
1907860SN/A[system.cpu.fuPool.FUList1.opList0]
1917860SN/Atype=OpDesc
1927860SN/AissueLat=1
1937860SN/AopClass=IntMult
1947860SN/AopLat=3
1957860SN/A
1967860SN/A[system.cpu.fuPool.FUList1.opList1]
1977860SN/Atype=OpDesc
1987860SN/AissueLat=19
1997860SN/AopClass=IntDiv
2007860SN/AopLat=20
2017860SN/A
2027860SN/A[system.cpu.fuPool.FUList2]
2037860SN/Atype=FUDesc
2047860SN/Achildren=opList0 opList1 opList2
2057860SN/Acount=4
2067860SN/AopList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
2077860SN/A
2087860SN/A[system.cpu.fuPool.FUList2.opList0]
2097860SN/Atype=OpDesc
2107860SN/AissueLat=1
2117860SN/AopClass=FloatAdd
2127860SN/AopLat=2
2137860SN/A
2147860SN/A[system.cpu.fuPool.FUList2.opList1]
2157860SN/Atype=OpDesc
2167860SN/AissueLat=1
2177860SN/AopClass=FloatCmp
2187860SN/AopLat=2
2197860SN/A
2207860SN/A[system.cpu.fuPool.FUList2.opList2]
2217860SN/Atype=OpDesc
2227860SN/AissueLat=1
2237860SN/AopClass=FloatCvt
2247860SN/AopLat=2
2257860SN/A
2267860SN/A[system.cpu.fuPool.FUList3]
2277860SN/Atype=FUDesc
2287860SN/Achildren=opList0 opList1 opList2
2297860SN/Acount=2
2307860SN/AopList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
2317860SN/A
2327860SN/A[system.cpu.fuPool.FUList3.opList0]
2337860SN/Atype=OpDesc
2347860SN/AissueLat=1
2357860SN/AopClass=FloatMult
2367860SN/AopLat=4
2377860SN/A
2387860SN/A[system.cpu.fuPool.FUList3.opList1]
2397860SN/Atype=OpDesc
2407860SN/AissueLat=12
2417860SN/AopClass=FloatDiv
2427860SN/AopLat=12
2437860SN/A
2447860SN/A[system.cpu.fuPool.FUList3.opList2]
2457860SN/Atype=OpDesc
2467860SN/AissueLat=24
2477860SN/AopClass=FloatSqrt
2487860SN/AopLat=24
2497860SN/A
2507860SN/A[system.cpu.fuPool.FUList4]
2517860SN/Atype=FUDesc
2527860SN/Achildren=opList
2537860SN/Acount=0
2547860SN/AopList=system.cpu.fuPool.FUList4.opList
2557860SN/A
2567860SN/A[system.cpu.fuPool.FUList4.opList]
2577860SN/Atype=OpDesc
2587860SN/AissueLat=1
2597860SN/AopClass=MemRead
2607860SN/AopLat=1
2617860SN/A
2627860SN/A[system.cpu.fuPool.FUList5]
2637860SN/Atype=FUDesc
2647860SN/Achildren=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
2657860SN/Acount=4
2667860SN/AopList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
2677860SN/A
2687860SN/A[system.cpu.fuPool.FUList5.opList00]
2697860SN/Atype=OpDesc
2707860SN/AissueLat=1
2717860SN/AopClass=SimdAdd
2727860SN/AopLat=1
2737860SN/A
2747860SN/A[system.cpu.fuPool.FUList5.opList01]
2757860SN/Atype=OpDesc
2767860SN/AissueLat=1
2777860SN/AopClass=SimdAddAcc
2787860SN/AopLat=1
2797860SN/A
2807860SN/A[system.cpu.fuPool.FUList5.opList02]
2817860SN/Atype=OpDesc
2827860SN/AissueLat=1
2837860SN/AopClass=SimdAlu
2847860SN/AopLat=1
2857860SN/A
2867860SN/A[system.cpu.fuPool.FUList5.opList03]
2877860SN/Atype=OpDesc
2887860SN/AissueLat=1
2897860SN/AopClass=SimdCmp
2907860SN/AopLat=1
2917860SN/A
2927860SN/A[system.cpu.fuPool.FUList5.opList04]
2937860SN/Atype=OpDesc
2947860SN/AissueLat=1
2957860SN/AopClass=SimdCvt
2967860SN/AopLat=1
2977860SN/A
2987860SN/A[system.cpu.fuPool.FUList5.opList05]
2997860SN/Atype=OpDesc
3007860SN/AissueLat=1
3017860SN/AopClass=SimdMisc
3027860SN/AopLat=1
3037860SN/A
3047860SN/A[system.cpu.fuPool.FUList5.opList06]
3057860SN/Atype=OpDesc
3067860SN/AissueLat=1
3077860SN/AopClass=SimdMult
3087860SN/AopLat=1
3097860SN/A
3107860SN/A[system.cpu.fuPool.FUList5.opList07]
3117860SN/Atype=OpDesc
3127860SN/AissueLat=1
3137860SN/AopClass=SimdMultAcc
3147860SN/AopLat=1
3157860SN/A
3167860SN/A[system.cpu.fuPool.FUList5.opList08]
3177860SN/Atype=OpDesc
3187860SN/AissueLat=1
3197860SN/AopClass=SimdShift
3207860SN/AopLat=1
3217860SN/A
3227860SN/A[system.cpu.fuPool.FUList5.opList09]
3237860SN/Atype=OpDesc
3247860SN/AissueLat=1
3257860SN/AopClass=SimdShiftAcc
3267860SN/AopLat=1
3277860SN/A
3287860SN/A[system.cpu.fuPool.FUList5.opList10]
3297860SN/Atype=OpDesc
3307860SN/AissueLat=1
3317860SN/AopClass=SimdSqrt
3327860SN/AopLat=1
3337860SN/A
3347860SN/A[system.cpu.fuPool.FUList5.opList11]
3357860SN/Atype=OpDesc
3367860SN/AissueLat=1
3377860SN/AopClass=SimdFloatAdd
3387860SN/AopLat=1
3397860SN/A
3407860SN/A[system.cpu.fuPool.FUList5.opList12]
3417860SN/Atype=OpDesc
3427860SN/AissueLat=1
3437860SN/AopClass=SimdFloatAlu
3447860SN/AopLat=1
3457860SN/A
3467860SN/A[system.cpu.fuPool.FUList5.opList13]
3477860SN/Atype=OpDesc
3487860SN/AissueLat=1
3497860SN/AopClass=SimdFloatCmp
3507860SN/AopLat=1
3517860SN/A
3527860SN/A[system.cpu.fuPool.FUList5.opList14]
3537860SN/Atype=OpDesc
3547860SN/AissueLat=1
3557860SN/AopClass=SimdFloatCvt
3567860SN/AopLat=1
3577860SN/A
3587860SN/A[system.cpu.fuPool.FUList5.opList15]
3597860SN/Atype=OpDesc
3607860SN/AissueLat=1
3617860SN/AopClass=SimdFloatDiv
3627860SN/AopLat=1
3637860SN/A
3647860SN/A[system.cpu.fuPool.FUList5.opList16]
3657860SN/Atype=OpDesc
3667860SN/AissueLat=1
3677860SN/AopClass=SimdFloatMisc
3687860SN/AopLat=1
3697860SN/A
3707860SN/A[system.cpu.fuPool.FUList5.opList17]
3717860SN/Atype=OpDesc
3727860SN/AissueLat=1
3737860SN/AopClass=SimdFloatMult
3747860SN/AopLat=1
3757860SN/A
3767860SN/A[system.cpu.fuPool.FUList5.opList18]
3777860SN/Atype=OpDesc
3787860SN/AissueLat=1
3797860SN/AopClass=SimdFloatMultAcc
3807860SN/AopLat=1
3817860SN/A
3827860SN/A[system.cpu.fuPool.FUList5.opList19]
3837860SN/Atype=OpDesc
3847860SN/AissueLat=1
3857860SN/AopClass=SimdFloatSqrt
3867860SN/AopLat=1
3877860SN/A
3887860SN/A[system.cpu.fuPool.FUList6]
3897860SN/Atype=FUDesc
3907860SN/Achildren=opList
3917860SN/Acount=0
3927860SN/AopList=system.cpu.fuPool.FUList6.opList
3937860SN/A
3947860SN/A[system.cpu.fuPool.FUList6.opList]
3957860SN/Atype=OpDesc
3967860SN/AissueLat=1
3977860SN/AopClass=MemWrite
3987860SN/AopLat=1
3997860SN/A
4007860SN/A[system.cpu.fuPool.FUList7]
4017860SN/Atype=FUDesc
4027860SN/Achildren=opList0 opList1
4037860SN/Acount=4
4047860SN/AopList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
4057860SN/A
4067860SN/A[system.cpu.fuPool.FUList7.opList0]
4077860SN/Atype=OpDesc
4087860SN/AissueLat=1
4097860SN/AopClass=MemRead
4107860SN/AopLat=1
4117860SN/A
4127860SN/A[system.cpu.fuPool.FUList7.opList1]
4137860SN/Atype=OpDesc
4147860SN/AissueLat=1
4157860SN/AopClass=MemWrite
4167860SN/AopLat=1
4177860SN/A
4187860SN/A[system.cpu.fuPool.FUList8]
4197860SN/Atype=FUDesc
4207860SN/Achildren=opList
4217860SN/Acount=1
4227860SN/AopList=system.cpu.fuPool.FUList8.opList
4237860SN/A
4247860SN/A[system.cpu.fuPool.FUList8.opList]
4257860SN/Atype=OpDesc
4267860SN/AissueLat=3
4277860SN/AopClass=IprAccess
4287860SN/AopLat=3
4297860SN/A
4307860SN/A[system.cpu.icache]
4317860SN/Atype=BaseCache
4328893Ssaidi@eecs.umich.eduaddr_ranges=0:18446744073709551615
4337860SN/Aassoc=2
4347860SN/Ablock_size=64
4359265SAli.Saidi@ARM.comclock=1
4367860SN/Aforward_snoops=true
4377860SN/Ahash_delay=1
4389265SAli.Saidi@ARM.comhit_latency=1000
4398150SN/Ais_top_level=true
4407860SN/Amax_miss_count=0
4417860SN/Amshrs=10
4427860SN/Aprefetch_on_access=false
4438835SAli.Saidi@ARM.comprefetcher=Null
4447860SN/AprioritizeRequests=false
4457860SN/Arepl=Null
4469265SAli.Saidi@ARM.comresponse_latency=1000
4477860SN/Asize=131072
4487860SN/Asubblock_size=0
4498835SAli.Saidi@ARM.comsystem=system
4507860SN/Atgts_per_mshr=20
4517860SN/Atrace_addr=0
4527860SN/Atwo_queue=false
4537860SN/Awrite_buffers=8
4547860SN/Acpu_side=system.cpu.icache_port
4558893Ssaidi@eecs.umich.edumem_side=system.cpu.toL2Bus.slave[0]
4567860SN/A
4578825Snilay@cs.wisc.edu[system.cpu.interrupts]
4588825Snilay@cs.wisc.edutype=ArmInterrupts
4598825Snilay@cs.wisc.edu
4607860SN/A[system.cpu.itb]
4617860SN/Atype=ArmTLB
4628825Snilay@cs.wisc.educhildren=walker
4637860SN/Asize=64
4648825Snilay@cs.wisc.eduwalker=system.cpu.itb.walker
4658825Snilay@cs.wisc.edu
4668825Snilay@cs.wisc.edu[system.cpu.itb.walker]
4678825Snilay@cs.wisc.edutype=ArmTableWalker
4689265SAli.Saidi@ARM.comclock=1
4699265SAli.Saidi@ARM.comnum_squash_per_cycle=2
4708825Snilay@cs.wisc.edusys=system
4718893Ssaidi@eecs.umich.eduport=system.cpu.toL2Bus.slave[2]
4727860SN/A
4737860SN/A[system.cpu.l2cache]
4747860SN/Atype=BaseCache
4758893Ssaidi@eecs.umich.eduaddr_ranges=0:18446744073709551615
4767860SN/Aassoc=2
4777860SN/Ablock_size=64
4789265SAli.Saidi@ARM.comclock=1
4797860SN/Aforward_snoops=true
4807860SN/Ahash_delay=1
4819265SAli.Saidi@ARM.comhit_latency=1000
4828150SN/Ais_top_level=false
4837860SN/Amax_miss_count=0
4847860SN/Amshrs=10
4857860SN/Aprefetch_on_access=false
4868835SAli.Saidi@ARM.comprefetcher=Null
4877860SN/AprioritizeRequests=false
4887860SN/Arepl=Null
4899265SAli.Saidi@ARM.comresponse_latency=1000
4907860SN/Asize=2097152
4917860SN/Asubblock_size=0
4928835SAli.Saidi@ARM.comsystem=system
4937860SN/Atgts_per_mshr=5
4947860SN/Atrace_addr=0
4957860SN/Atwo_queue=false
4967860SN/Awrite_buffers=8
4978893Ssaidi@eecs.umich.educpu_side=system.cpu.toL2Bus.master[0]
4988893Ssaidi@eecs.umich.edumem_side=system.membus.slave[1]
4997860SN/A
5007860SN/A[system.cpu.toL2Bus]
5019055Ssaidi@eecs.umich.edutype=CoherentBus
5027860SN/Ablock_size=64
5037860SN/Aclock=1000
5047860SN/Aheader_cycles=1
5057860SN/Ause_default_range=false
5069096Sandreas.hansson@arm.comwidth=8
5078893Ssaidi@eecs.umich.edumaster=system.cpu.l2cache.cpu_side
5088893Ssaidi@eecs.umich.eduslave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
5097860SN/A
5107860SN/A[system.cpu.tracer]
5117860SN/Atype=ExeTracer
5127860SN/A
5137860SN/A[system.cpu.workload]
5147860SN/Atype=LiveProcess
5157860SN/Acmd=perlbmk -I. -I lib lgred.makerand.pl
5169265SAli.Saidi@ARM.comcwd=build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing
5177860SN/Aegid=100
5187860SN/Aenv=
5197860SN/Aerrout=cerr
5207860SN/Aeuid=100
5219265SAli.Saidi@ARM.comexecutable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/perlbmk
5227860SN/Agid=100
5237860SN/Ainput=cin
5247860SN/Amax_stack_size=67108864
5257860SN/Aoutput=cout
5267860SN/Apid=100
5277860SN/Appid=99
5287860SN/Asimpoint=0
5297860SN/Asystem=system
5307860SN/Auid=100
5317860SN/A
5327860SN/A[system.membus]
5339055Ssaidi@eecs.umich.edutype=CoherentBus
5347860SN/Ablock_size=64
5357860SN/Aclock=1000
5367860SN/Aheader_cycles=1
5377860SN/Ause_default_range=false
5389096Sandreas.hansson@arm.comwidth=8
5399265SAli.Saidi@ARM.commaster=system.physmem.port
5408893Ssaidi@eecs.umich.eduslave=system.system_port system.cpu.l2cache.mem_side
5417860SN/A
5427860SN/A[system.physmem]
5438983Snate@binkert.orgtype=SimpleMemory
5449265SAli.Saidi@ARM.combandwidth=73.000000
5459265SAli.Saidi@ARM.comclock=1
5468983Snate@binkert.orgconf_table_reported=false
5478983Snate@binkert.orgin_addr_map=true
5487860SN/Alatency=30000
5497860SN/Alatency_var=0
5507860SN/Anull=false
5517860SN/Arange=0:134217727
5527860SN/Azero=false
5538893Ssaidi@eecs.umich.eduport=system.membus.master[0]
5547860SN/A
555