stats.txt revision 10892:bd37e25fb3b7
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.541068 # Number of seconds simulated 4sim_ticks 541067717500 # Number of ticks simulated 5final_tick 541067717500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 180313 # Simulator instruction rate (inst/s) 8host_op_rate 221989 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 152283805 # Simulator tick rate (ticks/s) 10host_mem_usage 322972 # Number of bytes of host memory used 11host_seconds 3553.02 # Real time elapsed on the host 12sim_insts 640655085 # Number of instructions simulated 13sim_ops 788730744 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 164736 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 18470272 # Number of bytes read from this memory 18system.physmem.bytes_read::total 18635008 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 164736 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 164736 # Number of instructions bytes read from this memory 21system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory 22system.physmem.bytes_written::total 4230272 # Number of bytes written to this memory 23system.physmem.num_reads::cpu.inst 2574 # Number of read requests responded to by this memory 24system.physmem.num_reads::cpu.data 288598 # Number of read requests responded to by this memory 25system.physmem.num_reads::total 291172 # Number of read requests responded to by this memory 26system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory 27system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory 28system.physmem.bw_read::cpu.inst 304465 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::cpu.data 34136710 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::total 34441175 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_inst_read::cpu.inst 304465 # Instruction read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::total 304465 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_write::writebacks 7818378 # Write bandwidth from this memory (bytes/s) 34system.physmem.bw_write::total 7818378 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_total::writebacks 7818378 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::cpu.inst 304465 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.data 34136710 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::total 42259553 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.readReqs 291172 # Number of read requests accepted 40system.physmem.writeReqs 66098 # Number of write requests accepted 41system.physmem.readBursts 291172 # Number of DRAM read bursts, including those serviced by the write queue 42system.physmem.writeBursts 66098 # Number of DRAM write bursts, including those merged in the write queue 43system.physmem.bytesReadDRAM 18613824 # Total number of bytes read from DRAM 44system.physmem.bytesReadWrQ 21184 # Total number of bytes read from write queue 45system.physmem.bytesWritten 4228224 # Total number of bytes written to DRAM 46system.physmem.bytesReadSys 18635008 # Total read bytes from the system interface side 47system.physmem.bytesWrittenSys 4230272 # Total written bytes from the system interface side 48system.physmem.servicedByWrQ 331 # Number of DRAM read bursts serviced by the write queue 49system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 50system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 51system.physmem.perBankRdBursts::0 18282 # Per bank write bursts 52system.physmem.perBankRdBursts::1 18127 # Per bank write bursts 53system.physmem.perBankRdBursts::2 18214 # Per bank write bursts 54system.physmem.perBankRdBursts::3 18173 # Per bank write bursts 55system.physmem.perBankRdBursts::4 18274 # Per bank write bursts 56system.physmem.perBankRdBursts::5 18402 # Per bank write bursts 57system.physmem.perBankRdBursts::6 18180 # Per bank write bursts 58system.physmem.perBankRdBursts::7 17989 # Per bank write bursts 59system.physmem.perBankRdBursts::8 18022 # Per bank write bursts 60system.physmem.perBankRdBursts::9 18061 # Per bank write bursts 61system.physmem.perBankRdBursts::10 18102 # Per bank write bursts 62system.physmem.perBankRdBursts::11 18198 # Per bank write bursts 63system.physmem.perBankRdBursts::12 18215 # Per bank write bursts 64system.physmem.perBankRdBursts::13 18265 # Per bank write bursts 65system.physmem.perBankRdBursts::14 18078 # Per bank write bursts 66system.physmem.perBankRdBursts::15 18259 # Per bank write bursts 67system.physmem.perBankWrBursts::0 4171 # Per bank write bursts 68system.physmem.perBankWrBursts::1 4098 # Per bank write bursts 69system.physmem.perBankWrBursts::2 4134 # Per bank write bursts 70system.physmem.perBankWrBursts::3 4146 # Per bank write bursts 71system.physmem.perBankWrBursts::4 4223 # Per bank write bursts 72system.physmem.perBankWrBursts::5 4224 # Per bank write bursts 73system.physmem.perBankWrBursts::6 4173 # Per bank write bursts 74system.physmem.perBankWrBursts::7 4092 # Per bank write bursts 75system.physmem.perBankWrBursts::8 4093 # Per bank write bursts 76system.physmem.perBankWrBursts::9 4096 # Per bank write bursts 77system.physmem.perBankWrBursts::10 4096 # Per bank write bursts 78system.physmem.perBankWrBursts::11 4096 # Per bank write bursts 79system.physmem.perBankWrBursts::12 4095 # Per bank write bursts 80system.physmem.perBankWrBursts::13 4095 # Per bank write bursts 81system.physmem.perBankWrBursts::14 4096 # Per bank write bursts 82system.physmem.perBankWrBursts::15 4138 # Per bank write bursts 83system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 84system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 85system.physmem.totGap 541067624000 # Total gap between requests 86system.physmem.readPktSize::0 0 # Read request sizes (log2) 87system.physmem.readPktSize::1 0 # Read request sizes (log2) 88system.physmem.readPktSize::2 0 # Read request sizes (log2) 89system.physmem.readPktSize::3 0 # Read request sizes (log2) 90system.physmem.readPktSize::4 0 # Read request sizes (log2) 91system.physmem.readPktSize::5 0 # Read request sizes (log2) 92system.physmem.readPktSize::6 291172 # Read request sizes (log2) 93system.physmem.writePktSize::0 0 # Write request sizes (log2) 94system.physmem.writePktSize::1 0 # Write request sizes (log2) 95system.physmem.writePktSize::2 0 # Write request sizes (log2) 96system.physmem.writePktSize::3 0 # Write request sizes (log2) 97system.physmem.writePktSize::4 0 # Write request sizes (log2) 98system.physmem.writePktSize::5 0 # Write request sizes (log2) 99system.physmem.writePktSize::6 66098 # Write request sizes (log2) 100system.physmem.rdQLenPdf::0 290452 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::1 372 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::2 17 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 132system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 133system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 134system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::15 898 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::16 898 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::17 4014 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::18 4018 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::19 4018 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::20 4018 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::21 4018 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::22 4018 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::23 4018 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::24 4018 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::25 4018 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::26 4018 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::27 4018 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::28 4018 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::29 4018 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::30 4020 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::31 4020 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::32 4017 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 196system.physmem.bytesPerActivate::samples 110882 # Bytes accessed per row activation 197system.physmem.bytesPerActivate::mean 205.996862 # Bytes accessed per row activation 198system.physmem.bytesPerActivate::gmean 134.129754 # Bytes accessed per row activation 199system.physmem.bytesPerActivate::stdev 256.860056 # Bytes accessed per row activation 200system.physmem.bytesPerActivate::0-127 45611 41.13% 41.13% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::128-255 43911 39.60% 80.74% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::256-383 9208 8.30% 89.04% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::384-511 1504 1.36% 90.40% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::512-639 772 0.70% 91.09% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::640-767 428 0.39% 91.48% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::768-895 846 0.76% 92.24% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::896-1023 594 0.54% 92.78% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::1024-1151 8008 7.22% 100.00% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::total 110882 # Bytes accessed per row activation 210system.physmem.rdPerTurnAround::samples 4017 # Reads before turning the bus around for writes 211system.physmem.rdPerTurnAround::mean 48.509335 # Reads before turning the bus around for writes 212system.physmem.rdPerTurnAround::gmean 34.234035 # Reads before turning the bus around for writes 213system.physmem.rdPerTurnAround::stdev 506.719748 # Reads before turning the bus around for writes 214system.physmem.rdPerTurnAround::0-1023 4015 99.95% 99.95% # Reads before turning the bus around for writes 215system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes 216system.physmem.rdPerTurnAround::31744-32767 1 0.02% 100.00% # Reads before turning the bus around for writes 217system.physmem.rdPerTurnAround::total 4017 # Reads before turning the bus around for writes 218system.physmem.wrPerTurnAround::samples 4017 # Writes before turning the bus around for reads 219system.physmem.wrPerTurnAround::mean 16.446602 # Writes before turning the bus around for reads 220system.physmem.wrPerTurnAround::gmean 16.426400 # Writes before turning the bus around for reads 221system.physmem.wrPerTurnAround::stdev 0.833021 # Writes before turning the bus around for reads 222system.physmem.wrPerTurnAround::16 3120 77.67% 77.67% # Writes before turning the bus around for reads 223system.physmem.wrPerTurnAround::18 897 22.33% 100.00% # Writes before turning the bus around for reads 224system.physmem.wrPerTurnAround::total 4017 # Writes before turning the bus around for reads 225system.physmem.totQLat 3065169000 # Total ticks spent queuing 226system.physmem.totMemAccLat 8518437750 # Total ticks spent from burst creation until serviced by the DRAM 227system.physmem.totBusLat 1454205000 # Total ticks spent in databus transfers 228system.physmem.avgQLat 10538.99 # Average queueing delay per DRAM burst 229system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 230system.physmem.avgMemAccLat 29288.99 # Average memory access latency per DRAM burst 231system.physmem.avgRdBW 34.40 # Average DRAM read bandwidth in MiByte/s 232system.physmem.avgWrBW 7.81 # Average achieved write bandwidth in MiByte/s 233system.physmem.avgRdBWSys 34.44 # Average system read bandwidth in MiByte/s 234system.physmem.avgWrBWSys 7.82 # Average system write bandwidth in MiByte/s 235system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 236system.physmem.busUtil 0.33 # Data bus utilization in percentage 237system.physmem.busUtilRead 0.27 # Data bus utilization in percentage for reads 238system.physmem.busUtilWrite 0.06 # Data bus utilization in percentage for writes 239system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing 240system.physmem.avgWrQLen 28.63 # Average write queue length when enqueuing 241system.physmem.readRowHits 194425 # Number of row buffer hits during reads 242system.physmem.writeRowHits 51597 # Number of row buffer hits during writes 243system.physmem.readRowHitRate 66.85 # Row buffer hit rate for reads 244system.physmem.writeRowHitRate 78.06 # Row buffer hit rate for writes 245system.physmem.avgGap 1514450.20 # Average gap between requests 246system.physmem.pageHitRate 68.93 # Row buffer hit rate, read and write combined 247system.physmem_0.actEnergy 420041160 # Energy for activate commands per rank (pJ) 248system.physmem_0.preEnergy 229189125 # Energy for precharge commands per rank (pJ) 249system.physmem_0.readEnergy 1135976400 # Energy for read commands per rank (pJ) 250system.physmem_0.writeEnergy 215531280 # Energy for write commands per rank (pJ) 251system.physmem_0.refreshEnergy 35339834400 # Energy for refresh commands per rank (pJ) 252system.physmem_0.actBackEnergy 108869403780 # Energy for active background per rank (pJ) 253system.physmem_0.preBackEnergy 229140586500 # Energy for precharge background per rank (pJ) 254system.physmem_0.totalEnergy 375350562645 # Total energy per rank (pJ) 255system.physmem_0.averagePower 693.723181 # Core power per rank (mW) 256system.physmem_0.memoryStateTime::IDLE 380482098250 # Time in different power states 257system.physmem_0.memoryStateTime::REF 18067400000 # Time in different power states 258system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 259system.physmem_0.memoryStateTime::ACT 142518050750 # Time in different power states 260system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 261system.physmem_1.actEnergy 418226760 # Energy for activate commands per rank (pJ) 262system.physmem_1.preEnergy 228199125 # Energy for precharge commands per rank (pJ) 263system.physmem_1.readEnergy 1132497600 # Energy for read commands per rank (pJ) 264system.physmem_1.writeEnergy 212576400 # Energy for write commands per rank (pJ) 265system.physmem_1.refreshEnergy 35339834400 # Energy for refresh commands per rank (pJ) 266system.physmem_1.actBackEnergy 107776907010 # Energy for active background per rank (pJ) 267system.physmem_1.preBackEnergy 230098917000 # Energy for precharge background per rank (pJ) 268system.physmem_1.totalEnergy 375207158295 # Total energy per rank (pJ) 269system.physmem_1.averagePower 693.458141 # Core power per rank (mW) 270system.physmem_1.memoryStateTime::IDLE 382081982750 # Time in different power states 271system.physmem_1.memoryStateTime::REF 18067400000 # Time in different power states 272system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 273system.physmem_1.memoryStateTime::ACT 140917403500 # Time in different power states 274system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 275system.cpu.branchPred.lookups 157565509 # Number of BP lookups 276system.cpu.branchPred.condPredicted 107229273 # Number of conditional branches predicted 277system.cpu.branchPred.condIncorrect 12892751 # Number of conditional branches incorrect 278system.cpu.branchPred.BTBLookups 98103751 # Number of BTB lookups 279system.cpu.branchPred.BTBHits 81778311 # Number of BTB hits 280system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 281system.cpu.branchPred.BTBHitPct 83.359005 # BTB Hit Percentage 282system.cpu.branchPred.usedRAS 19318729 # Number of times the RAS was used to get a target. 283system.cpu.branchPred.RASInCorrect 1315 # Number of incorrect RAS predictions. 284system.cpu_clk_domain.clock 500 # Clock period in ticks 285system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 286system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 287system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 288system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 289system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 290system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 291system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 292system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 293system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 294system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 295system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 296system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 297system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 298system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 299system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 300system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 301system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 302system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 303system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 304system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 305system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 306system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 307system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 308system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 309system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 310system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 311system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 312system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 313system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 314system.cpu.dtb.walker.walks 0 # Table walker walks requested 315system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 316system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 317system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 318system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 319system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 320system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 321system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 322system.cpu.dtb.inst_hits 0 # ITB inst hits 323system.cpu.dtb.inst_misses 0 # ITB inst misses 324system.cpu.dtb.read_hits 0 # DTB read hits 325system.cpu.dtb.read_misses 0 # DTB read misses 326system.cpu.dtb.write_hits 0 # DTB write hits 327system.cpu.dtb.write_misses 0 # DTB write misses 328system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 329system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 330system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 331system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 332system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 333system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 334system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 335system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 336system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 337system.cpu.dtb.read_accesses 0 # DTB read accesses 338system.cpu.dtb.write_accesses 0 # DTB write accesses 339system.cpu.dtb.inst_accesses 0 # ITB inst accesses 340system.cpu.dtb.hits 0 # DTB hits 341system.cpu.dtb.misses 0 # DTB misses 342system.cpu.dtb.accesses 0 # DTB accesses 343system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 344system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 345system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 346system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 347system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 348system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 349system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 350system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 351system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 352system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 353system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 354system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 355system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 356system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 357system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 358system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 359system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 360system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 361system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 362system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 363system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 364system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 365system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 366system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 367system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 368system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 369system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 370system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 371system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 372system.cpu.itb.walker.walks 0 # Table walker walks requested 373system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 374system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 375system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 376system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 377system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 378system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 379system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 380system.cpu.itb.inst_hits 0 # ITB inst hits 381system.cpu.itb.inst_misses 0 # ITB inst misses 382system.cpu.itb.read_hits 0 # DTB read hits 383system.cpu.itb.read_misses 0 # DTB read misses 384system.cpu.itb.write_hits 0 # DTB write hits 385system.cpu.itb.write_misses 0 # DTB write misses 386system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 387system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 388system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 389system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 390system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 391system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 392system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 393system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 394system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 395system.cpu.itb.read_accesses 0 # DTB read accesses 396system.cpu.itb.write_accesses 0 # DTB write accesses 397system.cpu.itb.inst_accesses 0 # ITB inst accesses 398system.cpu.itb.hits 0 # DTB hits 399system.cpu.itb.misses 0 # DTB misses 400system.cpu.itb.accesses 0 # DTB accesses 401system.cpu.workload.num_syscalls 673 # Number of system calls 402system.cpu.numCycles 1082135435 # number of cpu cycles simulated 403system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 404system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 405system.cpu.committedInsts 640655085 # Number of instructions committed 406system.cpu.committedOps 788730744 # Number of ops (including micro ops) committed 407system.cpu.discardedOps 23942424 # Number of ops (including micro ops) which were discarded before commit 408system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching 409system.cpu.cpi 1.689108 # CPI: cycles per instruction 410system.cpu.ipc 0.592029 # IPC: instructions per cycle 411system.cpu.tickCycles 1024380125 # Number of cycles that the object actually ticked 412system.cpu.idleCycles 57755310 # Total number of cycles that the object has spent stopped 413system.cpu.dcache.tags.replacements 778330 # number of replacements 414system.cpu.dcache.tags.tagsinuse 4092.458630 # Cycle average of tags in use 415system.cpu.dcache.tags.total_refs 378454621 # Total number of references to valid blocks. 416system.cpu.dcache.tags.sampled_refs 782426 # Sample count of references to valid blocks. 417system.cpu.dcache.tags.avg_refs 483.693820 # Average number of references to valid blocks. 418system.cpu.dcache.tags.warmup_cycle 795587500 # Cycle when the warmup percentage was hit. 419system.cpu.dcache.tags.occ_blocks::cpu.data 4092.458630 # Average occupied blocks per requestor 420system.cpu.dcache.tags.occ_percent::cpu.data 0.999135 # Average percentage of cache occupancy 421system.cpu.dcache.tags.occ_percent::total 0.999135 # Average percentage of cache occupancy 422system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 423system.cpu.dcache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id 424system.cpu.dcache.tags.age_task_id_blocks_1024::1 170 # Occupied blocks per task id 425system.cpu.dcache.tags.age_task_id_blocks_1024::2 964 # Occupied blocks per task id 426system.cpu.dcache.tags.age_task_id_blocks_1024::3 1346 # Occupied blocks per task id 427system.cpu.dcache.tags.age_task_id_blocks_1024::4 1586 # Occupied blocks per task id 428system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 429system.cpu.dcache.tags.tag_accesses 759395078 # Number of tag accesses 430system.cpu.dcache.tags.data_accesses 759395078 # Number of data accesses 431system.cpu.dcache.ReadReq_hits::cpu.data 249625893 # number of ReadReq hits 432system.cpu.dcache.ReadReq_hits::total 249625893 # number of ReadReq hits 433system.cpu.dcache.WriteReq_hits::cpu.data 128813765 # number of WriteReq hits 434system.cpu.dcache.WriteReq_hits::total 128813765 # number of WriteReq hits 435system.cpu.dcache.SoftPFReq_hits::cpu.data 3485 # number of SoftPFReq hits 436system.cpu.dcache.SoftPFReq_hits::total 3485 # number of SoftPFReq hits 437system.cpu.dcache.LoadLockedReq_hits::cpu.data 5739 # number of LoadLockedReq hits 438system.cpu.dcache.LoadLockedReq_hits::total 5739 # number of LoadLockedReq hits 439system.cpu.dcache.StoreCondReq_hits::cpu.data 5739 # number of StoreCondReq hits 440system.cpu.dcache.StoreCondReq_hits::total 5739 # number of StoreCondReq hits 441system.cpu.dcache.demand_hits::cpu.data 378439658 # number of demand (read+write) hits 442system.cpu.dcache.demand_hits::total 378439658 # number of demand (read+write) hits 443system.cpu.dcache.overall_hits::cpu.data 378443143 # number of overall hits 444system.cpu.dcache.overall_hits::total 378443143 # number of overall hits 445system.cpu.dcache.ReadReq_misses::cpu.data 713852 # number of ReadReq misses 446system.cpu.dcache.ReadReq_misses::total 713852 # number of ReadReq misses 447system.cpu.dcache.WriteReq_misses::cpu.data 137712 # number of WriteReq misses 448system.cpu.dcache.WriteReq_misses::total 137712 # number of WriteReq misses 449system.cpu.dcache.SoftPFReq_misses::cpu.data 141 # number of SoftPFReq misses 450system.cpu.dcache.SoftPFReq_misses::total 141 # number of SoftPFReq misses 451system.cpu.dcache.demand_misses::cpu.data 851564 # number of demand (read+write) misses 452system.cpu.dcache.demand_misses::total 851564 # number of demand (read+write) misses 453system.cpu.dcache.overall_misses::cpu.data 851705 # number of overall misses 454system.cpu.dcache.overall_misses::total 851705 # number of overall misses 455system.cpu.dcache.ReadReq_miss_latency::cpu.data 24973506500 # number of ReadReq miss cycles 456system.cpu.dcache.ReadReq_miss_latency::total 24973506500 # number of ReadReq miss cycles 457system.cpu.dcache.WriteReq_miss_latency::cpu.data 10064105500 # number of WriteReq miss cycles 458system.cpu.dcache.WriteReq_miss_latency::total 10064105500 # number of WriteReq miss cycles 459system.cpu.dcache.demand_miss_latency::cpu.data 35037612000 # number of demand (read+write) miss cycles 460system.cpu.dcache.demand_miss_latency::total 35037612000 # number of demand (read+write) miss cycles 461system.cpu.dcache.overall_miss_latency::cpu.data 35037612000 # number of overall miss cycles 462system.cpu.dcache.overall_miss_latency::total 35037612000 # number of overall miss cycles 463system.cpu.dcache.ReadReq_accesses::cpu.data 250339745 # number of ReadReq accesses(hits+misses) 464system.cpu.dcache.ReadReq_accesses::total 250339745 # number of ReadReq accesses(hits+misses) 465system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses) 466system.cpu.dcache.WriteReq_accesses::total 128951477 # number of WriteReq accesses(hits+misses) 467system.cpu.dcache.SoftPFReq_accesses::cpu.data 3626 # number of SoftPFReq accesses(hits+misses) 468system.cpu.dcache.SoftPFReq_accesses::total 3626 # number of SoftPFReq accesses(hits+misses) 469system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5739 # number of LoadLockedReq accesses(hits+misses) 470system.cpu.dcache.LoadLockedReq_accesses::total 5739 # number of LoadLockedReq accesses(hits+misses) 471system.cpu.dcache.StoreCondReq_accesses::cpu.data 5739 # number of StoreCondReq accesses(hits+misses) 472system.cpu.dcache.StoreCondReq_accesses::total 5739 # number of StoreCondReq accesses(hits+misses) 473system.cpu.dcache.demand_accesses::cpu.data 379291222 # number of demand (read+write) accesses 474system.cpu.dcache.demand_accesses::total 379291222 # number of demand (read+write) accesses 475system.cpu.dcache.overall_accesses::cpu.data 379294848 # number of overall (read+write) accesses 476system.cpu.dcache.overall_accesses::total 379294848 # number of overall (read+write) accesses 477system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002852 # miss rate for ReadReq accesses 478system.cpu.dcache.ReadReq_miss_rate::total 0.002852 # miss rate for ReadReq accesses 479system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001068 # miss rate for WriteReq accesses 480system.cpu.dcache.WriteReq_miss_rate::total 0.001068 # miss rate for WriteReq accesses 481system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.038886 # miss rate for SoftPFReq accesses 482system.cpu.dcache.SoftPFReq_miss_rate::total 0.038886 # miss rate for SoftPFReq accesses 483system.cpu.dcache.demand_miss_rate::cpu.data 0.002245 # miss rate for demand accesses 484system.cpu.dcache.demand_miss_rate::total 0.002245 # miss rate for demand accesses 485system.cpu.dcache.overall_miss_rate::cpu.data 0.002245 # miss rate for overall accesses 486system.cpu.dcache.overall_miss_rate::total 0.002245 # miss rate for overall accesses 487system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34984.151477 # average ReadReq miss latency 488system.cpu.dcache.ReadReq_avg_miss_latency::total 34984.151477 # average ReadReq miss latency 489system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73080.817213 # average WriteReq miss latency 490system.cpu.dcache.WriteReq_avg_miss_latency::total 73080.817213 # average WriteReq miss latency 491system.cpu.dcache.demand_avg_miss_latency::cpu.data 41145.013176 # average overall miss latency 492system.cpu.dcache.demand_avg_miss_latency::total 41145.013176 # average overall miss latency 493system.cpu.dcache.overall_avg_miss_latency::cpu.data 41138.201607 # average overall miss latency 494system.cpu.dcache.overall_avg_miss_latency::total 41138.201607 # average overall miss latency 495system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 496system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 497system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 498system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 499system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 500system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 501system.cpu.dcache.fast_writes 0 # number of fast writes performed 502system.cpu.dcache.cache_copies 0 # number of cache copies performed 503system.cpu.dcache.writebacks::writebacks 88940 # number of writebacks 504system.cpu.dcache.writebacks::total 88940 # number of writebacks 505system.cpu.dcache.ReadReq_mshr_hits::cpu.data 887 # number of ReadReq MSHR hits 506system.cpu.dcache.ReadReq_mshr_hits::total 887 # number of ReadReq MSHR hits 507system.cpu.dcache.WriteReq_mshr_hits::cpu.data 68390 # number of WriteReq MSHR hits 508system.cpu.dcache.WriteReq_mshr_hits::total 68390 # number of WriteReq MSHR hits 509system.cpu.dcache.demand_mshr_hits::cpu.data 69277 # number of demand (read+write) MSHR hits 510system.cpu.dcache.demand_mshr_hits::total 69277 # number of demand (read+write) MSHR hits 511system.cpu.dcache.overall_mshr_hits::cpu.data 69277 # number of overall MSHR hits 512system.cpu.dcache.overall_mshr_hits::total 69277 # number of overall MSHR hits 513system.cpu.dcache.ReadReq_mshr_misses::cpu.data 712965 # number of ReadReq MSHR misses 514system.cpu.dcache.ReadReq_mshr_misses::total 712965 # number of ReadReq MSHR misses 515system.cpu.dcache.WriteReq_mshr_misses::cpu.data 69322 # number of WriteReq MSHR misses 516system.cpu.dcache.WriteReq_mshr_misses::total 69322 # number of WriteReq MSHR misses 517system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 139 # number of SoftPFReq MSHR misses 518system.cpu.dcache.SoftPFReq_mshr_misses::total 139 # number of SoftPFReq MSHR misses 519system.cpu.dcache.demand_mshr_misses::cpu.data 782287 # number of demand (read+write) MSHR misses 520system.cpu.dcache.demand_mshr_misses::total 782287 # number of demand (read+write) MSHR misses 521system.cpu.dcache.overall_mshr_misses::cpu.data 782426 # number of overall MSHR misses 522system.cpu.dcache.overall_mshr_misses::total 782426 # number of overall MSHR misses 523system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24245308500 # number of ReadReq MSHR miss cycles 524system.cpu.dcache.ReadReq_mshr_miss_latency::total 24245308500 # number of ReadReq MSHR miss cycles 525system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5047418500 # number of WriteReq MSHR miss cycles 526system.cpu.dcache.WriteReq_mshr_miss_latency::total 5047418500 # number of WriteReq MSHR miss cycles 527system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1788000 # number of SoftPFReq MSHR miss cycles 528system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1788000 # number of SoftPFReq MSHR miss cycles 529system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29292727000 # number of demand (read+write) MSHR miss cycles 530system.cpu.dcache.demand_mshr_miss_latency::total 29292727000 # number of demand (read+write) MSHR miss cycles 531system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29294515000 # number of overall MSHR miss cycles 532system.cpu.dcache.overall_mshr_miss_latency::total 29294515000 # number of overall MSHR miss cycles 533system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002848 # mshr miss rate for ReadReq accesses 534system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002848 # mshr miss rate for ReadReq accesses 535system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000538 # mshr miss rate for WriteReq accesses 536system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000538 # mshr miss rate for WriteReq accesses 537system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.038334 # mshr miss rate for SoftPFReq accesses 538system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.038334 # mshr miss rate for SoftPFReq accesses 539system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002062 # mshr miss rate for demand accesses 540system.cpu.dcache.demand_mshr_miss_rate::total 0.002062 # mshr miss rate for demand accesses 541system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002063 # mshr miss rate for overall accesses 542system.cpu.dcache.overall_mshr_miss_rate::total 0.002063 # mshr miss rate for overall accesses 543system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34006.309566 # average ReadReq mshr miss latency 544system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34006.309566 # average ReadReq mshr miss latency 545system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72811.207120 # average WriteReq mshr miss latency 546system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72811.207120 # average WriteReq mshr miss latency 547system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12863.309353 # average SoftPFReq mshr miss latency 548system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12863.309353 # average SoftPFReq mshr miss latency 549system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 37444.987581 # average overall mshr miss latency 550system.cpu.dcache.demand_avg_mshr_miss_latency::total 37444.987581 # average overall mshr miss latency 551system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 37440.620583 # average overall mshr miss latency 552system.cpu.dcache.overall_avg_mshr_miss_latency::total 37440.620583 # average overall mshr miss latency 553system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 554system.cpu.icache.tags.replacements 23593 # number of replacements 555system.cpu.icache.tags.tagsinuse 1712.048816 # Cycle average of tags in use 556system.cpu.icache.tags.total_refs 288484492 # Total number of references to valid blocks. 557system.cpu.icache.tags.sampled_refs 25344 # Sample count of references to valid blocks. 558system.cpu.icache.tags.avg_refs 11382.752999 # Average number of references to valid blocks. 559system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 560system.cpu.icache.tags.occ_blocks::cpu.inst 1712.048816 # Average occupied blocks per requestor 561system.cpu.icache.tags.occ_percent::cpu.inst 0.835961 # Average percentage of cache occupancy 562system.cpu.icache.tags.occ_percent::total 0.835961 # Average percentage of cache occupancy 563system.cpu.icache.tags.occ_task_id_blocks::1024 1751 # Occupied blocks per task id 564system.cpu.icache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id 565system.cpu.icache.tags.age_task_id_blocks_1024::1 92 # Occupied blocks per task id 566system.cpu.icache.tags.age_task_id_blocks_1024::4 1603 # Occupied blocks per task id 567system.cpu.icache.tags.occ_task_id_percent::1024 0.854980 # Percentage of cache occupancy per task id 568system.cpu.icache.tags.tag_accesses 577045018 # Number of tag accesses 569system.cpu.icache.tags.data_accesses 577045018 # Number of data accesses 570system.cpu.icache.ReadReq_hits::cpu.inst 288484492 # number of ReadReq hits 571system.cpu.icache.ReadReq_hits::total 288484492 # number of ReadReq hits 572system.cpu.icache.demand_hits::cpu.inst 288484492 # number of demand (read+write) hits 573system.cpu.icache.demand_hits::total 288484492 # number of demand (read+write) hits 574system.cpu.icache.overall_hits::cpu.inst 288484492 # number of overall hits 575system.cpu.icache.overall_hits::total 288484492 # number of overall hits 576system.cpu.icache.ReadReq_misses::cpu.inst 25345 # number of ReadReq misses 577system.cpu.icache.ReadReq_misses::total 25345 # number of ReadReq misses 578system.cpu.icache.demand_misses::cpu.inst 25345 # number of demand (read+write) misses 579system.cpu.icache.demand_misses::total 25345 # number of demand (read+write) misses 580system.cpu.icache.overall_misses::cpu.inst 25345 # number of overall misses 581system.cpu.icache.overall_misses::total 25345 # number of overall misses 582system.cpu.icache.ReadReq_miss_latency::cpu.inst 499936000 # number of ReadReq miss cycles 583system.cpu.icache.ReadReq_miss_latency::total 499936000 # number of ReadReq miss cycles 584system.cpu.icache.demand_miss_latency::cpu.inst 499936000 # number of demand (read+write) miss cycles 585system.cpu.icache.demand_miss_latency::total 499936000 # number of demand (read+write) miss cycles 586system.cpu.icache.overall_miss_latency::cpu.inst 499936000 # number of overall miss cycles 587system.cpu.icache.overall_miss_latency::total 499936000 # number of overall miss cycles 588system.cpu.icache.ReadReq_accesses::cpu.inst 288509837 # number of ReadReq accesses(hits+misses) 589system.cpu.icache.ReadReq_accesses::total 288509837 # number of ReadReq accesses(hits+misses) 590system.cpu.icache.demand_accesses::cpu.inst 288509837 # number of demand (read+write) accesses 591system.cpu.icache.demand_accesses::total 288509837 # number of demand (read+write) accesses 592system.cpu.icache.overall_accesses::cpu.inst 288509837 # number of overall (read+write) accesses 593system.cpu.icache.overall_accesses::total 288509837 # number of overall (read+write) accesses 594system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000088 # miss rate for ReadReq accesses 595system.cpu.icache.ReadReq_miss_rate::total 0.000088 # miss rate for ReadReq accesses 596system.cpu.icache.demand_miss_rate::cpu.inst 0.000088 # miss rate for demand accesses 597system.cpu.icache.demand_miss_rate::total 0.000088 # miss rate for demand accesses 598system.cpu.icache.overall_miss_rate::cpu.inst 0.000088 # miss rate for overall accesses 599system.cpu.icache.overall_miss_rate::total 0.000088 # miss rate for overall accesses 600system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19725.231801 # average ReadReq miss latency 601system.cpu.icache.ReadReq_avg_miss_latency::total 19725.231801 # average ReadReq miss latency 602system.cpu.icache.demand_avg_miss_latency::cpu.inst 19725.231801 # average overall miss latency 603system.cpu.icache.demand_avg_miss_latency::total 19725.231801 # average overall miss latency 604system.cpu.icache.overall_avg_miss_latency::cpu.inst 19725.231801 # average overall miss latency 605system.cpu.icache.overall_avg_miss_latency::total 19725.231801 # average overall miss latency 606system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 607system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 608system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 609system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 610system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 611system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 612system.cpu.icache.fast_writes 0 # number of fast writes performed 613system.cpu.icache.cache_copies 0 # number of cache copies performed 614system.cpu.icache.ReadReq_mshr_misses::cpu.inst 25345 # number of ReadReq MSHR misses 615system.cpu.icache.ReadReq_mshr_misses::total 25345 # number of ReadReq MSHR misses 616system.cpu.icache.demand_mshr_misses::cpu.inst 25345 # number of demand (read+write) MSHR misses 617system.cpu.icache.demand_mshr_misses::total 25345 # number of demand (read+write) MSHR misses 618system.cpu.icache.overall_mshr_misses::cpu.inst 25345 # number of overall MSHR misses 619system.cpu.icache.overall_mshr_misses::total 25345 # number of overall MSHR misses 620system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 474592000 # number of ReadReq MSHR miss cycles 621system.cpu.icache.ReadReq_mshr_miss_latency::total 474592000 # number of ReadReq MSHR miss cycles 622system.cpu.icache.demand_mshr_miss_latency::cpu.inst 474592000 # number of demand (read+write) MSHR miss cycles 623system.cpu.icache.demand_mshr_miss_latency::total 474592000 # number of demand (read+write) MSHR miss cycles 624system.cpu.icache.overall_mshr_miss_latency::cpu.inst 474592000 # number of overall MSHR miss cycles 625system.cpu.icache.overall_mshr_miss_latency::total 474592000 # number of overall MSHR miss cycles 626system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000088 # mshr miss rate for ReadReq accesses 627system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000088 # mshr miss rate for ReadReq accesses 628system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000088 # mshr miss rate for demand accesses 629system.cpu.icache.demand_mshr_miss_rate::total 0.000088 # mshr miss rate for demand accesses 630system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000088 # mshr miss rate for overall accesses 631system.cpu.icache.overall_mshr_miss_rate::total 0.000088 # mshr miss rate for overall accesses 632system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18725.271257 # average ReadReq mshr miss latency 633system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18725.271257 # average ReadReq mshr miss latency 634system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18725.271257 # average overall mshr miss latency 635system.cpu.icache.demand_avg_mshr_miss_latency::total 18725.271257 # average overall mshr miss latency 636system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18725.271257 # average overall mshr miss latency 637system.cpu.icache.overall_avg_mshr_miss_latency::total 18725.271257 # average overall mshr miss latency 638system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 639system.cpu.l2cache.tags.replacements 258392 # number of replacements 640system.cpu.l2cache.tags.tagsinuse 32574.171271 # Cycle average of tags in use 641system.cpu.l2cache.tags.total_refs 1245331 # Total number of references to valid blocks. 642system.cpu.l2cache.tags.sampled_refs 291136 # Sample count of references to valid blocks. 643system.cpu.l2cache.tags.avg_refs 4.277489 # Average number of references to valid blocks. 644system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 645system.cpu.l2cache.tags.occ_blocks::writebacks 2589.797972 # Average occupied blocks per requestor 646system.cpu.l2cache.tags.occ_blocks::cpu.inst 90.410409 # Average occupied blocks per requestor 647system.cpu.l2cache.tags.occ_blocks::cpu.data 29893.962890 # Average occupied blocks per requestor 648system.cpu.l2cache.tags.occ_percent::writebacks 0.079034 # Average percentage of cache occupancy 649system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002759 # Average percentage of cache occupancy 650system.cpu.l2cache.tags.occ_percent::cpu.data 0.912291 # Average percentage of cache occupancy 651system.cpu.l2cache.tags.occ_percent::total 0.994085 # Average percentage of cache occupancy 652system.cpu.l2cache.tags.occ_task_id_blocks::1024 32744 # Occupied blocks per task id 653system.cpu.l2cache.tags.age_task_id_blocks_1024::0 80 # Occupied blocks per task id 654system.cpu.l2cache.tags.age_task_id_blocks_1024::1 148 # Occupied blocks per task id 655system.cpu.l2cache.tags.age_task_id_blocks_1024::2 288 # Occupied blocks per task id 656system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2812 # Occupied blocks per task id 657system.cpu.l2cache.tags.age_task_id_blocks_1024::4 29416 # Occupied blocks per task id 658system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999268 # Percentage of cache occupancy per task id 659system.cpu.l2cache.tags.tag_accesses 13211274 # Number of tag accesses 660system.cpu.l2cache.tags.data_accesses 13211274 # Number of data accesses 661system.cpu.l2cache.Writeback_hits::writebacks 88940 # number of Writeback hits 662system.cpu.l2cache.Writeback_hits::total 88940 # number of Writeback hits 663system.cpu.l2cache.ReadExReq_hits::cpu.data 3231 # number of ReadExReq hits 664system.cpu.l2cache.ReadExReq_hits::total 3231 # number of ReadExReq hits 665system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 22766 # number of ReadCleanReq hits 666system.cpu.l2cache.ReadCleanReq_hits::total 22766 # number of ReadCleanReq hits 667system.cpu.l2cache.ReadSharedReq_hits::cpu.data 490569 # number of ReadSharedReq hits 668system.cpu.l2cache.ReadSharedReq_hits::total 490569 # number of ReadSharedReq hits 669system.cpu.l2cache.demand_hits::cpu.inst 22766 # number of demand (read+write) hits 670system.cpu.l2cache.demand_hits::cpu.data 493800 # number of demand (read+write) hits 671system.cpu.l2cache.demand_hits::total 516566 # number of demand (read+write) hits 672system.cpu.l2cache.overall_hits::cpu.inst 22766 # number of overall hits 673system.cpu.l2cache.overall_hits::cpu.data 493800 # number of overall hits 674system.cpu.l2cache.overall_hits::total 516566 # number of overall hits 675system.cpu.l2cache.ReadExReq_misses::cpu.data 66091 # number of ReadExReq misses 676system.cpu.l2cache.ReadExReq_misses::total 66091 # number of ReadExReq misses 677system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2579 # number of ReadCleanReq misses 678system.cpu.l2cache.ReadCleanReq_misses::total 2579 # number of ReadCleanReq misses 679system.cpu.l2cache.ReadSharedReq_misses::cpu.data 222535 # number of ReadSharedReq misses 680system.cpu.l2cache.ReadSharedReq_misses::total 222535 # number of ReadSharedReq misses 681system.cpu.l2cache.demand_misses::cpu.inst 2579 # number of demand (read+write) misses 682system.cpu.l2cache.demand_misses::cpu.data 288626 # number of demand (read+write) misses 683system.cpu.l2cache.demand_misses::total 291205 # number of demand (read+write) misses 684system.cpu.l2cache.overall_misses::cpu.inst 2579 # number of overall misses 685system.cpu.l2cache.overall_misses::cpu.data 288626 # number of overall misses 686system.cpu.l2cache.overall_misses::total 291205 # number of overall misses 687system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4909508000 # number of ReadExReq miss cycles 688system.cpu.l2cache.ReadExReq_miss_latency::total 4909508000 # number of ReadExReq miss cycles 689system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 197530500 # number of ReadCleanReq miss cycles 690system.cpu.l2cache.ReadCleanReq_miss_latency::total 197530500 # number of ReadCleanReq miss cycles 691system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 18026385000 # number of ReadSharedReq miss cycles 692system.cpu.l2cache.ReadSharedReq_miss_latency::total 18026385000 # number of ReadSharedReq miss cycles 693system.cpu.l2cache.demand_miss_latency::cpu.inst 197530500 # number of demand (read+write) miss cycles 694system.cpu.l2cache.demand_miss_latency::cpu.data 22935893000 # number of demand (read+write) miss cycles 695system.cpu.l2cache.demand_miss_latency::total 23133423500 # number of demand (read+write) miss cycles 696system.cpu.l2cache.overall_miss_latency::cpu.inst 197530500 # number of overall miss cycles 697system.cpu.l2cache.overall_miss_latency::cpu.data 22935893000 # number of overall miss cycles 698system.cpu.l2cache.overall_miss_latency::total 23133423500 # number of overall miss cycles 699system.cpu.l2cache.Writeback_accesses::writebacks 88940 # number of Writeback accesses(hits+misses) 700system.cpu.l2cache.Writeback_accesses::total 88940 # number of Writeback accesses(hits+misses) 701system.cpu.l2cache.ReadExReq_accesses::cpu.data 69322 # number of ReadExReq accesses(hits+misses) 702system.cpu.l2cache.ReadExReq_accesses::total 69322 # number of ReadExReq accesses(hits+misses) 703system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 25345 # number of ReadCleanReq accesses(hits+misses) 704system.cpu.l2cache.ReadCleanReq_accesses::total 25345 # number of ReadCleanReq accesses(hits+misses) 705system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 713104 # number of ReadSharedReq accesses(hits+misses) 706system.cpu.l2cache.ReadSharedReq_accesses::total 713104 # number of ReadSharedReq accesses(hits+misses) 707system.cpu.l2cache.demand_accesses::cpu.inst 25345 # number of demand (read+write) accesses 708system.cpu.l2cache.demand_accesses::cpu.data 782426 # number of demand (read+write) accesses 709system.cpu.l2cache.demand_accesses::total 807771 # number of demand (read+write) accesses 710system.cpu.l2cache.overall_accesses::cpu.inst 25345 # number of overall (read+write) accesses 711system.cpu.l2cache.overall_accesses::cpu.data 782426 # number of overall (read+write) accesses 712system.cpu.l2cache.overall_accesses::total 807771 # number of overall (read+write) accesses 713system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.953391 # miss rate for ReadExReq accesses 714system.cpu.l2cache.ReadExReq_miss_rate::total 0.953391 # miss rate for ReadExReq accesses 715system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.101756 # miss rate for ReadCleanReq accesses 716system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.101756 # miss rate for ReadCleanReq accesses 717system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.312065 # miss rate for ReadSharedReq accesses 718system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.312065 # miss rate for ReadSharedReq accesses 719system.cpu.l2cache.demand_miss_rate::cpu.inst 0.101756 # miss rate for demand accesses 720system.cpu.l2cache.demand_miss_rate::cpu.data 0.368886 # miss rate for demand accesses 721system.cpu.l2cache.demand_miss_rate::total 0.360504 # miss rate for demand accesses 722system.cpu.l2cache.overall_miss_rate::cpu.inst 0.101756 # miss rate for overall accesses 723system.cpu.l2cache.overall_miss_rate::cpu.data 0.368886 # miss rate for overall accesses 724system.cpu.l2cache.overall_miss_rate::total 0.360504 # miss rate for overall accesses 725system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74284.062883 # average ReadExReq miss latency 726system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74284.062883 # average ReadExReq miss latency 727system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76591.896084 # average ReadCleanReq miss latency 728system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76591.896084 # average ReadCleanReq miss latency 729system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 81004.718359 # average ReadSharedReq miss latency 730system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 81004.718359 # average ReadSharedReq miss latency 731system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76591.896084 # average overall miss latency 732system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79465.789638 # average overall miss latency 733system.cpu.l2cache.demand_avg_miss_latency::total 79440.337563 # average overall miss latency 734system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76591.896084 # average overall miss latency 735system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79465.789638 # average overall miss latency 736system.cpu.l2cache.overall_avg_miss_latency::total 79440.337563 # average overall miss latency 737system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 738system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 739system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 740system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 741system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 742system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 743system.cpu.l2cache.fast_writes 0 # number of fast writes performed 744system.cpu.l2cache.cache_copies 0 # number of cache copies performed 745system.cpu.l2cache.writebacks::writebacks 66098 # number of writebacks 746system.cpu.l2cache.writebacks::total 66098 # number of writebacks 747system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 4 # number of ReadCleanReq MSHR hits 748system.cpu.l2cache.ReadCleanReq_mshr_hits::total 4 # number of ReadCleanReq MSHR hits 749system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 28 # number of ReadSharedReq MSHR hits 750system.cpu.l2cache.ReadSharedReq_mshr_hits::total 28 # number of ReadSharedReq MSHR hits 751system.cpu.l2cache.demand_mshr_hits::cpu.inst 4 # number of demand (read+write) MSHR hits 752system.cpu.l2cache.demand_mshr_hits::cpu.data 28 # number of demand (read+write) MSHR hits 753system.cpu.l2cache.demand_mshr_hits::total 32 # number of demand (read+write) MSHR hits 754system.cpu.l2cache.overall_mshr_hits::cpu.inst 4 # number of overall MSHR hits 755system.cpu.l2cache.overall_mshr_hits::cpu.data 28 # number of overall MSHR hits 756system.cpu.l2cache.overall_mshr_hits::total 32 # number of overall MSHR hits 757system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 369 # number of CleanEvict MSHR misses 758system.cpu.l2cache.CleanEvict_mshr_misses::total 369 # number of CleanEvict MSHR misses 759system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66091 # number of ReadExReq MSHR misses 760system.cpu.l2cache.ReadExReq_mshr_misses::total 66091 # number of ReadExReq MSHR misses 761system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2575 # number of ReadCleanReq MSHR misses 762system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2575 # number of ReadCleanReq MSHR misses 763system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 222507 # number of ReadSharedReq MSHR misses 764system.cpu.l2cache.ReadSharedReq_mshr_misses::total 222507 # number of ReadSharedReq MSHR misses 765system.cpu.l2cache.demand_mshr_misses::cpu.inst 2575 # number of demand (read+write) MSHR misses 766system.cpu.l2cache.demand_mshr_misses::cpu.data 288598 # number of demand (read+write) MSHR misses 767system.cpu.l2cache.demand_mshr_misses::total 291173 # number of demand (read+write) MSHR misses 768system.cpu.l2cache.overall_mshr_misses::cpu.inst 2575 # number of overall MSHR misses 769system.cpu.l2cache.overall_mshr_misses::cpu.data 288598 # number of overall MSHR misses 770system.cpu.l2cache.overall_mshr_misses::total 291173 # number of overall MSHR misses 771system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4248598000 # number of ReadExReq MSHR miss cycles 772system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4248598000 # number of ReadExReq MSHR miss cycles 773system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 171535500 # number of ReadCleanReq MSHR miss cycles 774system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 171535500 # number of ReadCleanReq MSHR miss cycles 775system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 15799227000 # number of ReadSharedReq MSHR miss cycles 776system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 15799227000 # number of ReadSharedReq MSHR miss cycles 777system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 171535500 # number of demand (read+write) MSHR miss cycles 778system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 20047825000 # number of demand (read+write) MSHR miss cycles 779system.cpu.l2cache.demand_mshr_miss_latency::total 20219360500 # number of demand (read+write) MSHR miss cycles 780system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 171535500 # number of overall MSHR miss cycles 781system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 20047825000 # number of overall MSHR miss cycles 782system.cpu.l2cache.overall_mshr_miss_latency::total 20219360500 # number of overall MSHR miss cycles 783system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 784system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 785system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.953391 # mshr miss rate for ReadExReq accesses 786system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.953391 # mshr miss rate for ReadExReq accesses 787system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.101598 # mshr miss rate for ReadCleanReq accesses 788system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.101598 # mshr miss rate for ReadCleanReq accesses 789system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312026 # mshr miss rate for ReadSharedReq accesses 790system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312026 # mshr miss rate for ReadSharedReq accesses 791system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.101598 # mshr miss rate for demand accesses 792system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.368850 # mshr miss rate for demand accesses 793system.cpu.l2cache.demand_mshr_miss_rate::total 0.360465 # mshr miss rate for demand accesses 794system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.101598 # mshr miss rate for overall accesses 795system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.368850 # mshr miss rate for overall accesses 796system.cpu.l2cache.overall_mshr_miss_rate::total 0.360465 # mshr miss rate for overall accesses 797system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64284.062883 # average ReadExReq mshr miss latency 798system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64284.062883 # average ReadExReq mshr miss latency 799system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66615.728155 # average ReadCleanReq mshr miss latency 800system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66615.728155 # average ReadCleanReq mshr miss latency 801system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71005.527916 # average ReadSharedReq mshr miss latency 802system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71005.527916 # average ReadSharedReq mshr miss latency 803system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66615.728155 # average overall mshr miss latency 804system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69466.264492 # average overall mshr miss latency 805system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69441.055661 # average overall mshr miss latency 806system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66615.728155 # average overall mshr miss latency 807system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69466.264492 # average overall mshr miss latency 808system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69441.055661 # average overall mshr miss latency 809system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 810system.cpu.toL2Bus.trans_dist::ReadResp 738448 # Transaction distribution 811system.cpu.toL2Bus.trans_dist::Writeback 155038 # Transaction distribution 812system.cpu.toL2Bus.trans_dist::CleanEvict 901935 # Transaction distribution 813system.cpu.toL2Bus.trans_dist::ReadExReq 69322 # Transaction distribution 814system.cpu.toL2Bus.trans_dist::ReadExResp 69322 # Transaction distribution 815system.cpu.toL2Bus.trans_dist::ReadCleanReq 25345 # Transaction distribution 816system.cpu.toL2Bus.trans_dist::ReadSharedReq 713104 # Transaction distribution 817system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 72953 # Packet count per connected master and slave (bytes) 818system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2341169 # Packet count per connected master and slave (bytes) 819system.cpu.toL2Bus.pkt_count::total 2414122 # Packet count per connected master and slave (bytes) 820system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1622016 # Cumulative packet size per connected master and slave (bytes) 821system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55767424 # Cumulative packet size per connected master and slave (bytes) 822system.cpu.toL2Bus.pkt_size::total 57389440 # Cumulative packet size per connected master and slave (bytes) 823system.cpu.toL2Bus.snoops 258392 # Total snoops (count) 824system.cpu.toL2Bus.snoop_fanout::samples 1868086 # Request fanout histogram 825system.cpu.toL2Bus.snoop_fanout::mean 1.138319 # Request fanout histogram 826system.cpu.toL2Bus.snoop_fanout::stdev 0.345235 # Request fanout histogram 827system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 828system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 829system.cpu.toL2Bus.snoop_fanout::1 1609694 86.17% 86.17% # Request fanout histogram 830system.cpu.toL2Bus.snoop_fanout::2 258392 13.83% 100.00% # Request fanout histogram 831system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 832system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 833system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 834system.cpu.toL2Bus.snoop_fanout::total 1868086 # Request fanout histogram 835system.cpu.toL2Bus.reqLayer0.occupancy 893787000 # Layer occupancy (ticks) 836system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) 837system.cpu.toL2Bus.respLayer0.occupancy 38017996 # Layer occupancy (ticks) 838system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 839system.cpu.toL2Bus.respLayer1.occupancy 1173652972 # Layer occupancy (ticks) 840system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) 841system.membus.trans_dist::ReadResp 225081 # Transaction distribution 842system.membus.trans_dist::Writeback 66098 # Transaction distribution 843system.membus.trans_dist::CleanEvict 190637 # Transaction distribution 844system.membus.trans_dist::ReadExReq 66091 # Transaction distribution 845system.membus.trans_dist::ReadExResp 66091 # Transaction distribution 846system.membus.trans_dist::ReadSharedReq 225081 # Transaction distribution 847system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 839079 # Packet count per connected master and slave (bytes) 848system.membus.pkt_count::total 839079 # Packet count per connected master and slave (bytes) 849system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22865280 # Cumulative packet size per connected master and slave (bytes) 850system.membus.pkt_size::total 22865280 # Cumulative packet size per connected master and slave (bytes) 851system.membus.snoops 0 # Total snoops (count) 852system.membus.snoop_fanout::samples 547907 # Request fanout histogram 853system.membus.snoop_fanout::mean 0 # Request fanout histogram 854system.membus.snoop_fanout::stdev 0 # Request fanout histogram 855system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 856system.membus.snoop_fanout::0 547907 100.00% 100.00% # Request fanout histogram 857system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 858system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 859system.membus.snoop_fanout::min_value 0 # Request fanout histogram 860system.membus.snoop_fanout::max_value 0 # Request fanout histogram 861system.membus.snoop_fanout::total 547907 # Request fanout histogram 862system.membus.reqLayer0.occupancy 916769500 # Layer occupancy (ticks) 863system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) 864system.membus.respLayer1.occupancy 1554235250 # Layer occupancy (ticks) 865system.membus.respLayer1.utilization 0.3 # Layer utilization (%) 866 867---------- End Simulation Statistics ---------- 868