stats.txt revision 10827:7f5467f2f8b8
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.545048 # Number of seconds simulated 4sim_ticks 545048444500 # Number of ticks simulated 5final_tick 545048444500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 177094 # Simulator instruction rate (inst/s) 8host_op_rate 218026 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 150665678 # Simulator tick rate (ticks/s) 10host_mem_usage 323140 # Number of bytes of host memory used 11host_seconds 3617.60 # Real time elapsed on the host 12sim_insts 640655085 # Number of instructions simulated 13sim_ops 788730744 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 164544 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 18429312 # Number of bytes read from this memory 18system.physmem.bytes_read::total 18593856 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 164544 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 164544 # Number of instructions bytes read from this memory 21system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory 22system.physmem.bytes_written::total 4230272 # Number of bytes written to this memory 23system.physmem.num_reads::cpu.inst 2571 # Number of read requests responded to by this memory 24system.physmem.num_reads::cpu.data 287958 # Number of read requests responded to by this memory 25system.physmem.num_reads::total 290529 # Number of read requests responded to by this memory 26system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory 27system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory 28system.physmem.bw_read::cpu.inst 301889 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::cpu.data 33812246 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::total 34114135 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_inst_read::cpu.inst 301889 # Instruction read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::total 301889 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_write::writebacks 7761277 # Write bandwidth from this memory (bytes/s) 34system.physmem.bw_write::total 7761277 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_total::writebacks 7761277 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::cpu.inst 301889 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.data 33812246 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::total 41875412 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.readReqs 290529 # Number of read requests accepted 40system.physmem.writeReqs 66098 # Number of write requests accepted 41system.physmem.readBursts 290529 # Number of DRAM read bursts, including those serviced by the write queue 42system.physmem.writeBursts 66098 # Number of DRAM write bursts, including those merged in the write queue 43system.physmem.bytesReadDRAM 18574016 # Total number of bytes read from DRAM 44system.physmem.bytesReadWrQ 19840 # Total number of bytes read from write queue 45system.physmem.bytesWritten 4228992 # Total number of bytes written to DRAM 46system.physmem.bytesReadSys 18593856 # Total read bytes from the system interface side 47system.physmem.bytesWrittenSys 4230272 # Total written bytes from the system interface side 48system.physmem.servicedByWrQ 310 # Number of DRAM read bursts serviced by the write queue 49system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 50system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 51system.physmem.perBankRdBursts::0 18284 # Per bank write bursts 52system.physmem.perBankRdBursts::1 18137 # Per bank write bursts 53system.physmem.perBankRdBursts::2 18223 # Per bank write bursts 54system.physmem.perBankRdBursts::3 18185 # Per bank write bursts 55system.physmem.perBankRdBursts::4 18266 # Per bank write bursts 56system.physmem.perBankRdBursts::5 18315 # Per bank write bursts 57system.physmem.perBankRdBursts::6 18094 # Per bank write bursts 58system.physmem.perBankRdBursts::7 17909 # Per bank write bursts 59system.physmem.perBankRdBursts::8 17941 # Per bank write bursts 60system.physmem.perBankRdBursts::9 17963 # Per bank write bursts 61system.physmem.perBankRdBursts::10 18019 # Per bank write bursts 62system.physmem.perBankRdBursts::11 18118 # Per bank write bursts 63system.physmem.perBankRdBursts::12 18147 # Per bank write bursts 64system.physmem.perBankRdBursts::13 18275 # Per bank write bursts 65system.physmem.perBankRdBursts::14 18077 # Per bank write bursts 66system.physmem.perBankRdBursts::15 18266 # Per bank write bursts 67system.physmem.perBankWrBursts::0 4174 # Per bank write bursts 68system.physmem.perBankWrBursts::1 4102 # Per bank write bursts 69system.physmem.perBankWrBursts::2 4137 # Per bank write bursts 70system.physmem.perBankWrBursts::3 4147 # Per bank write bursts 71system.physmem.perBankWrBursts::4 4226 # Per bank write bursts 72system.physmem.perBankWrBursts::5 4225 # Per bank write bursts 73system.physmem.perBankWrBursts::6 4171 # Per bank write bursts 74system.physmem.perBankWrBursts::7 4094 # Per bank write bursts 75system.physmem.perBankWrBursts::8 4095 # Per bank write bursts 76system.physmem.perBankWrBursts::9 4090 # Per bank write bursts 77system.physmem.perBankWrBursts::10 4090 # Per bank write bursts 78system.physmem.perBankWrBursts::11 4097 # Per bank write bursts 79system.physmem.perBankWrBursts::12 4098 # Per bank write bursts 80system.physmem.perBankWrBursts::13 4096 # Per bank write bursts 81system.physmem.perBankWrBursts::14 4096 # Per bank write bursts 82system.physmem.perBankWrBursts::15 4140 # Per bank write bursts 83system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 84system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 85system.physmem.totGap 545048350000 # Total gap between requests 86system.physmem.readPktSize::0 0 # Read request sizes (log2) 87system.physmem.readPktSize::1 0 # Read request sizes (log2) 88system.physmem.readPktSize::2 0 # Read request sizes (log2) 89system.physmem.readPktSize::3 0 # Read request sizes (log2) 90system.physmem.readPktSize::4 0 # Read request sizes (log2) 91system.physmem.readPktSize::5 0 # Read request sizes (log2) 92system.physmem.readPktSize::6 290529 # Read request sizes (log2) 93system.physmem.writePktSize::0 0 # Write request sizes (log2) 94system.physmem.writePktSize::1 0 # Write request sizes (log2) 95system.physmem.writePktSize::2 0 # Write request sizes (log2) 96system.physmem.writePktSize::3 0 # Write request sizes (log2) 97system.physmem.writePktSize::4 0 # Write request sizes (log2) 98system.physmem.writePktSize::5 0 # Write request sizes (log2) 99system.physmem.writePktSize::6 66098 # Write request sizes (log2) 100system.physmem.rdQLenPdf::0 289827 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::1 376 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::2 16 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 132system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 133system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 134system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::15 967 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::16 967 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::17 4010 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::18 4010 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::19 4010 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::20 4009 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::21 4010 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::22 4009 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::23 4009 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::24 4009 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::25 4009 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::26 4009 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::27 4010 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::28 4009 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::29 4009 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::30 4009 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::31 4009 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::32 4009 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 196system.physmem.bytesPerActivate::samples 112309 # Bytes accessed per row activation 197system.physmem.bytesPerActivate::mean 203.026151 # Bytes accessed per row activation 198system.physmem.bytesPerActivate::gmean 132.211216 # Bytes accessed per row activation 199system.physmem.bytesPerActivate::stdev 254.422571 # Bytes accessed per row activation 200system.physmem.bytesPerActivate::0-127 47277 42.10% 42.10% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::128-255 43772 38.97% 81.07% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::256-383 8960 7.98% 89.05% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::384-511 1911 1.70% 90.75% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::512-639 490 0.44% 91.19% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::640-767 736 0.66% 91.84% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::768-895 729 0.65% 92.49% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::896-1023 499 0.44% 92.93% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::1024-1151 7935 7.07% 100.00% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::total 112309 # Bytes accessed per row activation 210system.physmem.rdPerTurnAround::samples 4009 # Reads before turning the bus around for writes 211system.physmem.rdPerTurnAround::mean 48.524570 # Reads before turning the bus around for writes 212system.physmem.rdPerTurnAround::gmean 36.056534 # Reads before turning the bus around for writes 213system.physmem.rdPerTurnAround::stdev 507.518625 # Reads before turning the bus around for writes 214system.physmem.rdPerTurnAround::0-1023 4006 99.93% 99.93% # Reads before turning the bus around for writes 215system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.95% # Reads before turning the bus around for writes 216system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes 217system.physmem.rdPerTurnAround::31744-32767 1 0.02% 100.00% # Reads before turning the bus around for writes 218system.physmem.rdPerTurnAround::total 4009 # Reads before turning the bus around for writes 219system.physmem.wrPerTurnAround::samples 4009 # Writes before turning the bus around for reads 220system.physmem.wrPerTurnAround::mean 16.482415 # Writes before turning the bus around for reads 221system.physmem.wrPerTurnAround::gmean 16.461068 # Writes before turning the bus around for reads 222system.physmem.wrPerTurnAround::stdev 0.856030 # Writes before turning the bus around for reads 223system.physmem.wrPerTurnAround::16 3042 75.88% 75.88% # Writes before turning the bus around for reads 224system.physmem.wrPerTurnAround::17 1 0.02% 75.90% # Writes before turning the bus around for reads 225system.physmem.wrPerTurnAround::18 965 24.07% 99.98% # Writes before turning the bus around for reads 226system.physmem.wrPerTurnAround::19 1 0.02% 100.00% # Writes before turning the bus around for reads 227system.physmem.wrPerTurnAround::total 4009 # Writes before turning the bus around for reads 228system.physmem.totQLat 2724193250 # Total ticks spent queuing 229system.physmem.totMemAccLat 8165799500 # Total ticks spent from burst creation until serviced by the DRAM 230system.physmem.totBusLat 1451095000 # Total ticks spent in databus transfers 231system.physmem.avgQLat 9386.68 # Average queueing delay per DRAM burst 232system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 233system.physmem.avgMemAccLat 28136.68 # Average memory access latency per DRAM burst 234system.physmem.avgRdBW 34.08 # Average DRAM read bandwidth in MiByte/s 235system.physmem.avgWrBW 7.76 # Average achieved write bandwidth in MiByte/s 236system.physmem.avgRdBWSys 34.11 # Average system read bandwidth in MiByte/s 237system.physmem.avgWrBWSys 7.76 # Average system write bandwidth in MiByte/s 238system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 239system.physmem.busUtil 0.33 # Data bus utilization in percentage 240system.physmem.busUtilRead 0.27 # Data bus utilization in percentage for reads 241system.physmem.busUtilWrite 0.06 # Data bus utilization in percentage for writes 242system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing 243system.physmem.avgWrQLen 21.79 # Average write queue length when enqueuing 244system.physmem.readRowHits 193908 # Number of row buffer hits during reads 245system.physmem.writeRowHits 50072 # Number of row buffer hits during writes 246system.physmem.readRowHitRate 66.81 # Row buffer hit rate for reads 247system.physmem.writeRowHitRate 75.75 # Row buffer hit rate for writes 248system.physmem.avgGap 1528342.92 # Average gap between requests 249system.physmem.pageHitRate 68.47 # Row buffer hit rate, read and write combined 250system.physmem_0.actEnergy 423889200 # Energy for activate commands per rank (pJ) 251system.physmem_0.preEnergy 231288750 # Energy for precharge commands per rank (pJ) 252system.physmem_0.readEnergy 1134182400 # Energy for read commands per rank (pJ) 253system.physmem_0.writeEnergy 215628480 # Energy for write commands per rank (pJ) 254system.physmem_0.refreshEnergy 35599708560 # Energy for refresh commands per rank (pJ) 255system.physmem_0.actBackEnergy 106422668235 # Energy for active background per rank (pJ) 256system.physmem_0.preBackEnergy 233674110000 # Energy for precharge background per rank (pJ) 257system.physmem_0.totalEnergy 377701475625 # Total energy per rank (pJ) 258system.physmem_0.averagePower 692.972318 # Core power per rank (mW) 259system.physmem_0.memoryStateTime::IDLE 388027097500 # Time in different power states 260system.physmem_0.memoryStateTime::REF 18200260000 # Time in different power states 261system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 262system.physmem_0.memoryStateTime::ACT 138818528500 # Time in different power states 263system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 264system.physmem_1.actEnergy 425113920 # Energy for activate commands per rank (pJ) 265system.physmem_1.preEnergy 231957000 # Energy for precharge commands per rank (pJ) 266system.physmem_1.readEnergy 1129245000 # Energy for read commands per rank (pJ) 267system.physmem_1.writeEnergy 212556960 # Energy for write commands per rank (pJ) 268system.physmem_1.refreshEnergy 35599708560 # Energy for refresh commands per rank (pJ) 269system.physmem_1.actBackEnergy 106328346345 # Energy for active background per rank (pJ) 270system.physmem_1.preBackEnergy 233756848500 # Energy for precharge background per rank (pJ) 271system.physmem_1.totalEnergy 377683776285 # Total energy per rank (pJ) 272system.physmem_1.averagePower 692.939845 # Core power per rank (mW) 273system.physmem_1.memoryStateTime::IDLE 388162097500 # Time in different power states 274system.physmem_1.memoryStateTime::REF 18200260000 # Time in different power states 275system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 276system.physmem_1.memoryStateTime::ACT 138683202500 # Time in different power states 277system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 278system.cpu.branchPred.lookups 155052076 # Number of BP lookups 279system.cpu.branchPred.condPredicted 105344550 # Number of conditional branches predicted 280system.cpu.branchPred.condIncorrect 12879569 # Number of conditional branches incorrect 281system.cpu.branchPred.BTBLookups 90401009 # Number of BTB lookups 282system.cpu.branchPred.BTBHits 82966187 # Number of BTB hits 283system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 284system.cpu.branchPred.BTBHitPct 91.775731 # BTB Hit Percentage 285system.cpu.branchPred.usedRAS 19284792 # Number of times the RAS was used to get a target. 286system.cpu.branchPred.RASInCorrect 1316 # Number of incorrect RAS predictions. 287system.cpu_clk_domain.clock 500 # Clock period in ticks 288system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 289system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 290system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 291system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 292system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 293system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 294system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 295system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 296system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 297system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 298system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 299system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 300system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 301system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 302system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 303system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 304system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 305system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 306system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 307system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 308system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 309system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 310system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 311system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 312system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 313system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 314system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 315system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 316system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 317system.cpu.dtb.walker.walks 0 # Table walker walks requested 318system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 319system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 320system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 321system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 322system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 323system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 324system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 325system.cpu.dtb.inst_hits 0 # ITB inst hits 326system.cpu.dtb.inst_misses 0 # ITB inst misses 327system.cpu.dtb.read_hits 0 # DTB read hits 328system.cpu.dtb.read_misses 0 # DTB read misses 329system.cpu.dtb.write_hits 0 # DTB write hits 330system.cpu.dtb.write_misses 0 # DTB write misses 331system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 332system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 333system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 334system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 335system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 336system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 337system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 338system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 339system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 340system.cpu.dtb.read_accesses 0 # DTB read accesses 341system.cpu.dtb.write_accesses 0 # DTB write accesses 342system.cpu.dtb.inst_accesses 0 # ITB inst accesses 343system.cpu.dtb.hits 0 # DTB hits 344system.cpu.dtb.misses 0 # DTB misses 345system.cpu.dtb.accesses 0 # DTB accesses 346system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 347system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 348system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 349system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 350system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 351system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 352system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 353system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 354system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 355system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 356system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 357system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 358system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 359system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 360system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 361system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 362system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 363system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 364system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 365system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 366system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 367system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 368system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 369system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 370system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 371system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 372system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 373system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 374system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 375system.cpu.itb.walker.walks 0 # Table walker walks requested 376system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 377system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 378system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 379system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 380system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 381system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 382system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 383system.cpu.itb.inst_hits 0 # ITB inst hits 384system.cpu.itb.inst_misses 0 # ITB inst misses 385system.cpu.itb.read_hits 0 # DTB read hits 386system.cpu.itb.read_misses 0 # DTB read misses 387system.cpu.itb.write_hits 0 # DTB write hits 388system.cpu.itb.write_misses 0 # DTB write misses 389system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 390system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 391system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 392system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 393system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 394system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 395system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 396system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 397system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 398system.cpu.itb.read_accesses 0 # DTB read accesses 399system.cpu.itb.write_accesses 0 # DTB write accesses 400system.cpu.itb.inst_accesses 0 # ITB inst accesses 401system.cpu.itb.hits 0 # DTB hits 402system.cpu.itb.misses 0 # DTB misses 403system.cpu.itb.accesses 0 # DTB accesses 404system.cpu.workload.num_syscalls 673 # Number of system calls 405system.cpu.numCycles 1090096889 # number of cpu cycles simulated 406system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 407system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 408system.cpu.committedInsts 640655085 # Number of instructions committed 409system.cpu.committedOps 788730744 # Number of ops (including micro ops) committed 410system.cpu.discardedOps 22623818 # Number of ops (including micro ops) which were discarded before commit 411system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching 412system.cpu.cpi 1.701535 # CPI: cycles per instruction 413system.cpu.ipc 0.587705 # IPC: instructions per cycle 414system.cpu.tickCycles 1030366439 # Number of cycles that the object actually ticked 415system.cpu.idleCycles 59730450 # Total number of cycles that the object has spent stopped 416system.cpu.dcache.tags.replacements 778156 # number of replacements 417system.cpu.dcache.tags.tagsinuse 4092.460333 # Cycle average of tags in use 418system.cpu.dcache.tags.total_refs 378456871 # Total number of references to valid blocks. 419system.cpu.dcache.tags.sampled_refs 782252 # Sample count of references to valid blocks. 420system.cpu.dcache.tags.avg_refs 483.804287 # Average number of references to valid blocks. 421system.cpu.dcache.tags.warmup_cycle 802330000 # Cycle when the warmup percentage was hit. 422system.cpu.dcache.tags.occ_blocks::cpu.data 4092.460333 # Average occupied blocks per requestor 423system.cpu.dcache.tags.occ_percent::cpu.data 0.999136 # Average percentage of cache occupancy 424system.cpu.dcache.tags.occ_percent::total 0.999136 # Average percentage of cache occupancy 425system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 426system.cpu.dcache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id 427system.cpu.dcache.tags.age_task_id_blocks_1024::1 172 # Occupied blocks per task id 428system.cpu.dcache.tags.age_task_id_blocks_1024::2 962 # Occupied blocks per task id 429system.cpu.dcache.tags.age_task_id_blocks_1024::3 1339 # Occupied blocks per task id 430system.cpu.dcache.tags.age_task_id_blocks_1024::4 1593 # Occupied blocks per task id 431system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 432system.cpu.dcache.tags.tag_accesses 759399046 # Number of tag accesses 433system.cpu.dcache.tags.data_accesses 759399046 # Number of data accesses 434system.cpu.dcache.ReadReq_hits::cpu.data 249628143 # number of ReadReq hits 435system.cpu.dcache.ReadReq_hits::total 249628143 # number of ReadReq hits 436system.cpu.dcache.WriteReq_hits::cpu.data 128813765 # number of WriteReq hits 437system.cpu.dcache.WriteReq_hits::total 128813765 # number of WriteReq hits 438system.cpu.dcache.SoftPFReq_hits::cpu.data 3485 # number of SoftPFReq hits 439system.cpu.dcache.SoftPFReq_hits::total 3485 # number of SoftPFReq hits 440system.cpu.dcache.LoadLockedReq_hits::cpu.data 5739 # number of LoadLockedReq hits 441system.cpu.dcache.LoadLockedReq_hits::total 5739 # number of LoadLockedReq hits 442system.cpu.dcache.StoreCondReq_hits::cpu.data 5739 # number of StoreCondReq hits 443system.cpu.dcache.StoreCondReq_hits::total 5739 # number of StoreCondReq hits 444system.cpu.dcache.demand_hits::cpu.data 378441908 # number of demand (read+write) hits 445system.cpu.dcache.demand_hits::total 378441908 # number of demand (read+write) hits 446system.cpu.dcache.overall_hits::cpu.data 378445393 # number of overall hits 447system.cpu.dcache.overall_hits::total 378445393 # number of overall hits 448system.cpu.dcache.ReadReq_misses::cpu.data 713673 # number of ReadReq misses 449system.cpu.dcache.ReadReq_misses::total 713673 # number of ReadReq misses 450system.cpu.dcache.WriteReq_misses::cpu.data 137712 # number of WriteReq misses 451system.cpu.dcache.WriteReq_misses::total 137712 # number of WriteReq misses 452system.cpu.dcache.SoftPFReq_misses::cpu.data 141 # number of SoftPFReq misses 453system.cpu.dcache.SoftPFReq_misses::total 141 # number of SoftPFReq misses 454system.cpu.dcache.demand_misses::cpu.data 851385 # number of demand (read+write) misses 455system.cpu.dcache.demand_misses::total 851385 # number of demand (read+write) misses 456system.cpu.dcache.overall_misses::cpu.data 851526 # number of overall misses 457system.cpu.dcache.overall_misses::total 851526 # number of overall misses 458system.cpu.dcache.ReadReq_miss_latency::cpu.data 24678796218 # number of ReadReq miss cycles 459system.cpu.dcache.ReadReq_miss_latency::total 24678796218 # number of ReadReq miss cycles 460system.cpu.dcache.WriteReq_miss_latency::cpu.data 10203720250 # number of WriteReq miss cycles 461system.cpu.dcache.WriteReq_miss_latency::total 10203720250 # number of WriteReq miss cycles 462system.cpu.dcache.demand_miss_latency::cpu.data 34882516468 # number of demand (read+write) miss cycles 463system.cpu.dcache.demand_miss_latency::total 34882516468 # number of demand (read+write) miss cycles 464system.cpu.dcache.overall_miss_latency::cpu.data 34882516468 # number of overall miss cycles 465system.cpu.dcache.overall_miss_latency::total 34882516468 # number of overall miss cycles 466system.cpu.dcache.ReadReq_accesses::cpu.data 250341816 # number of ReadReq accesses(hits+misses) 467system.cpu.dcache.ReadReq_accesses::total 250341816 # number of ReadReq accesses(hits+misses) 468system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses) 469system.cpu.dcache.WriteReq_accesses::total 128951477 # number of WriteReq accesses(hits+misses) 470system.cpu.dcache.SoftPFReq_accesses::cpu.data 3626 # number of SoftPFReq accesses(hits+misses) 471system.cpu.dcache.SoftPFReq_accesses::total 3626 # number of SoftPFReq accesses(hits+misses) 472system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5739 # number of LoadLockedReq accesses(hits+misses) 473system.cpu.dcache.LoadLockedReq_accesses::total 5739 # number of LoadLockedReq accesses(hits+misses) 474system.cpu.dcache.StoreCondReq_accesses::cpu.data 5739 # number of StoreCondReq accesses(hits+misses) 475system.cpu.dcache.StoreCondReq_accesses::total 5739 # number of StoreCondReq accesses(hits+misses) 476system.cpu.dcache.demand_accesses::cpu.data 379293293 # number of demand (read+write) accesses 477system.cpu.dcache.demand_accesses::total 379293293 # number of demand (read+write) accesses 478system.cpu.dcache.overall_accesses::cpu.data 379296919 # number of overall (read+write) accesses 479system.cpu.dcache.overall_accesses::total 379296919 # number of overall (read+write) accesses 480system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002851 # miss rate for ReadReq accesses 481system.cpu.dcache.ReadReq_miss_rate::total 0.002851 # miss rate for ReadReq accesses 482system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001068 # miss rate for WriteReq accesses 483system.cpu.dcache.WriteReq_miss_rate::total 0.001068 # miss rate for WriteReq accesses 484system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.038886 # miss rate for SoftPFReq accesses 485system.cpu.dcache.SoftPFReq_miss_rate::total 0.038886 # miss rate for SoftPFReq accesses 486system.cpu.dcache.demand_miss_rate::cpu.data 0.002245 # miss rate for demand accesses 487system.cpu.dcache.demand_miss_rate::total 0.002245 # miss rate for demand accesses 488system.cpu.dcache.overall_miss_rate::cpu.data 0.002245 # miss rate for overall accesses 489system.cpu.dcache.overall_miss_rate::total 0.002245 # miss rate for overall accesses 490system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34579.977410 # average ReadReq miss latency 491system.cpu.dcache.ReadReq_avg_miss_latency::total 34579.977410 # average ReadReq miss latency 492system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 74094.634091 # average WriteReq miss latency 493system.cpu.dcache.WriteReq_avg_miss_latency::total 74094.634091 # average WriteReq miss latency 494system.cpu.dcache.demand_avg_miss_latency::cpu.data 40971.495232 # average overall miss latency 495system.cpu.dcache.demand_avg_miss_latency::total 40971.495232 # average overall miss latency 496system.cpu.dcache.overall_avg_miss_latency::cpu.data 40964.710964 # average overall miss latency 497system.cpu.dcache.overall_avg_miss_latency::total 40964.710964 # average overall miss latency 498system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 499system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 500system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 501system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 502system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 503system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 504system.cpu.dcache.fast_writes 0 # number of fast writes performed 505system.cpu.dcache.cache_copies 0 # number of cache copies performed 506system.cpu.dcache.writebacks::writebacks 91420 # number of writebacks 507system.cpu.dcache.writebacks::total 91420 # number of writebacks 508system.cpu.dcache.ReadReq_mshr_hits::cpu.data 882 # number of ReadReq MSHR hits 509system.cpu.dcache.ReadReq_mshr_hits::total 882 # number of ReadReq MSHR hits 510system.cpu.dcache.WriteReq_mshr_hits::cpu.data 68390 # number of WriteReq MSHR hits 511system.cpu.dcache.WriteReq_mshr_hits::total 68390 # number of WriteReq MSHR hits 512system.cpu.dcache.demand_mshr_hits::cpu.data 69272 # number of demand (read+write) MSHR hits 513system.cpu.dcache.demand_mshr_hits::total 69272 # number of demand (read+write) MSHR hits 514system.cpu.dcache.overall_mshr_hits::cpu.data 69272 # number of overall MSHR hits 515system.cpu.dcache.overall_mshr_hits::total 69272 # number of overall MSHR hits 516system.cpu.dcache.ReadReq_mshr_misses::cpu.data 712791 # number of ReadReq MSHR misses 517system.cpu.dcache.ReadReq_mshr_misses::total 712791 # number of ReadReq MSHR misses 518system.cpu.dcache.WriteReq_mshr_misses::cpu.data 69322 # number of WriteReq MSHR misses 519system.cpu.dcache.WriteReq_mshr_misses::total 69322 # number of WriteReq MSHR misses 520system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 139 # number of SoftPFReq MSHR misses 521system.cpu.dcache.SoftPFReq_mshr_misses::total 139 # number of SoftPFReq MSHR misses 522system.cpu.dcache.demand_mshr_misses::cpu.data 782113 # number of demand (read+write) MSHR misses 523system.cpu.dcache.demand_mshr_misses::total 782113 # number of demand (read+write) MSHR misses 524system.cpu.dcache.overall_mshr_misses::cpu.data 782252 # number of overall MSHR misses 525system.cpu.dcache.overall_mshr_misses::total 782252 # number of overall MSHR misses 526system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23523501277 # number of ReadReq MSHR miss cycles 527system.cpu.dcache.ReadReq_mshr_miss_latency::total 23523501277 # number of ReadReq MSHR miss cycles 528system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5052240750 # number of WriteReq MSHR miss cycles 529system.cpu.dcache.WriteReq_mshr_miss_latency::total 5052240750 # number of WriteReq MSHR miss cycles 530system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1719000 # number of SoftPFReq MSHR miss cycles 531system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1719000 # number of SoftPFReq MSHR miss cycles 532system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28575742027 # number of demand (read+write) MSHR miss cycles 533system.cpu.dcache.demand_mshr_miss_latency::total 28575742027 # number of demand (read+write) MSHR miss cycles 534system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28577461027 # number of overall MSHR miss cycles 535system.cpu.dcache.overall_mshr_miss_latency::total 28577461027 # number of overall MSHR miss cycles 536system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002847 # mshr miss rate for ReadReq accesses 537system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002847 # mshr miss rate for ReadReq accesses 538system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000538 # mshr miss rate for WriteReq accesses 539system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000538 # mshr miss rate for WriteReq accesses 540system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.038334 # mshr miss rate for SoftPFReq accesses 541system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.038334 # mshr miss rate for SoftPFReq accesses 542system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002062 # mshr miss rate for demand accesses 543system.cpu.dcache.demand_mshr_miss_rate::total 0.002062 # mshr miss rate for demand accesses 544system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002062 # mshr miss rate for overall accesses 545system.cpu.dcache.overall_mshr_miss_rate::total 0.002062 # mshr miss rate for overall accesses 546system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33001.961693 # average ReadReq mshr miss latency 547system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33001.961693 # average ReadReq mshr miss latency 548system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72880.770174 # average WriteReq mshr miss latency 549system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72880.770174 # average WriteReq mshr miss latency 550system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12366.906475 # average SoftPFReq mshr miss latency 551system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12366.906475 # average SoftPFReq mshr miss latency 552system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36536.590016 # average overall mshr miss latency 553system.cpu.dcache.demand_avg_mshr_miss_latency::total 36536.590016 # average overall mshr miss latency 554system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 36532.295254 # average overall mshr miss latency 555system.cpu.dcache.overall_avg_mshr_miss_latency::total 36532.295254 # average overall mshr miss latency 556system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 557system.cpu.icache.tags.replacements 23595 # number of replacements 558system.cpu.icache.tags.tagsinuse 1710.136306 # Cycle average of tags in use 559system.cpu.icache.tags.total_refs 292011682 # Total number of references to valid blocks. 560system.cpu.icache.tags.sampled_refs 25344 # Sample count of references to valid blocks. 561system.cpu.icache.tags.avg_refs 11521.925584 # Average number of references to valid blocks. 562system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 563system.cpu.icache.tags.occ_blocks::cpu.inst 1710.136306 # Average occupied blocks per requestor 564system.cpu.icache.tags.occ_percent::cpu.inst 0.835027 # Average percentage of cache occupancy 565system.cpu.icache.tags.occ_percent::total 0.835027 # Average percentage of cache occupancy 566system.cpu.icache.tags.occ_task_id_blocks::1024 1749 # Occupied blocks per task id 567system.cpu.icache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id 568system.cpu.icache.tags.age_task_id_blocks_1024::1 92 # Occupied blocks per task id 569system.cpu.icache.tags.age_task_id_blocks_1024::4 1601 # Occupied blocks per task id 570system.cpu.icache.tags.occ_task_id_percent::1024 0.854004 # Percentage of cache occupancy per task id 571system.cpu.icache.tags.tag_accesses 584099398 # Number of tag accesses 572system.cpu.icache.tags.data_accesses 584099398 # Number of data accesses 573system.cpu.icache.ReadReq_hits::cpu.inst 292011682 # number of ReadReq hits 574system.cpu.icache.ReadReq_hits::total 292011682 # number of ReadReq hits 575system.cpu.icache.demand_hits::cpu.inst 292011682 # number of demand (read+write) hits 576system.cpu.icache.demand_hits::total 292011682 # number of demand (read+write) hits 577system.cpu.icache.overall_hits::cpu.inst 292011682 # number of overall hits 578system.cpu.icache.overall_hits::total 292011682 # number of overall hits 579system.cpu.icache.ReadReq_misses::cpu.inst 25345 # number of ReadReq misses 580system.cpu.icache.ReadReq_misses::total 25345 # number of ReadReq misses 581system.cpu.icache.demand_misses::cpu.inst 25345 # number of demand (read+write) misses 582system.cpu.icache.demand_misses::total 25345 # number of demand (read+write) misses 583system.cpu.icache.overall_misses::cpu.inst 25345 # number of overall misses 584system.cpu.icache.overall_misses::total 25345 # number of overall misses 585system.cpu.icache.ReadReq_miss_latency::cpu.inst 498945745 # number of ReadReq miss cycles 586system.cpu.icache.ReadReq_miss_latency::total 498945745 # number of ReadReq miss cycles 587system.cpu.icache.demand_miss_latency::cpu.inst 498945745 # number of demand (read+write) miss cycles 588system.cpu.icache.demand_miss_latency::total 498945745 # number of demand (read+write) miss cycles 589system.cpu.icache.overall_miss_latency::cpu.inst 498945745 # number of overall miss cycles 590system.cpu.icache.overall_miss_latency::total 498945745 # number of overall miss cycles 591system.cpu.icache.ReadReq_accesses::cpu.inst 292037027 # number of ReadReq accesses(hits+misses) 592system.cpu.icache.ReadReq_accesses::total 292037027 # number of ReadReq accesses(hits+misses) 593system.cpu.icache.demand_accesses::cpu.inst 292037027 # number of demand (read+write) accesses 594system.cpu.icache.demand_accesses::total 292037027 # number of demand (read+write) accesses 595system.cpu.icache.overall_accesses::cpu.inst 292037027 # number of overall (read+write) accesses 596system.cpu.icache.overall_accesses::total 292037027 # number of overall (read+write) accesses 597system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000087 # miss rate for ReadReq accesses 598system.cpu.icache.ReadReq_miss_rate::total 0.000087 # miss rate for ReadReq accesses 599system.cpu.icache.demand_miss_rate::cpu.inst 0.000087 # miss rate for demand accesses 600system.cpu.icache.demand_miss_rate::total 0.000087 # miss rate for demand accesses 601system.cpu.icache.overall_miss_rate::cpu.inst 0.000087 # miss rate for overall accesses 602system.cpu.icache.overall_miss_rate::total 0.000087 # miss rate for overall accesses 603system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19686.160781 # average ReadReq miss latency 604system.cpu.icache.ReadReq_avg_miss_latency::total 19686.160781 # average ReadReq miss latency 605system.cpu.icache.demand_avg_miss_latency::cpu.inst 19686.160781 # average overall miss latency 606system.cpu.icache.demand_avg_miss_latency::total 19686.160781 # average overall miss latency 607system.cpu.icache.overall_avg_miss_latency::cpu.inst 19686.160781 # average overall miss latency 608system.cpu.icache.overall_avg_miss_latency::total 19686.160781 # average overall miss latency 609system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 610system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 611system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 612system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 613system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 614system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 615system.cpu.icache.fast_writes 0 # number of fast writes performed 616system.cpu.icache.cache_copies 0 # number of cache copies performed 617system.cpu.icache.ReadReq_mshr_misses::cpu.inst 25345 # number of ReadReq MSHR misses 618system.cpu.icache.ReadReq_mshr_misses::total 25345 # number of ReadReq MSHR misses 619system.cpu.icache.demand_mshr_misses::cpu.inst 25345 # number of demand (read+write) MSHR misses 620system.cpu.icache.demand_mshr_misses::total 25345 # number of demand (read+write) MSHR misses 621system.cpu.icache.overall_mshr_misses::cpu.inst 25345 # number of overall MSHR misses 622system.cpu.icache.overall_mshr_misses::total 25345 # number of overall MSHR misses 623system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 459825255 # number of ReadReq MSHR miss cycles 624system.cpu.icache.ReadReq_mshr_miss_latency::total 459825255 # number of ReadReq MSHR miss cycles 625system.cpu.icache.demand_mshr_miss_latency::cpu.inst 459825255 # number of demand (read+write) MSHR miss cycles 626system.cpu.icache.demand_mshr_miss_latency::total 459825255 # number of demand (read+write) MSHR miss cycles 627system.cpu.icache.overall_mshr_miss_latency::cpu.inst 459825255 # number of overall MSHR miss cycles 628system.cpu.icache.overall_mshr_miss_latency::total 459825255 # number of overall MSHR miss cycles 629system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000087 # mshr miss rate for ReadReq accesses 630system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000087 # mshr miss rate for ReadReq accesses 631system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000087 # mshr miss rate for demand accesses 632system.cpu.icache.demand_mshr_miss_rate::total 0.000087 # mshr miss rate for demand accesses 633system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000087 # mshr miss rate for overall accesses 634system.cpu.icache.overall_mshr_miss_rate::total 0.000087 # mshr miss rate for overall accesses 635system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18142.641744 # average ReadReq mshr miss latency 636system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18142.641744 # average ReadReq mshr miss latency 637system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18142.641744 # average overall mshr miss latency 638system.cpu.icache.demand_avg_mshr_miss_latency::total 18142.641744 # average overall mshr miss latency 639system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18142.641744 # average overall mshr miss latency 640system.cpu.icache.overall_avg_mshr_miss_latency::total 18142.641744 # average overall mshr miss latency 641system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 642system.cpu.l2cache.tags.replacements 257749 # number of replacements 643system.cpu.l2cache.tags.tagsinuse 32573.780035 # Cycle average of tags in use 644system.cpu.l2cache.tags.total_refs 539008 # Total number of references to valid blocks. 645system.cpu.l2cache.tags.sampled_refs 290493 # Sample count of references to valid blocks. 646system.cpu.l2cache.tags.avg_refs 1.855494 # Average number of references to valid blocks. 647system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 648system.cpu.l2cache.tags.occ_blocks::writebacks 2882.224162 # Average occupied blocks per requestor 649system.cpu.l2cache.tags.occ_blocks::cpu.inst 89.373270 # Average occupied blocks per requestor 650system.cpu.l2cache.tags.occ_blocks::cpu.data 29602.182603 # Average occupied blocks per requestor 651system.cpu.l2cache.tags.occ_percent::writebacks 0.087959 # Average percentage of cache occupancy 652system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002727 # Average percentage of cache occupancy 653system.cpu.l2cache.tags.occ_percent::cpu.data 0.903387 # Average percentage of cache occupancy 654system.cpu.l2cache.tags.occ_percent::total 0.994073 # Average percentage of cache occupancy 655system.cpu.l2cache.tags.occ_task_id_blocks::1024 32744 # Occupied blocks per task id 656system.cpu.l2cache.tags.age_task_id_blocks_1024::0 80 # Occupied blocks per task id 657system.cpu.l2cache.tags.age_task_id_blocks_1024::1 149 # Occupied blocks per task id 658system.cpu.l2cache.tags.age_task_id_blocks_1024::2 288 # Occupied blocks per task id 659system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2792 # Occupied blocks per task id 660system.cpu.l2cache.tags.age_task_id_blocks_1024::4 29435 # Occupied blocks per task id 661system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999268 # Percentage of cache occupancy per task id 662system.cpu.l2cache.tags.tag_accesses 7551951 # Number of tag accesses 663system.cpu.l2cache.tags.data_accesses 7551951 # Number of data accesses 664system.cpu.l2cache.ReadReq_hits::cpu.inst 22768 # number of ReadReq hits 665system.cpu.l2cache.ReadReq_hits::cpu.data 491036 # number of ReadReq hits 666system.cpu.l2cache.ReadReq_hits::total 513804 # number of ReadReq hits 667system.cpu.l2cache.Writeback_hits::writebacks 91420 # number of Writeback hits 668system.cpu.l2cache.Writeback_hits::total 91420 # number of Writeback hits 669system.cpu.l2cache.ReadExReq_hits::cpu.data 3231 # number of ReadExReq hits 670system.cpu.l2cache.ReadExReq_hits::total 3231 # number of ReadExReq hits 671system.cpu.l2cache.demand_hits::cpu.inst 22768 # number of demand (read+write) hits 672system.cpu.l2cache.demand_hits::cpu.data 494267 # number of demand (read+write) hits 673system.cpu.l2cache.demand_hits::total 517035 # number of demand (read+write) hits 674system.cpu.l2cache.overall_hits::cpu.inst 22768 # number of overall hits 675system.cpu.l2cache.overall_hits::cpu.data 494267 # number of overall hits 676system.cpu.l2cache.overall_hits::total 517035 # number of overall hits 677system.cpu.l2cache.ReadReq_misses::cpu.inst 2577 # number of ReadReq misses 678system.cpu.l2cache.ReadReq_misses::cpu.data 221894 # number of ReadReq misses 679system.cpu.l2cache.ReadReq_misses::total 224471 # number of ReadReq misses 680system.cpu.l2cache.ReadExReq_misses::cpu.data 66091 # number of ReadExReq misses 681system.cpu.l2cache.ReadExReq_misses::total 66091 # number of ReadExReq misses 682system.cpu.l2cache.demand_misses::cpu.inst 2577 # number of demand (read+write) misses 683system.cpu.l2cache.demand_misses::cpu.data 287985 # number of demand (read+write) misses 684system.cpu.l2cache.demand_misses::total 290562 # number of demand (read+write) misses 685system.cpu.l2cache.overall_misses::cpu.inst 2577 # number of overall misses 686system.cpu.l2cache.overall_misses::cpu.data 287985 # number of overall misses 687system.cpu.l2cache.overall_misses::total 290562 # number of overall misses 688system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 195416750 # number of ReadReq miss cycles 689system.cpu.l2cache.ReadReq_miss_latency::cpu.data 17656346250 # number of ReadReq miss cycles 690system.cpu.l2cache.ReadReq_miss_latency::total 17851763000 # number of ReadReq miss cycles 691system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4948991250 # number of ReadExReq miss cycles 692system.cpu.l2cache.ReadExReq_miss_latency::total 4948991250 # number of ReadExReq miss cycles 693system.cpu.l2cache.demand_miss_latency::cpu.inst 195416750 # number of demand (read+write) miss cycles 694system.cpu.l2cache.demand_miss_latency::cpu.data 22605337500 # number of demand (read+write) miss cycles 695system.cpu.l2cache.demand_miss_latency::total 22800754250 # number of demand (read+write) miss cycles 696system.cpu.l2cache.overall_miss_latency::cpu.inst 195416750 # number of overall miss cycles 697system.cpu.l2cache.overall_miss_latency::cpu.data 22605337500 # number of overall miss cycles 698system.cpu.l2cache.overall_miss_latency::total 22800754250 # number of overall miss cycles 699system.cpu.l2cache.ReadReq_accesses::cpu.inst 25345 # number of ReadReq accesses(hits+misses) 700system.cpu.l2cache.ReadReq_accesses::cpu.data 712930 # number of ReadReq accesses(hits+misses) 701system.cpu.l2cache.ReadReq_accesses::total 738275 # number of ReadReq accesses(hits+misses) 702system.cpu.l2cache.Writeback_accesses::writebacks 91420 # number of Writeback accesses(hits+misses) 703system.cpu.l2cache.Writeback_accesses::total 91420 # number of Writeback accesses(hits+misses) 704system.cpu.l2cache.ReadExReq_accesses::cpu.data 69322 # number of ReadExReq accesses(hits+misses) 705system.cpu.l2cache.ReadExReq_accesses::total 69322 # number of ReadExReq accesses(hits+misses) 706system.cpu.l2cache.demand_accesses::cpu.inst 25345 # number of demand (read+write) accesses 707system.cpu.l2cache.demand_accesses::cpu.data 782252 # number of demand (read+write) accesses 708system.cpu.l2cache.demand_accesses::total 807597 # number of demand (read+write) accesses 709system.cpu.l2cache.overall_accesses::cpu.inst 25345 # number of overall (read+write) accesses 710system.cpu.l2cache.overall_accesses::cpu.data 782252 # number of overall (read+write) accesses 711system.cpu.l2cache.overall_accesses::total 807597 # number of overall (read+write) accesses 712system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.101677 # miss rate for ReadReq accesses 713system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.311242 # miss rate for ReadReq accesses 714system.cpu.l2cache.ReadReq_miss_rate::total 0.304048 # miss rate for ReadReq accesses 715system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.953391 # miss rate for ReadExReq accesses 716system.cpu.l2cache.ReadExReq_miss_rate::total 0.953391 # miss rate for ReadExReq accesses 717system.cpu.l2cache.demand_miss_rate::cpu.inst 0.101677 # miss rate for demand accesses 718system.cpu.l2cache.demand_miss_rate::cpu.data 0.368149 # miss rate for demand accesses 719system.cpu.l2cache.demand_miss_rate::total 0.359786 # miss rate for demand accesses 720system.cpu.l2cache.overall_miss_rate::cpu.inst 0.101677 # miss rate for overall accesses 721system.cpu.l2cache.overall_miss_rate::cpu.data 0.368149 # miss rate for overall accesses 722system.cpu.l2cache.overall_miss_rate::total 0.359786 # miss rate for overall accesses 723system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 75831.102057 # average ReadReq miss latency 724system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 79571.084617 # average ReadReq miss latency 725system.cpu.l2cache.ReadReq_avg_miss_latency::total 79528.148402 # average ReadReq miss latency 726system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74881.470246 # average ReadExReq miss latency 727system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74881.470246 # average ReadExReq miss latency 728system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75831.102057 # average overall miss latency 729system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78494.843481 # average overall miss latency 730system.cpu.l2cache.demand_avg_miss_latency::total 78471.218707 # average overall miss latency 731system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75831.102057 # average overall miss latency 732system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78494.843481 # average overall miss latency 733system.cpu.l2cache.overall_avg_miss_latency::total 78471.218707 # average overall miss latency 734system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 735system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 736system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 737system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 738system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 739system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 740system.cpu.l2cache.fast_writes 0 # number of fast writes performed 741system.cpu.l2cache.cache_copies 0 # number of cache copies performed 742system.cpu.l2cache.writebacks::writebacks 66098 # number of writebacks 743system.cpu.l2cache.writebacks::total 66098 # number of writebacks 744system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 5 # number of ReadReq MSHR hits 745system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 27 # number of ReadReq MSHR hits 746system.cpu.l2cache.ReadReq_mshr_hits::total 32 # number of ReadReq MSHR hits 747system.cpu.l2cache.demand_mshr_hits::cpu.inst 5 # number of demand (read+write) MSHR hits 748system.cpu.l2cache.demand_mshr_hits::cpu.data 27 # number of demand (read+write) MSHR hits 749system.cpu.l2cache.demand_mshr_hits::total 32 # number of demand (read+write) MSHR hits 750system.cpu.l2cache.overall_mshr_hits::cpu.inst 5 # number of overall MSHR hits 751system.cpu.l2cache.overall_mshr_hits::cpu.data 27 # number of overall MSHR hits 752system.cpu.l2cache.overall_mshr_hits::total 32 # number of overall MSHR hits 753system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2572 # number of ReadReq MSHR misses 754system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 221867 # number of ReadReq MSHR misses 755system.cpu.l2cache.ReadReq_mshr_misses::total 224439 # number of ReadReq MSHR misses 756system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66091 # number of ReadExReq MSHR misses 757system.cpu.l2cache.ReadExReq_mshr_misses::total 66091 # number of ReadExReq MSHR misses 758system.cpu.l2cache.demand_mshr_misses::cpu.inst 2572 # number of demand (read+write) MSHR misses 759system.cpu.l2cache.demand_mshr_misses::cpu.data 287958 # number of demand (read+write) MSHR misses 760system.cpu.l2cache.demand_mshr_misses::total 290530 # number of demand (read+write) MSHR misses 761system.cpu.l2cache.overall_mshr_misses::cpu.inst 2572 # number of overall MSHR misses 762system.cpu.l2cache.overall_mshr_misses::cpu.data 287958 # number of overall MSHR misses 763system.cpu.l2cache.overall_mshr_misses::total 290530 # number of overall MSHR misses 764system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 162876000 # number of ReadReq MSHR miss cycles 765system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 14878894250 # number of ReadReq MSHR miss cycles 766system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15041770250 # number of ReadReq MSHR miss cycles 767system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4120650250 # number of ReadExReq MSHR miss cycles 768system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4120650250 # number of ReadExReq MSHR miss cycles 769system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 162876000 # number of demand (read+write) MSHR miss cycles 770system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 18999544500 # number of demand (read+write) MSHR miss cycles 771system.cpu.l2cache.demand_mshr_miss_latency::total 19162420500 # number of demand (read+write) MSHR miss cycles 772system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 162876000 # number of overall MSHR miss cycles 773system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 18999544500 # number of overall MSHR miss cycles 774system.cpu.l2cache.overall_mshr_miss_latency::total 19162420500 # number of overall MSHR miss cycles 775system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.101480 # mshr miss rate for ReadReq accesses 776system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.311204 # mshr miss rate for ReadReq accesses 777system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.304005 # mshr miss rate for ReadReq accesses 778system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.953391 # mshr miss rate for ReadExReq accesses 779system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.953391 # mshr miss rate for ReadExReq accesses 780system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.101480 # mshr miss rate for demand accesses 781system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.368114 # mshr miss rate for demand accesses 782system.cpu.l2cache.demand_mshr_miss_rate::total 0.359746 # mshr miss rate for demand accesses 783system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.101480 # mshr miss rate for overall accesses 784system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.368114 # mshr miss rate for overall accesses 785system.cpu.l2cache.overall_mshr_miss_rate::total 0.359746 # mshr miss rate for overall accesses 786system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63326.594090 # average ReadReq mshr miss latency 787system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67062.223089 # average ReadReq mshr miss latency 788system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67019.413961 # average ReadReq mshr miss latency 789system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62348.129851 # average ReadExReq mshr miss latency 790system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62348.129851 # average ReadExReq mshr miss latency 791system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63326.594090 # average overall mshr miss latency 792system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65980.262747 # average overall mshr miss latency 793system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65956.770385 # average overall mshr miss latency 794system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63326.594090 # average overall mshr miss latency 795system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65980.262747 # average overall mshr miss latency 796system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65956.770385 # average overall mshr miss latency 797system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 798system.cpu.toL2Bus.trans_dist::ReadReq 738275 # Transaction distribution 799system.cpu.toL2Bus.trans_dist::ReadResp 738274 # Transaction distribution 800system.cpu.toL2Bus.trans_dist::Writeback 91420 # Transaction distribution 801system.cpu.toL2Bus.trans_dist::ReadExReq 69322 # Transaction distribution 802system.cpu.toL2Bus.trans_dist::ReadExResp 69322 # Transaction distribution 803system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50689 # Packet count per connected master and slave (bytes) 804system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1655924 # Packet count per connected master and slave (bytes) 805system.cpu.toL2Bus.pkt_count::total 1706613 # Packet count per connected master and slave (bytes) 806system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1622016 # Cumulative packet size per connected master and slave (bytes) 807system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55915008 # Cumulative packet size per connected master and slave (bytes) 808system.cpu.toL2Bus.pkt_size::total 57537024 # Cumulative packet size per connected master and slave (bytes) 809system.cpu.toL2Bus.snoops 0 # Total snoops (count) 810system.cpu.toL2Bus.snoop_fanout::samples 899017 # Request fanout histogram 811system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram 812system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram 813system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 814system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 815system.cpu.toL2Bus.snoop_fanout::1 899017 100.00% 100.00% # Request fanout histogram 816system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 817system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 818system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 819system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 820system.cpu.toL2Bus.snoop_fanout::total 899017 # Request fanout histogram 821system.cpu.toL2Bus.reqLayer0.occupancy 540928500 # Layer occupancy (ticks) 822system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 823system.cpu.toL2Bus.respLayer0.occupancy 38568245 # Layer occupancy (ticks) 824system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 825system.cpu.toL2Bus.respLayer1.occupancy 1224009973 # Layer occupancy (ticks) 826system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) 827system.membus.trans_dist::ReadReq 224438 # Transaction distribution 828system.membus.trans_dist::ReadResp 224438 # Transaction distribution 829system.membus.trans_dist::Writeback 66098 # Transaction distribution 830system.membus.trans_dist::ReadExReq 66091 # Transaction distribution 831system.membus.trans_dist::ReadExResp 66091 # Transaction distribution 832system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 647156 # Packet count per connected master and slave (bytes) 833system.membus.pkt_count::total 647156 # Packet count per connected master and slave (bytes) 834system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22824128 # Cumulative packet size per connected master and slave (bytes) 835system.membus.pkt_size::total 22824128 # Cumulative packet size per connected master and slave (bytes) 836system.membus.snoops 0 # Total snoops (count) 837system.membus.snoop_fanout::samples 356627 # Request fanout histogram 838system.membus.snoop_fanout::mean 0 # Request fanout histogram 839system.membus.snoop_fanout::stdev 0 # Request fanout histogram 840system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 841system.membus.snoop_fanout::0 356627 100.00% 100.00% # Request fanout histogram 842system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 843system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 844system.membus.snoop_fanout::min_value 0 # Request fanout histogram 845system.membus.snoop_fanout::max_value 0 # Request fanout histogram 846system.membus.snoop_fanout::total 356627 # Request fanout histogram 847system.membus.reqLayer0.occupancy 732101500 # Layer occupancy (ticks) 848system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) 849system.membus.respLayer1.occupancy 1551130500 # Layer occupancy (ticks) 850system.membus.respLayer1.utilization 0.3 # Layer utilization (%) 851 852---------- End Simulation Statistics ---------- 853