config.ini revision 10260
1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=System 13children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain 17eventq_index=0 18init_param=0 19kernel= 20load_addr_mask=1099511627775 21load_offset=0 22mem_mode=timing 23mem_ranges= 24memories=system.physmem 25num_work_ids=16 26readfile= 27symbolfile= 28work_begin_ckpt_count=0 29work_begin_cpu_id_exit=-1 30work_begin_exit_count=0 31work_cpus_ckpt_count=0 32work_end_ckpt_count=0 33work_end_exit_count=0 34work_item_id=-1 35system_port=system.membus.slave[0] 36 37[system.clk_domain] 38type=SrcClockDomain 39clock=1000 40eventq_index=0 41voltage_domain=system.voltage_domain 42 43[system.cpu] 44type=MinorCPU 45children=branchPred dcache dstage2_mmu dtb executeFuncUnits icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload 46branchPred=system.cpu.branchPred 47checker=Null 48clk_domain=system.cpu_clk_domain 49cpu_id=0 50decodeCycleInput=true 51decodeInputBufferSize=3 52decodeInputWidth=2 53decodeToExecuteForwardDelay=1 54do_checkpoint_insts=true 55do_quiesce=true 56do_statistics_insts=true 57dstage2_mmu=system.cpu.dstage2_mmu 58dtb=system.cpu.dtb 59enableIdling=true 60eventq_index=0 61executeAllowEarlyMemoryIssue=true 62executeBranchDelay=1 63executeCommitLimit=2 64executeCycleInput=true 65executeFuncUnits=system.cpu.executeFuncUnits 66executeInputBufferSize=7 67executeInputWidth=2 68executeIssueLimit=2 69executeLSQMaxStoreBufferStoresPerCycle=2 70executeLSQRequestsQueueSize=1 71executeLSQStoreBufferSize=5 72executeLSQTransfersQueueSize=2 73executeMaxAccessesInMemory=2 74executeMemoryCommitLimit=1 75executeMemoryIssueLimit=1 76executeMemoryWidth=0 77executeSetTraceTimeOnCommit=true 78executeSetTraceTimeOnIssue=false 79fetch1FetchLimit=1 80fetch1LineSnapWidth=0 81fetch1LineWidth=0 82fetch1ToFetch2BackwardDelay=1 83fetch1ToFetch2ForwardDelay=1 84fetch2CycleInput=true 85fetch2InputBufferSize=2 86fetch2ToDecodeForwardDelay=1 87function_trace=false 88function_trace_start=0 89interrupts=system.cpu.interrupts 90isa=system.cpu.isa 91istage2_mmu=system.cpu.istage2_mmu 92itb=system.cpu.itb 93max_insts_all_threads=0 94max_insts_any_thread=0 95max_loads_all_threads=0 96max_loads_any_thread=0 97numThreads=1 98profile=0 99progress_interval=0 100simpoint_start_insts= 101switched_out=false 102system=system 103tracer=system.cpu.tracer 104workload=system.cpu.workload 105dcache_port=system.cpu.dcache.cpu_side 106icache_port=system.cpu.icache.cpu_side 107 108[system.cpu.branchPred] 109type=BranchPredictor 110BTBEntries=4096 111BTBTagSize=16 112RASSize=16 113choiceCtrBits=2 114choicePredictorSize=8192 115eventq_index=0 116globalCtrBits=2 117globalPredictorSize=8192 118instShiftAmt=2 119localCtrBits=2 120localHistoryTableSize=2048 121localPredictorSize=2048 122numThreads=1 123predType=tournament 124 125[system.cpu.dcache] 126type=BaseCache 127children=tags 128addr_ranges=0:18446744073709551615 129assoc=2 130clk_domain=system.cpu_clk_domain 131eventq_index=0 132forward_snoops=true 133hit_latency=2 134is_top_level=true 135max_miss_count=0 136mshrs=4 137prefetch_on_access=false 138prefetcher=Null 139response_latency=2 140sequential_access=false 141size=262144 142system=system 143tags=system.cpu.dcache.tags 144tgts_per_mshr=20 145two_queue=false 146write_buffers=8 147cpu_side=system.cpu.dcache_port 148mem_side=system.cpu.toL2Bus.slave[1] 149 150[system.cpu.dcache.tags] 151type=LRU 152assoc=2 153block_size=64 154clk_domain=system.cpu_clk_domain 155eventq_index=0 156hit_latency=2 157sequential_access=false 158size=262144 159 160[system.cpu.dstage2_mmu] 161type=ArmStage2MMU 162children=stage2_tlb 163eventq_index=0 164stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb 165tlb=system.cpu.dtb 166 167[system.cpu.dstage2_mmu.stage2_tlb] 168type=ArmTLB 169children=walker 170eventq_index=0 171is_stage2=true 172size=32 173walker=system.cpu.dstage2_mmu.stage2_tlb.walker 174 175[system.cpu.dstage2_mmu.stage2_tlb.walker] 176type=ArmTableWalker 177clk_domain=system.cpu_clk_domain 178eventq_index=0 179is_stage2=true 180num_squash_per_cycle=2 181sys=system 182port=system.cpu.toL2Bus.slave[5] 183 184[system.cpu.dtb] 185type=ArmTLB 186children=walker 187eventq_index=0 188is_stage2=false 189size=64 190walker=system.cpu.dtb.walker 191 192[system.cpu.dtb.walker] 193type=ArmTableWalker 194clk_domain=system.cpu_clk_domain 195eventq_index=0 196is_stage2=false 197num_squash_per_cycle=2 198sys=system 199port=system.cpu.toL2Bus.slave[3] 200 201[system.cpu.executeFuncUnits] 202type=MinorFUPool 203children=funcUnits0 funcUnits1 funcUnits2 funcUnits3 funcUnits4 funcUnits5 funcUnits6 204eventq_index=0 205funcUnits=system.cpu.executeFuncUnits.funcUnits0 system.cpu.executeFuncUnits.funcUnits1 system.cpu.executeFuncUnits.funcUnits2 system.cpu.executeFuncUnits.funcUnits3 system.cpu.executeFuncUnits.funcUnits4 system.cpu.executeFuncUnits.funcUnits5 system.cpu.executeFuncUnits.funcUnits6 206 207[system.cpu.executeFuncUnits.funcUnits0] 208type=MinorFU 209children=opClasses timings 210eventq_index=0 211issueLat=1 212opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses 213opLat=3 214timings=system.cpu.executeFuncUnits.funcUnits0.timings 215 216[system.cpu.executeFuncUnits.funcUnits0.opClasses] 217type=MinorOpClassSet 218children=opClasses 219eventq_index=0 220opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses 221 222[system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses] 223type=MinorOpClass 224eventq_index=0 225opClass=IntAlu 226 227[system.cpu.executeFuncUnits.funcUnits0.timings] 228type=MinorFUTiming 229children=opClasses 230description=Int 231eventq_index=0 232extraAssumedLat=0 233extraCommitLat=0 234extraCommitLatExpr=Null 235mask=0 236match=0 237opClasses=system.cpu.executeFuncUnits.funcUnits0.timings.opClasses 238srcRegsRelativeLats=2 239suppress=false 240 241[system.cpu.executeFuncUnits.funcUnits0.timings.opClasses] 242type=MinorOpClassSet 243eventq_index=0 244opClasses= 245 246[system.cpu.executeFuncUnits.funcUnits1] 247type=MinorFU 248children=opClasses timings 249eventq_index=0 250issueLat=1 251opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses 252opLat=3 253timings=system.cpu.executeFuncUnits.funcUnits1.timings 254 255[system.cpu.executeFuncUnits.funcUnits1.opClasses] 256type=MinorOpClassSet 257children=opClasses 258eventq_index=0 259opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses 260 261[system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses] 262type=MinorOpClass 263eventq_index=0 264opClass=IntAlu 265 266[system.cpu.executeFuncUnits.funcUnits1.timings] 267type=MinorFUTiming 268children=opClasses 269description=Int 270eventq_index=0 271extraAssumedLat=0 272extraCommitLat=0 273extraCommitLatExpr=Null 274mask=0 275match=0 276opClasses=system.cpu.executeFuncUnits.funcUnits1.timings.opClasses 277srcRegsRelativeLats=2 278suppress=false 279 280[system.cpu.executeFuncUnits.funcUnits1.timings.opClasses] 281type=MinorOpClassSet 282eventq_index=0 283opClasses= 284 285[system.cpu.executeFuncUnits.funcUnits2] 286type=MinorFU 287children=opClasses timings 288eventq_index=0 289issueLat=1 290opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses 291opLat=3 292timings=system.cpu.executeFuncUnits.funcUnits2.timings 293 294[system.cpu.executeFuncUnits.funcUnits2.opClasses] 295type=MinorOpClassSet 296children=opClasses 297eventq_index=0 298opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses 299 300[system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses] 301type=MinorOpClass 302eventq_index=0 303opClass=IntMult 304 305[system.cpu.executeFuncUnits.funcUnits2.timings] 306type=MinorFUTiming 307children=opClasses 308description=Mul 309eventq_index=0 310extraAssumedLat=0 311extraCommitLat=0 312extraCommitLatExpr=Null 313mask=0 314match=0 315opClasses=system.cpu.executeFuncUnits.funcUnits2.timings.opClasses 316srcRegsRelativeLats=0 317suppress=false 318 319[system.cpu.executeFuncUnits.funcUnits2.timings.opClasses] 320type=MinorOpClassSet 321eventq_index=0 322opClasses= 323 324[system.cpu.executeFuncUnits.funcUnits3] 325type=MinorFU 326children=opClasses 327eventq_index=0 328issueLat=9 329opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses 330opLat=9 331timings= 332 333[system.cpu.executeFuncUnits.funcUnits3.opClasses] 334type=MinorOpClassSet 335children=opClasses 336eventq_index=0 337opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses 338 339[system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses] 340type=MinorOpClass 341eventq_index=0 342opClass=IntDiv 343 344[system.cpu.executeFuncUnits.funcUnits4] 345type=MinorFU 346children=opClasses timings 347eventq_index=0 348issueLat=1 349opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses 350opLat=6 351timings=system.cpu.executeFuncUnits.funcUnits4.timings 352 353[system.cpu.executeFuncUnits.funcUnits4.opClasses] 354type=MinorOpClassSet 355children=opClasses00 opClasses01 opClasses02 opClasses03 opClasses04 opClasses05 opClasses06 opClasses07 opClasses08 opClasses09 opClasses10 opClasses11 opClasses12 opClasses13 opClasses14 opClasses15 opClasses16 opClasses17 opClasses18 opClasses19 opClasses20 opClasses21 opClasses22 opClasses23 opClasses24 opClasses25 356eventq_index=0 357opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25 358 359[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00] 360type=MinorOpClass 361eventq_index=0 362opClass=FloatAdd 363 364[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01] 365type=MinorOpClass 366eventq_index=0 367opClass=FloatCmp 368 369[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02] 370type=MinorOpClass 371eventq_index=0 372opClass=FloatCvt 373 374[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03] 375type=MinorOpClass 376eventq_index=0 377opClass=FloatMult 378 379[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04] 380type=MinorOpClass 381eventq_index=0 382opClass=FloatDiv 383 384[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05] 385type=MinorOpClass 386eventq_index=0 387opClass=FloatSqrt 388 389[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06] 390type=MinorOpClass 391eventq_index=0 392opClass=SimdAdd 393 394[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07] 395type=MinorOpClass 396eventq_index=0 397opClass=SimdAddAcc 398 399[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08] 400type=MinorOpClass 401eventq_index=0 402opClass=SimdAlu 403 404[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09] 405type=MinorOpClass 406eventq_index=0 407opClass=SimdCmp 408 409[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10] 410type=MinorOpClass 411eventq_index=0 412opClass=SimdCvt 413 414[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11] 415type=MinorOpClass 416eventq_index=0 417opClass=SimdMisc 418 419[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12] 420type=MinorOpClass 421eventq_index=0 422opClass=SimdMult 423 424[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13] 425type=MinorOpClass 426eventq_index=0 427opClass=SimdMultAcc 428 429[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14] 430type=MinorOpClass 431eventq_index=0 432opClass=SimdShift 433 434[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15] 435type=MinorOpClass 436eventq_index=0 437opClass=SimdShiftAcc 438 439[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16] 440type=MinorOpClass 441eventq_index=0 442opClass=SimdSqrt 443 444[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17] 445type=MinorOpClass 446eventq_index=0 447opClass=SimdFloatAdd 448 449[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18] 450type=MinorOpClass 451eventq_index=0 452opClass=SimdFloatAlu 453 454[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19] 455type=MinorOpClass 456eventq_index=0 457opClass=SimdFloatCmp 458 459[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20] 460type=MinorOpClass 461eventq_index=0 462opClass=SimdFloatCvt 463 464[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21] 465type=MinorOpClass 466eventq_index=0 467opClass=SimdFloatDiv 468 469[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22] 470type=MinorOpClass 471eventq_index=0 472opClass=SimdFloatMisc 473 474[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23] 475type=MinorOpClass 476eventq_index=0 477opClass=SimdFloatMult 478 479[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24] 480type=MinorOpClass 481eventq_index=0 482opClass=SimdFloatMultAcc 483 484[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25] 485type=MinorOpClass 486eventq_index=0 487opClass=SimdFloatSqrt 488 489[system.cpu.executeFuncUnits.funcUnits4.timings] 490type=MinorFUTiming 491children=opClasses 492description=FloatSimd 493eventq_index=0 494extraAssumedLat=0 495extraCommitLat=0 496extraCommitLatExpr=Null 497mask=0 498match=0 499opClasses=system.cpu.executeFuncUnits.funcUnits4.timings.opClasses 500srcRegsRelativeLats=2 501suppress=false 502 503[system.cpu.executeFuncUnits.funcUnits4.timings.opClasses] 504type=MinorOpClassSet 505eventq_index=0 506opClasses= 507 508[system.cpu.executeFuncUnits.funcUnits5] 509type=MinorFU 510children=opClasses timings 511eventq_index=0 512issueLat=1 513opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses 514opLat=1 515timings=system.cpu.executeFuncUnits.funcUnits5.timings 516 517[system.cpu.executeFuncUnits.funcUnits5.opClasses] 518type=MinorOpClassSet 519children=opClasses0 opClasses1 520eventq_index=0 521opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1 522 523[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0] 524type=MinorOpClass 525eventq_index=0 526opClass=MemRead 527 528[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1] 529type=MinorOpClass 530eventq_index=0 531opClass=MemWrite 532 533[system.cpu.executeFuncUnits.funcUnits5.timings] 534type=MinorFUTiming 535children=opClasses 536description=Mem 537eventq_index=0 538extraAssumedLat=2 539extraCommitLat=0 540extraCommitLatExpr=Null 541mask=0 542match=0 543opClasses=system.cpu.executeFuncUnits.funcUnits5.timings.opClasses 544srcRegsRelativeLats=1 545suppress=false 546 547[system.cpu.executeFuncUnits.funcUnits5.timings.opClasses] 548type=MinorOpClassSet 549eventq_index=0 550opClasses= 551 552[system.cpu.executeFuncUnits.funcUnits6] 553type=MinorFU 554children=opClasses 555eventq_index=0 556issueLat=1 557opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses 558opLat=1 559timings= 560 561[system.cpu.executeFuncUnits.funcUnits6.opClasses] 562type=MinorOpClassSet 563children=opClasses0 opClasses1 564eventq_index=0 565opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1 566 567[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0] 568type=MinorOpClass 569eventq_index=0 570opClass=IprAccess 571 572[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1] 573type=MinorOpClass 574eventq_index=0 575opClass=InstPrefetch 576 577[system.cpu.icache] 578type=BaseCache 579children=tags 580addr_ranges=0:18446744073709551615 581assoc=2 582clk_domain=system.cpu_clk_domain 583eventq_index=0 584forward_snoops=true 585hit_latency=2 586is_top_level=true 587max_miss_count=0 588mshrs=4 589prefetch_on_access=false 590prefetcher=Null 591response_latency=2 592sequential_access=false 593size=131072 594system=system 595tags=system.cpu.icache.tags 596tgts_per_mshr=20 597two_queue=false 598write_buffers=8 599cpu_side=system.cpu.icache_port 600mem_side=system.cpu.toL2Bus.slave[0] 601 602[system.cpu.icache.tags] 603type=LRU 604assoc=2 605block_size=64 606clk_domain=system.cpu_clk_domain 607eventq_index=0 608hit_latency=2 609sequential_access=false 610size=131072 611 612[system.cpu.interrupts] 613type=ArmInterrupts 614eventq_index=0 615 616[system.cpu.isa] 617type=ArmISA 618eventq_index=0 619fpsid=1090793632 620id_aa64afr0_el1=0 621id_aa64afr1_el1=0 622id_aa64dfr0_el1=1052678 623id_aa64dfr1_el1=0 624id_aa64isar0_el1=0 625id_aa64isar1_el1=0 626id_aa64mmfr0_el1=15728642 627id_aa64mmfr1_el1=0 628id_aa64pfr0_el1=17 629id_aa64pfr1_el1=0 630id_isar0=34607377 631id_isar1=34677009 632id_isar2=555950401 633id_isar3=17899825 634id_isar4=268501314 635id_isar5=0 636id_mmfr0=270536963 637id_mmfr1=0 638id_mmfr2=19070976 639id_mmfr3=34611729 640id_pfr0=49 641id_pfr1=4113 642midr=1091551472 643system=system 644 645[system.cpu.istage2_mmu] 646type=ArmStage2MMU 647children=stage2_tlb 648eventq_index=0 649stage2_tlb=system.cpu.istage2_mmu.stage2_tlb 650tlb=system.cpu.itb 651 652[system.cpu.istage2_mmu.stage2_tlb] 653type=ArmTLB 654children=walker 655eventq_index=0 656is_stage2=true 657size=32 658walker=system.cpu.istage2_mmu.stage2_tlb.walker 659 660[system.cpu.istage2_mmu.stage2_tlb.walker] 661type=ArmTableWalker 662clk_domain=system.cpu_clk_domain 663eventq_index=0 664is_stage2=true 665num_squash_per_cycle=2 666sys=system 667port=system.cpu.toL2Bus.slave[4] 668 669[system.cpu.itb] 670type=ArmTLB 671children=walker 672eventq_index=0 673is_stage2=false 674size=64 675walker=system.cpu.itb.walker 676 677[system.cpu.itb.walker] 678type=ArmTableWalker 679clk_domain=system.cpu_clk_domain 680eventq_index=0 681is_stage2=false 682num_squash_per_cycle=2 683sys=system 684port=system.cpu.toL2Bus.slave[2] 685 686[system.cpu.l2cache] 687type=BaseCache 688children=tags 689addr_ranges=0:18446744073709551615 690assoc=8 691clk_domain=system.cpu_clk_domain 692eventq_index=0 693forward_snoops=true 694hit_latency=20 695is_top_level=false 696max_miss_count=0 697mshrs=20 698prefetch_on_access=false 699prefetcher=Null 700response_latency=20 701sequential_access=false 702size=2097152 703system=system 704tags=system.cpu.l2cache.tags 705tgts_per_mshr=12 706two_queue=false 707write_buffers=8 708cpu_side=system.cpu.toL2Bus.master[0] 709mem_side=system.membus.slave[1] 710 711[system.cpu.l2cache.tags] 712type=LRU 713assoc=8 714block_size=64 715clk_domain=system.cpu_clk_domain 716eventq_index=0 717hit_latency=20 718sequential_access=false 719size=2097152 720 721[system.cpu.toL2Bus] 722type=CoherentBus 723clk_domain=system.cpu_clk_domain 724eventq_index=0 725header_cycles=1 726system=system 727use_default_range=false 728width=32 729master=system.cpu.l2cache.cpu_side 730slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port 731 732[system.cpu.tracer] 733type=ExeTracer 734eventq_index=0 735 736[system.cpu.workload] 737type=LiveProcess 738cmd=perlbmk -I. -I lib lgred.makerand.pl 739cwd=build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/minor-timing 740egid=100 741env= 742errout=cerr 743euid=100 744eventq_index=0 745executable=/arm/projectscratch/pd/sysrandd/dist/cpu2000/binaries/arm/linux/perlbmk 746gid=100 747input=cin 748max_stack_size=67108864 749output=cout 750pid=100 751ppid=99 752simpoint=0 753system=system 754uid=100 755 756[system.cpu_clk_domain] 757type=SrcClockDomain 758clock=500 759eventq_index=0 760voltage_domain=system.voltage_domain 761 762[system.membus] 763type=CoherentBus 764clk_domain=system.clk_domain 765eventq_index=0 766header_cycles=1 767system=system 768use_default_range=false 769width=8 770master=system.physmem.port 771slave=system.system_port system.cpu.l2cache.mem_side 772 773[system.physmem] 774type=DRAMCtrl 775activation_limit=4 776addr_mapping=RoRaBaChCo 777banks_per_rank=8 778burst_length=8 779channels=1 780clk_domain=system.clk_domain 781conf_table_reported=true 782device_bus_width=8 783device_rowbuffer_size=1024 784devices_per_rank=8 785eventq_index=0 786in_addr_map=true 787max_accesses_per_row=16 788mem_sched_policy=frfcfs 789min_writes_per_switch=16 790null=false 791page_policy=open_adaptive 792range=0:134217727 793ranks_per_channel=2 794read_buffer_size=32 795static_backend_latency=10000 796static_frontend_latency=10000 797tBURST=5000 798tCL=13750 799tRAS=35000 800tRCD=13750 801tREFI=7800000 802tRFC=300000 803tRP=13750 804tRRD=6250 805tWTR=7500 806tXAW=40000 807write_buffer_size=64 808write_high_thresh_perc=85 809write_low_thresh_perc=50 810port=system.membus.master[0] 811 812[system.voltage_domain] 813type=VoltageDomain 814eventq_index=0 815voltage=1.000000 816 817