stats.txt revision 9988:0b2e590c85be
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.068510 # Number of seconds simulated 4sim_ticks 68509635500 # Number of ticks simulated 5final_tick 68509635500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 105106 # Simulator instruction rate (inst/s) 8host_op_rate 134373 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 26372946 # Simulator tick rate (ticks/s) 10host_mem_usage 303620 # Number of bytes of host memory used 11host_seconds 2597.72 # Real time elapsed on the host 12sim_insts 273036725 # Number of instructions simulated 13sim_ops 349064449 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 194560 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 272384 # Number of bytes read from this memory 16system.physmem.bytes_read::total 466944 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 194560 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 194560 # Number of instructions bytes read from this memory 19system.physmem.num_reads::cpu.inst 3040 # Number of read requests responded to by this memory 20system.physmem.num_reads::cpu.data 4256 # Number of read requests responded to by this memory 21system.physmem.num_reads::total 7296 # Number of read requests responded to by this memory 22system.physmem.bw_read::cpu.inst 2839892 # Total read bandwidth from this memory (bytes/s) 23system.physmem.bw_read::cpu.data 3975849 # Total read bandwidth from this memory (bytes/s) 24system.physmem.bw_read::total 6815742 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_inst_read::cpu.inst 2839892 # Instruction read bandwidth from this memory (bytes/s) 26system.physmem.bw_inst_read::total 2839892 # Instruction read bandwidth from this memory (bytes/s) 27system.physmem.bw_total::cpu.inst 2839892 # Total bandwidth to/from this memory (bytes/s) 28system.physmem.bw_total::cpu.data 3975849 # Total bandwidth to/from this memory (bytes/s) 29system.physmem.bw_total::total 6815742 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.readReqs 7296 # Number of read requests accepted 31system.physmem.writeReqs 0 # Number of write requests accepted 32system.physmem.readBursts 7296 # Number of DRAM read bursts, including those serviced by the write queue 33system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 34system.physmem.bytesReadDRAM 466944 # Total number of bytes read from DRAM 35system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 36system.physmem.bytesWritten 0 # Total number of bytes written to DRAM 37system.physmem.bytesReadSys 466944 # Total read bytes from the system interface side 38system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 39system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 40system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 41system.physmem.neitherReadNorWriteReqs 2 # Number of requests that are neither read nor write 42system.physmem.perBankRdBursts::0 607 # Per bank write bursts 43system.physmem.perBankRdBursts::1 801 # Per bank write bursts 44system.physmem.perBankRdBursts::2 608 # Per bank write bursts 45system.physmem.perBankRdBursts::3 526 # Per bank write bursts 46system.physmem.perBankRdBursts::4 444 # Per bank write bursts 47system.physmem.perBankRdBursts::5 356 # Per bank write bursts 48system.physmem.perBankRdBursts::6 162 # Per bank write bursts 49system.physmem.perBankRdBursts::7 220 # Per bank write bursts 50system.physmem.perBankRdBursts::8 207 # Per bank write bursts 51system.physmem.perBankRdBursts::9 294 # Per bank write bursts 52system.physmem.perBankRdBursts::10 324 # Per bank write bursts 53system.physmem.perBankRdBursts::11 416 # Per bank write bursts 54system.physmem.perBankRdBursts::12 529 # Per bank write bursts 55system.physmem.perBankRdBursts::13 687 # Per bank write bursts 56system.physmem.perBankRdBursts::14 611 # Per bank write bursts 57system.physmem.perBankRdBursts::15 504 # Per bank write bursts 58system.physmem.perBankWrBursts::0 0 # Per bank write bursts 59system.physmem.perBankWrBursts::1 0 # Per bank write bursts 60system.physmem.perBankWrBursts::2 0 # Per bank write bursts 61system.physmem.perBankWrBursts::3 0 # Per bank write bursts 62system.physmem.perBankWrBursts::4 0 # Per bank write bursts 63system.physmem.perBankWrBursts::5 0 # Per bank write bursts 64system.physmem.perBankWrBursts::6 0 # Per bank write bursts 65system.physmem.perBankWrBursts::7 0 # Per bank write bursts 66system.physmem.perBankWrBursts::8 0 # Per bank write bursts 67system.physmem.perBankWrBursts::9 0 # Per bank write bursts 68system.physmem.perBankWrBursts::10 0 # Per bank write bursts 69system.physmem.perBankWrBursts::11 0 # Per bank write bursts 70system.physmem.perBankWrBursts::12 0 # Per bank write bursts 71system.physmem.perBankWrBursts::13 0 # Per bank write bursts 72system.physmem.perBankWrBursts::14 0 # Per bank write bursts 73system.physmem.perBankWrBursts::15 0 # Per bank write bursts 74system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 75system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 76system.physmem.totGap 68509447000 # Total gap between requests 77system.physmem.readPktSize::0 0 # Read request sizes (log2) 78system.physmem.readPktSize::1 0 # Read request sizes (log2) 79system.physmem.readPktSize::2 0 # Read request sizes (log2) 80system.physmem.readPktSize::3 0 # Read request sizes (log2) 81system.physmem.readPktSize::4 0 # Read request sizes (log2) 82system.physmem.readPktSize::5 0 # Read request sizes (log2) 83system.physmem.readPktSize::6 7296 # Read request sizes (log2) 84system.physmem.writePktSize::0 0 # Write request sizes (log2) 85system.physmem.writePktSize::1 0 # Write request sizes (log2) 86system.physmem.writePktSize::2 0 # Write request sizes (log2) 87system.physmem.writePktSize::3 0 # Write request sizes (log2) 88system.physmem.writePktSize::4 0 # Write request sizes (log2) 89system.physmem.writePktSize::5 0 # Write request sizes (log2) 90system.physmem.writePktSize::6 0 # Write request sizes (log2) 91system.physmem.rdQLenPdf::0 4378 # What read queue length does an incoming req see 92system.physmem.rdQLenPdf::1 2103 # What read queue length does an incoming req see 93system.physmem.rdQLenPdf::2 570 # What read queue length does an incoming req see 94system.physmem.rdQLenPdf::3 177 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::4 67 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 123system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 124system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 125system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 126system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 127system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 128system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 129system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 130system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 131system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 132system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 133system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 134system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 155system.physmem.bytesPerActivate::samples 1278 # Bytes accessed per row activation 156system.physmem.bytesPerActivate::mean 364.419405 # Bytes accessed per row activation 157system.physmem.bytesPerActivate::gmean 165.521659 # Bytes accessed per row activation 158system.physmem.bytesPerActivate::stdev 755.556461 # Bytes accessed per row activation 159system.physmem.bytesPerActivate::64-65 528 41.31% 41.31% # Bytes accessed per row activation 160system.physmem.bytesPerActivate::128-129 217 16.98% 58.29% # Bytes accessed per row activation 161system.physmem.bytesPerActivate::192-193 132 10.33% 68.62% # Bytes accessed per row activation 162system.physmem.bytesPerActivate::256-257 73 5.71% 74.33% # Bytes accessed per row activation 163system.physmem.bytesPerActivate::320-321 38 2.97% 77.31% # Bytes accessed per row activation 164system.physmem.bytesPerActivate::384-385 36 2.82% 80.13% # Bytes accessed per row activation 165system.physmem.bytesPerActivate::448-449 30 2.35% 82.47% # Bytes accessed per row activation 166system.physmem.bytesPerActivate::512-513 40 3.13% 85.60% # Bytes accessed per row activation 167system.physmem.bytesPerActivate::576-577 15 1.17% 86.78% # Bytes accessed per row activation 168system.physmem.bytesPerActivate::640-641 24 1.88% 88.65% # Bytes accessed per row activation 169system.physmem.bytesPerActivate::704-705 7 0.55% 89.20% # Bytes accessed per row activation 170system.physmem.bytesPerActivate::768-769 13 1.02% 90.22% # Bytes accessed per row activation 171system.physmem.bytesPerActivate::832-833 4 0.31% 90.53% # Bytes accessed per row activation 172system.physmem.bytesPerActivate::896-897 10 0.78% 91.31% # Bytes accessed per row activation 173system.physmem.bytesPerActivate::960-961 5 0.39% 91.71% # Bytes accessed per row activation 174system.physmem.bytesPerActivate::1024-1025 6 0.47% 92.18% # Bytes accessed per row activation 175system.physmem.bytesPerActivate::1088-1089 7 0.55% 92.72% # Bytes accessed per row activation 176system.physmem.bytesPerActivate::1152-1153 7 0.55% 93.27% # Bytes accessed per row activation 177system.physmem.bytesPerActivate::1216-1217 3 0.23% 93.51% # Bytes accessed per row activation 178system.physmem.bytesPerActivate::1280-1281 4 0.31% 93.82% # Bytes accessed per row activation 179system.physmem.bytesPerActivate::1344-1345 3 0.23% 94.05% # Bytes accessed per row activation 180system.physmem.bytesPerActivate::1408-1409 6 0.47% 94.52% # Bytes accessed per row activation 181system.physmem.bytesPerActivate::1472-1473 5 0.39% 94.91% # Bytes accessed per row activation 182system.physmem.bytesPerActivate::1536-1537 5 0.39% 95.31% # Bytes accessed per row activation 183system.physmem.bytesPerActivate::1600-1601 2 0.16% 95.46% # Bytes accessed per row activation 184system.physmem.bytesPerActivate::1664-1665 5 0.39% 95.85% # Bytes accessed per row activation 185system.physmem.bytesPerActivate::1728-1729 4 0.31% 96.17% # Bytes accessed per row activation 186system.physmem.bytesPerActivate::1792-1793 2 0.16% 96.32% # Bytes accessed per row activation 187system.physmem.bytesPerActivate::1920-1921 2 0.16% 96.48% # Bytes accessed per row activation 188system.physmem.bytesPerActivate::2048-2049 3 0.23% 96.71% # Bytes accessed per row activation 189system.physmem.bytesPerActivate::2112-2113 4 0.31% 97.03% # Bytes accessed per row activation 190system.physmem.bytesPerActivate::2176-2177 2 0.16% 97.18% # Bytes accessed per row activation 191system.physmem.bytesPerActivate::2240-2241 1 0.08% 97.26% # Bytes accessed per row activation 192system.physmem.bytesPerActivate::2304-2305 1 0.08% 97.34% # Bytes accessed per row activation 193system.physmem.bytesPerActivate::2368-2369 2 0.16% 97.50% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::2432-2433 1 0.08% 97.57% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::2560-2561 2 0.16% 97.73% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::2624-2625 1 0.08% 97.81% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::2752-2753 1 0.08% 97.89% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::2816-2817 1 0.08% 97.97% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::2880-2881 2 0.16% 98.12% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::2944-2945 1 0.08% 98.20% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::3008-3009 2 0.16% 98.36% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::3136-3137 2 0.16% 98.51% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::3200-3201 2 0.16% 98.67% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::3328-3329 1 0.08% 98.75% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::3584-3585 2 0.16% 98.90% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::3712-3713 1 0.08% 98.98% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::4032-4033 1 0.08% 99.06% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::4096-4097 1 0.08% 99.14% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::4160-4161 1 0.08% 99.22% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::4608-4609 3 0.23% 99.45% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::4736-4737 1 0.08% 99.53% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::6464-6465 1 0.08% 99.61% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::6528-6529 1 0.08% 99.69% # Bytes accessed per row activation 214system.physmem.bytesPerActivate::6912-6913 1 0.08% 99.77% # Bytes accessed per row activation 215system.physmem.bytesPerActivate::7552-7553 1 0.08% 99.84% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::8192-8193 2 0.16% 100.00% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::total 1278 # Bytes accessed per row activation 218system.physmem.totQLat 61296000 # Total ticks spent queuing 219system.physmem.totMemAccLat 197202250 # Total ticks spent from burst creation until serviced by the DRAM 220system.physmem.totBusLat 36480000 # Total ticks spent in databus transfers 221system.physmem.totBankLat 99426250 # Total ticks spent accessing banks 222system.physmem.avgQLat 8401.32 # Average queueing delay per DRAM burst 223system.physmem.avgBankLat 13627.50 # Average bank access latency per DRAM burst 224system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 225system.physmem.avgMemAccLat 27028.82 # Average memory access latency per DRAM burst 226system.physmem.avgRdBW 6.82 # Average DRAM read bandwidth in MiByte/s 227system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 228system.physmem.avgRdBWSys 6.82 # Average system read bandwidth in MiByte/s 229system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 230system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 231system.physmem.busUtil 0.05 # Data bus utilization in percentage 232system.physmem.busUtilRead 0.05 # Data bus utilization in percentage for reads 233system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 234system.physmem.avgRdQLen 0.00 # Average read queue length when enqueuing 235system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 236system.physmem.readRowHits 6018 # Number of row buffer hits during reads 237system.physmem.writeRowHits 0 # Number of row buffer hits during writes 238system.physmem.readRowHitRate 82.48 # Row buffer hit rate for reads 239system.physmem.writeRowHitRate nan # Row buffer hit rate for writes 240system.physmem.avgGap 9390000.96 # Average gap between requests 241system.physmem.pageHitRate 82.48 # Row buffer hit rate, read and write combined 242system.physmem.prechargeAllPercent 1.14 # Percentage of time for which DRAM has all the banks in precharge state 243system.membus.throughput 6815742 # Throughput (bytes/s) 244system.membus.trans_dist::ReadReq 4471 # Transaction distribution 245system.membus.trans_dist::ReadResp 4471 # Transaction distribution 246system.membus.trans_dist::UpgradeReq 2 # Transaction distribution 247system.membus.trans_dist::UpgradeResp 2 # Transaction distribution 248system.membus.trans_dist::ReadExReq 2825 # Transaction distribution 249system.membus.trans_dist::ReadExResp 2825 # Transaction distribution 250system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14596 # Packet count per connected master and slave (bytes) 251system.membus.pkt_count::total 14596 # Packet count per connected master and slave (bytes) 252system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 466944 # Cumulative packet size per connected master and slave (bytes) 253system.membus.tot_pkt_size::total 466944 # Cumulative packet size per connected master and slave (bytes) 254system.membus.data_through_bus 466944 # Total data (bytes) 255system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 256system.membus.reqLayer0.occupancy 8937500 # Layer occupancy (ticks) 257system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 258system.membus.respLayer1.occupancy 67899498 # Layer occupancy (ticks) 259system.membus.respLayer1.utilization 0.1 # Layer utilization (%) 260system.cpu.branchPred.lookups 35425567 # Number of BP lookups 261system.cpu.branchPred.condPredicted 21222314 # Number of conditional branches predicted 262system.cpu.branchPred.condIncorrect 1660593 # Number of conditional branches incorrect 263system.cpu.branchPred.BTBLookups 19605313 # Number of BTB lookups 264system.cpu.branchPred.BTBHits 16823422 # Number of BTB hits 265system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 266system.cpu.branchPred.BTBHitPct 85.810525 # BTB Hit Percentage 267system.cpu.branchPred.usedRAS 6781780 # Number of times the RAS was used to get a target. 268system.cpu.branchPred.RASInCorrect 8434 # Number of incorrect RAS predictions. 269system.cpu.dtb.inst_hits 0 # ITB inst hits 270system.cpu.dtb.inst_misses 0 # ITB inst misses 271system.cpu.dtb.read_hits 0 # DTB read hits 272system.cpu.dtb.read_misses 0 # DTB read misses 273system.cpu.dtb.write_hits 0 # DTB write hits 274system.cpu.dtb.write_misses 0 # DTB write misses 275system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 276system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 277system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 278system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 279system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 280system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 281system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 282system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 283system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 284system.cpu.dtb.read_accesses 0 # DTB read accesses 285system.cpu.dtb.write_accesses 0 # DTB write accesses 286system.cpu.dtb.inst_accesses 0 # ITB inst accesses 287system.cpu.dtb.hits 0 # DTB hits 288system.cpu.dtb.misses 0 # DTB misses 289system.cpu.dtb.accesses 0 # DTB accesses 290system.cpu.itb.inst_hits 0 # ITB inst hits 291system.cpu.itb.inst_misses 0 # ITB inst misses 292system.cpu.itb.read_hits 0 # DTB read hits 293system.cpu.itb.read_misses 0 # DTB read misses 294system.cpu.itb.write_hits 0 # DTB write hits 295system.cpu.itb.write_misses 0 # DTB write misses 296system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 297system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 298system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 299system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 300system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 301system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 302system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 303system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 304system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 305system.cpu.itb.read_accesses 0 # DTB read accesses 306system.cpu.itb.write_accesses 0 # DTB write accesses 307system.cpu.itb.inst_accesses 0 # ITB inst accesses 308system.cpu.itb.hits 0 # DTB hits 309system.cpu.itb.misses 0 # DTB misses 310system.cpu.itb.accesses 0 # DTB accesses 311system.cpu.workload.num_syscalls 191 # Number of system calls 312system.cpu.numCycles 137019272 # number of cpu cycles simulated 313system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 314system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 315system.cpu.fetch.icacheStallCycles 39008530 # Number of cycles fetch is stalled on an Icache miss 316system.cpu.fetch.Insts 318058207 # Number of instructions fetch has processed 317system.cpu.fetch.Branches 35425567 # Number of branches that fetch encountered 318system.cpu.fetch.predictedBranches 23605202 # Number of branches that fetch has predicted taken 319system.cpu.fetch.Cycles 70950828 # Number of cycles fetch has run and was not squashing or blocked 320system.cpu.fetch.SquashCycles 6887573 # Number of cycles fetch has spent squashing 321system.cpu.fetch.BlockedCycles 21494775 # Number of cycles fetch has spent blocked 322system.cpu.fetch.MiscStallCycles 105 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 323system.cpu.fetch.PendingTrapStallCycles 1573 # Number of stall cycles due to pending traps 324system.cpu.fetch.IcacheWaitRetryStallCycles 61 # Number of stall cycles due to full MSHR 325system.cpu.fetch.CacheLines 37609299 # Number of cache lines fetched 326system.cpu.fetch.IcacheSquashes 515132 # Number of outstanding Icache misses that were squashed 327system.cpu.fetch.rateDist::samples 136671204 # Number of instructions fetched each cycle (Total) 328system.cpu.fetch.rateDist::mean 2.983776 # Number of instructions fetched each cycle (Total) 329system.cpu.fetch.rateDist::stdev 3.454359 # Number of instructions fetched each cycle (Total) 330system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 331system.cpu.fetch.rateDist::0 66353464 48.55% 48.55% # Number of instructions fetched each cycle (Total) 332system.cpu.fetch.rateDist::1 6794042 4.97% 53.52% # Number of instructions fetched each cycle (Total) 333system.cpu.fetch.rateDist::2 5704725 4.17% 57.69% # Number of instructions fetched each cycle (Total) 334system.cpu.fetch.rateDist::3 6102503 4.47% 62.16% # Number of instructions fetched each cycle (Total) 335system.cpu.fetch.rateDist::4 4920388 3.60% 65.76% # Number of instructions fetched each cycle (Total) 336system.cpu.fetch.rateDist::5 4084365 2.99% 68.75% # Number of instructions fetched each cycle (Total) 337system.cpu.fetch.rateDist::6 3186134 2.33% 71.08% # Number of instructions fetched each cycle (Total) 338system.cpu.fetch.rateDist::7 4139625 3.03% 74.11% # Number of instructions fetched each cycle (Total) 339system.cpu.fetch.rateDist::8 35385958 25.89% 100.00% # Number of instructions fetched each cycle (Total) 340system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 341system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 342system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 343system.cpu.fetch.rateDist::total 136671204 # Number of instructions fetched each cycle (Total) 344system.cpu.fetch.branchRate 0.258544 # Number of branch fetches per cycle 345system.cpu.fetch.rate 2.321266 # Number of inst fetches per cycle 346system.cpu.decode.IdleCycles 45524127 # Number of cycles decode is idle 347system.cpu.decode.BlockedCycles 16648036 # Number of cycles decode is blocked 348system.cpu.decode.RunCycles 66820925 # Number of cycles decode is running 349system.cpu.decode.UnblockCycles 2531461 # Number of cycles decode is unblocking 350system.cpu.decode.SquashCycles 5146655 # Number of cycles decode is squashing 351system.cpu.decode.BranchResolved 7342433 # Number of times decode resolved a branch 352system.cpu.decode.BranchMispred 69027 # Number of times decode detected a branch misprediction 353system.cpu.decode.DecodedInsts 401839978 # Number of instructions handled by decode 354system.cpu.decode.SquashedInsts 214083 # Number of squashed instructions handled by decode 355system.cpu.rename.SquashCycles 5146655 # Number of cycles rename is squashing 356system.cpu.rename.IdleCycles 51074305 # Number of cycles rename is idle 357system.cpu.rename.BlockCycles 1910036 # Number of cycles rename is blocking 358system.cpu.rename.serializeStallCycles 332499 # count of cycles rename stalled for serializing inst 359system.cpu.rename.RunCycles 63741314 # Number of cycles rename is running 360system.cpu.rename.UnblockCycles 14466395 # Number of cycles rename is unblocking 361system.cpu.rename.RenamedInsts 394244633 # Number of instructions processed by rename 362system.cpu.rename.ROBFullEvents 55 # Number of times rename has blocked due to ROB full 363system.cpu.rename.IQFullEvents 1658642 # Number of times rename has blocked due to IQ full 364system.cpu.rename.LSQFullEvents 10186296 # Number of times rename has blocked due to LSQ full 365system.cpu.rename.FullRegisterEvents 1132 # Number of times there has been no free registers 366system.cpu.rename.RenamedOperands 432779208 # Number of destination operands rename has renamed 367system.cpu.rename.RenameLookups 2333721873 # Number of register rename lookups that rename has made 368system.cpu.rename.int_rename_lookups 1575557795 # Number of integer rename lookups 369system.cpu.rename.fp_rename_lookups 200430073 # Number of floating rename lookups 370system.cpu.rename.CommittedMaps 384566193 # Number of HB maps that are committed 371system.cpu.rename.UndoneMaps 48213015 # Number of HB maps that are undone due to squashing 372system.cpu.rename.serializingInsts 11816 # count of serializing insts renamed 373system.cpu.rename.tempSerializingInsts 11815 # count of temporary serializing insts renamed 374system.cpu.rename.skidInsts 36510705 # count of insts added to the skid buffer 375system.cpu.memDep0.insertedLoads 103606610 # Number of loads inserted to the mem dependence unit. 376system.cpu.memDep0.insertedStores 91402094 # Number of stores inserted to the mem dependence unit. 377system.cpu.memDep0.conflictingLoads 4304684 # Number of conflicting loads. 378system.cpu.memDep0.conflictingStores 5331956 # Number of conflicting stores. 379system.cpu.iq.iqInstsAdded 384603029 # Number of instructions added to the IQ (excludes non-spec) 380system.cpu.iq.iqNonSpecInstsAdded 22794 # Number of non-speculative instructions added to the IQ 381system.cpu.iq.iqInstsIssued 374241110 # Number of instructions issued 382system.cpu.iq.iqSquashedInstsIssued 1211414 # Number of squashed instructions issued 383system.cpu.iq.iqSquashedInstsExamined 34812310 # Number of squashed instructions iterated over during squash; mainly for profiling 384system.cpu.iq.iqSquashedOperandsExamined 87759919 # Number of squashed operands that are examined and possibly removed from graph 385system.cpu.iq.iqSquashedNonSpecRemoved 674 # Number of squashed non-spec instructions that were removed 386system.cpu.iq.issued_per_cycle::samples 136671204 # Number of insts issued each cycle 387system.cpu.iq.issued_per_cycle::mean 2.738259 # Number of insts issued each cycle 388system.cpu.iq.issued_per_cycle::stdev 2.024772 # Number of insts issued each cycle 389system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 390system.cpu.iq.issued_per_cycle::0 25129949 18.39% 18.39% # Number of insts issued each cycle 391system.cpu.iq.issued_per_cycle::1 19927179 14.58% 32.97% # Number of insts issued each cycle 392system.cpu.iq.issued_per_cycle::2 20562891 15.05% 48.01% # Number of insts issued each cycle 393system.cpu.iq.issued_per_cycle::3 18173263 13.30% 61.31% # Number of insts issued each cycle 394system.cpu.iq.issued_per_cycle::4 24036101 17.59% 78.90% # Number of insts issued each cycle 395system.cpu.iq.issued_per_cycle::5 15736190 11.51% 90.41% # Number of insts issued each cycle 396system.cpu.iq.issued_per_cycle::6 8814920 6.45% 96.86% # Number of insts issued each cycle 397system.cpu.iq.issued_per_cycle::7 3372202 2.47% 99.33% # Number of insts issued each cycle 398system.cpu.iq.issued_per_cycle::8 918509 0.67% 100.00% # Number of insts issued each cycle 399system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 400system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 401system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 402system.cpu.iq.issued_per_cycle::total 136671204 # Number of insts issued each cycle 403system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 404system.cpu.iq.fu_full::IntAlu 8708 0.05% 0.05% # attempts to use FU when none available 405system.cpu.iq.fu_full::IntMult 4694 0.03% 0.08% # attempts to use FU when none available 406system.cpu.iq.fu_full::IntDiv 0 0.00% 0.08% # attempts to use FU when none available 407system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.08% # attempts to use FU when none available 408system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.08% # attempts to use FU when none available 409system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.08% # attempts to use FU when none available 410system.cpu.iq.fu_full::FloatMult 0 0.00% 0.08% # attempts to use FU when none available 411system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.08% # attempts to use FU when none available 412system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.08% # attempts to use FU when none available 413system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.08% # attempts to use FU when none available 414system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.08% # attempts to use FU when none available 415system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.08% # attempts to use FU when none available 416system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.08% # attempts to use FU when none available 417system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.08% # attempts to use FU when none available 418system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.08% # attempts to use FU when none available 419system.cpu.iq.fu_full::SimdMult 0 0.00% 0.08% # attempts to use FU when none available 420system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.08% # attempts to use FU when none available 421system.cpu.iq.fu_full::SimdShift 0 0.00% 0.08% # attempts to use FU when none available 422system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.08% # attempts to use FU when none available 423system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.08% # attempts to use FU when none available 424system.cpu.iq.fu_full::SimdFloatAdd 46360 0.26% 0.34% # attempts to use FU when none available 425system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.34% # attempts to use FU when none available 426system.cpu.iq.fu_full::SimdFloatCmp 7648 0.04% 0.38% # attempts to use FU when none available 427system.cpu.iq.fu_full::SimdFloatCvt 433 0.00% 0.38% # attempts to use FU when none available 428system.cpu.iq.fu_full::SimdFloatDiv 2 0.00% 0.38% # attempts to use FU when none available 429system.cpu.iq.fu_full::SimdFloatMisc 190801 1.08% 1.46% # attempts to use FU when none available 430system.cpu.iq.fu_full::SimdFloatMult 4328 0.02% 1.48% # attempts to use FU when none available 431system.cpu.iq.fu_full::SimdFloatMultAcc 241338 1.36% 2.85% # attempts to use FU when none available 432system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.85% # attempts to use FU when none available 433system.cpu.iq.fu_full::MemRead 9265240 52.28% 55.13% # attempts to use FU when none available 434system.cpu.iq.fu_full::MemWrite 7952555 44.87% 100.00% # attempts to use FU when none available 435system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 436system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 437system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 438system.cpu.iq.FU_type_0::IntAlu 126474576 33.79% 33.79% # Type of FU issued 439system.cpu.iq.FU_type_0::IntMult 2175710 0.58% 34.38% # Type of FU issued 440system.cpu.iq.FU_type_0::IntDiv 0 0.00% 34.38% # Type of FU issued 441system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 34.38% # Type of FU issued 442system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 34.38% # Type of FU issued 443system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 34.38% # Type of FU issued 444system.cpu.iq.FU_type_0::FloatMult 0 0.00% 34.38% # Type of FU issued 445system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 34.38% # Type of FU issued 446system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 34.38% # Type of FU issued 447system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 34.38% # Type of FU issued 448system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 34.38% # Type of FU issued 449system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 34.38% # Type of FU issued 450system.cpu.iq.FU_type_0::SimdCmp 3 0.00% 34.38% # Type of FU issued 451system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 34.38% # Type of FU issued 452system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 34.38% # Type of FU issued 453system.cpu.iq.FU_type_0::SimdMult 0 0.00% 34.38% # Type of FU issued 454system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 34.38% # Type of FU issued 455system.cpu.iq.FU_type_0::SimdShift 0 0.00% 34.38% # Type of FU issued 456system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 34.38% # Type of FU issued 457system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 34.38% # Type of FU issued 458system.cpu.iq.FU_type_0::SimdFloatAdd 6781686 1.81% 36.19% # Type of FU issued 459system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 36.19% # Type of FU issued 460system.cpu.iq.FU_type_0::SimdFloatCmp 8476200 2.26% 38.45% # Type of FU issued 461system.cpu.iq.FU_type_0::SimdFloatCvt 3430464 0.92% 39.37% # Type of FU issued 462system.cpu.iq.FU_type_0::SimdFloatDiv 1596092 0.43% 39.80% # Type of FU issued 463system.cpu.iq.FU_type_0::SimdFloatMisc 20867035 5.58% 45.37% # Type of FU issued 464system.cpu.iq.FU_type_0::SimdFloatMult 7174148 1.92% 47.29% # Type of FU issued 465system.cpu.iq.FU_type_0::SimdFloatMultAcc 7130628 1.91% 49.19% # Type of FU issued 466system.cpu.iq.FU_type_0::SimdFloatSqrt 175287 0.05% 49.24% # Type of FU issued 467system.cpu.iq.FU_type_0::MemRead 101661693 27.16% 76.41% # Type of FU issued 468system.cpu.iq.FU_type_0::MemWrite 88297588 23.59% 100.00% # Type of FU issued 469system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 470system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 471system.cpu.iq.FU_type_0::total 374241110 # Type of FU issued 472system.cpu.iq.rate 2.731303 # Inst issue rate 473system.cpu.iq.fu_busy_cnt 17722107 # FU busy when requested 474system.cpu.iq.fu_busy_rate 0.047355 # FU busy rate (busy events/executed inst) 475system.cpu.iq.int_inst_queue_reads 654665747 # Number of integer instruction queue reads 476system.cpu.iq.int_inst_queue_writes 289075917 # Number of integer instruction queue writes 477system.cpu.iq.int_inst_queue_wakeup_accesses 250124446 # Number of integer instruction queue wakeup accesses 478system.cpu.iq.fp_inst_queue_reads 249421198 # Number of floating instruction queue reads 479system.cpu.iq.fp_inst_queue_writes 130376340 # Number of floating instruction queue writes 480system.cpu.iq.fp_inst_queue_wakeup_accesses 118073548 # Number of floating instruction queue wakeup accesses 481system.cpu.iq.int_alu_accesses 263342959 # Number of integer alu accesses 482system.cpu.iq.fp_alu_accesses 128620258 # Number of floating point alu accesses 483system.cpu.iew.lsq.thread0.forwLoads 11085750 # Number of loads that had data forwarded from stores 484system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 485system.cpu.iew.lsq.thread0.squashedLoads 8957862 # Number of loads squashed 486system.cpu.iew.lsq.thread0.ignoredResponses 109225 # Number of memory responses ignored because the instruction is squashed 487system.cpu.iew.lsq.thread0.memOrderViolation 14255 # Number of memory ordering violations 488system.cpu.iew.lsq.thread0.squashedStores 9026511 # Number of stores squashed 489system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 490system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 491system.cpu.iew.lsq.thread0.rescheduledLoads 173986 # Number of loads that were rescheduled 492system.cpu.iew.lsq.thread0.cacheBlocked 1905 # Number of times an access to memory failed due to the cache being blocked 493system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 494system.cpu.iew.iewSquashCycles 5146655 # Number of cycles IEW is squashing 495system.cpu.iew.iewBlockCycles 274797 # Number of cycles IEW is blocking 496system.cpu.iew.iewUnblockCycles 35672 # Number of cycles IEW is unblocking 497system.cpu.iew.iewDispatchedInsts 384627381 # Number of instructions dispatched to IQ 498system.cpu.iew.iewDispSquashedInsts 873173 # Number of squashed instructions skipped by dispatch 499system.cpu.iew.iewDispLoadInsts 103606610 # Number of dispatched load instructions 500system.cpu.iew.iewDispStoreInsts 91402094 # Number of dispatched store instructions 501system.cpu.iew.iewDispNonSpecInsts 11760 # Number of dispatched non-speculative instructions 502system.cpu.iew.iewIQFullEvents 340 # Number of times the IQ has become full, causing a stall 503system.cpu.iew.iewLSQFullEvents 365 # Number of times the LSQ has become full, causing a stall 504system.cpu.iew.memOrderViolationEvents 14255 # Number of memory order violations 505system.cpu.iew.predictedTakenIncorrect 1300817 # Number of branches that were predicted taken incorrectly 506system.cpu.iew.predictedNotTakenIncorrect 370830 # Number of branches that were predicted not taken incorrectly 507system.cpu.iew.branchMispredicts 1671647 # Number of branch mispredicts detected at execute 508system.cpu.iew.iewExecutedInsts 370280641 # Number of executed instructions 509system.cpu.iew.iewExecLoadInsts 100372061 # Number of load instructions executed 510system.cpu.iew.iewExecSquashedInsts 3960469 # Number of squashed instructions skipped in execute 511system.cpu.iew.exec_swp 0 # number of swp insts executed 512system.cpu.iew.exec_nop 1558 # number of nop insts executed 513system.cpu.iew.exec_refs 187586293 # number of memory reference insts executed 514system.cpu.iew.exec_branches 32011507 # Number of branches executed 515system.cpu.iew.exec_stores 87214232 # Number of stores executed 516system.cpu.iew.exec_rate 2.702398 # Inst execution rate 517system.cpu.iew.wb_sent 368867964 # cumulative count of insts sent to commit 518system.cpu.iew.wb_count 368197994 # cumulative count of insts written-back 519system.cpu.iew.wb_producers 183086265 # num instructions producing a value 520system.cpu.iew.wb_consumers 363871713 # num instructions consuming a value 521system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 522system.cpu.iew.wb_rate 2.687199 # insts written-back per cycle 523system.cpu.iew.wb_fanout 0.503162 # average fanout of values written-back 524system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 525system.cpu.commit.commitSquashedInsts 35562440 # The number of squashed insts skipped by commit 526system.cpu.commit.commitNonSpecStalls 22120 # The number of times commit has been forced to stall to communicate backwards 527system.cpu.commit.branchMispredicts 1591916 # The number of times a branch was mispredicted 528system.cpu.commit.committed_per_cycle::samples 131524549 # Number of insts commited each cycle 529system.cpu.commit.committed_per_cycle::mean 2.653992 # Number of insts commited each cycle 530system.cpu.commit.committed_per_cycle::stdev 2.659233 # Number of insts commited each cycle 531system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 532system.cpu.commit.committed_per_cycle::0 34720675 26.40% 26.40% # Number of insts commited each cycle 533system.cpu.commit.committed_per_cycle::1 28457654 21.64% 48.04% # Number of insts commited each cycle 534system.cpu.commit.committed_per_cycle::2 13339371 10.14% 58.18% # Number of insts commited each cycle 535system.cpu.commit.committed_per_cycle::3 11431101 8.69% 66.87% # Number of insts commited each cycle 536system.cpu.commit.committed_per_cycle::4 13773309 10.47% 77.34% # Number of insts commited each cycle 537system.cpu.commit.committed_per_cycle::5 7413510 5.64% 82.98% # Number of insts commited each cycle 538system.cpu.commit.committed_per_cycle::6 3874860 2.95% 85.92% # Number of insts commited each cycle 539system.cpu.commit.committed_per_cycle::7 3887136 2.96% 88.88% # Number of insts commited each cycle 540system.cpu.commit.committed_per_cycle::8 14626933 11.12% 100.00% # Number of insts commited each cycle 541system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 542system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 543system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 544system.cpu.commit.committed_per_cycle::total 131524549 # Number of insts commited each cycle 545system.cpu.commit.committedInsts 273037337 # Number of instructions committed 546system.cpu.commit.committedOps 349065061 # Number of ops (including micro ops) committed 547system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 548system.cpu.commit.refs 177024331 # Number of memory references committed 549system.cpu.commit.loads 94648748 # Number of loads committed 550system.cpu.commit.membars 11033 # Number of memory barriers committed 551system.cpu.commit.branches 30563497 # Number of branches committed 552system.cpu.commit.fp_insts 114216705 # Number of committed floating point instructions. 553system.cpu.commit.int_insts 279584611 # Number of committed integer instructions. 554system.cpu.commit.function_calls 6225112 # Number of function calls committed. 555system.cpu.commit.bw_lim_events 14626933 # number cycles where commit BW limit reached 556system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 557system.cpu.rob.rob_reads 501522594 # The number of ROB reads 558system.cpu.rob.rob_writes 774405807 # The number of ROB writes 559system.cpu.timesIdled 6645 # Number of times that the entire CPU went into an idle state and unscheduled itself 560system.cpu.idleCycles 348068 # Total number of cycles that the CPU has spent unscheduled due to idling 561system.cpu.committedInsts 273036725 # Number of Instructions Simulated 562system.cpu.committedOps 349064449 # Number of Ops (including micro ops) Simulated 563system.cpu.committedInsts_total 273036725 # Number of Instructions Simulated 564system.cpu.cpi 0.501835 # CPI: Cycles Per Instruction 565system.cpu.cpi_total 0.501835 # CPI: Total CPI of All Threads 566system.cpu.ipc 1.992688 # IPC: Instructions Per Cycle 567system.cpu.ipc_total 1.992688 # IPC: Total IPC of All Threads 568system.cpu.int_regfile_reads 1769988396 # number of integer regfile reads 569system.cpu.int_regfile_writes 233047297 # number of integer regfile writes 570system.cpu.fp_regfile_reads 188164665 # number of floating regfile reads 571system.cpu.fp_regfile_writes 132532739 # number of floating regfile writes 572system.cpu.misc_regfile_reads 566941334 # number of misc regfile reads 573system.cpu.misc_regfile_writes 34421755 # number of misc regfile writes 574system.cpu.toL2Bus.throughput 20093174 # Throughput (bytes/s) 575system.cpu.toL2Bus.trans_dist::ReadReq 17631 # Transaction distribution 576system.cpu.toL2Bus.trans_dist::ReadResp 17631 # Transaction distribution 577system.cpu.toL2Bus.trans_dist::Writeback 1036 # Transaction distribution 578system.cpu.toL2Bus.trans_dist::UpgradeReq 2 # Transaction distribution 579system.cpu.toL2Bus.trans_dist::UpgradeResp 2 # Transaction distribution 580system.cpu.toL2Bus.trans_dist::ReadExReq 2842 # Transaction distribution 581system.cpu.toL2Bus.trans_dist::ReadExResp 2842 # Transaction distribution 582system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 31714 # Packet count per connected master and slave (bytes) 583system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10268 # Packet count per connected master and slave (bytes) 584system.cpu.toL2Bus.pkt_count::total 41982 # Packet count per connected master and slave (bytes) 585system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1014720 # Cumulative packet size per connected master and slave (bytes) 586system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 361600 # Cumulative packet size per connected master and slave (bytes) 587system.cpu.toL2Bus.tot_pkt_size::total 1376320 # Cumulative packet size per connected master and slave (bytes) 588system.cpu.toL2Bus.data_through_bus 1376320 # Total data (bytes) 589system.cpu.toL2Bus.snoop_data_through_bus 256 # Total snoop data (bytes) 590system.cpu.toL2Bus.reqLayer0.occupancy 11791500 # Layer occupancy (ticks) 591system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 592system.cpu.toL2Bus.respLayer0.occupancy 24322738 # Layer occupancy (ticks) 593system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 594system.cpu.toL2Bus.respLayer1.occupancy 7408962 # Layer occupancy (ticks) 595system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 596system.cpu.icache.tags.replacements 13968 # number of replacements 597system.cpu.icache.tags.tagsinuse 1848.251388 # Cycle average of tags in use 598system.cpu.icache.tags.total_refs 37591948 # Total number of references to valid blocks. 599system.cpu.icache.tags.sampled_refs 15858 # Sample count of references to valid blocks. 600system.cpu.icache.tags.avg_refs 2370.535250 # Average number of references to valid blocks. 601system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 602system.cpu.icache.tags.occ_blocks::cpu.inst 1848.251388 # Average occupied blocks per requestor 603system.cpu.icache.tags.occ_percent::cpu.inst 0.902466 # Average percentage of cache occupancy 604system.cpu.icache.tags.occ_percent::total 0.902466 # Average percentage of cache occupancy 605system.cpu.icache.ReadReq_hits::cpu.inst 37591948 # number of ReadReq hits 606system.cpu.icache.ReadReq_hits::total 37591948 # number of ReadReq hits 607system.cpu.icache.demand_hits::cpu.inst 37591948 # number of demand (read+write) hits 608system.cpu.icache.demand_hits::total 37591948 # number of demand (read+write) hits 609system.cpu.icache.overall_hits::cpu.inst 37591948 # number of overall hits 610system.cpu.icache.overall_hits::total 37591948 # number of overall hits 611system.cpu.icache.ReadReq_misses::cpu.inst 17349 # number of ReadReq misses 612system.cpu.icache.ReadReq_misses::total 17349 # number of ReadReq misses 613system.cpu.icache.demand_misses::cpu.inst 17349 # number of demand (read+write) misses 614system.cpu.icache.demand_misses::total 17349 # number of demand (read+write) misses 615system.cpu.icache.overall_misses::cpu.inst 17349 # number of overall misses 616system.cpu.icache.overall_misses::total 17349 # number of overall misses 617system.cpu.icache.ReadReq_miss_latency::cpu.inst 451171984 # number of ReadReq miss cycles 618system.cpu.icache.ReadReq_miss_latency::total 451171984 # number of ReadReq miss cycles 619system.cpu.icache.demand_miss_latency::cpu.inst 451171984 # number of demand (read+write) miss cycles 620system.cpu.icache.demand_miss_latency::total 451171984 # number of demand (read+write) miss cycles 621system.cpu.icache.overall_miss_latency::cpu.inst 451171984 # number of overall miss cycles 622system.cpu.icache.overall_miss_latency::total 451171984 # number of overall miss cycles 623system.cpu.icache.ReadReq_accesses::cpu.inst 37609297 # number of ReadReq accesses(hits+misses) 624system.cpu.icache.ReadReq_accesses::total 37609297 # number of ReadReq accesses(hits+misses) 625system.cpu.icache.demand_accesses::cpu.inst 37609297 # number of demand (read+write) accesses 626system.cpu.icache.demand_accesses::total 37609297 # number of demand (read+write) accesses 627system.cpu.icache.overall_accesses::cpu.inst 37609297 # number of overall (read+write) accesses 628system.cpu.icache.overall_accesses::total 37609297 # number of overall (read+write) accesses 629system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000461 # miss rate for ReadReq accesses 630system.cpu.icache.ReadReq_miss_rate::total 0.000461 # miss rate for ReadReq accesses 631system.cpu.icache.demand_miss_rate::cpu.inst 0.000461 # miss rate for demand accesses 632system.cpu.icache.demand_miss_rate::total 0.000461 # miss rate for demand accesses 633system.cpu.icache.overall_miss_rate::cpu.inst 0.000461 # miss rate for overall accesses 634system.cpu.icache.overall_miss_rate::total 0.000461 # miss rate for overall accesses 635system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 26005.647818 # average ReadReq miss latency 636system.cpu.icache.ReadReq_avg_miss_latency::total 26005.647818 # average ReadReq miss latency 637system.cpu.icache.demand_avg_miss_latency::cpu.inst 26005.647818 # average overall miss latency 638system.cpu.icache.demand_avg_miss_latency::total 26005.647818 # average overall miss latency 639system.cpu.icache.overall_avg_miss_latency::cpu.inst 26005.647818 # average overall miss latency 640system.cpu.icache.overall_avg_miss_latency::total 26005.647818 # average overall miss latency 641system.cpu.icache.blocked_cycles::no_mshrs 2002 # number of cycles access was blocked 642system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 643system.cpu.icache.blocked::no_mshrs 23 # number of cycles access was blocked 644system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 645system.cpu.icache.avg_blocked_cycles::no_mshrs 87.043478 # average number of cycles each access was blocked 646system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 647system.cpu.icache.fast_writes 0 # number of fast writes performed 648system.cpu.icache.cache_copies 0 # number of cache copies performed 649system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1490 # number of ReadReq MSHR hits 650system.cpu.icache.ReadReq_mshr_hits::total 1490 # number of ReadReq MSHR hits 651system.cpu.icache.demand_mshr_hits::cpu.inst 1490 # number of demand (read+write) MSHR hits 652system.cpu.icache.demand_mshr_hits::total 1490 # number of demand (read+write) MSHR hits 653system.cpu.icache.overall_mshr_hits::cpu.inst 1490 # number of overall MSHR hits 654system.cpu.icache.overall_mshr_hits::total 1490 # number of overall MSHR hits 655system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15859 # number of ReadReq MSHR misses 656system.cpu.icache.ReadReq_mshr_misses::total 15859 # number of ReadReq MSHR misses 657system.cpu.icache.demand_mshr_misses::cpu.inst 15859 # number of demand (read+write) MSHR misses 658system.cpu.icache.demand_mshr_misses::total 15859 # number of demand (read+write) MSHR misses 659system.cpu.icache.overall_mshr_misses::cpu.inst 15859 # number of overall MSHR misses 660system.cpu.icache.overall_mshr_misses::total 15859 # number of overall MSHR misses 661system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 359132259 # number of ReadReq MSHR miss cycles 662system.cpu.icache.ReadReq_mshr_miss_latency::total 359132259 # number of ReadReq MSHR miss cycles 663system.cpu.icache.demand_mshr_miss_latency::cpu.inst 359132259 # number of demand (read+write) MSHR miss cycles 664system.cpu.icache.demand_mshr_miss_latency::total 359132259 # number of demand (read+write) MSHR miss cycles 665system.cpu.icache.overall_mshr_miss_latency::cpu.inst 359132259 # number of overall MSHR miss cycles 666system.cpu.icache.overall_mshr_miss_latency::total 359132259 # number of overall MSHR miss cycles 667system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000422 # mshr miss rate for ReadReq accesses 668system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000422 # mshr miss rate for ReadReq accesses 669system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000422 # mshr miss rate for demand accesses 670system.cpu.icache.demand_mshr_miss_rate::total 0.000422 # mshr miss rate for demand accesses 671system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000422 # mshr miss rate for overall accesses 672system.cpu.icache.overall_mshr_miss_rate::total 0.000422 # mshr miss rate for overall accesses 673system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22645.328142 # average ReadReq mshr miss latency 674system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22645.328142 # average ReadReq mshr miss latency 675system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22645.328142 # average overall mshr miss latency 676system.cpu.icache.demand_avg_mshr_miss_latency::total 22645.328142 # average overall mshr miss latency 677system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22645.328142 # average overall mshr miss latency 678system.cpu.icache.overall_avg_mshr_miss_latency::total 22645.328142 # average overall mshr miss latency 679system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 680system.cpu.l2cache.tags.replacements 0 # number of replacements 681system.cpu.l2cache.tags.tagsinuse 3941.799565 # Cycle average of tags in use 682system.cpu.l2cache.tags.total_refs 13198 # Total number of references to valid blocks. 683system.cpu.l2cache.tags.sampled_refs 5394 # Sample count of references to valid blocks. 684system.cpu.l2cache.tags.avg_refs 2.446793 # Average number of references to valid blocks. 685system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 686system.cpu.l2cache.tags.occ_blocks::writebacks 379.005926 # Average occupied blocks per requestor 687system.cpu.l2cache.tags.occ_blocks::cpu.inst 2786.464306 # Average occupied blocks per requestor 688system.cpu.l2cache.tags.occ_blocks::cpu.data 776.329333 # Average occupied blocks per requestor 689system.cpu.l2cache.tags.occ_percent::writebacks 0.011566 # Average percentage of cache occupancy 690system.cpu.l2cache.tags.occ_percent::cpu.inst 0.085036 # Average percentage of cache occupancy 691system.cpu.l2cache.tags.occ_percent::cpu.data 0.023692 # Average percentage of cache occupancy 692system.cpu.l2cache.tags.occ_percent::total 0.120294 # Average percentage of cache occupancy 693system.cpu.l2cache.ReadReq_hits::cpu.inst 12803 # number of ReadReq hits 694system.cpu.l2cache.ReadReq_hits::cpu.data 301 # number of ReadReq hits 695system.cpu.l2cache.ReadReq_hits::total 13104 # number of ReadReq hits 696system.cpu.l2cache.Writeback_hits::writebacks 1036 # number of Writeback hits 697system.cpu.l2cache.Writeback_hits::total 1036 # number of Writeback hits 698system.cpu.l2cache.ReadExReq_hits::cpu.data 17 # number of ReadExReq hits 699system.cpu.l2cache.ReadExReq_hits::total 17 # number of ReadExReq hits 700system.cpu.l2cache.demand_hits::cpu.inst 12803 # number of demand (read+write) hits 701system.cpu.l2cache.demand_hits::cpu.data 318 # number of demand (read+write) hits 702system.cpu.l2cache.demand_hits::total 13121 # number of demand (read+write) hits 703system.cpu.l2cache.overall_hits::cpu.inst 12803 # number of overall hits 704system.cpu.l2cache.overall_hits::cpu.data 318 # number of overall hits 705system.cpu.l2cache.overall_hits::total 13121 # number of overall hits 706system.cpu.l2cache.ReadReq_misses::cpu.inst 3052 # number of ReadReq misses 707system.cpu.l2cache.ReadReq_misses::cpu.data 1471 # number of ReadReq misses 708system.cpu.l2cache.ReadReq_misses::total 4523 # number of ReadReq misses 709system.cpu.l2cache.UpgradeReq_misses::cpu.data 2 # number of UpgradeReq misses 710system.cpu.l2cache.UpgradeReq_misses::total 2 # number of UpgradeReq misses 711system.cpu.l2cache.ReadExReq_misses::cpu.data 2825 # number of ReadExReq misses 712system.cpu.l2cache.ReadExReq_misses::total 2825 # number of ReadExReq misses 713system.cpu.l2cache.demand_misses::cpu.inst 3052 # number of demand (read+write) misses 714system.cpu.l2cache.demand_misses::cpu.data 4296 # number of demand (read+write) misses 715system.cpu.l2cache.demand_misses::total 7348 # number of demand (read+write) misses 716system.cpu.l2cache.overall_misses::cpu.inst 3052 # number of overall misses 717system.cpu.l2cache.overall_misses::cpu.data 4296 # number of overall misses 718system.cpu.l2cache.overall_misses::total 7348 # number of overall misses 719system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 215204250 # number of ReadReq miss cycles 720system.cpu.l2cache.ReadReq_miss_latency::cpu.data 109433000 # number of ReadReq miss cycles 721system.cpu.l2cache.ReadReq_miss_latency::total 324637250 # number of ReadReq miss cycles 722system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 200213000 # number of ReadExReq miss cycles 723system.cpu.l2cache.ReadExReq_miss_latency::total 200213000 # number of ReadExReq miss cycles 724system.cpu.l2cache.demand_miss_latency::cpu.inst 215204250 # number of demand (read+write) miss cycles 725system.cpu.l2cache.demand_miss_latency::cpu.data 309646000 # number of demand (read+write) miss cycles 726system.cpu.l2cache.demand_miss_latency::total 524850250 # number of demand (read+write) miss cycles 727system.cpu.l2cache.overall_miss_latency::cpu.inst 215204250 # number of overall miss cycles 728system.cpu.l2cache.overall_miss_latency::cpu.data 309646000 # number of overall miss cycles 729system.cpu.l2cache.overall_miss_latency::total 524850250 # number of overall miss cycles 730system.cpu.l2cache.ReadReq_accesses::cpu.inst 15855 # number of ReadReq accesses(hits+misses) 731system.cpu.l2cache.ReadReq_accesses::cpu.data 1772 # number of ReadReq accesses(hits+misses) 732system.cpu.l2cache.ReadReq_accesses::total 17627 # number of ReadReq accesses(hits+misses) 733system.cpu.l2cache.Writeback_accesses::writebacks 1036 # number of Writeback accesses(hits+misses) 734system.cpu.l2cache.Writeback_accesses::total 1036 # number of Writeback accesses(hits+misses) 735system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2 # number of UpgradeReq accesses(hits+misses) 736system.cpu.l2cache.UpgradeReq_accesses::total 2 # number of UpgradeReq accesses(hits+misses) 737system.cpu.l2cache.ReadExReq_accesses::cpu.data 2842 # number of ReadExReq accesses(hits+misses) 738system.cpu.l2cache.ReadExReq_accesses::total 2842 # number of ReadExReq accesses(hits+misses) 739system.cpu.l2cache.demand_accesses::cpu.inst 15855 # number of demand (read+write) accesses 740system.cpu.l2cache.demand_accesses::cpu.data 4614 # number of demand (read+write) accesses 741system.cpu.l2cache.demand_accesses::total 20469 # number of demand (read+write) accesses 742system.cpu.l2cache.overall_accesses::cpu.inst 15855 # number of overall (read+write) accesses 743system.cpu.l2cache.overall_accesses::cpu.data 4614 # number of overall (read+write) accesses 744system.cpu.l2cache.overall_accesses::total 20469 # number of overall (read+write) accesses 745system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.192494 # miss rate for ReadReq accesses 746system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.830135 # miss rate for ReadReq accesses 747system.cpu.l2cache.ReadReq_miss_rate::total 0.256595 # miss rate for ReadReq accesses 748system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses 749system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses 750system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.994018 # miss rate for ReadExReq accesses 751system.cpu.l2cache.ReadExReq_miss_rate::total 0.994018 # miss rate for ReadExReq accesses 752system.cpu.l2cache.demand_miss_rate::cpu.inst 0.192494 # miss rate for demand accesses 753system.cpu.l2cache.demand_miss_rate::cpu.data 0.931079 # miss rate for demand accesses 754system.cpu.l2cache.demand_miss_rate::total 0.358982 # miss rate for demand accesses 755system.cpu.l2cache.overall_miss_rate::cpu.inst 0.192494 # miss rate for overall accesses 756system.cpu.l2cache.overall_miss_rate::cpu.data 0.931079 # miss rate for overall accesses 757system.cpu.l2cache.overall_miss_rate::total 0.358982 # miss rate for overall accesses 758system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70512.532765 # average ReadReq miss latency 759system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 74393.609789 # average ReadReq miss latency 760system.cpu.l2cache.ReadReq_avg_miss_latency::total 71774.762326 # average ReadReq miss latency 761system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70871.858407 # average ReadExReq miss latency 762system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70871.858407 # average ReadExReq miss latency 763system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70512.532765 # average overall miss latency 764system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72077.746741 # average overall miss latency 765system.cpu.l2cache.demand_avg_miss_latency::total 71427.633370 # average overall miss latency 766system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70512.532765 # average overall miss latency 767system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72077.746741 # average overall miss latency 768system.cpu.l2cache.overall_avg_miss_latency::total 71427.633370 # average overall miss latency 769system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 770system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 771system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 772system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 773system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 774system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 775system.cpu.l2cache.fast_writes 0 # number of fast writes performed 776system.cpu.l2cache.cache_copies 0 # number of cache copies performed 777system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 12 # number of ReadReq MSHR hits 778system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 40 # number of ReadReq MSHR hits 779system.cpu.l2cache.ReadReq_mshr_hits::total 52 # number of ReadReq MSHR hits 780system.cpu.l2cache.demand_mshr_hits::cpu.inst 12 # number of demand (read+write) MSHR hits 781system.cpu.l2cache.demand_mshr_hits::cpu.data 40 # number of demand (read+write) MSHR hits 782system.cpu.l2cache.demand_mshr_hits::total 52 # number of demand (read+write) MSHR hits 783system.cpu.l2cache.overall_mshr_hits::cpu.inst 12 # number of overall MSHR hits 784system.cpu.l2cache.overall_mshr_hits::cpu.data 40 # number of overall MSHR hits 785system.cpu.l2cache.overall_mshr_hits::total 52 # number of overall MSHR hits 786system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3040 # number of ReadReq MSHR misses 787system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1431 # number of ReadReq MSHR misses 788system.cpu.l2cache.ReadReq_mshr_misses::total 4471 # number of ReadReq MSHR misses 789system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2 # number of UpgradeReq MSHR misses 790system.cpu.l2cache.UpgradeReq_mshr_misses::total 2 # number of UpgradeReq MSHR misses 791system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 2825 # number of ReadExReq MSHR misses 792system.cpu.l2cache.ReadExReq_mshr_misses::total 2825 # number of ReadExReq MSHR misses 793system.cpu.l2cache.demand_mshr_misses::cpu.inst 3040 # number of demand (read+write) MSHR misses 794system.cpu.l2cache.demand_mshr_misses::cpu.data 4256 # number of demand (read+write) MSHR misses 795system.cpu.l2cache.demand_mshr_misses::total 7296 # number of demand (read+write) MSHR misses 796system.cpu.l2cache.overall_mshr_misses::cpu.inst 3040 # number of overall MSHR misses 797system.cpu.l2cache.overall_mshr_misses::cpu.data 4256 # number of overall MSHR misses 798system.cpu.l2cache.overall_mshr_misses::total 7296 # number of overall MSHR misses 799system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 176370000 # number of ReadReq MSHR miss cycles 800system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 88886000 # number of ReadReq MSHR miss cycles 801system.cpu.l2cache.ReadReq_mshr_miss_latency::total 265256000 # number of ReadReq MSHR miss cycles 802system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 20002 # number of UpgradeReq MSHR miss cycles 803system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 20002 # number of UpgradeReq MSHR miss cycles 804system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 165233500 # number of ReadExReq MSHR miss cycles 805system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 165233500 # number of ReadExReq MSHR miss cycles 806system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 176370000 # number of demand (read+write) MSHR miss cycles 807system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 254119500 # number of demand (read+write) MSHR miss cycles 808system.cpu.l2cache.demand_mshr_miss_latency::total 430489500 # number of demand (read+write) MSHR miss cycles 809system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 176370000 # number of overall MSHR miss cycles 810system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 254119500 # number of overall MSHR miss cycles 811system.cpu.l2cache.overall_mshr_miss_latency::total 430489500 # number of overall MSHR miss cycles 812system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.191738 # mshr miss rate for ReadReq accesses 813system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.807562 # mshr miss rate for ReadReq accesses 814system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.253645 # mshr miss rate for ReadReq accesses 815system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses 816system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses 817system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994018 # mshr miss rate for ReadExReq accesses 818system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994018 # mshr miss rate for ReadExReq accesses 819system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.191738 # mshr miss rate for demand accesses 820system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.922410 # mshr miss rate for demand accesses 821system.cpu.l2cache.demand_mshr_miss_rate::total 0.356441 # mshr miss rate for demand accesses 822system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.191738 # mshr miss rate for overall accesses 823system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.922410 # mshr miss rate for overall accesses 824system.cpu.l2cache.overall_mshr_miss_rate::total 0.356441 # mshr miss rate for overall accesses 825system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58016.447368 # average ReadReq mshr miss latency 826system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62114.605171 # average ReadReq mshr miss latency 827system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59328.114516 # average ReadReq mshr miss latency 828system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency 829system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency 830system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58489.734513 # average ReadExReq mshr miss latency 831system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58489.734513 # average ReadExReq mshr miss latency 832system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58016.447368 # average overall mshr miss latency 833system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59708.529135 # average overall mshr miss latency 834system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59003.495066 # average overall mshr miss latency 835system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58016.447368 # average overall mshr miss latency 836system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59708.529135 # average overall mshr miss latency 837system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59003.495066 # average overall mshr miss latency 838system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 839system.cpu.dcache.tags.replacements 1417 # number of replacements 840system.cpu.dcache.tags.tagsinuse 3102.941006 # Cycle average of tags in use 841system.cpu.dcache.tags.total_refs 170982340 # Total number of references to valid blocks. 842system.cpu.dcache.tags.sampled_refs 4614 # Sample count of references to valid blocks. 843system.cpu.dcache.tags.avg_refs 37057.290854 # Average number of references to valid blocks. 844system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 845system.cpu.dcache.tags.occ_blocks::cpu.data 3102.941006 # Average occupied blocks per requestor 846system.cpu.dcache.tags.occ_percent::cpu.data 0.757554 # Average percentage of cache occupancy 847system.cpu.dcache.tags.occ_percent::total 0.757554 # Average percentage of cache occupancy 848system.cpu.dcache.ReadReq_hits::cpu.data 88929043 # number of ReadReq hits 849system.cpu.dcache.ReadReq_hits::total 88929043 # number of ReadReq hits 850system.cpu.dcache.WriteReq_hits::cpu.data 82031381 # number of WriteReq hits 851system.cpu.dcache.WriteReq_hits::total 82031381 # number of WriteReq hits 852system.cpu.dcache.LoadLockedReq_hits::cpu.data 11009 # number of LoadLockedReq hits 853system.cpu.dcache.LoadLockedReq_hits::total 11009 # number of LoadLockedReq hits 854system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits 855system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits 856system.cpu.dcache.demand_hits::cpu.data 170960424 # number of demand (read+write) hits 857system.cpu.dcache.demand_hits::total 170960424 # number of demand (read+write) hits 858system.cpu.dcache.overall_hits::cpu.data 170960424 # number of overall hits 859system.cpu.dcache.overall_hits::total 170960424 # number of overall hits 860system.cpu.dcache.ReadReq_misses::cpu.data 3956 # number of ReadReq misses 861system.cpu.dcache.ReadReq_misses::total 3956 # number of ReadReq misses 862system.cpu.dcache.WriteReq_misses::cpu.data 21284 # number of WriteReq misses 863system.cpu.dcache.WriteReq_misses::total 21284 # number of WriteReq misses 864system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses 865system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses 866system.cpu.dcache.demand_misses::cpu.data 25240 # number of demand (read+write) misses 867system.cpu.dcache.demand_misses::total 25240 # number of demand (read+write) misses 868system.cpu.dcache.overall_misses::cpu.data 25240 # number of overall misses 869system.cpu.dcache.overall_misses::total 25240 # number of overall misses 870system.cpu.dcache.ReadReq_miss_latency::cpu.data 235586955 # number of ReadReq miss cycles 871system.cpu.dcache.ReadReq_miss_latency::total 235586955 # number of ReadReq miss cycles 872system.cpu.dcache.WriteReq_miss_latency::cpu.data 1260992389 # number of WriteReq miss cycles 873system.cpu.dcache.WriteReq_miss_latency::total 1260992389 # number of WriteReq miss cycles 874system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 170250 # number of LoadLockedReq miss cycles 875system.cpu.dcache.LoadLockedReq_miss_latency::total 170250 # number of LoadLockedReq miss cycles 876system.cpu.dcache.demand_miss_latency::cpu.data 1496579344 # number of demand (read+write) miss cycles 877system.cpu.dcache.demand_miss_latency::total 1496579344 # number of demand (read+write) miss cycles 878system.cpu.dcache.overall_miss_latency::cpu.data 1496579344 # number of overall miss cycles 879system.cpu.dcache.overall_miss_latency::total 1496579344 # number of overall miss cycles 880system.cpu.dcache.ReadReq_accesses::cpu.data 88932999 # number of ReadReq accesses(hits+misses) 881system.cpu.dcache.ReadReq_accesses::total 88932999 # number of ReadReq accesses(hits+misses) 882system.cpu.dcache.WriteReq_accesses::cpu.data 82052665 # number of WriteReq accesses(hits+misses) 883system.cpu.dcache.WriteReq_accesses::total 82052665 # number of WriteReq accesses(hits+misses) 884system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11011 # number of LoadLockedReq accesses(hits+misses) 885system.cpu.dcache.LoadLockedReq_accesses::total 11011 # number of LoadLockedReq accesses(hits+misses) 886system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses) 887system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) 888system.cpu.dcache.demand_accesses::cpu.data 170985664 # number of demand (read+write) accesses 889system.cpu.dcache.demand_accesses::total 170985664 # number of demand (read+write) accesses 890system.cpu.dcache.overall_accesses::cpu.data 170985664 # number of overall (read+write) accesses 891system.cpu.dcache.overall_accesses::total 170985664 # number of overall (read+write) accesses 892system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000044 # miss rate for ReadReq accesses 893system.cpu.dcache.ReadReq_miss_rate::total 0.000044 # miss rate for ReadReq accesses 894system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000259 # miss rate for WriteReq accesses 895system.cpu.dcache.WriteReq_miss_rate::total 0.000259 # miss rate for WriteReq accesses 896system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000182 # miss rate for LoadLockedReq accesses 897system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000182 # miss rate for LoadLockedReq accesses 898system.cpu.dcache.demand_miss_rate::cpu.data 0.000148 # miss rate for demand accesses 899system.cpu.dcache.demand_miss_rate::total 0.000148 # miss rate for demand accesses 900system.cpu.dcache.overall_miss_rate::cpu.data 0.000148 # miss rate for overall accesses 901system.cpu.dcache.overall_miss_rate::total 0.000148 # miss rate for overall accesses 902system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 59551.808645 # average ReadReq miss latency 903system.cpu.dcache.ReadReq_avg_miss_latency::total 59551.808645 # average ReadReq miss latency 904system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59246.024666 # average WriteReq miss latency 905system.cpu.dcache.WriteReq_avg_miss_latency::total 59246.024666 # average WriteReq miss latency 906system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 85125 # average LoadLockedReq miss latency 907system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 85125 # average LoadLockedReq miss latency 908system.cpu.dcache.demand_avg_miss_latency::cpu.data 59293.951823 # average overall miss latency 909system.cpu.dcache.demand_avg_miss_latency::total 59293.951823 # average overall miss latency 910system.cpu.dcache.overall_avg_miss_latency::cpu.data 59293.951823 # average overall miss latency 911system.cpu.dcache.overall_avg_miss_latency::total 59293.951823 # average overall miss latency 912system.cpu.dcache.blocked_cycles::no_mshrs 28312 # number of cycles access was blocked 913system.cpu.dcache.blocked_cycles::no_targets 1224 # number of cycles access was blocked 914system.cpu.dcache.blocked::no_mshrs 411 # number of cycles access was blocked 915system.cpu.dcache.blocked::no_targets 12 # number of cycles access was blocked 916system.cpu.dcache.avg_blocked_cycles::no_mshrs 68.885645 # average number of cycles each access was blocked 917system.cpu.dcache.avg_blocked_cycles::no_targets 102 # average number of cycles each access was blocked 918system.cpu.dcache.fast_writes 0 # number of fast writes performed 919system.cpu.dcache.cache_copies 0 # number of cache copies performed 920system.cpu.dcache.writebacks::writebacks 1036 # number of writebacks 921system.cpu.dcache.writebacks::total 1036 # number of writebacks 922system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2182 # number of ReadReq MSHR hits 923system.cpu.dcache.ReadReq_mshr_hits::total 2182 # number of ReadReq MSHR hits 924system.cpu.dcache.WriteReq_mshr_hits::cpu.data 18442 # number of WriteReq MSHR hits 925system.cpu.dcache.WriteReq_mshr_hits::total 18442 # number of WriteReq MSHR hits 926system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits 927system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits 928system.cpu.dcache.demand_mshr_hits::cpu.data 20624 # number of demand (read+write) MSHR hits 929system.cpu.dcache.demand_mshr_hits::total 20624 # number of demand (read+write) MSHR hits 930system.cpu.dcache.overall_mshr_hits::cpu.data 20624 # number of overall MSHR hits 931system.cpu.dcache.overall_mshr_hits::total 20624 # number of overall MSHR hits 932system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1774 # number of ReadReq MSHR misses 933system.cpu.dcache.ReadReq_mshr_misses::total 1774 # number of ReadReq MSHR misses 934system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2842 # number of WriteReq MSHR misses 935system.cpu.dcache.WriteReq_mshr_misses::total 2842 # number of WriteReq MSHR misses 936system.cpu.dcache.demand_mshr_misses::cpu.data 4616 # number of demand (read+write) MSHR misses 937system.cpu.dcache.demand_mshr_misses::total 4616 # number of demand (read+write) MSHR misses 938system.cpu.dcache.overall_mshr_misses::cpu.data 4616 # number of overall MSHR misses 939system.cpu.dcache.overall_mshr_misses::total 4616 # number of overall MSHR misses 940system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 114384040 # number of ReadReq MSHR miss cycles 941system.cpu.dcache.ReadReq_mshr_miss_latency::total 114384040 # number of ReadReq MSHR miss cycles 942system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 203208498 # number of WriteReq MSHR miss cycles 943system.cpu.dcache.WriteReq_mshr_miss_latency::total 203208498 # number of WriteReq MSHR miss cycles 944system.cpu.dcache.demand_mshr_miss_latency::cpu.data 317592538 # number of demand (read+write) MSHR miss cycles 945system.cpu.dcache.demand_mshr_miss_latency::total 317592538 # number of demand (read+write) MSHR miss cycles 946system.cpu.dcache.overall_mshr_miss_latency::cpu.data 317592538 # number of overall MSHR miss cycles 947system.cpu.dcache.overall_mshr_miss_latency::total 317592538 # number of overall MSHR miss cycles 948system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000020 # mshr miss rate for ReadReq accesses 949system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000020 # mshr miss rate for ReadReq accesses 950system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses 951system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000035 # mshr miss rate for WriteReq accesses 952system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for demand accesses 953system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses 954system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses 955system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses 956system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 64478.038331 # average ReadReq mshr miss latency 957system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 64478.038331 # average ReadReq mshr miss latency 958system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71501.934553 # average WriteReq mshr miss latency 959system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71501.934553 # average WriteReq mshr miss latency 960system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68802.542894 # average overall mshr miss latency 961system.cpu.dcache.demand_avg_mshr_miss_latency::total 68802.542894 # average overall mshr miss latency 962system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68802.542894 # average overall mshr miss latency 963system.cpu.dcache.overall_avg_mshr_miss_latency::total 68802.542894 # average overall mshr miss latency 964system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 965 966---------- End Simulation Statistics ---------- 967