stats.txt revision 11680:b4d943429dc6
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.122178 # Number of seconds simulated 4sim_ticks 122177531500 # Number of ticks simulated 5final_tick 122177531500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 120262 # Simulator instruction rate (inst/s) 8host_op_rate 144388 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 53814187 # Simulator tick rate (ticks/s) 10host_mem_usage 292180 # Number of bytes of host memory used 11host_seconds 2270.36 # Real time elapsed on the host 12sim_insts 273037218 # Number of instructions simulated 13sim_ops 327811600 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.pwrStateResidencyTicks::UNDEFINED 122177531500 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.inst 1888192 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 14650048 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.l2cache.prefetcher 169280 # Number of bytes read from this memory 20system.physmem.bytes_read::total 16707520 # Number of bytes read from this memory 21system.physmem.bytes_inst_read::cpu.inst 1888192 # Number of instructions bytes read from this memory 22system.physmem.bytes_inst_read::total 1888192 # Number of instructions bytes read from this memory 23system.physmem.num_reads::cpu.inst 29503 # Number of read requests responded to by this memory 24system.physmem.num_reads::cpu.data 228907 # Number of read requests responded to by this memory 25system.physmem.num_reads::cpu.l2cache.prefetcher 2645 # Number of read requests responded to by this memory 26system.physmem.num_reads::total 261055 # Number of read requests responded to by this memory 27system.physmem.bw_read::cpu.inst 15454495 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_read::cpu.data 119907874 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::cpu.l2cache.prefetcher 1385525 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::total 136747893 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_inst_read::cpu.inst 15454495 # Instruction read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::total 15454495 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_total::cpu.inst 15454495 # Total bandwidth to/from this memory (bytes/s) 34system.physmem.bw_total::cpu.data 119907874 # Total bandwidth to/from this memory (bytes/s) 35system.physmem.bw_total::cpu.l2cache.prefetcher 1385525 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::total 136747893 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.readReqs 261056 # Number of read requests accepted 38system.physmem.writeReqs 0 # Number of write requests accepted 39system.physmem.readBursts 261056 # Number of DRAM read bursts, including those serviced by the write queue 40system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 41system.physmem.bytesReadDRAM 16707584 # Total number of bytes read from DRAM 42system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 43system.physmem.bytesWritten 0 # Total number of bytes written to DRAM 44system.physmem.bytesReadSys 16707584 # Total read bytes from the system interface side 45system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 46system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 47system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 48system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 49system.physmem.perBankRdBursts::0 1259 # Per bank write bursts 50system.physmem.perBankRdBursts::1 69992 # Per bank write bursts 51system.physmem.perBankRdBursts::2 1296 # Per bank write bursts 52system.physmem.perBankRdBursts::3 10759 # Per bank write bursts 53system.physmem.perBankRdBursts::4 42908 # Per bank write bursts 54system.physmem.perBankRdBursts::5 121819 # Per bank write bursts 55system.physmem.perBankRdBursts::6 160 # Per bank write bursts 56system.physmem.perBankRdBursts::7 257 # Per bank write bursts 57system.physmem.perBankRdBursts::8 228 # Per bank write bursts 58system.physmem.perBankRdBursts::9 562 # Per bank write bursts 59system.physmem.perBankRdBursts::10 7776 # Per bank write bursts 60system.physmem.perBankRdBursts::11 812 # Per bank write bursts 61system.physmem.perBankRdBursts::12 1213 # Per bank write bursts 62system.physmem.perBankRdBursts::13 743 # Per bank write bursts 63system.physmem.perBankRdBursts::14 662 # Per bank write bursts 64system.physmem.perBankRdBursts::15 610 # Per bank write bursts 65system.physmem.perBankWrBursts::0 0 # Per bank write bursts 66system.physmem.perBankWrBursts::1 0 # Per bank write bursts 67system.physmem.perBankWrBursts::2 0 # Per bank write bursts 68system.physmem.perBankWrBursts::3 0 # Per bank write bursts 69system.physmem.perBankWrBursts::4 0 # Per bank write bursts 70system.physmem.perBankWrBursts::5 0 # Per bank write bursts 71system.physmem.perBankWrBursts::6 0 # Per bank write bursts 72system.physmem.perBankWrBursts::7 0 # Per bank write bursts 73system.physmem.perBankWrBursts::8 0 # Per bank write bursts 74system.physmem.perBankWrBursts::9 0 # Per bank write bursts 75system.physmem.perBankWrBursts::10 0 # Per bank write bursts 76system.physmem.perBankWrBursts::11 0 # Per bank write bursts 77system.physmem.perBankWrBursts::12 0 # Per bank write bursts 78system.physmem.perBankWrBursts::13 0 # Per bank write bursts 79system.physmem.perBankWrBursts::14 0 # Per bank write bursts 80system.physmem.perBankWrBursts::15 0 # Per bank write bursts 81system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 82system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 83system.physmem.totGap 122177522000 # Total gap between requests 84system.physmem.readPktSize::0 0 # Read request sizes (log2) 85system.physmem.readPktSize::1 0 # Read request sizes (log2) 86system.physmem.readPktSize::2 0 # Read request sizes (log2) 87system.physmem.readPktSize::3 0 # Read request sizes (log2) 88system.physmem.readPktSize::4 0 # Read request sizes (log2) 89system.physmem.readPktSize::5 0 # Read request sizes (log2) 90system.physmem.readPktSize::6 261056 # Read request sizes (log2) 91system.physmem.writePktSize::0 0 # Write request sizes (log2) 92system.physmem.writePktSize::1 0 # Write request sizes (log2) 93system.physmem.writePktSize::2 0 # Write request sizes (log2) 94system.physmem.writePktSize::3 0 # Write request sizes (log2) 95system.physmem.writePktSize::4 0 # Write request sizes (log2) 96system.physmem.writePktSize::5 0 # Write request sizes (log2) 97system.physmem.writePktSize::6 0 # Write request sizes (log2) 98system.physmem.rdQLenPdf::0 204133 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::1 43349 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::2 12134 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::3 301 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::4 235 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::5 214 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::6 176 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::7 231 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::8 127 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::9 64 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::10 33 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::11 24 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::12 19 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::13 16 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 130system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 131system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 132system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 133system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 134system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 194system.physmem.bytesPerActivate::samples 67229 # Bytes accessed per row activation 195system.physmem.bytesPerActivate::mean 248.480388 # Bytes accessed per row activation 196system.physmem.bytesPerActivate::gmean 181.727737 # Bytes accessed per row activation 197system.physmem.bytesPerActivate::stdev 204.056429 # Bytes accessed per row activation 198system.physmem.bytesPerActivate::0-127 18253 27.15% 27.15% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::128-255 21438 31.89% 59.04% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::256-383 11486 17.08% 76.12% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::384-511 6691 9.95% 86.08% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::512-639 4636 6.90% 92.97% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::640-767 2199 3.27% 96.24% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::768-895 1378 2.05% 98.29% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::896-1023 426 0.63% 98.93% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::1024-1151 722 1.07% 100.00% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::total 67229 # Bytes accessed per row activation 208system.physmem.totQLat 4621160381 # Total ticks spent queuing 209system.physmem.totMemAccLat 9515960381 # Total ticks spent from burst creation until serviced by the DRAM 210system.physmem.totBusLat 1305280000 # Total ticks spent in databus transfers 211system.physmem.avgQLat 17701.80 # Average queueing delay per DRAM burst 212system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 213system.physmem.avgMemAccLat 36451.80 # Average memory access latency per DRAM burst 214system.physmem.avgRdBW 136.75 # Average DRAM read bandwidth in MiByte/s 215system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 216system.physmem.avgRdBWSys 136.75 # Average system read bandwidth in MiByte/s 217system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 218system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 219system.physmem.busUtil 1.07 # Data bus utilization in percentage 220system.physmem.busUtilRead 1.07 # Data bus utilization in percentage for reads 221system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 222system.physmem.avgRdQLen 1.60 # Average read queue length when enqueuing 223system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 224system.physmem.readRowHits 193817 # Number of row buffer hits during reads 225system.physmem.writeRowHits 0 # Number of row buffer hits during writes 226system.physmem.readRowHitRate 74.24 # Row buffer hit rate for reads 227system.physmem.writeRowHitRate nan # Row buffer hit rate for writes 228system.physmem.avgGap 468012.69 # Average gap between requests 229system.physmem.pageHitRate 74.24 # Row buffer hit rate, read and write combined 230system.physmem_0.actEnergy 445443180 # Energy for activate commands per rank (pJ) 231system.physmem_0.preEnergy 236747280 # Energy for precharge commands per rank (pJ) 232system.physmem_0.readEnergy 1773933000 # Energy for read commands per rank (pJ) 233system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) 234system.physmem_0.refreshEnergy 9531222480.000002 # Energy for refresh commands per rank (pJ) 235system.physmem_0.actBackEnergy 4632019500 # Energy for active background per rank (pJ) 236system.physmem_0.preBackEnergy 224464800 # Energy for precharge background per rank (pJ) 237system.physmem_0.actPowerDownEnergy 45099806190 # Energy for active power-down per rank (pJ) 238system.physmem_0.prePowerDownEnergy 3562907040 # Energy for precharge power-down per rank (pJ) 239system.physmem_0.selfRefreshEnergy 919525950 # Energy for self refresh per rank (pJ) 240system.physmem_0.totalEnergy 66426265230 # Total energy per rank (pJ) 241system.physmem_0.averagePower 543.686420 # Core power per rank (mW) 242system.physmem_0.totalIdleTime 111434381144 # Total Idle time Per DRAM Rank 243system.physmem_0.memoryStateTime::IDLE 154081000 # Time in different power states 244system.physmem_0.memoryStateTime::REF 4033332000 # Time in different power states 245system.physmem_0.memoryStateTime::SREF 3253133750 # Time in different power states 246system.physmem_0.memoryStateTime::PRE_PDN 9278182481 # Time in different power states 247system.physmem_0.memoryStateTime::ACT 6555604606 # Time in different power states 248system.physmem_0.memoryStateTime::ACT_PDN 98903197663 # Time in different power states 249system.physmem_1.actEnergy 34636140 # Energy for activate commands per rank (pJ) 250system.physmem_1.preEnergy 18382980 # Energy for precharge commands per rank (pJ) 251system.physmem_1.readEnergy 89999700 # Energy for read commands per rank (pJ) 252system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) 253system.physmem_1.refreshEnergy 3038165520.000000 # Energy for refresh commands per rank (pJ) 254system.physmem_1.actBackEnergy 716380560 # Energy for active background per rank (pJ) 255system.physmem_1.preBackEnergy 121415040 # Energy for precharge background per rank (pJ) 256system.physmem_1.actPowerDownEnergy 10108537890 # Energy for active power-down per rank (pJ) 257system.physmem_1.prePowerDownEnergy 3723173760 # Energy for precharge power-down per rank (pJ) 258system.physmem_1.selfRefreshEnergy 21583783695 # Energy for self refresh per rank (pJ) 259system.physmem_1.totalEnergy 39434924925 # Total energy per rank (pJ) 260system.physmem_1.averagePower 322.767403 # Core power per rank (mW) 261system.physmem_1.totalIdleTime 120289757500 # Total Idle time Per DRAM Rank 262system.physmem_1.memoryStateTime::IDLE 194586000 # Time in different power states 263system.physmem_1.memoryStateTime::REF 1289158000 # Time in different power states 264system.physmem_1.memoryStateTime::SREF 88425719250 # Time in different power states 265system.physmem_1.memoryStateTime::PRE_PDN 9695988513 # Time in different power states 266system.physmem_1.memoryStateTime::ACT 404030000 # Time in different power states 267system.physmem_1.memoryStateTime::ACT_PDN 22168049737 # Time in different power states 268system.pwrStateResidencyTicks::UNDEFINED 122177531500 # Cumulative time (in ticks) in various power states 269system.cpu.branchPred.lookups 35971486 # Number of BP lookups 270system.cpu.branchPred.condPredicted 19267078 # Number of conditional branches predicted 271system.cpu.branchPred.condIncorrect 984296 # Number of conditional branches incorrect 272system.cpu.branchPred.BTBLookups 17894197 # Number of BTB lookups 273system.cpu.branchPred.BTBHits 13923261 # Number of BTB hits 274system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 275system.cpu.branchPred.BTBHitPct 77.808806 # BTB Hit Percentage 276system.cpu.branchPred.usedRAS 6951889 # Number of times the RAS was used to get a target. 277system.cpu.branchPred.RASInCorrect 4417 # Number of incorrect RAS predictions. 278system.cpu.branchPred.indirectLookups 2517219 # Number of indirect predictor lookups. 279system.cpu.branchPred.indirectHits 2473355 # Number of indirect target hits. 280system.cpu.branchPred.indirectMisses 43864 # Number of indirect misses. 281system.cpu.branchPredindirectMispredicted 128904 # Number of mispredicted indirect branches. 282system.cpu_clk_domain.clock 500 # Clock period in ticks 283system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 122177531500 # Cumulative time (in ticks) in various power states 284system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 285system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 286system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 287system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 288system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 289system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 290system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 291system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 292system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 293system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 294system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 295system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 296system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 297system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 298system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 299system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 300system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 301system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 302system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 303system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 304system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 305system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 306system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 307system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 308system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 309system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 310system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 311system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 312system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 313system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 122177531500 # Cumulative time (in ticks) in various power states 314system.cpu.dtb.walker.walks 0 # Table walker walks requested 315system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 316system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 317system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 318system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 319system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 320system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 321system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 322system.cpu.dtb.inst_hits 0 # ITB inst hits 323system.cpu.dtb.inst_misses 0 # ITB inst misses 324system.cpu.dtb.read_hits 0 # DTB read hits 325system.cpu.dtb.read_misses 0 # DTB read misses 326system.cpu.dtb.write_hits 0 # DTB write hits 327system.cpu.dtb.write_misses 0 # DTB write misses 328system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 329system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 330system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 331system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 332system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 333system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 334system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 335system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 336system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 337system.cpu.dtb.read_accesses 0 # DTB read accesses 338system.cpu.dtb.write_accesses 0 # DTB write accesses 339system.cpu.dtb.inst_accesses 0 # ITB inst accesses 340system.cpu.dtb.hits 0 # DTB hits 341system.cpu.dtb.misses 0 # DTB misses 342system.cpu.dtb.accesses 0 # DTB accesses 343system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 122177531500 # Cumulative time (in ticks) in various power states 344system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 345system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 346system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 347system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 348system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 349system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 350system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 351system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 352system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 353system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 354system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 355system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 356system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 357system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 358system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 359system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 360system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 361system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 362system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 363system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 364system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 365system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 366system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 367system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 368system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 369system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 370system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 371system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 372system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 373system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 122177531500 # Cumulative time (in ticks) in various power states 374system.cpu.itb.walker.walks 0 # Table walker walks requested 375system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 376system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 377system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 378system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 379system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 380system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 381system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 382system.cpu.itb.inst_hits 0 # ITB inst hits 383system.cpu.itb.inst_misses 0 # ITB inst misses 384system.cpu.itb.read_hits 0 # DTB read hits 385system.cpu.itb.read_misses 0 # DTB read misses 386system.cpu.itb.write_hits 0 # DTB write hits 387system.cpu.itb.write_misses 0 # DTB write misses 388system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 389system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 390system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 391system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 392system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 393system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 394system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 395system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 396system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 397system.cpu.itb.read_accesses 0 # DTB read accesses 398system.cpu.itb.write_accesses 0 # DTB write accesses 399system.cpu.itb.inst_accesses 0 # ITB inst accesses 400system.cpu.itb.hits 0 # DTB hits 401system.cpu.itb.misses 0 # DTB misses 402system.cpu.itb.accesses 0 # DTB accesses 403system.cpu.workload.num_syscalls 191 # Number of system calls 404system.cpu.pwrStateResidencyTicks::ON 122177531500 # Cumulative time (in ticks) in various power states 405system.cpu.numCycles 244355064 # number of cpu cycles simulated 406system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 407system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 408system.cpu.fetch.icacheStallCycles 12854090 # Number of cycles fetch is stalled on an Icache miss 409system.cpu.fetch.Insts 309386185 # Number of instructions fetch has processed 410system.cpu.fetch.Branches 35971486 # Number of branches that fetch encountered 411system.cpu.fetch.predictedBranches 23348505 # Number of branches that fetch has predicted taken 412system.cpu.fetch.Cycles 227028352 # Number of cycles fetch has run and was not squashing or blocked 413system.cpu.fetch.SquashCycles 1990311 # Number of cycles fetch has spent squashing 414system.cpu.fetch.MiscStallCycles 1601 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 415system.cpu.fetch.PendingTrapStallCycles 93 # Number of stall cycles due to pending traps 416system.cpu.fetch.IcacheWaitRetryStallCycles 3162 # Number of stall cycles due to full MSHR 417system.cpu.fetch.CacheLines 82203694 # Number of cache lines fetched 418system.cpu.fetch.IcacheSquashes 34298 # Number of outstanding Icache misses that were squashed 419system.cpu.fetch.rateDist::samples 240882453 # Number of instructions fetched each cycle (Total) 420system.cpu.fetch.rateDist::mean 1.544883 # Number of instructions fetched each cycle (Total) 421system.cpu.fetch.rateDist::stdev 1.296552 # Number of instructions fetched each cycle (Total) 422system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 423system.cpu.fetch.rateDist::0 80675861 33.49% 33.49% # Number of instructions fetched each cycle (Total) 424system.cpu.fetch.rateDist::1 40201773 16.69% 50.18% # Number of instructions fetched each cycle (Total) 425system.cpu.fetch.rateDist::2 28081031 11.66% 61.84% # Number of instructions fetched each cycle (Total) 426system.cpu.fetch.rateDist::3 91923788 38.16% 100.00% # Number of instructions fetched each cycle (Total) 427system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 428system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 429system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) 430system.cpu.fetch.rateDist::total 240882453 # Number of instructions fetched each cycle (Total) 431system.cpu.fetch.branchRate 0.147210 # Number of branch fetches per cycle 432system.cpu.fetch.rate 1.266134 # Number of inst fetches per cycle 433system.cpu.decode.IdleCycles 26812973 # Number of cycles decode is idle 434system.cpu.decode.BlockedCycles 90710528 # Number of cycles decode is blocked 435system.cpu.decode.RunCycles 98252382 # Number of cycles decode is running 436system.cpu.decode.UnblockCycles 24245286 # Number of cycles decode is unblocking 437system.cpu.decode.SquashCycles 861284 # Number of cycles decode is squashing 438system.cpu.decode.BranchResolved 6686689 # Number of times decode resolved a branch 439system.cpu.decode.BranchMispred 134210 # Number of times decode detected a branch misprediction 440system.cpu.decode.DecodedInsts 348538542 # Number of instructions handled by decode 441system.cpu.decode.SquashedInsts 3411137 # Number of squashed instructions handled by decode 442system.cpu.rename.SquashCycles 861284 # Number of cycles rename is squashing 443system.cpu.rename.IdleCycles 43083632 # Number of cycles rename is idle 444system.cpu.rename.BlockCycles 37000044 # Number of cycles rename is blocking 445system.cpu.rename.serializeStallCycles 289266 # count of cycles rename stalled for serializing inst 446system.cpu.rename.RunCycles 105269732 # Number of cycles rename is running 447system.cpu.rename.UnblockCycles 54378495 # Number of cycles rename is unblocking 448system.cpu.rename.RenamedInsts 344597413 # Number of instructions processed by rename 449system.cpu.rename.SquashedInsts 1451618 # Number of squashed instructions processed by rename 450system.cpu.rename.ROBFullEvents 7112089 # Number of times rename has blocked due to ROB full 451system.cpu.rename.IQFullEvents 85489 # Number of times rename has blocked due to IQ full 452system.cpu.rename.LQFullEvents 7460814 # Number of times rename has blocked due to LQ full 453system.cpu.rename.SQFullEvents 27903739 # Number of times rename has blocked due to SQ full 454system.cpu.rename.FullRegisterEvents 3277402 # Number of times there has been no free registers 455system.cpu.rename.RenamedOperands 394869828 # Number of destination operands rename has renamed 456system.cpu.rename.RenameLookups 2218091968 # Number of register rename lookups that rename has made 457system.cpu.rename.int_rename_lookups 335911643 # Number of integer rename lookups 458system.cpu.rename.fp_rename_lookups 192912802 # Number of floating rename lookups 459system.cpu.rename.CommittedMaps 372230048 # Number of HB maps that are committed 460system.cpu.rename.UndoneMaps 22639780 # Number of HB maps that are undone due to squashing 461system.cpu.rename.serializingInsts 11606 # count of serializing insts renamed 462system.cpu.rename.tempSerializingInsts 11574 # count of temporary serializing insts renamed 463system.cpu.rename.skidInsts 57375410 # count of insts added to the skid buffer 464system.cpu.memDep0.insertedLoads 89984183 # Number of loads inserted to the mem dependence unit. 465system.cpu.memDep0.insertedStores 84392474 # Number of stores inserted to the mem dependence unit. 466system.cpu.memDep0.conflictingLoads 1977179 # Number of conflicting loads. 467system.cpu.memDep0.conflictingStores 1898949 # Number of conflicting stores. 468system.cpu.iq.iqInstsAdded 343275804 # Number of instructions added to the IQ (excludes non-spec) 469system.cpu.iq.iqNonSpecInstsAdded 22622 # Number of non-speculative instructions added to the IQ 470system.cpu.iq.iqInstsIssued 339466020 # Number of instructions issued 471system.cpu.iq.iqSquashedInstsIssued 967573 # Number of squashed instructions issued 472system.cpu.iq.iqSquashedInstsExamined 15486826 # Number of squashed instructions iterated over during squash; mainly for profiling 473system.cpu.iq.iqSquashedOperandsExamined 37253539 # Number of squashed operands that are examined and possibly removed from graph 474system.cpu.iq.iqSquashedNonSpecRemoved 502 # Number of squashed non-spec instructions that were removed 475system.cpu.iq.issued_per_cycle::samples 240882453 # Number of insts issued each cycle 476system.cpu.iq.issued_per_cycle::mean 1.409260 # Number of insts issued each cycle 477system.cpu.iq.issued_per_cycle::stdev 1.140571 # Number of insts issued each cycle 478system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 479system.cpu.iq.issued_per_cycle::0 60724616 25.21% 25.21% # Number of insts issued each cycle 480system.cpu.iq.issued_per_cycle::1 76160793 31.62% 56.83% # Number of insts issued each cycle 481system.cpu.iq.issued_per_cycle::2 59430978 24.67% 81.50% # Number of insts issued each cycle 482system.cpu.iq.issued_per_cycle::3 34569007 14.35% 95.85% # Number of insts issued each cycle 483system.cpu.iq.issued_per_cycle::4 9283720 3.85% 99.70% # Number of insts issued each cycle 484system.cpu.iq.issued_per_cycle::5 678664 0.28% 99.99% # Number of insts issued each cycle 485system.cpu.iq.issued_per_cycle::6 34675 0.01% 100.00% # Number of insts issued each cycle 486system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 487system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 488system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 489system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 490system.cpu.iq.issued_per_cycle::max_value 6 # Number of insts issued each cycle 491system.cpu.iq.issued_per_cycle::total 240882453 # Number of insts issued each cycle 492system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 493system.cpu.iq.fu_full::IntAlu 9218221 7.75% 7.75% # attempts to use FU when none available 494system.cpu.iq.fu_full::IntMult 7322 0.01% 7.76% # attempts to use FU when none available 495system.cpu.iq.fu_full::IntDiv 0 0.00% 7.76% # attempts to use FU when none available 496system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.76% # attempts to use FU when none available 497system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.76% # attempts to use FU when none available 498system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.76% # attempts to use FU when none available 499system.cpu.iq.fu_full::FloatMult 0 0.00% 7.76% # attempts to use FU when none available 500system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.76% # attempts to use FU when none available 501system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.76% # attempts to use FU when none available 502system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.76% # attempts to use FU when none available 503system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.76% # attempts to use FU when none available 504system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.76% # attempts to use FU when none available 505system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.76% # attempts to use FU when none available 506system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.76% # attempts to use FU when none available 507system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.76% # attempts to use FU when none available 508system.cpu.iq.fu_full::SimdMult 0 0.00% 7.76% # attempts to use FU when none available 509system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.76% # attempts to use FU when none available 510system.cpu.iq.fu_full::SimdShift 0 0.00% 7.76% # attempts to use FU when none available 511system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.76% # attempts to use FU when none available 512system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.76% # attempts to use FU when none available 513system.cpu.iq.fu_full::SimdFloatAdd 238834 0.20% 7.96% # attempts to use FU when none available 514system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.96% # attempts to use FU when none available 515system.cpu.iq.fu_full::SimdFloatCmp 138891 0.12% 8.08% # attempts to use FU when none available 516system.cpu.iq.fu_full::SimdFloatCvt 70679 0.06% 8.14% # attempts to use FU when none available 517system.cpu.iq.fu_full::SimdFloatDiv 68365 0.06% 8.19% # attempts to use FU when none available 518system.cpu.iq.fu_full::SimdFloatMisc 640804 0.54% 8.73% # attempts to use FU when none available 519system.cpu.iq.fu_full::SimdFloatMult 296732 0.25% 8.98% # attempts to use FU when none available 520system.cpu.iq.fu_full::SimdFloatMultAcc 541759 0.46% 9.44% # attempts to use FU when none available 521system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.44% # attempts to use FU when none available 522system.cpu.iq.fu_full::MemRead 51504063 43.31% 52.75% # attempts to use FU when none available 523system.cpu.iq.fu_full::MemWrite 56187426 47.25% 100.00% # attempts to use FU when none available 524system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 525system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 526system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 527system.cpu.iq.FU_type_0::IntAlu 108184064 31.87% 31.87% # Type of FU issued 528system.cpu.iq.FU_type_0::IntMult 2148340 0.63% 32.50% # Type of FU issued 529system.cpu.iq.FU_type_0::IntDiv 0 0.00% 32.50% # Type of FU issued 530system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 32.50% # Type of FU issued 531system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 32.50% # Type of FU issued 532system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 32.50% # Type of FU issued 533system.cpu.iq.FU_type_0::FloatMult 0 0.00% 32.50% # Type of FU issued 534system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 32.50% # Type of FU issued 535system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 32.50% # Type of FU issued 536system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 32.50% # Type of FU issued 537system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 32.50% # Type of FU issued 538system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 32.50% # Type of FU issued 539system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 32.50% # Type of FU issued 540system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 32.50% # Type of FU issued 541system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 32.50% # Type of FU issued 542system.cpu.iq.FU_type_0::SimdMult 0 0.00% 32.50% # Type of FU issued 543system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 32.50% # Type of FU issued 544system.cpu.iq.FU_type_0::SimdShift 0 0.00% 32.50% # Type of FU issued 545system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 32.50% # Type of FU issued 546system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 32.50% # Type of FU issued 547system.cpu.iq.FU_type_0::SimdFloatAdd 6792701 2.00% 34.50% # Type of FU issued 548system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 34.50% # Type of FU issued 549system.cpu.iq.FU_type_0::SimdFloatCmp 8634973 2.54% 37.05% # Type of FU issued 550system.cpu.iq.FU_type_0::SimdFloatCvt 3210554 0.95% 37.99% # Type of FU issued 551system.cpu.iq.FU_type_0::SimdFloatDiv 1592986 0.47% 38.46% # Type of FU issued 552system.cpu.iq.FU_type_0::SimdFloatMisc 20863316 6.15% 44.61% # Type of FU issued 553system.cpu.iq.FU_type_0::SimdFloatMult 7179113 2.11% 46.72% # Type of FU issued 554system.cpu.iq.FU_type_0::SimdFloatMultAcc 7141894 2.10% 48.83% # Type of FU issued 555system.cpu.iq.FU_type_0::SimdFloatSqrt 175297 0.05% 48.88% # Type of FU issued 556system.cpu.iq.FU_type_0::MemRead 90024187 26.52% 75.40% # Type of FU issued 557system.cpu.iq.FU_type_0::MemWrite 83518595 24.60% 100.00% # Type of FU issued 558system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 559system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 560system.cpu.iq.FU_type_0::total 339466020 # Type of FU issued 561system.cpu.iq.rate 1.389233 # Inst issue rate 562system.cpu.iq.fu_busy_cnt 118913096 # FU busy when requested 563system.cpu.iq.fu_busy_rate 0.350295 # FU busy rate (busy events/executed inst) 564system.cpu.iq.int_inst_queue_reads 756328552 # Number of integer instruction queue reads 565system.cpu.iq.int_inst_queue_writes 235151256 # Number of integer instruction queue writes 566system.cpu.iq.int_inst_queue_wakeup_accesses 219171646 # Number of integer instruction queue wakeup accesses 567system.cpu.iq.fp_inst_queue_reads 283366610 # Number of floating instruction queue reads 568system.cpu.iq.fp_inst_queue_writes 123646075 # Number of floating instruction queue writes 569system.cpu.iq.fp_inst_queue_wakeup_accesses 116917582 # Number of floating instruction queue wakeup accesses 570system.cpu.iq.int_alu_accesses 293624810 # Number of integer alu accesses 571system.cpu.iq.fp_alu_accesses 164754306 # Number of floating point alu accesses 572system.cpu.iew.lsq.thread0.forwLoads 5408815 # Number of loads that had data forwarded from stores 573system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 574system.cpu.iew.lsq.thread0.squashedLoads 4251908 # Number of loads squashed 575system.cpu.iew.lsq.thread0.ignoredResponses 7378 # Number of memory responses ignored because the instruction is squashed 576system.cpu.iew.lsq.thread0.memOrderViolation 12082 # Number of memory ordering violations 577system.cpu.iew.lsq.thread0.squashedStores 2016857 # Number of stores squashed 578system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 579system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 580system.cpu.iew.lsq.thread0.rescheduledLoads 126936 # Number of loads that were rescheduled 581system.cpu.iew.lsq.thread0.cacheBlocked 613330 # Number of times an access to memory failed due to the cache being blocked 582system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 583system.cpu.iew.iewSquashCycles 861284 # Number of cycles IEW is squashing 584system.cpu.iew.iewBlockCycles 1350225 # Number of cycles IEW is blocking 585system.cpu.iew.iewUnblockCycles 1508994 # Number of cycles IEW is unblocking 586system.cpu.iew.iewDispatchedInsts 343299844 # Number of instructions dispatched to IQ 587system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch 588system.cpu.iew.iewDispLoadInsts 89984183 # Number of dispatched load instructions 589system.cpu.iew.iewDispStoreInsts 84392474 # Number of dispatched store instructions 590system.cpu.iew.iewDispNonSpecInsts 11589 # Number of dispatched non-speculative instructions 591system.cpu.iew.iewIQFullEvents 7652 # Number of times the IQ has become full, causing a stall 592system.cpu.iew.iewLSQFullEvents 1502014 # Number of times the LSQ has become full, causing a stall 593system.cpu.iew.memOrderViolationEvents 12082 # Number of memory order violations 594system.cpu.iew.predictedTakenIncorrect 438026 # Number of branches that were predicted taken incorrectly 595system.cpu.iew.predictedNotTakenIncorrect 454508 # Number of branches that were predicted not taken incorrectly 596system.cpu.iew.branchMispredicts 892534 # Number of branch mispredicts detected at execute 597system.cpu.iew.iewExecutedInsts 337437017 # Number of executed instructions 598system.cpu.iew.iewExecLoadInsts 89435625 # Number of load instructions executed 599system.cpu.iew.iewExecSquashedInsts 2029003 # Number of squashed instructions skipped in execute 600system.cpu.iew.exec_swp 0 # number of swp insts executed 601system.cpu.iew.exec_nop 1418 # number of nop insts executed 602system.cpu.iew.exec_refs 172563316 # number of memory reference insts executed 603system.cpu.iew.exec_branches 31556143 # Number of branches executed 604system.cpu.iew.exec_stores 83127691 # Number of stores executed 605system.cpu.iew.exec_rate 1.380929 # Inst execution rate 606system.cpu.iew.wb_sent 336235772 # cumulative count of insts sent to commit 607system.cpu.iew.wb_count 336089228 # cumulative count of insts written-back 608system.cpu.iew.wb_producers 151786231 # num instructions producing a value 609system.cpu.iew.wb_consumers 263562514 # num instructions consuming a value 610system.cpu.iew.wb_rate 1.375413 # insts written-back per cycle 611system.cpu.iew.wb_fanout 0.575902 # average fanout of values written-back 612system.cpu.commit.commitSquashedInsts 14164375 # The number of squashed insts skipped by commit 613system.cpu.commit.commitNonSpecStalls 22120 # The number of times commit has been forced to stall to communicate backwards 614system.cpu.commit.branchMispredicts 850425 # The number of times a branch was mispredicted 615system.cpu.commit.committed_per_cycle::samples 238692959 # Number of insts commited each cycle 616system.cpu.commit.committed_per_cycle::mean 1.373364 # Number of insts commited each cycle 617system.cpu.commit.committed_per_cycle::stdev 2.035708 # Number of insts commited each cycle 618system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 619system.cpu.commit.committed_per_cycle::0 107534765 45.05% 45.05% # Number of insts commited each cycle 620system.cpu.commit.committed_per_cycle::1 67583251 28.31% 73.37% # Number of insts commited each cycle 621system.cpu.commit.committed_per_cycle::2 20880103 8.75% 82.11% # Number of insts commited each cycle 622system.cpu.commit.committed_per_cycle::3 13256001 5.55% 87.67% # Number of insts commited each cycle 623system.cpu.commit.committed_per_cycle::4 8658859 3.63% 91.29% # Number of insts commited each cycle 624system.cpu.commit.committed_per_cycle::5 4515867 1.89% 93.19% # Number of insts commited each cycle 625system.cpu.commit.committed_per_cycle::6 3014415 1.26% 94.45% # Number of insts commited each cycle 626system.cpu.commit.committed_per_cycle::7 2598093 1.09% 95.54% # Number of insts commited each cycle 627system.cpu.commit.committed_per_cycle::8 10651605 4.46% 100.00% # Number of insts commited each cycle 628system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 629system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 630system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 631system.cpu.commit.committed_per_cycle::total 238692959 # Number of insts commited each cycle 632system.cpu.commit.committedInsts 273037830 # Number of instructions committed 633system.cpu.commit.committedOps 327812212 # Number of ops (including micro ops) committed 634system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 635system.cpu.commit.refs 168107892 # Number of memory references committed 636system.cpu.commit.loads 85732275 # Number of loads committed 637system.cpu.commit.membars 11033 # Number of memory barriers committed 638system.cpu.commit.branches 30563525 # Number of branches committed 639system.cpu.commit.fp_insts 114216705 # Number of committed floating point instructions. 640system.cpu.commit.int_insts 258331703 # Number of committed integer instructions. 641system.cpu.commit.function_calls 6225114 # Number of function calls committed. 642system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 643system.cpu.commit.op_class_0::IntAlu 104312485 31.82% 31.82% # Class of committed instruction 644system.cpu.commit.op_class_0::IntMult 2145917 0.65% 32.48% # Class of committed instruction 645system.cpu.commit.op_class_0::IntDiv 0 0.00% 32.48% # Class of committed instruction 646system.cpu.commit.op_class_0::FloatAdd 0 0.00% 32.48% # Class of committed instruction 647system.cpu.commit.op_class_0::FloatCmp 0 0.00% 32.48% # Class of committed instruction 648system.cpu.commit.op_class_0::FloatCvt 0 0.00% 32.48% # Class of committed instruction 649system.cpu.commit.op_class_0::FloatMult 0 0.00% 32.48% # Class of committed instruction 650system.cpu.commit.op_class_0::FloatDiv 0 0.00% 32.48% # Class of committed instruction 651system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 32.48% # Class of committed instruction 652system.cpu.commit.op_class_0::SimdAdd 0 0.00% 32.48% # Class of committed instruction 653system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 32.48% # Class of committed instruction 654system.cpu.commit.op_class_0::SimdAlu 0 0.00% 32.48% # Class of committed instruction 655system.cpu.commit.op_class_0::SimdCmp 0 0.00% 32.48% # Class of committed instruction 656system.cpu.commit.op_class_0::SimdCvt 0 0.00% 32.48% # Class of committed instruction 657system.cpu.commit.op_class_0::SimdMisc 0 0.00% 32.48% # Class of committed instruction 658system.cpu.commit.op_class_0::SimdMult 0 0.00% 32.48% # Class of committed instruction 659system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 32.48% # Class of committed instruction 660system.cpu.commit.op_class_0::SimdShift 0 0.00% 32.48% # Class of committed instruction 661system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 32.48% # Class of committed instruction 662system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 32.48% # Class of committed instruction 663system.cpu.commit.op_class_0::SimdFloatAdd 6594343 2.01% 34.49% # Class of committed instruction 664system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 34.49% # Class of committed instruction 665system.cpu.commit.op_class_0::SimdFloatCmp 7943502 2.42% 36.91% # Class of committed instruction 666system.cpu.commit.op_class_0::SimdFloatCvt 3118180 0.95% 37.86% # Class of committed instruction 667system.cpu.commit.op_class_0::SimdFloatDiv 1563217 0.48% 38.34% # Class of committed instruction 668system.cpu.commit.op_class_0::SimdFloatMisc 19652356 6.00% 44.33% # Class of committed instruction 669system.cpu.commit.op_class_0::SimdFloatMult 7136937 2.18% 46.51% # Class of committed instruction 670system.cpu.commit.op_class_0::SimdFloatMultAcc 7062098 2.15% 48.66% # Class of committed instruction 671system.cpu.commit.op_class_0::SimdFloatSqrt 175285 0.05% 48.72% # Class of committed instruction 672system.cpu.commit.op_class_0::MemRead 85732275 26.15% 74.87% # Class of committed instruction 673system.cpu.commit.op_class_0::MemWrite 82375617 25.13% 100.00% # Class of committed instruction 674system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 675system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 676system.cpu.commit.op_class_0::total 327812212 # Class of committed instruction 677system.cpu.commit.bw_lim_events 10651605 # number cycles where commit BW limit reached 678system.cpu.rob.rob_reads 570015418 # The number of ROB reads 679system.cpu.rob.rob_writes 686144847 # The number of ROB writes 680system.cpu.timesIdled 39403 # Number of times that the entire CPU went into an idle state and unscheduled itself 681system.cpu.idleCycles 3472611 # Total number of cycles that the CPU has spent unscheduled due to idling 682system.cpu.committedInsts 273037218 # Number of Instructions Simulated 683system.cpu.committedOps 327811600 # Number of Ops (including micro ops) Simulated 684system.cpu.cpi 0.894951 # CPI: Cycles Per Instruction 685system.cpu.cpi_total 0.894951 # CPI: Total CPI of All Threads 686system.cpu.ipc 1.117379 # IPC: Instructions Per Cycle 687system.cpu.ipc_total 1.117379 # IPC: Total IPC of All Threads 688system.cpu.int_regfile_reads 325163205 # number of integer regfile reads 689system.cpu.int_regfile_writes 134094196 # number of integer regfile writes 690system.cpu.fp_regfile_reads 186638267 # number of floating regfile reads 691system.cpu.fp_regfile_writes 131663703 # number of floating regfile writes 692system.cpu.cc_regfile_reads 1279409265 # number of cc regfile reads 693system.cpu.cc_regfile_writes 80058845 # number of cc regfile writes 694system.cpu.misc_regfile_reads 1056731782 # number of misc regfile reads 695system.cpu.misc_regfile_writes 34421755 # number of misc regfile writes 696system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 122177531500 # Cumulative time (in ticks) in various power states 697system.cpu.dcache.tags.replacements 1542799 # number of replacements 698system.cpu.dcache.tags.tagsinuse 511.841241 # Cycle average of tags in use 699system.cpu.dcache.tags.total_refs 162053309 # Total number of references to valid blocks. 700system.cpu.dcache.tags.sampled_refs 1543311 # Sample count of references to valid blocks. 701system.cpu.dcache.tags.avg_refs 105.003664 # Average number of references to valid blocks. 702system.cpu.dcache.tags.warmup_cycle 91635000 # Cycle when the warmup percentage was hit. 703system.cpu.dcache.tags.occ_blocks::cpu.data 511.841241 # Average occupied blocks per requestor 704system.cpu.dcache.tags.occ_percent::cpu.data 0.999690 # Average percentage of cache occupancy 705system.cpu.dcache.tags.occ_percent::total 0.999690 # Average percentage of cache occupancy 706system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 707system.cpu.dcache.tags.age_task_id_blocks_1024::0 109 # Occupied blocks per task id 708system.cpu.dcache.tags.age_task_id_blocks_1024::1 311 # Occupied blocks per task id 709system.cpu.dcache.tags.age_task_id_blocks_1024::2 91 # Occupied blocks per task id 710system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id 711system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 712system.cpu.dcache.tags.tag_accesses 333480485 # Number of tag accesses 713system.cpu.dcache.tags.data_accesses 333480485 # Number of data accesses 714system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 122177531500 # Cumulative time (in ticks) in various power states 715system.cpu.dcache.ReadReq_hits::cpu.data 81040424 # number of ReadReq hits 716system.cpu.dcache.ReadReq_hits::total 81040424 # number of ReadReq hits 717system.cpu.dcache.WriteReq_hits::cpu.data 80921391 # number of WriteReq hits 718system.cpu.dcache.WriteReq_hits::total 80921391 # number of WriteReq hits 719system.cpu.dcache.SoftPFReq_hits::cpu.data 69631 # number of SoftPFReq hits 720system.cpu.dcache.SoftPFReq_hits::total 69631 # number of SoftPFReq hits 721system.cpu.dcache.LoadLockedReq_hits::cpu.data 10908 # number of LoadLockedReq hits 722system.cpu.dcache.LoadLockedReq_hits::total 10908 # number of LoadLockedReq hits 723system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits 724system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits 725system.cpu.dcache.demand_hits::cpu.data 161961815 # number of demand (read+write) hits 726system.cpu.dcache.demand_hits::total 161961815 # number of demand (read+write) hits 727system.cpu.dcache.overall_hits::cpu.data 162031446 # number of overall hits 728system.cpu.dcache.overall_hits::total 162031446 # number of overall hits 729system.cpu.dcache.ReadReq_misses::cpu.data 2784008 # number of ReadReq misses 730system.cpu.dcache.ReadReq_misses::total 2784008 # number of ReadReq misses 731system.cpu.dcache.WriteReq_misses::cpu.data 1131308 # number of WriteReq misses 732system.cpu.dcache.WriteReq_misses::total 1131308 # number of WriteReq misses 733system.cpu.dcache.SoftPFReq_misses::cpu.data 18 # number of SoftPFReq misses 734system.cpu.dcache.SoftPFReq_misses::total 18 # number of SoftPFReq misses 735system.cpu.dcache.LoadLockedReq_misses::cpu.data 4 # number of LoadLockedReq misses 736system.cpu.dcache.LoadLockedReq_misses::total 4 # number of LoadLockedReq misses 737system.cpu.dcache.demand_misses::cpu.data 3915316 # number of demand (read+write) misses 738system.cpu.dcache.demand_misses::total 3915316 # number of demand (read+write) misses 739system.cpu.dcache.overall_misses::cpu.data 3915334 # number of overall misses 740system.cpu.dcache.overall_misses::total 3915334 # number of overall misses 741system.cpu.dcache.ReadReq_miss_latency::cpu.data 47872980500 # number of ReadReq miss cycles 742system.cpu.dcache.ReadReq_miss_latency::total 47872980500 # number of ReadReq miss cycles 743system.cpu.dcache.WriteReq_miss_latency::cpu.data 9172353414 # number of WriteReq miss cycles 744system.cpu.dcache.WriteReq_miss_latency::total 9172353414 # number of WriteReq miss cycles 745system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 194000 # number of LoadLockedReq miss cycles 746system.cpu.dcache.LoadLockedReq_miss_latency::total 194000 # number of LoadLockedReq miss cycles 747system.cpu.dcache.demand_miss_latency::cpu.data 57045333914 # number of demand (read+write) miss cycles 748system.cpu.dcache.demand_miss_latency::total 57045333914 # number of demand (read+write) miss cycles 749system.cpu.dcache.overall_miss_latency::cpu.data 57045333914 # number of overall miss cycles 750system.cpu.dcache.overall_miss_latency::total 57045333914 # number of overall miss cycles 751system.cpu.dcache.ReadReq_accesses::cpu.data 83824432 # number of ReadReq accesses(hits+misses) 752system.cpu.dcache.ReadReq_accesses::total 83824432 # number of ReadReq accesses(hits+misses) 753system.cpu.dcache.WriteReq_accesses::cpu.data 82052699 # number of WriteReq accesses(hits+misses) 754system.cpu.dcache.WriteReq_accesses::total 82052699 # number of WriteReq accesses(hits+misses) 755system.cpu.dcache.SoftPFReq_accesses::cpu.data 69649 # number of SoftPFReq accesses(hits+misses) 756system.cpu.dcache.SoftPFReq_accesses::total 69649 # number of SoftPFReq accesses(hits+misses) 757system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10912 # number of LoadLockedReq accesses(hits+misses) 758system.cpu.dcache.LoadLockedReq_accesses::total 10912 # number of LoadLockedReq accesses(hits+misses) 759system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses) 760system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) 761system.cpu.dcache.demand_accesses::cpu.data 165877131 # number of demand (read+write) accesses 762system.cpu.dcache.demand_accesses::total 165877131 # number of demand (read+write) accesses 763system.cpu.dcache.overall_accesses::cpu.data 165946780 # number of overall (read+write) accesses 764system.cpu.dcache.overall_accesses::total 165946780 # number of overall (read+write) accesses 765system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.033212 # miss rate for ReadReq accesses 766system.cpu.dcache.ReadReq_miss_rate::total 0.033212 # miss rate for ReadReq accesses 767system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013788 # miss rate for WriteReq accesses 768system.cpu.dcache.WriteReq_miss_rate::total 0.013788 # miss rate for WriteReq accesses 769system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000258 # miss rate for SoftPFReq accesses 770system.cpu.dcache.SoftPFReq_miss_rate::total 0.000258 # miss rate for SoftPFReq accesses 771system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000367 # miss rate for LoadLockedReq accesses 772system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000367 # miss rate for LoadLockedReq accesses 773system.cpu.dcache.demand_miss_rate::cpu.data 0.023604 # miss rate for demand accesses 774system.cpu.dcache.demand_miss_rate::total 0.023604 # miss rate for demand accesses 775system.cpu.dcache.overall_miss_rate::cpu.data 0.023594 # miss rate for overall accesses 776system.cpu.dcache.overall_miss_rate::total 0.023594 # miss rate for overall accesses 777system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17195.705077 # average ReadReq miss latency 778system.cpu.dcache.ReadReq_avg_miss_latency::total 17195.705077 # average ReadReq miss latency 779system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 8107.742024 # average WriteReq miss latency 780system.cpu.dcache.WriteReq_avg_miss_latency::total 8107.742024 # average WriteReq miss latency 781system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 48500 # average LoadLockedReq miss latency 782system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 48500 # average LoadLockedReq miss latency 783system.cpu.dcache.demand_avg_miss_latency::cpu.data 14569.790513 # average overall miss latency 784system.cpu.dcache.demand_avg_miss_latency::total 14569.790513 # average overall miss latency 785system.cpu.dcache.overall_avg_miss_latency::cpu.data 14569.723532 # average overall miss latency 786system.cpu.dcache.overall_avg_miss_latency::total 14569.723532 # average overall miss latency 787system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 788system.cpu.dcache.blocked_cycles::no_targets 1090477 # number of cycles access was blocked 789system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 790system.cpu.dcache.blocked::no_targets 136210 # number of cycles access was blocked 791system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 792system.cpu.dcache.avg_blocked_cycles::no_targets 8.005851 # average number of cycles each access was blocked 793system.cpu.dcache.writebacks::writebacks 1542799 # number of writebacks 794system.cpu.dcache.writebacks::total 1542799 # number of writebacks 795system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1461435 # number of ReadReq MSHR hits 796system.cpu.dcache.ReadReq_mshr_hits::total 1461435 # number of ReadReq MSHR hits 797system.cpu.dcache.WriteReq_mshr_hits::cpu.data 910564 # number of WriteReq MSHR hits 798system.cpu.dcache.WriteReq_mshr_hits::total 910564 # number of WriteReq MSHR hits 799system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 4 # number of LoadLockedReq MSHR hits 800system.cpu.dcache.LoadLockedReq_mshr_hits::total 4 # number of LoadLockedReq MSHR hits 801system.cpu.dcache.demand_mshr_hits::cpu.data 2371999 # number of demand (read+write) MSHR hits 802system.cpu.dcache.demand_mshr_hits::total 2371999 # number of demand (read+write) MSHR hits 803system.cpu.dcache.overall_mshr_hits::cpu.data 2371999 # number of overall MSHR hits 804system.cpu.dcache.overall_mshr_hits::total 2371999 # number of overall MSHR hits 805system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1322573 # number of ReadReq MSHR misses 806system.cpu.dcache.ReadReq_mshr_misses::total 1322573 # number of ReadReq MSHR misses 807system.cpu.dcache.WriteReq_mshr_misses::cpu.data 220744 # number of WriteReq MSHR misses 808system.cpu.dcache.WriteReq_mshr_misses::total 220744 # number of WriteReq MSHR misses 809system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 11 # number of SoftPFReq MSHR misses 810system.cpu.dcache.SoftPFReq_mshr_misses::total 11 # number of SoftPFReq MSHR misses 811system.cpu.dcache.demand_mshr_misses::cpu.data 1543317 # number of demand (read+write) MSHR misses 812system.cpu.dcache.demand_mshr_misses::total 1543317 # number of demand (read+write) MSHR misses 813system.cpu.dcache.overall_mshr_misses::cpu.data 1543328 # number of overall MSHR misses 814system.cpu.dcache.overall_mshr_misses::total 1543328 # number of overall MSHR misses 815system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 27142024000 # number of ReadReq MSHR miss cycles 816system.cpu.dcache.ReadReq_mshr_miss_latency::total 27142024000 # number of ReadReq MSHR miss cycles 817system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1845028694 # number of WriteReq MSHR miss cycles 818system.cpu.dcache.WriteReq_mshr_miss_latency::total 1845028694 # number of WriteReq MSHR miss cycles 819system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1269000 # number of SoftPFReq MSHR miss cycles 820system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1269000 # number of SoftPFReq MSHR miss cycles 821system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28987052694 # number of demand (read+write) MSHR miss cycles 822system.cpu.dcache.demand_mshr_miss_latency::total 28987052694 # number of demand (read+write) MSHR miss cycles 823system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28988321694 # number of overall MSHR miss cycles 824system.cpu.dcache.overall_mshr_miss_latency::total 28988321694 # number of overall MSHR miss cycles 825system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015778 # mshr miss rate for ReadReq accesses 826system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015778 # mshr miss rate for ReadReq accesses 827system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002690 # mshr miss rate for WriteReq accesses 828system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002690 # mshr miss rate for WriteReq accesses 829system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.000158 # mshr miss rate for SoftPFReq accesses 830system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.000158 # mshr miss rate for SoftPFReq accesses 831system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.009304 # mshr miss rate for demand accesses 832system.cpu.dcache.demand_mshr_miss_rate::total 0.009304 # mshr miss rate for demand accesses 833system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.009300 # mshr miss rate for overall accesses 834system.cpu.dcache.overall_mshr_miss_rate::total 0.009300 # mshr miss rate for overall accesses 835system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 20522.136774 # average ReadReq mshr miss latency 836system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 20522.136774 # average ReadReq mshr miss latency 837system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8358.228056 # average WriteReq mshr miss latency 838system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8358.228056 # average WriteReq mshr miss latency 839system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 115363.636364 # average SoftPFReq mshr miss latency 840system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 115363.636364 # average SoftPFReq mshr miss latency 841system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18782.306353 # average overall mshr miss latency 842system.cpu.dcache.demand_avg_mshr_miss_latency::total 18782.306353 # average overall mshr miss latency 843system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18782.994732 # average overall mshr miss latency 844system.cpu.dcache.overall_avg_mshr_miss_latency::total 18782.994732 # average overall mshr miss latency 845system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 122177531500 # Cumulative time (in ticks) in various power states 846system.cpu.icache.tags.replacements 725588 # number of replacements 847system.cpu.icache.tags.tagsinuse 511.809147 # Cycle average of tags in use 848system.cpu.icache.tags.total_refs 81470653 # Total number of references to valid blocks. 849system.cpu.icache.tags.sampled_refs 726100 # Sample count of references to valid blocks. 850system.cpu.icache.tags.avg_refs 112.203075 # Average number of references to valid blocks. 851system.cpu.icache.tags.warmup_cycle 346654500 # Cycle when the warmup percentage was hit. 852system.cpu.icache.tags.occ_blocks::cpu.inst 511.809147 # Average occupied blocks per requestor 853system.cpu.icache.tags.occ_percent::cpu.inst 0.999627 # Average percentage of cache occupancy 854system.cpu.icache.tags.occ_percent::total 0.999627 # Average percentage of cache occupancy 855system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 856system.cpu.icache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id 857system.cpu.icache.tags.age_task_id_blocks_1024::1 131 # Occupied blocks per task id 858system.cpu.icache.tags.age_task_id_blocks_1024::2 243 # Occupied blocks per task id 859system.cpu.icache.tags.age_task_id_blocks_1024::3 14 # Occupied blocks per task id 860system.cpu.icache.tags.age_task_id_blocks_1024::4 70 # Occupied blocks per task id 861system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 862system.cpu.icache.tags.tag_accesses 165133459 # Number of tag accesses 863system.cpu.icache.tags.data_accesses 165133459 # Number of data accesses 864system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 122177531500 # Cumulative time (in ticks) in various power states 865system.cpu.icache.ReadReq_hits::cpu.inst 81470653 # number of ReadReq hits 866system.cpu.icache.ReadReq_hits::total 81470653 # number of ReadReq hits 867system.cpu.icache.demand_hits::cpu.inst 81470653 # number of demand (read+write) hits 868system.cpu.icache.demand_hits::total 81470653 # number of demand (read+write) hits 869system.cpu.icache.overall_hits::cpu.inst 81470653 # number of overall hits 870system.cpu.icache.overall_hits::total 81470653 # number of overall hits 871system.cpu.icache.ReadReq_misses::cpu.inst 733019 # number of ReadReq misses 872system.cpu.icache.ReadReq_misses::total 733019 # number of ReadReq misses 873system.cpu.icache.demand_misses::cpu.inst 733019 # number of demand (read+write) misses 874system.cpu.icache.demand_misses::total 733019 # number of demand (read+write) misses 875system.cpu.icache.overall_misses::cpu.inst 733019 # number of overall misses 876system.cpu.icache.overall_misses::total 733019 # number of overall misses 877system.cpu.icache.ReadReq_miss_latency::cpu.inst 8417582442 # number of ReadReq miss cycles 878system.cpu.icache.ReadReq_miss_latency::total 8417582442 # number of ReadReq miss cycles 879system.cpu.icache.demand_miss_latency::cpu.inst 8417582442 # number of demand (read+write) miss cycles 880system.cpu.icache.demand_miss_latency::total 8417582442 # number of demand (read+write) miss cycles 881system.cpu.icache.overall_miss_latency::cpu.inst 8417582442 # number of overall miss cycles 882system.cpu.icache.overall_miss_latency::total 8417582442 # number of overall miss cycles 883system.cpu.icache.ReadReq_accesses::cpu.inst 82203672 # number of ReadReq accesses(hits+misses) 884system.cpu.icache.ReadReq_accesses::total 82203672 # number of ReadReq accesses(hits+misses) 885system.cpu.icache.demand_accesses::cpu.inst 82203672 # number of demand (read+write) accesses 886system.cpu.icache.demand_accesses::total 82203672 # number of demand (read+write) accesses 887system.cpu.icache.overall_accesses::cpu.inst 82203672 # number of overall (read+write) accesses 888system.cpu.icache.overall_accesses::total 82203672 # number of overall (read+write) accesses 889system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.008917 # miss rate for ReadReq accesses 890system.cpu.icache.ReadReq_miss_rate::total 0.008917 # miss rate for ReadReq accesses 891system.cpu.icache.demand_miss_rate::cpu.inst 0.008917 # miss rate for demand accesses 892system.cpu.icache.demand_miss_rate::total 0.008917 # miss rate for demand accesses 893system.cpu.icache.overall_miss_rate::cpu.inst 0.008917 # miss rate for overall accesses 894system.cpu.icache.overall_miss_rate::total 0.008917 # miss rate for overall accesses 895system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 11483.443733 # average ReadReq miss latency 896system.cpu.icache.ReadReq_avg_miss_latency::total 11483.443733 # average ReadReq miss latency 897system.cpu.icache.demand_avg_miss_latency::cpu.inst 11483.443733 # average overall miss latency 898system.cpu.icache.demand_avg_miss_latency::total 11483.443733 # average overall miss latency 899system.cpu.icache.overall_avg_miss_latency::cpu.inst 11483.443733 # average overall miss latency 900system.cpu.icache.overall_avg_miss_latency::total 11483.443733 # average overall miss latency 901system.cpu.icache.blocked_cycles::no_mshrs 142274 # number of cycles access was blocked 902system.cpu.icache.blocked_cycles::no_targets 124 # number of cycles access was blocked 903system.cpu.icache.blocked::no_mshrs 4376 # number of cycles access was blocked 904system.cpu.icache.blocked::no_targets 3 # number of cycles access was blocked 905system.cpu.icache.avg_blocked_cycles::no_mshrs 32.512340 # average number of cycles each access was blocked 906system.cpu.icache.avg_blocked_cycles::no_targets 41.333333 # average number of cycles each access was blocked 907system.cpu.icache.writebacks::writebacks 725588 # number of writebacks 908system.cpu.icache.writebacks::total 725588 # number of writebacks 909system.cpu.icache.ReadReq_mshr_hits::cpu.inst 6903 # number of ReadReq MSHR hits 910system.cpu.icache.ReadReq_mshr_hits::total 6903 # number of ReadReq MSHR hits 911system.cpu.icache.demand_mshr_hits::cpu.inst 6903 # number of demand (read+write) MSHR hits 912system.cpu.icache.demand_mshr_hits::total 6903 # number of demand (read+write) MSHR hits 913system.cpu.icache.overall_mshr_hits::cpu.inst 6903 # number of overall MSHR hits 914system.cpu.icache.overall_mshr_hits::total 6903 # number of overall MSHR hits 915system.cpu.icache.ReadReq_mshr_misses::cpu.inst 726116 # number of ReadReq MSHR misses 916system.cpu.icache.ReadReq_mshr_misses::total 726116 # number of ReadReq MSHR misses 917system.cpu.icache.demand_mshr_misses::cpu.inst 726116 # number of demand (read+write) MSHR misses 918system.cpu.icache.demand_mshr_misses::total 726116 # number of demand (read+write) MSHR misses 919system.cpu.icache.overall_mshr_misses::cpu.inst 726116 # number of overall MSHR misses 920system.cpu.icache.overall_mshr_misses::total 726116 # number of overall MSHR misses 921system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 7892899950 # number of ReadReq MSHR miss cycles 922system.cpu.icache.ReadReq_mshr_miss_latency::total 7892899950 # number of ReadReq MSHR miss cycles 923system.cpu.icache.demand_mshr_miss_latency::cpu.inst 7892899950 # number of demand (read+write) MSHR miss cycles 924system.cpu.icache.demand_mshr_miss_latency::total 7892899950 # number of demand (read+write) MSHR miss cycles 925system.cpu.icache.overall_mshr_miss_latency::cpu.inst 7892899950 # number of overall MSHR miss cycles 926system.cpu.icache.overall_mshr_miss_latency::total 7892899950 # number of overall MSHR miss cycles 927system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.008833 # mshr miss rate for ReadReq accesses 928system.cpu.icache.ReadReq_mshr_miss_rate::total 0.008833 # mshr miss rate for ReadReq accesses 929system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.008833 # mshr miss rate for demand accesses 930system.cpu.icache.demand_mshr_miss_rate::total 0.008833 # mshr miss rate for demand accesses 931system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.008833 # mshr miss rate for overall accesses 932system.cpu.icache.overall_mshr_miss_rate::total 0.008833 # mshr miss rate for overall accesses 933system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 10870.026208 # average ReadReq mshr miss latency 934system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 10870.026208 # average ReadReq mshr miss latency 935system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 10870.026208 # average overall mshr miss latency 936system.cpu.icache.demand_avg_mshr_miss_latency::total 10870.026208 # average overall mshr miss latency 937system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 10870.026208 # average overall mshr miss latency 938system.cpu.icache.overall_avg_mshr_miss_latency::total 10870.026208 # average overall mshr miss latency 939system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 122177531500 # Cumulative time (in ticks) in various power states 940system.cpu.l2cache.prefetcher.num_hwpf_issued 404432 # number of hwpf issued 941system.cpu.l2cache.prefetcher.pfIdentified 404544 # number of prefetch candidates identified 942system.cpu.l2cache.prefetcher.pfBufferHit 102 # number of redundant prefetches already in prefetch queue 943system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 944system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 945system.cpu.l2cache.prefetcher.pfSpanPage 28328 # number of prefetches not generated due to page crossing 946system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 122177531500 # Cumulative time (in ticks) in various power states 947system.cpu.l2cache.tags.replacements 0 # number of replacements 948system.cpu.l2cache.tags.tagsinuse 5246.342429 # Cycle average of tags in use 949system.cpu.l2cache.tags.total_refs 1813751 # Total number of references to valid blocks. 950system.cpu.l2cache.tags.sampled_refs 6313 # Sample count of references to valid blocks. 951system.cpu.l2cache.tags.avg_refs 287.304134 # Average number of references to valid blocks. 952system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 953system.cpu.l2cache.tags.occ_blocks::writebacks 5152.962075 # Average occupied blocks per requestor 954system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 93.380354 # Average occupied blocks per requestor 955system.cpu.l2cache.tags.occ_percent::writebacks 0.314512 # Average percentage of cache occupancy 956system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.005699 # Average percentage of cache occupancy 957system.cpu.l2cache.tags.occ_percent::total 0.320211 # Average percentage of cache occupancy 958system.cpu.l2cache.tags.occ_task_id_blocks::1022 192 # Occupied blocks per task id 959system.cpu.l2cache.tags.occ_task_id_blocks::1024 6121 # Occupied blocks per task id 960system.cpu.l2cache.tags.age_task_id_blocks_1022::0 16 # Occupied blocks per task id 961system.cpu.l2cache.tags.age_task_id_blocks_1022::1 22 # Occupied blocks per task id 962system.cpu.l2cache.tags.age_task_id_blocks_1022::2 48 # Occupied blocks per task id 963system.cpu.l2cache.tags.age_task_id_blocks_1022::3 3 # Occupied blocks per task id 964system.cpu.l2cache.tags.age_task_id_blocks_1022::4 103 # Occupied blocks per task id 965system.cpu.l2cache.tags.age_task_id_blocks_1024::0 162 # Occupied blocks per task id 966system.cpu.l2cache.tags.age_task_id_blocks_1024::1 554 # Occupied blocks per task id 967system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1140 # Occupied blocks per task id 968system.cpu.l2cache.tags.age_task_id_blocks_1024::3 141 # Occupied blocks per task id 969system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4124 # Occupied blocks per task id 970system.cpu.l2cache.tags.occ_task_id_percent::1022 0.011719 # Percentage of cache occupancy per task id 971system.cpu.l2cache.tags.occ_task_id_percent::1024 0.373596 # Percentage of cache occupancy per task id 972system.cpu.l2cache.tags.tag_accesses 70548166 # Number of tag accesses 973system.cpu.l2cache.tags.data_accesses 70548166 # Number of data accesses 974system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 122177531500 # Cumulative time (in ticks) in various power states 975system.cpu.l2cache.WritebackDirty_hits::writebacks 968244 # number of WritebackDirty hits 976system.cpu.l2cache.WritebackDirty_hits::total 968244 # number of WritebackDirty hits 977system.cpu.l2cache.WritebackClean_hits::writebacks 1045693 # number of WritebackClean hits 978system.cpu.l2cache.WritebackClean_hits::total 1045693 # number of WritebackClean hits 979system.cpu.l2cache.UpgradeReq_hits::cpu.data 1 # number of UpgradeReq hits 980system.cpu.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits 981system.cpu.l2cache.ReadExReq_hits::cpu.data 219960 # number of ReadExReq hits 982system.cpu.l2cache.ReadExReq_hits::total 219960 # number of ReadExReq hits 983system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 696520 # number of ReadCleanReq hits 984system.cpu.l2cache.ReadCleanReq_hits::total 696520 # number of ReadCleanReq hits 985system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1094361 # number of ReadSharedReq hits 986system.cpu.l2cache.ReadSharedReq_hits::total 1094361 # number of ReadSharedReq hits 987system.cpu.l2cache.demand_hits::cpu.inst 696520 # number of demand (read+write) hits 988system.cpu.l2cache.demand_hits::cpu.data 1314321 # number of demand (read+write) hits 989system.cpu.l2cache.demand_hits::total 2010841 # number of demand (read+write) hits 990system.cpu.l2cache.overall_hits::cpu.inst 696520 # number of overall hits 991system.cpu.l2cache.overall_hits::cpu.data 1314321 # number of overall hits 992system.cpu.l2cache.overall_hits::total 2010841 # number of overall hits 993system.cpu.l2cache.UpgradeReq_misses::cpu.data 16 # number of UpgradeReq misses 994system.cpu.l2cache.UpgradeReq_misses::total 16 # number of UpgradeReq misses 995system.cpu.l2cache.ReadExReq_misses::cpu.data 779 # number of ReadExReq misses 996system.cpu.l2cache.ReadExReq_misses::total 779 # number of ReadExReq misses 997system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 29515 # number of ReadCleanReq misses 998system.cpu.l2cache.ReadCleanReq_misses::total 29515 # number of ReadCleanReq misses 999system.cpu.l2cache.ReadSharedReq_misses::cpu.data 228211 # number of ReadSharedReq misses 1000system.cpu.l2cache.ReadSharedReq_misses::total 228211 # number of ReadSharedReq misses 1001system.cpu.l2cache.demand_misses::cpu.inst 29515 # number of demand (read+write) misses 1002system.cpu.l2cache.demand_misses::cpu.data 228990 # number of demand (read+write) misses 1003system.cpu.l2cache.demand_misses::total 258505 # number of demand (read+write) misses 1004system.cpu.l2cache.overall_misses::cpu.inst 29515 # number of overall misses 1005system.cpu.l2cache.overall_misses::cpu.data 228990 # number of overall misses 1006system.cpu.l2cache.overall_misses::total 258505 # number of overall misses 1007system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 43000 # number of UpgradeReq miss cycles 1008system.cpu.l2cache.UpgradeReq_miss_latency::total 43000 # number of UpgradeReq miss cycles 1009system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 70551500 # number of ReadExReq miss cycles 1010system.cpu.l2cache.ReadExReq_miss_latency::total 70551500 # number of ReadExReq miss cycles 1011system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2627115000 # number of ReadCleanReq miss cycles 1012system.cpu.l2cache.ReadCleanReq_miss_latency::total 2627115000 # number of ReadCleanReq miss cycles 1013system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 18006396500 # number of ReadSharedReq miss cycles 1014system.cpu.l2cache.ReadSharedReq_miss_latency::total 18006396500 # number of ReadSharedReq miss cycles 1015system.cpu.l2cache.demand_miss_latency::cpu.inst 2627115000 # number of demand (read+write) miss cycles 1016system.cpu.l2cache.demand_miss_latency::cpu.data 18076948000 # number of demand (read+write) miss cycles 1017system.cpu.l2cache.demand_miss_latency::total 20704063000 # number of demand (read+write) miss cycles 1018system.cpu.l2cache.overall_miss_latency::cpu.inst 2627115000 # number of overall miss cycles 1019system.cpu.l2cache.overall_miss_latency::cpu.data 18076948000 # number of overall miss cycles 1020system.cpu.l2cache.overall_miss_latency::total 20704063000 # number of overall miss cycles 1021system.cpu.l2cache.WritebackDirty_accesses::writebacks 968244 # number of WritebackDirty accesses(hits+misses) 1022system.cpu.l2cache.WritebackDirty_accesses::total 968244 # number of WritebackDirty accesses(hits+misses) 1023system.cpu.l2cache.WritebackClean_accesses::writebacks 1045693 # number of WritebackClean accesses(hits+misses) 1024system.cpu.l2cache.WritebackClean_accesses::total 1045693 # number of WritebackClean accesses(hits+misses) 1025system.cpu.l2cache.UpgradeReq_accesses::cpu.data 17 # number of UpgradeReq accesses(hits+misses) 1026system.cpu.l2cache.UpgradeReq_accesses::total 17 # number of UpgradeReq accesses(hits+misses) 1027system.cpu.l2cache.ReadExReq_accesses::cpu.data 220739 # number of ReadExReq accesses(hits+misses) 1028system.cpu.l2cache.ReadExReq_accesses::total 220739 # number of ReadExReq accesses(hits+misses) 1029system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 726035 # number of ReadCleanReq accesses(hits+misses) 1030system.cpu.l2cache.ReadCleanReq_accesses::total 726035 # number of ReadCleanReq accesses(hits+misses) 1031system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1322572 # number of ReadSharedReq accesses(hits+misses) 1032system.cpu.l2cache.ReadSharedReq_accesses::total 1322572 # number of ReadSharedReq accesses(hits+misses) 1033system.cpu.l2cache.demand_accesses::cpu.inst 726035 # number of demand (read+write) accesses 1034system.cpu.l2cache.demand_accesses::cpu.data 1543311 # number of demand (read+write) accesses 1035system.cpu.l2cache.demand_accesses::total 2269346 # number of demand (read+write) accesses 1036system.cpu.l2cache.overall_accesses::cpu.inst 726035 # number of overall (read+write) accesses 1037system.cpu.l2cache.overall_accesses::cpu.data 1543311 # number of overall (read+write) accesses 1038system.cpu.l2cache.overall_accesses::total 2269346 # number of overall (read+write) accesses 1039system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.941176 # miss rate for UpgradeReq accesses 1040system.cpu.l2cache.UpgradeReq_miss_rate::total 0.941176 # miss rate for UpgradeReq accesses 1041system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.003529 # miss rate for ReadExReq accesses 1042system.cpu.l2cache.ReadExReq_miss_rate::total 0.003529 # miss rate for ReadExReq accesses 1043system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.040652 # miss rate for ReadCleanReq accesses 1044system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.040652 # miss rate for ReadCleanReq accesses 1045system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.172551 # miss rate for ReadSharedReq accesses 1046system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.172551 # miss rate for ReadSharedReq accesses 1047system.cpu.l2cache.demand_miss_rate::cpu.inst 0.040652 # miss rate for demand accesses 1048system.cpu.l2cache.demand_miss_rate::cpu.data 0.148376 # miss rate for demand accesses 1049system.cpu.l2cache.demand_miss_rate::total 0.113912 # miss rate for demand accesses 1050system.cpu.l2cache.overall_miss_rate::cpu.inst 0.040652 # miss rate for overall accesses 1051system.cpu.l2cache.overall_miss_rate::cpu.data 0.148376 # miss rate for overall accesses 1052system.cpu.l2cache.overall_miss_rate::total 0.113912 # miss rate for overall accesses 1053system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 2687.500000 # average UpgradeReq miss latency 1054system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 2687.500000 # average UpgradeReq miss latency 1055system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 90566.752246 # average ReadExReq miss latency 1056system.cpu.l2cache.ReadExReq_avg_miss_latency::total 90566.752246 # average ReadExReq miss latency 1057system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 89009.486702 # average ReadCleanReq miss latency 1058system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 89009.486702 # average ReadCleanReq miss latency 1059system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 78902.403916 # average ReadSharedReq miss latency 1060system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 78902.403916 # average ReadSharedReq miss latency 1061system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 89009.486702 # average overall miss latency 1062system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78942.084807 # average overall miss latency 1063system.cpu.l2cache.demand_avg_miss_latency::total 80091.537881 # average overall miss latency 1064system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 89009.486702 # average overall miss latency 1065system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78942.084807 # average overall miss latency 1066system.cpu.l2cache.overall_avg_miss_latency::total 80091.537881 # average overall miss latency 1067system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1068system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1069system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1070system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1071system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1072system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1073system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 49 # number of ReadExReq MSHR hits 1074system.cpu.l2cache.ReadExReq_mshr_hits::total 49 # number of ReadExReq MSHR hits 1075system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 11 # number of ReadCleanReq MSHR hits 1076system.cpu.l2cache.ReadCleanReq_mshr_hits::total 11 # number of ReadCleanReq MSHR hits 1077system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 34 # number of ReadSharedReq MSHR hits 1078system.cpu.l2cache.ReadSharedReq_mshr_hits::total 34 # number of ReadSharedReq MSHR hits 1079system.cpu.l2cache.demand_mshr_hits::cpu.inst 11 # number of demand (read+write) MSHR hits 1080system.cpu.l2cache.demand_mshr_hits::cpu.data 83 # number of demand (read+write) MSHR hits 1081system.cpu.l2cache.demand_mshr_hits::total 94 # number of demand (read+write) MSHR hits 1082system.cpu.l2cache.overall_mshr_hits::cpu.inst 11 # number of overall MSHR hits 1083system.cpu.l2cache.overall_mshr_hits::cpu.data 83 # number of overall MSHR hits 1084system.cpu.l2cache.overall_mshr_hits::total 94 # number of overall MSHR hits 1085system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 54467 # number of HardPFReq MSHR misses 1086system.cpu.l2cache.HardPFReq_mshr_misses::total 54467 # number of HardPFReq MSHR misses 1087system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 16 # number of UpgradeReq MSHR misses 1088system.cpu.l2cache.UpgradeReq_mshr_misses::total 16 # number of UpgradeReq MSHR misses 1089system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 730 # number of ReadExReq MSHR misses 1090system.cpu.l2cache.ReadExReq_mshr_misses::total 730 # number of ReadExReq MSHR misses 1091system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 29504 # number of ReadCleanReq MSHR misses 1092system.cpu.l2cache.ReadCleanReq_mshr_misses::total 29504 # number of ReadCleanReq MSHR misses 1093system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 228177 # number of ReadSharedReq MSHR misses 1094system.cpu.l2cache.ReadSharedReq_mshr_misses::total 228177 # number of ReadSharedReq MSHR misses 1095system.cpu.l2cache.demand_mshr_misses::cpu.inst 29504 # number of demand (read+write) MSHR misses 1096system.cpu.l2cache.demand_mshr_misses::cpu.data 228907 # number of demand (read+write) MSHR misses 1097system.cpu.l2cache.demand_mshr_misses::total 258411 # number of demand (read+write) MSHR misses 1098system.cpu.l2cache.overall_mshr_misses::cpu.inst 29504 # number of overall MSHR misses 1099system.cpu.l2cache.overall_mshr_misses::cpu.data 228907 # number of overall MSHR misses 1100system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 54467 # number of overall MSHR misses 1101system.cpu.l2cache.overall_mshr_misses::total 312878 # number of overall MSHR misses 1102system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 206471258 # number of HardPFReq MSHR miss cycles 1103system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 206471258 # number of HardPFReq MSHR miss cycles 1104system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 251000 # number of UpgradeReq MSHR miss cycles 1105system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 251000 # number of UpgradeReq MSHR miss cycles 1106system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 64550000 # number of ReadExReq MSHR miss cycles 1107system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 64550000 # number of ReadExReq MSHR miss cycles 1108system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 2449507500 # number of ReadCleanReq MSHR miss cycles 1109system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 2449507500 # number of ReadCleanReq MSHR miss cycles 1110system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 16634852500 # number of ReadSharedReq MSHR miss cycles 1111system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 16634852500 # number of ReadSharedReq MSHR miss cycles 1112system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 2449507500 # number of demand (read+write) MSHR miss cycles 1113system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 16699402500 # number of demand (read+write) MSHR miss cycles 1114system.cpu.l2cache.demand_mshr_miss_latency::total 19148910000 # number of demand (read+write) MSHR miss cycles 1115system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 2449507500 # number of overall MSHR miss cycles 1116system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 16699402500 # number of overall MSHR miss cycles 1117system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 206471258 # number of overall MSHR miss cycles 1118system.cpu.l2cache.overall_mshr_miss_latency::total 19355381258 # number of overall MSHR miss cycles 1119system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1120system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 1121system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.941176 # mshr miss rate for UpgradeReq accesses 1122system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.941176 # mshr miss rate for UpgradeReq accesses 1123system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.003307 # mshr miss rate for ReadExReq accesses 1124system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.003307 # mshr miss rate for ReadExReq accesses 1125system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.040637 # mshr miss rate for ReadCleanReq accesses 1126system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.040637 # mshr miss rate for ReadCleanReq accesses 1127system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.172525 # mshr miss rate for ReadSharedReq accesses 1128system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.172525 # mshr miss rate for ReadSharedReq accesses 1129system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.040637 # mshr miss rate for demand accesses 1130system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.148322 # mshr miss rate for demand accesses 1131system.cpu.l2cache.demand_mshr_miss_rate::total 0.113870 # mshr miss rate for demand accesses 1132system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.040637 # mshr miss rate for overall accesses 1133system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.148322 # mshr miss rate for overall accesses 1134system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses 1135system.cpu.l2cache.overall_mshr_miss_rate::total 0.137871 # mshr miss rate for overall accesses 1136system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3790.758771 # average HardPFReq mshr miss latency 1137system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 3790.758771 # average HardPFReq mshr miss latency 1138system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15687.500000 # average UpgradeReq mshr miss latency 1139system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15687.500000 # average UpgradeReq mshr miss latency 1140system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 88424.657534 # average ReadExReq mshr miss latency 1141system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 88424.657534 # average ReadExReq mshr miss latency 1142system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 83022.895201 # average ReadCleanReq mshr miss latency 1143system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 83022.895201 # average ReadCleanReq mshr miss latency 1144system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72903.283416 # average ReadSharedReq mshr miss latency 1145system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72903.283416 # average ReadSharedReq mshr miss latency 1146system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 83022.895201 # average overall mshr miss latency 1147system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72952.782134 # average overall mshr miss latency 1148system.cpu.l2cache.demand_avg_mshr_miss_latency::total 74102.534335 # average overall mshr miss latency 1149system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 83022.895201 # average overall mshr miss latency 1150system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72952.782134 # average overall mshr miss latency 1151system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3790.758771 # average overall mshr miss latency 1152system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61862.391277 # average overall mshr miss latency 1153system.cpu.toL2Bus.snoop_filter.tot_requests 4537831 # Total number of requests made to the snoop filter. 1154system.cpu.toL2Bus.snoop_filter.hit_single_requests 2268421 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1155system.cpu.toL2Bus.snoop_filter.hit_multi_requests 254469 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1156system.cpu.toL2Bus.snoop_filter.tot_snoops 51822 # Total number of snoops made to the snoop filter. 1157system.cpu.toL2Bus.snoop_filter.hit_single_snoops 51821 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1158system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1159system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 122177531500 # Cumulative time (in ticks) in various power states 1160system.cpu.toL2Bus.trans_dist::ReadResp 2048687 # Transaction distribution 1161system.cpu.toL2Bus.trans_dist::WritebackDirty 968244 # Transaction distribution 1162system.cpu.toL2Bus.trans_dist::WritebackClean 1300143 # Transaction distribution 1163system.cpu.toL2Bus.trans_dist::HardPFReq 55841 # Transaction distribution 1164system.cpu.toL2Bus.trans_dist::UpgradeReq 17 # Transaction distribution 1165system.cpu.toL2Bus.trans_dist::UpgradeResp 17 # Transaction distribution 1166system.cpu.toL2Bus.trans_dist::ReadExReq 220739 # Transaction distribution 1167system.cpu.toL2Bus.trans_dist::ReadExResp 220739 # Transaction distribution 1168system.cpu.toL2Bus.trans_dist::ReadCleanReq 726116 # Transaction distribution 1169system.cpu.toL2Bus.trans_dist::ReadSharedReq 1322572 # Transaction distribution 1170system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2177738 # Packet count per connected master and slave (bytes) 1171system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4629455 # Packet count per connected master and slave (bytes) 1172system.cpu.toL2Bus.pkt_count::total 6807193 # Packet count per connected master and slave (bytes) 1173system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 92903808 # Cumulative packet size per connected master and slave (bytes) 1174system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 197511040 # Cumulative packet size per connected master and slave (bytes) 1175system.cpu.toL2Bus.pkt_size::total 290414848 # Cumulative packet size per connected master and slave (bytes) 1176system.cpu.toL2Bus.snoops 55922 # Total snoops (count) 1177system.cpu.toL2Bus.snoopTraffic 5184 # Total snoop traffic (bytes) 1178system.cpu.toL2Bus.snoop_fanout::samples 2325285 # Request fanout histogram 1179system.cpu.toL2Bus.snoop_fanout::mean 0.131736 # Request fanout histogram 1180system.cpu.toL2Bus.snoop_fanout::stdev 0.338205 # Request fanout histogram 1181system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1182system.cpu.toL2Bus.snoop_fanout::0 2018962 86.83% 86.83% # Request fanout histogram 1183system.cpu.toL2Bus.snoop_fanout::1 306322 13.17% 100.00% # Request fanout histogram 1184system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% # Request fanout histogram 1185system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1186system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1187system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 1188system.cpu.toL2Bus.snoop_fanout::total 2325285 # Request fanout histogram 1189system.cpu.toL2Bus.reqLayer0.occupancy 4537302500 # Layer occupancy (ticks) 1190system.cpu.toL2Bus.reqLayer0.utilization 3.7 # Layer utilization (%) 1191system.cpu.toL2Bus.respLayer0.occupancy 1089460423 # Layer occupancy (ticks) 1192system.cpu.toL2Bus.respLayer0.utilization 0.9 # Layer utilization (%) 1193system.cpu.toL2Bus.respLayer1.occupancy 2314997455 # Layer occupancy (ticks) 1194system.cpu.toL2Bus.respLayer1.utilization 1.9 # Layer utilization (%) 1195system.membus.snoop_filter.tot_requests 261072 # Total number of requests made to the snoop filter. 1196system.membus.snoop_filter.hit_single_requests 253753 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1197system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1198system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 1199system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1200system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1201system.membus.pwrStateResidencyTicks::UNDEFINED 122177531500 # Cumulative time (in ticks) in various power states 1202system.membus.trans_dist::ReadResp 260325 # Transaction distribution 1203system.membus.trans_dist::UpgradeReq 16 # Transaction distribution 1204system.membus.trans_dist::ReadExReq 730 # Transaction distribution 1205system.membus.trans_dist::ReadExResp 730 # Transaction distribution 1206system.membus.trans_dist::ReadSharedReq 260326 # Transaction distribution 1207system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 522127 # Packet count per connected master and slave (bytes) 1208system.membus.pkt_count::total 522127 # Packet count per connected master and slave (bytes) 1209system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16707520 # Cumulative packet size per connected master and slave (bytes) 1210system.membus.pkt_size::total 16707520 # Cumulative packet size per connected master and slave (bytes) 1211system.membus.snoops 0 # Total snoops (count) 1212system.membus.snoopTraffic 0 # Total snoop traffic (bytes) 1213system.membus.snoop_fanout::samples 261072 # Request fanout histogram 1214system.membus.snoop_fanout::mean 0 # Request fanout histogram 1215system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1216system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1217system.membus.snoop_fanout::0 261072 100.00% 100.00% # Request fanout histogram 1218system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 1219system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1220system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1221system.membus.snoop_fanout::max_value 0 # Request fanout histogram 1222system.membus.snoop_fanout::total 261072 # Request fanout histogram 1223system.membus.reqLayer0.occupancy 329884354 # Layer occupancy (ticks) 1224system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) 1225system.membus.respLayer1.occupancy 1377672131 # Layer occupancy (ticks) 1226system.membus.respLayer1.utilization 1.1 # Layer utilization (%) 1227 1228---------- End Simulation Statistics ---------- 1229