stats.txt revision 10798:74e3c7359393
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.112554 # Number of seconds simulated 4sim_ticks 112553814500 # Number of ticks simulated 5final_tick 112553814500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 123079 # Simulator instruction rate (inst/s) 8host_op_rate 147770 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 50736526 # Simulator tick rate (ticks/s) 10host_mem_usage 257068 # Number of bytes of host memory used 11host_seconds 2218.40 # Real time elapsed on the host 12sim_insts 273037219 # Number of instructions simulated 13sim_ops 327811601 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 187136 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 114176 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.l2cache.prefetcher 167616 # Number of bytes read from this memory 19system.physmem.bytes_read::total 468928 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 187136 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 187136 # Number of instructions bytes read from this memory 22system.physmem.num_reads::cpu.inst 2924 # Number of read requests responded to by this memory 23system.physmem.num_reads::cpu.data 1784 # Number of read requests responded to by this memory 24system.physmem.num_reads::cpu.l2cache.prefetcher 2619 # Number of read requests responded to by this memory 25system.physmem.num_reads::total 7327 # Number of read requests responded to by this memory 26system.physmem.bw_read::cpu.inst 1662636 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::cpu.data 1014413 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_read::cpu.l2cache.prefetcher 1489208 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::total 4166256 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_inst_read::cpu.inst 1662636 # Instruction read bandwidth from this memory (bytes/s) 31system.physmem.bw_inst_read::total 1662636 # Instruction read bandwidth from this memory (bytes/s) 32system.physmem.bw_total::cpu.inst 1662636 # Total bandwidth to/from this memory (bytes/s) 33system.physmem.bw_total::cpu.data 1014413 # Total bandwidth to/from this memory (bytes/s) 34system.physmem.bw_total::cpu.l2cache.prefetcher 1489208 # Total bandwidth to/from this memory (bytes/s) 35system.physmem.bw_total::total 4166256 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.readReqs 7327 # Number of read requests accepted 37system.physmem.writeReqs 0 # Number of write requests accepted 38system.physmem.readBursts 7327 # Number of DRAM read bursts, including those serviced by the write queue 39system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 40system.physmem.bytesReadDRAM 468928 # Total number of bytes read from DRAM 41system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 42system.physmem.bytesWritten 0 # Total number of bytes written to DRAM 43system.physmem.bytesReadSys 468928 # Total read bytes from the system interface side 44system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 45system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 46system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 47system.physmem.neitherReadNorWriteReqs 1 # Number of requests that are neither read nor write 48system.physmem.perBankRdBursts::0 589 # Per bank write bursts 49system.physmem.perBankRdBursts::1 789 # Per bank write bursts 50system.physmem.perBankRdBursts::2 601 # Per bank write bursts 51system.physmem.perBankRdBursts::3 520 # Per bank write bursts 52system.physmem.perBankRdBursts::4 444 # Per bank write bursts 53system.physmem.perBankRdBursts::5 346 # Per bank write bursts 54system.physmem.perBankRdBursts::6 153 # Per bank write bursts 55system.physmem.perBankRdBursts::7 255 # Per bank write bursts 56system.physmem.perBankRdBursts::8 219 # Per bank write bursts 57system.physmem.perBankRdBursts::9 290 # Per bank write bursts 58system.physmem.perBankRdBursts::10 315 # Per bank write bursts 59system.physmem.perBankRdBursts::11 411 # Per bank write bursts 60system.physmem.perBankRdBursts::12 547 # Per bank write bursts 61system.physmem.perBankRdBursts::13 678 # Per bank write bursts 62system.physmem.perBankRdBursts::14 615 # Per bank write bursts 63system.physmem.perBankRdBursts::15 555 # Per bank write bursts 64system.physmem.perBankWrBursts::0 0 # Per bank write bursts 65system.physmem.perBankWrBursts::1 0 # Per bank write bursts 66system.physmem.perBankWrBursts::2 0 # Per bank write bursts 67system.physmem.perBankWrBursts::3 0 # Per bank write bursts 68system.physmem.perBankWrBursts::4 0 # Per bank write bursts 69system.physmem.perBankWrBursts::5 0 # Per bank write bursts 70system.physmem.perBankWrBursts::6 0 # Per bank write bursts 71system.physmem.perBankWrBursts::7 0 # Per bank write bursts 72system.physmem.perBankWrBursts::8 0 # Per bank write bursts 73system.physmem.perBankWrBursts::9 0 # Per bank write bursts 74system.physmem.perBankWrBursts::10 0 # Per bank write bursts 75system.physmem.perBankWrBursts::11 0 # Per bank write bursts 76system.physmem.perBankWrBursts::12 0 # Per bank write bursts 77system.physmem.perBankWrBursts::13 0 # Per bank write bursts 78system.physmem.perBankWrBursts::14 0 # Per bank write bursts 79system.physmem.perBankWrBursts::15 0 # Per bank write bursts 80system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 81system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 82system.physmem.totGap 112553656000 # Total gap between requests 83system.physmem.readPktSize::0 0 # Read request sizes (log2) 84system.physmem.readPktSize::1 0 # Read request sizes (log2) 85system.physmem.readPktSize::2 0 # Read request sizes (log2) 86system.physmem.readPktSize::3 0 # Read request sizes (log2) 87system.physmem.readPktSize::4 0 # Read request sizes (log2) 88system.physmem.readPktSize::5 0 # Read request sizes (log2) 89system.physmem.readPktSize::6 7327 # Read request sizes (log2) 90system.physmem.writePktSize::0 0 # Write request sizes (log2) 91system.physmem.writePktSize::1 0 # Write request sizes (log2) 92system.physmem.writePktSize::2 0 # Write request sizes (log2) 93system.physmem.writePktSize::3 0 # Write request sizes (log2) 94system.physmem.writePktSize::4 0 # Write request sizes (log2) 95system.physmem.writePktSize::5 0 # Write request sizes (log2) 96system.physmem.writePktSize::6 0 # Write request sizes (log2) 97system.physmem.rdQLenPdf::0 3994 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::1 1457 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::2 473 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::3 301 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::4 246 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::5 203 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::6 178 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::7 150 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::8 184 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::9 56 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::10 30 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::11 22 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::12 18 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::13 15 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 129system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 130system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 131system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 132system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 133system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 134system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 193system.physmem.bytesPerActivate::samples 1397 # Bytes accessed per row activation 194system.physmem.bytesPerActivate::mean 334.064424 # Bytes accessed per row activation 195system.physmem.bytesPerActivate::gmean 193.482672 # Bytes accessed per row activation 196system.physmem.bytesPerActivate::stdev 348.087808 # Bytes accessed per row activation 197system.physmem.bytesPerActivate::0-127 504 36.08% 36.08% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::128-255 315 22.55% 58.63% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::256-383 145 10.38% 69.01% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::384-511 78 5.58% 74.59% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::512-639 51 3.65% 78.24% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::640-767 45 3.22% 81.46% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::768-895 28 2.00% 83.46% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::896-1023 21 1.50% 84.97% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::1024-1151 210 15.03% 100.00% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::total 1397 # Bytes accessed per row activation 207system.physmem.totQLat 96387273 # Total ticks spent queuing 208system.physmem.totMemAccLat 233768523 # Total ticks spent from burst creation until serviced by the DRAM 209system.physmem.totBusLat 36635000 # Total ticks spent in databus transfers 210system.physmem.avgQLat 13155.08 # Average queueing delay per DRAM burst 211system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 212system.physmem.avgMemAccLat 31905.08 # Average memory access latency per DRAM burst 213system.physmem.avgRdBW 4.17 # Average DRAM read bandwidth in MiByte/s 214system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 215system.physmem.avgRdBWSys 4.17 # Average system read bandwidth in MiByte/s 216system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 217system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 218system.physmem.busUtil 0.03 # Data bus utilization in percentage 219system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads 220system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 221system.physmem.avgRdQLen 1.44 # Average read queue length when enqueuing 222system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 223system.physmem.readRowHits 5921 # Number of row buffer hits during reads 224system.physmem.writeRowHits 0 # Number of row buffer hits during writes 225system.physmem.readRowHitRate 80.81 # Row buffer hit rate for reads 226system.physmem.writeRowHitRate nan # Row buffer hit rate for writes 227system.physmem.avgGap 15361492.56 # Average gap between requests 228system.physmem.pageHitRate 80.81 # Row buffer hit rate, read and write combined 229system.physmem_0.actEnergy 4883760 # Energy for activate commands per rank (pJ) 230system.physmem_0.preEnergy 2664750 # Energy for precharge commands per rank (pJ) 231system.physmem_0.readEnergy 28688400 # Energy for read commands per rank (pJ) 232system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) 233system.physmem_0.refreshEnergy 7351234800 # Energy for refresh commands per rank (pJ) 234system.physmem_0.actBackEnergy 3253381020 # Energy for active background per rank (pJ) 235system.physmem_0.preBackEnergy 64676459250 # Energy for precharge background per rank (pJ) 236system.physmem_0.totalEnergy 75317311980 # Total energy per rank (pJ) 237system.physmem_0.averagePower 669.186805 # Core power per rank (mW) 238system.physmem_0.memoryStateTime::IDLE 107592163396 # Time in different power states 239system.physmem_0.memoryStateTime::REF 3758300000 # Time in different power states 240system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 241system.physmem_0.memoryStateTime::ACT 1200480604 # Time in different power states 242system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 243system.physmem_1.actEnergy 5654880 # Energy for activate commands per rank (pJ) 244system.physmem_1.preEnergy 3085500 # Energy for precharge commands per rank (pJ) 245system.physmem_1.readEnergy 28158000 # Energy for read commands per rank (pJ) 246system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) 247system.physmem_1.refreshEnergy 7351234800 # Energy for refresh commands per rank (pJ) 248system.physmem_1.actBackEnergy 3298234320 # Energy for active background per rank (pJ) 249system.physmem_1.preBackEnergy 64637123250 # Energy for precharge background per rank (pJ) 250system.physmem_1.totalEnergy 75323490750 # Total energy per rank (pJ) 251system.physmem_1.averagePower 669.241613 # Core power per rank (mW) 252system.physmem_1.memoryStateTime::IDLE 107525247142 # Time in different power states 253system.physmem_1.memoryStateTime::REF 3758300000 # Time in different power states 254system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 255system.physmem_1.memoryStateTime::ACT 1266984612 # Time in different power states 256system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 257system.cpu.branchPred.lookups 37745757 # Number of BP lookups 258system.cpu.branchPred.condPredicted 20165080 # Number of conditional branches predicted 259system.cpu.branchPred.condIncorrect 1746215 # Number of conditional branches incorrect 260system.cpu.branchPred.BTBLookups 18666199 # Number of BTB lookups 261system.cpu.branchPred.BTBHits 17299874 # Number of BTB hits 262system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 263system.cpu.branchPred.BTBHitPct 92.680218 # BTB Hit Percentage 264system.cpu.branchPred.usedRAS 7225607 # Number of times the RAS was used to get a target. 265system.cpu.branchPred.RASInCorrect 3815 # Number of incorrect RAS predictions. 266system.cpu_clk_domain.clock 500 # Clock period in ticks 267system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 268system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 269system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 270system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 271system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 272system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 273system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 274system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 275system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 276system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 277system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 278system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 279system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 280system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 281system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 282system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 283system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 284system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 285system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 286system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 287system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 288system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 289system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 290system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 291system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 292system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 293system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 294system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 295system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 296system.cpu.dtb.walker.walks 0 # Table walker walks requested 297system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 298system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 299system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 300system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 301system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 302system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 303system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 304system.cpu.dtb.inst_hits 0 # ITB inst hits 305system.cpu.dtb.inst_misses 0 # ITB inst misses 306system.cpu.dtb.read_hits 0 # DTB read hits 307system.cpu.dtb.read_misses 0 # DTB read misses 308system.cpu.dtb.write_hits 0 # DTB write hits 309system.cpu.dtb.write_misses 0 # DTB write misses 310system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 311system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 312system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 313system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 314system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 315system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 316system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 317system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 318system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 319system.cpu.dtb.read_accesses 0 # DTB read accesses 320system.cpu.dtb.write_accesses 0 # DTB write accesses 321system.cpu.dtb.inst_accesses 0 # ITB inst accesses 322system.cpu.dtb.hits 0 # DTB hits 323system.cpu.dtb.misses 0 # DTB misses 324system.cpu.dtb.accesses 0 # DTB accesses 325system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 326system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 327system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 328system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 329system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 330system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 331system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 332system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 333system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 334system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 335system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 336system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 337system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 338system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 339system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 340system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 341system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 342system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 343system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 344system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 345system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 346system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 347system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 348system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 349system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 350system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 351system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 352system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 353system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 354system.cpu.itb.walker.walks 0 # Table walker walks requested 355system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 356system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 357system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 358system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 359system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 360system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 361system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 362system.cpu.itb.inst_hits 0 # ITB inst hits 363system.cpu.itb.inst_misses 0 # ITB inst misses 364system.cpu.itb.read_hits 0 # DTB read hits 365system.cpu.itb.read_misses 0 # DTB read misses 366system.cpu.itb.write_hits 0 # DTB write hits 367system.cpu.itb.write_misses 0 # DTB write misses 368system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 369system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 370system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 371system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 372system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 373system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 374system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 375system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 376system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 377system.cpu.itb.read_accesses 0 # DTB read accesses 378system.cpu.itb.write_accesses 0 # DTB write accesses 379system.cpu.itb.inst_accesses 0 # ITB inst accesses 380system.cpu.itb.hits 0 # DTB hits 381system.cpu.itb.misses 0 # DTB misses 382system.cpu.itb.accesses 0 # DTB accesses 383system.cpu.workload.num_syscalls 191 # Number of system calls 384system.cpu.numCycles 225107630 # number of cpu cycles simulated 385system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 386system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 387system.cpu.fetch.icacheStallCycles 12251626 # Number of cycles fetch is stalled on an Icache miss 388system.cpu.fetch.Insts 334050460 # Number of instructions fetch has processed 389system.cpu.fetch.Branches 37745757 # Number of branches that fetch encountered 390system.cpu.fetch.predictedBranches 24525481 # Number of branches that fetch has predicted taken 391system.cpu.fetch.Cycles 210773788 # Number of cycles fetch has run and was not squashing or blocked 392system.cpu.fetch.SquashCycles 3510701 # Number of cycles fetch has spent squashing 393system.cpu.fetch.MiscStallCycles 1259 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 394system.cpu.fetch.IcacheWaitRetryStallCycles 2425 # Number of stall cycles due to full MSHR 395system.cpu.fetch.CacheLines 89095014 # Number of cache lines fetched 396system.cpu.fetch.IcacheSquashes 21830 # Number of outstanding Icache misses that were squashed 397system.cpu.fetch.rateDist::samples 224784448 # Number of instructions fetched each cycle (Total) 398system.cpu.fetch.rateDist::mean 1.802641 # Number of instructions fetched each cycle (Total) 399system.cpu.fetch.rateDist::stdev 1.228554 # Number of instructions fetched each cycle (Total) 400system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 401system.cpu.fetch.rateDist::0 51100209 22.73% 22.73% # Number of instructions fetched each cycle (Total) 402system.cpu.fetch.rateDist::1 42897495 19.08% 41.82% # Number of instructions fetched each cycle (Total) 403system.cpu.fetch.rateDist::2 30052167 13.37% 55.19% # Number of instructions fetched each cycle (Total) 404system.cpu.fetch.rateDist::3 100734577 44.81% 100.00% # Number of instructions fetched each cycle (Total) 405system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 406system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 407system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) 408system.cpu.fetch.rateDist::total 224784448 # Number of instructions fetched each cycle (Total) 409system.cpu.fetch.branchRate 0.167679 # Number of branch fetches per cycle 410system.cpu.fetch.rate 1.483959 # Number of inst fetches per cycle 411system.cpu.decode.IdleCycles 27670459 # Number of cycles decode is idle 412system.cpu.decode.BlockedCycles 63847459 # Number of cycles decode is blocked 413system.cpu.decode.RunCycles 108576617 # Number of cycles decode is running 414system.cpu.decode.UnblockCycles 23069322 # Number of cycles decode is unblocking 415system.cpu.decode.SquashCycles 1620591 # Number of cycles decode is squashing 416system.cpu.decode.BranchResolved 6880031 # Number of times decode resolved a branch 417system.cpu.decode.BranchMispred 135198 # Number of times decode detected a branch misprediction 418system.cpu.decode.DecodedInsts 363530052 # Number of instructions handled by decode 419system.cpu.decode.SquashedInsts 6167703 # Number of squashed instructions handled by decode 420system.cpu.rename.SquashCycles 1620591 # Number of cycles rename is squashing 421system.cpu.rename.IdleCycles 44985233 # Number of cycles rename is idle 422system.cpu.rename.BlockCycles 17899875 # Number of cycles rename is blocking 423system.cpu.rename.serializeStallCycles 341878 # count of cycles rename stalled for serializing inst 424system.cpu.rename.RunCycles 113387886 # Number of cycles rename is running 425system.cpu.rename.UnblockCycles 46548985 # Number of cycles rename is unblocking 426system.cpu.rename.RenamedInsts 355747640 # Number of instructions processed by rename 427system.cpu.rename.SquashedInsts 2899285 # Number of squashed instructions processed by rename 428system.cpu.rename.ROBFullEvents 6598470 # Number of times rename has blocked due to ROB full 429system.cpu.rename.IQFullEvents 195112 # Number of times rename has blocked due to IQ full 430system.cpu.rename.LQFullEvents 7751940 # Number of times rename has blocked due to LQ full 431system.cpu.rename.SQFullEvents 21223571 # Number of times rename has blocked due to SQ full 432system.cpu.rename.FullRegisterEvents 2892429 # Number of times there has been no free registers 433system.cpu.rename.RenamedOperands 403401871 # Number of destination operands rename has renamed 434system.cpu.rename.RenameLookups 2533892950 # Number of register rename lookups that rename has made 435system.cpu.rename.int_rename_lookups 350207607 # Number of integer rename lookups 436system.cpu.rename.fp_rename_lookups 194891234 # Number of floating rename lookups 437system.cpu.rename.CommittedMaps 372230051 # Number of HB maps that are committed 438system.cpu.rename.UndoneMaps 31171820 # Number of HB maps that are undone due to squashing 439system.cpu.rename.serializingInsts 17015 # count of serializing insts renamed 440system.cpu.rename.tempSerializingInsts 17024 # count of temporary serializing insts renamed 441system.cpu.rename.skidInsts 55320329 # count of insts added to the skid buffer 442system.cpu.memDep0.insertedLoads 92416671 # Number of loads inserted to the mem dependence unit. 443system.cpu.memDep0.insertedStores 88482299 # Number of stores inserted to the mem dependence unit. 444system.cpu.memDep0.conflictingLoads 1659115 # Number of conflicting loads. 445system.cpu.memDep0.conflictingStores 1844729 # Number of conflicting stores. 446system.cpu.iq.iqInstsAdded 353235129 # Number of instructions added to the IQ (excludes non-spec) 447system.cpu.iq.iqNonSpecInstsAdded 28024 # Number of non-speculative instructions added to the IQ 448system.cpu.iq.iqInstsIssued 346404668 # Number of instructions issued 449system.cpu.iq.iqSquashedInstsIssued 2300304 # Number of squashed instructions issued 450system.cpu.iq.iqSquashedInstsExamined 25451552 # Number of squashed instructions iterated over during squash; mainly for profiling 451system.cpu.iq.iqSquashedOperandsExamined 73599170 # Number of squashed operands that are examined and possibly removed from graph 452system.cpu.iq.iqSquashedNonSpecRemoved 5904 # Number of squashed non-spec instructions that were removed 453system.cpu.iq.issued_per_cycle::samples 224784448 # Number of insts issued each cycle 454system.cpu.iq.issued_per_cycle::mean 1.541053 # Number of insts issued each cycle 455system.cpu.iq.issued_per_cycle::stdev 1.099675 # Number of insts issued each cycle 456system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 457system.cpu.iq.issued_per_cycle::0 40431348 17.99% 17.99% # Number of insts issued each cycle 458system.cpu.iq.issued_per_cycle::1 78272117 34.82% 52.81% # Number of insts issued each cycle 459system.cpu.iq.issued_per_cycle::2 61035980 27.15% 79.96% # Number of insts issued each cycle 460system.cpu.iq.issued_per_cycle::3 34788778 15.48% 95.44% # Number of insts issued each cycle 461system.cpu.iq.issued_per_cycle::4 9595638 4.27% 99.71% # Number of insts issued each cycle 462system.cpu.iq.issued_per_cycle::5 651817 0.29% 100.00% # Number of insts issued each cycle 463system.cpu.iq.issued_per_cycle::6 8770 0.00% 100.00% # Number of insts issued each cycle 464system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 465system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 466system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 467system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 468system.cpu.iq.issued_per_cycle::max_value 6 # Number of insts issued each cycle 469system.cpu.iq.issued_per_cycle::total 224784448 # Number of insts issued each cycle 470system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 471system.cpu.iq.fu_full::IntAlu 9471276 7.62% 7.62% # attempts to use FU when none available 472system.cpu.iq.fu_full::IntMult 7330 0.01% 7.63% # attempts to use FU when none available 473system.cpu.iq.fu_full::IntDiv 0 0.00% 7.63% # attempts to use FU when none available 474system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.63% # attempts to use FU when none available 475system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.63% # attempts to use FU when none available 476system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.63% # attempts to use FU when none available 477system.cpu.iq.fu_full::FloatMult 0 0.00% 7.63% # attempts to use FU when none available 478system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.63% # attempts to use FU when none available 479system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.63% # attempts to use FU when none available 480system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.63% # attempts to use FU when none available 481system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.63% # attempts to use FU when none available 482system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.63% # attempts to use FU when none available 483system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.63% # attempts to use FU when none available 484system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.63% # attempts to use FU when none available 485system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.63% # attempts to use FU when none available 486system.cpu.iq.fu_full::SimdMult 0 0.00% 7.63% # attempts to use FU when none available 487system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.63% # attempts to use FU when none available 488system.cpu.iq.fu_full::SimdShift 0 0.00% 7.63% # attempts to use FU when none available 489system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.63% # attempts to use FU when none available 490system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.63% # attempts to use FU when none available 491system.cpu.iq.fu_full::SimdFloatAdd 257049 0.21% 7.83% # attempts to use FU when none available 492system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.83% # attempts to use FU when none available 493system.cpu.iq.fu_full::SimdFloatCmp 126990 0.10% 7.94% # attempts to use FU when none available 494system.cpu.iq.fu_full::SimdFloatCvt 92940 0.07% 8.01% # attempts to use FU when none available 495system.cpu.iq.fu_full::SimdFloatDiv 68000 0.05% 8.06% # attempts to use FU when none available 496system.cpu.iq.fu_full::SimdFloatMisc 719474 0.58% 8.64% # attempts to use FU when none available 497system.cpu.iq.fu_full::SimdFloatMult 316340 0.25% 8.90% # attempts to use FU when none available 498system.cpu.iq.fu_full::SimdFloatMultAcc 682824 0.55% 9.45% # attempts to use FU when none available 499system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.45% # attempts to use FU when none available 500system.cpu.iq.fu_full::MemRead 53604156 43.13% 52.57% # attempts to use FU when none available 501system.cpu.iq.fu_full::MemWrite 58946138 47.43% 100.00% # attempts to use FU when none available 502system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 503system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 504system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 505system.cpu.iq.FU_type_0::IntAlu 110656025 31.94% 31.94% # Type of FU issued 506system.cpu.iq.FU_type_0::IntMult 2148357 0.62% 32.56% # Type of FU issued 507system.cpu.iq.FU_type_0::IntDiv 0 0.00% 32.56% # Type of FU issued 508system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 32.56% # Type of FU issued 509system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 32.56% # Type of FU issued 510system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 32.56% # Type of FU issued 511system.cpu.iq.FU_type_0::FloatMult 0 0.00% 32.56% # Type of FU issued 512system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 32.56% # Type of FU issued 513system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 32.56% # Type of FU issued 514system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 32.56% # Type of FU issued 515system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 32.56% # Type of FU issued 516system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 32.56% # Type of FU issued 517system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 32.56% # Type of FU issued 518system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 32.56% # Type of FU issued 519system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 32.56% # Type of FU issued 520system.cpu.iq.FU_type_0::SimdMult 0 0.00% 32.56% # Type of FU issued 521system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 32.56% # Type of FU issued 522system.cpu.iq.FU_type_0::SimdShift 0 0.00% 32.56% # Type of FU issued 523system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 32.56% # Type of FU issued 524system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 32.56% # Type of FU issued 525system.cpu.iq.FU_type_0::SimdFloatAdd 6798490 1.96% 34.53% # Type of FU issued 526system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 34.53% # Type of FU issued 527system.cpu.iq.FU_type_0::SimdFloatCmp 8668315 2.50% 37.03% # Type of FU issued 528system.cpu.iq.FU_type_0::SimdFloatCvt 3332477 0.96% 37.99% # Type of FU issued 529system.cpu.iq.FU_type_0::SimdFloatDiv 1592461 0.46% 38.45% # Type of FU issued 530system.cpu.iq.FU_type_0::SimdFloatMisc 20930112 6.04% 44.49% # Type of FU issued 531system.cpu.iq.FU_type_0::SimdFloatMult 7182294 2.07% 46.57% # Type of FU issued 532system.cpu.iq.FU_type_0::SimdFloatMultAcc 7148952 2.06% 48.63% # Type of FU issued 533system.cpu.iq.FU_type_0::SimdFloatSqrt 175286 0.05% 48.68% # Type of FU issued 534system.cpu.iq.FU_type_0::MemRead 91886799 26.53% 75.21% # Type of FU issued 535system.cpu.iq.FU_type_0::MemWrite 85885100 24.79% 100.00% # Type of FU issued 536system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 537system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 538system.cpu.iq.FU_type_0::total 346404668 # Type of FU issued 539system.cpu.iq.rate 1.538840 # Inst issue rate 540system.cpu.iq.fu_busy_cnt 124292517 # FU busy when requested 541system.cpu.iq.fu_busy_rate 0.358807 # FU busy rate (busy events/executed inst) 542system.cpu.iq.int_inst_queue_reads 756686876 # Number of integer instruction queue reads 543system.cpu.iq.int_inst_queue_writes 251708205 # Number of integer instruction queue writes 544system.cpu.iq.int_inst_queue_wakeup_accesses 223263085 # Number of integer instruction queue wakeup accesses 545system.cpu.iq.fp_inst_queue_reads 287499729 # Number of floating instruction queue reads 546system.cpu.iq.fp_inst_queue_writes 127016687 # Number of floating instruction queue writes 547system.cpu.iq.fp_inst_queue_wakeup_accesses 117424806 # Number of floating instruction queue wakeup accesses 548system.cpu.iq.int_alu_accesses 303164482 # Number of integer alu accesses 549system.cpu.iq.fp_alu_accesses 167532703 # Number of floating point alu accesses 550system.cpu.iew.lsq.thread0.forwLoads 5066223 # Number of loads that had data forwarded from stores 551system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 552system.cpu.iew.lsq.thread0.squashedLoads 6684396 # Number of loads squashed 553system.cpu.iew.lsq.thread0.ignoredResponses 13685 # Number of memory responses ignored because the instruction is squashed 554system.cpu.iew.lsq.thread0.memOrderViolation 10191 # Number of memory ordering violations 555system.cpu.iew.lsq.thread0.squashedStores 6106682 # Number of stores squashed 556system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 557system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 558system.cpu.iew.lsq.thread0.rescheduledLoads 154303 # Number of loads that were rescheduled 559system.cpu.iew.lsq.thread0.cacheBlocked 567640 # Number of times an access to memory failed due to the cache being blocked 560system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 561system.cpu.iew.iewSquashCycles 1620591 # Number of cycles IEW is squashing 562system.cpu.iew.iewBlockCycles 2121620 # Number of cycles IEW is blocking 563system.cpu.iew.iewUnblockCycles 330440 # Number of cycles IEW is unblocking 564system.cpu.iew.iewDispatchedInsts 353264020 # Number of instructions dispatched to IQ 565system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch 566system.cpu.iew.iewDispLoadInsts 92416671 # Number of dispatched load instructions 567system.cpu.iew.iewDispStoreInsts 88482299 # Number of dispatched store instructions 568system.cpu.iew.iewDispNonSpecInsts 16991 # Number of dispatched non-speculative instructions 569system.cpu.iew.iewIQFullEvents 8046 # Number of times the IQ has become full, causing a stall 570system.cpu.iew.iewLSQFullEvents 336925 # Number of times the LSQ has become full, causing a stall 571system.cpu.iew.memOrderViolationEvents 10191 # Number of memory order violations 572system.cpu.iew.predictedTakenIncorrect 1220622 # Number of branches that were predicted taken incorrectly 573system.cpu.iew.predictedNotTakenIncorrect 439103 # Number of branches that were predicted not taken incorrectly 574system.cpu.iew.branchMispredicts 1659725 # Number of branch mispredicts detected at execute 575system.cpu.iew.iewExecutedInsts 342414286 # Number of executed instructions 576system.cpu.iew.iewExecLoadInsts 90666955 # Number of load instructions executed 577system.cpu.iew.iewExecSquashedInsts 3990382 # Number of squashed instructions skipped in execute 578system.cpu.iew.exec_swp 0 # number of swp insts executed 579system.cpu.iew.exec_nop 867 # number of nop insts executed 580system.cpu.iew.exec_refs 175255989 # number of memory reference insts executed 581system.cpu.iew.exec_branches 31752931 # Number of branches executed 582system.cpu.iew.exec_stores 84589034 # Number of stores executed 583system.cpu.iew.exec_rate 1.521114 # Inst execution rate 584system.cpu.iew.wb_sent 340946352 # cumulative count of insts sent to commit 585system.cpu.iew.wb_count 340687891 # cumulative count of insts written-back 586system.cpu.iew.wb_producers 153731206 # num instructions producing a value 587system.cpu.iew.wb_consumers 266896125 # num instructions consuming a value 588system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 589system.cpu.iew.wb_rate 1.513444 # insts written-back per cycle 590system.cpu.iew.wb_fanout 0.575996 # average fanout of values written-back 591system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 592system.cpu.commit.commitSquashedInsts 23077118 # The number of squashed insts skipped by commit 593system.cpu.commit.commitNonSpecStalls 22120 # The number of times commit has been forced to stall to communicate backwards 594system.cpu.commit.branchMispredicts 1611456 # The number of times a branch was mispredicted 595system.cpu.commit.committed_per_cycle::samples 221059297 # Number of insts commited each cycle 596system.cpu.commit.committed_per_cycle::mean 1.482915 # Number of insts commited each cycle 597system.cpu.commit.committed_per_cycle::stdev 2.052167 # Number of insts commited each cycle 598system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 599system.cpu.commit.committed_per_cycle::0 87356112 39.52% 39.52% # Number of insts commited each cycle 600system.cpu.commit.committed_per_cycle::1 70369552 31.83% 71.35% # Number of insts commited each cycle 601system.cpu.commit.committed_per_cycle::2 20804455 9.41% 80.76% # Number of insts commited each cycle 602system.cpu.commit.committed_per_cycle::3 13442204 6.08% 86.84% # Number of insts commited each cycle 603system.cpu.commit.committed_per_cycle::4 8808979 3.98% 90.83% # Number of insts commited each cycle 604system.cpu.commit.committed_per_cycle::5 4514912 2.04% 92.87% # Number of insts commited each cycle 605system.cpu.commit.committed_per_cycle::6 2991653 1.35% 94.22% # Number of insts commited each cycle 606system.cpu.commit.committed_per_cycle::7 2424695 1.10% 95.32% # Number of insts commited each cycle 607system.cpu.commit.committed_per_cycle::8 10346735 4.68% 100.00% # Number of insts commited each cycle 608system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 609system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 610system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 611system.cpu.commit.committed_per_cycle::total 221059297 # Number of insts commited each cycle 612system.cpu.commit.committedInsts 273037831 # Number of instructions committed 613system.cpu.commit.committedOps 327812213 # Number of ops (including micro ops) committed 614system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 615system.cpu.commit.refs 168107892 # Number of memory references committed 616system.cpu.commit.loads 85732275 # Number of loads committed 617system.cpu.commit.membars 11033 # Number of memory barriers committed 618system.cpu.commit.branches 30563525 # Number of branches committed 619system.cpu.commit.fp_insts 114216705 # Number of committed floating point instructions. 620system.cpu.commit.int_insts 258331704 # Number of committed integer instructions. 621system.cpu.commit.function_calls 6225114 # Number of function calls committed. 622system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 623system.cpu.commit.op_class_0::IntAlu 104312486 31.82% 31.82% # Class of committed instruction 624system.cpu.commit.op_class_0::IntMult 2145917 0.65% 32.48% # Class of committed instruction 625system.cpu.commit.op_class_0::IntDiv 0 0.00% 32.48% # Class of committed instruction 626system.cpu.commit.op_class_0::FloatAdd 0 0.00% 32.48% # Class of committed instruction 627system.cpu.commit.op_class_0::FloatCmp 0 0.00% 32.48% # Class of committed instruction 628system.cpu.commit.op_class_0::FloatCvt 0 0.00% 32.48% # Class of committed instruction 629system.cpu.commit.op_class_0::FloatMult 0 0.00% 32.48% # Class of committed instruction 630system.cpu.commit.op_class_0::FloatDiv 0 0.00% 32.48% # Class of committed instruction 631system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 32.48% # Class of committed instruction 632system.cpu.commit.op_class_0::SimdAdd 0 0.00% 32.48% # Class of committed instruction 633system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 32.48% # Class of committed instruction 634system.cpu.commit.op_class_0::SimdAlu 0 0.00% 32.48% # Class of committed instruction 635system.cpu.commit.op_class_0::SimdCmp 0 0.00% 32.48% # Class of committed instruction 636system.cpu.commit.op_class_0::SimdCvt 0 0.00% 32.48% # Class of committed instruction 637system.cpu.commit.op_class_0::SimdMisc 0 0.00% 32.48% # Class of committed instruction 638system.cpu.commit.op_class_0::SimdMult 0 0.00% 32.48% # Class of committed instruction 639system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 32.48% # Class of committed instruction 640system.cpu.commit.op_class_0::SimdShift 0 0.00% 32.48% # Class of committed instruction 641system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 32.48% # Class of committed instruction 642system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 32.48% # Class of committed instruction 643system.cpu.commit.op_class_0::SimdFloatAdd 6594343 2.01% 34.49% # Class of committed instruction 644system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 34.49% # Class of committed instruction 645system.cpu.commit.op_class_0::SimdFloatCmp 7943502 2.42% 36.91% # Class of committed instruction 646system.cpu.commit.op_class_0::SimdFloatCvt 3118180 0.95% 37.86% # Class of committed instruction 647system.cpu.commit.op_class_0::SimdFloatDiv 1563217 0.48% 38.34% # Class of committed instruction 648system.cpu.commit.op_class_0::SimdFloatMisc 19652356 6.00% 44.33% # Class of committed instruction 649system.cpu.commit.op_class_0::SimdFloatMult 7136937 2.18% 46.51% # Class of committed instruction 650system.cpu.commit.op_class_0::SimdFloatMultAcc 7062098 2.15% 48.66% # Class of committed instruction 651system.cpu.commit.op_class_0::SimdFloatSqrt 175285 0.05% 48.72% # Class of committed instruction 652system.cpu.commit.op_class_0::MemRead 85732275 26.15% 74.87% # Class of committed instruction 653system.cpu.commit.op_class_0::MemWrite 82375617 25.13% 100.00% # Class of committed instruction 654system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 655system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 656system.cpu.commit.op_class_0::total 327812213 # Class of committed instruction 657system.cpu.commit.bw_lim_events 10346735 # number cycles where commit BW limit reached 658system.cpu.rob.rob_reads 561599370 # The number of ROB reads 659system.cpu.rob.rob_writes 705507733 # The number of ROB writes 660system.cpu.timesIdled 50679 # Number of times that the entire CPU went into an idle state and unscheduled itself 661system.cpu.idleCycles 323182 # Total number of cycles that the CPU has spent unscheduled due to idling 662system.cpu.committedInsts 273037219 # Number of Instructions Simulated 663system.cpu.committedOps 327811601 # Number of Ops (including micro ops) Simulated 664system.cpu.cpi 0.824458 # CPI: Cycles Per Instruction 665system.cpu.cpi_total 0.824458 # CPI: Total CPI of All Threads 666system.cpu.ipc 1.212919 # IPC: Instructions Per Cycle 667system.cpu.ipc_total 1.212919 # IPC: Total IPC of All Threads 668system.cpu.int_regfile_reads 331300708 # number of integer regfile reads 669system.cpu.int_regfile_writes 136940215 # number of integer regfile writes 670system.cpu.fp_regfile_reads 187107289 # number of floating regfile reads 671system.cpu.fp_regfile_writes 132177847 # number of floating regfile writes 672system.cpu.cc_regfile_reads 1297030245 # number of cc regfile reads 673system.cpu.cc_regfile_writes 80242169 # number of cc regfile writes 674system.cpu.misc_regfile_reads 1182847920 # number of misc regfile reads 675system.cpu.misc_regfile_writes 34421755 # number of misc regfile writes 676system.cpu.dcache.tags.replacements 1533856 # number of replacements 677system.cpu.dcache.tags.tagsinuse 511.843197 # Cycle average of tags in use 678system.cpu.dcache.tags.total_refs 163689216 # Total number of references to valid blocks. 679system.cpu.dcache.tags.sampled_refs 1534368 # Sample count of references to valid blocks. 680system.cpu.dcache.tags.avg_refs 106.681849 # Average number of references to valid blocks. 681system.cpu.dcache.tags.warmup_cycle 83394000 # Cycle when the warmup percentage was hit. 682system.cpu.dcache.tags.occ_blocks::cpu.data 511.843197 # Average occupied blocks per requestor 683system.cpu.dcache.tags.occ_percent::cpu.data 0.999694 # Average percentage of cache occupancy 684system.cpu.dcache.tags.occ_percent::total 0.999694 # Average percentage of cache occupancy 685system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 686system.cpu.dcache.tags.age_task_id_blocks_1024::0 111 # Occupied blocks per task id 687system.cpu.dcache.tags.age_task_id_blocks_1024::1 311 # Occupied blocks per task id 688system.cpu.dcache.tags.age_task_id_blocks_1024::2 89 # Occupied blocks per task id 689system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id 690system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 691system.cpu.dcache.tags.tag_accesses 336633502 # Number of tag accesses 692system.cpu.dcache.tags.data_accesses 336633502 # Number of data accesses 693system.cpu.dcache.ReadReq_hits::cpu.data 82631348 # number of ReadReq hits 694system.cpu.dcache.ReadReq_hits::total 82631348 # number of ReadReq hits 695system.cpu.dcache.WriteReq_hits::cpu.data 80965582 # number of WriteReq hits 696system.cpu.dcache.WriteReq_hits::total 80965582 # number of WriteReq hits 697system.cpu.dcache.SoftPFReq_hits::cpu.data 70480 # number of SoftPFReq hits 698system.cpu.dcache.SoftPFReq_hits::total 70480 # number of SoftPFReq hits 699system.cpu.dcache.LoadLockedReq_hits::cpu.data 10909 # number of LoadLockedReq hits 700system.cpu.dcache.LoadLockedReq_hits::total 10909 # number of LoadLockedReq hits 701system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits 702system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits 703system.cpu.dcache.demand_hits::cpu.data 163596930 # number of demand (read+write) hits 704system.cpu.dcache.demand_hits::total 163596930 # number of demand (read+write) hits 705system.cpu.dcache.overall_hits::cpu.data 163667410 # number of overall hits 706system.cpu.dcache.overall_hits::total 163667410 # number of overall hits 707system.cpu.dcache.ReadReq_misses::cpu.data 2773213 # number of ReadReq misses 708system.cpu.dcache.ReadReq_misses::total 2773213 # number of ReadReq misses 709system.cpu.dcache.WriteReq_misses::cpu.data 1087117 # number of WriteReq misses 710system.cpu.dcache.WriteReq_misses::total 1087117 # number of WriteReq misses 711system.cpu.dcache.SoftPFReq_misses::cpu.data 18 # number of SoftPFReq misses 712system.cpu.dcache.SoftPFReq_misses::total 18 # number of SoftPFReq misses 713system.cpu.dcache.LoadLockedReq_misses::cpu.data 5 # number of LoadLockedReq misses 714system.cpu.dcache.LoadLockedReq_misses::total 5 # number of LoadLockedReq misses 715system.cpu.dcache.demand_misses::cpu.data 3860330 # number of demand (read+write) misses 716system.cpu.dcache.demand_misses::total 3860330 # number of demand (read+write) misses 717system.cpu.dcache.overall_misses::cpu.data 3860348 # number of overall misses 718system.cpu.dcache.overall_misses::total 3860348 # number of overall misses 719system.cpu.dcache.ReadReq_miss_latency::cpu.data 22349106216 # number of ReadReq miss cycles 720system.cpu.dcache.ReadReq_miss_latency::total 22349106216 # number of ReadReq miss cycles 721system.cpu.dcache.WriteReq_miss_latency::cpu.data 8902471046 # number of WriteReq miss cycles 722system.cpu.dcache.WriteReq_miss_latency::total 8902471046 # number of WriteReq miss cycles 723system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 189750 # number of LoadLockedReq miss cycles 724system.cpu.dcache.LoadLockedReq_miss_latency::total 189750 # number of LoadLockedReq miss cycles 725system.cpu.dcache.demand_miss_latency::cpu.data 31251577262 # number of demand (read+write) miss cycles 726system.cpu.dcache.demand_miss_latency::total 31251577262 # number of demand (read+write) miss cycles 727system.cpu.dcache.overall_miss_latency::cpu.data 31251577262 # number of overall miss cycles 728system.cpu.dcache.overall_miss_latency::total 31251577262 # number of overall miss cycles 729system.cpu.dcache.ReadReq_accesses::cpu.data 85404561 # number of ReadReq accesses(hits+misses) 730system.cpu.dcache.ReadReq_accesses::total 85404561 # number of ReadReq accesses(hits+misses) 731system.cpu.dcache.WriteReq_accesses::cpu.data 82052699 # number of WriteReq accesses(hits+misses) 732system.cpu.dcache.WriteReq_accesses::total 82052699 # number of WriteReq accesses(hits+misses) 733system.cpu.dcache.SoftPFReq_accesses::cpu.data 70498 # number of SoftPFReq accesses(hits+misses) 734system.cpu.dcache.SoftPFReq_accesses::total 70498 # number of SoftPFReq accesses(hits+misses) 735system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10914 # number of LoadLockedReq accesses(hits+misses) 736system.cpu.dcache.LoadLockedReq_accesses::total 10914 # number of LoadLockedReq accesses(hits+misses) 737system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses) 738system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) 739system.cpu.dcache.demand_accesses::cpu.data 167457260 # number of demand (read+write) accesses 740system.cpu.dcache.demand_accesses::total 167457260 # number of demand (read+write) accesses 741system.cpu.dcache.overall_accesses::cpu.data 167527758 # number of overall (read+write) accesses 742system.cpu.dcache.overall_accesses::total 167527758 # number of overall (read+write) accesses 743system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.032471 # miss rate for ReadReq accesses 744system.cpu.dcache.ReadReq_miss_rate::total 0.032471 # miss rate for ReadReq accesses 745system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013249 # miss rate for WriteReq accesses 746system.cpu.dcache.WriteReq_miss_rate::total 0.013249 # miss rate for WriteReq accesses 747system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000255 # miss rate for SoftPFReq accesses 748system.cpu.dcache.SoftPFReq_miss_rate::total 0.000255 # miss rate for SoftPFReq accesses 749system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000458 # miss rate for LoadLockedReq accesses 750system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000458 # miss rate for LoadLockedReq accesses 751system.cpu.dcache.demand_miss_rate::cpu.data 0.023053 # miss rate for demand accesses 752system.cpu.dcache.demand_miss_rate::total 0.023053 # miss rate for demand accesses 753system.cpu.dcache.overall_miss_rate::cpu.data 0.023043 # miss rate for overall accesses 754system.cpu.dcache.overall_miss_rate::total 0.023043 # miss rate for overall accesses 755system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 8058.921625 # average ReadReq miss latency 756system.cpu.dcache.ReadReq_avg_miss_latency::total 8058.921625 # average ReadReq miss latency 757system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 8189.064329 # average WriteReq miss latency 758system.cpu.dcache.WriteReq_avg_miss_latency::total 8189.064329 # average WriteReq miss latency 759system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 37950 # average LoadLockedReq miss latency 760system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 37950 # average LoadLockedReq miss latency 761system.cpu.dcache.demand_avg_miss_latency::cpu.data 8095.571431 # average overall miss latency 762system.cpu.dcache.demand_avg_miss_latency::total 8095.571431 # average overall miss latency 763system.cpu.dcache.overall_avg_miss_latency::cpu.data 8095.533683 # average overall miss latency 764system.cpu.dcache.overall_avg_miss_latency::total 8095.533683 # average overall miss latency 765system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 766system.cpu.dcache.blocked_cycles::no_targets 918314 # number of cycles access was blocked 767system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 768system.cpu.dcache.blocked::no_targets 117385 # number of cycles access was blocked 769system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 770system.cpu.dcache.avg_blocked_cycles::no_targets 7.823095 # average number of cycles each access was blocked 771system.cpu.dcache.fast_writes 0 # number of fast writes performed 772system.cpu.dcache.cache_copies 0 # number of cache copies performed 773system.cpu.dcache.writebacks::writebacks 966341 # number of writebacks 774system.cpu.dcache.writebacks::total 966341 # number of writebacks 775system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1459499 # number of ReadReq MSHR hits 776system.cpu.dcache.ReadReq_mshr_hits::total 1459499 # number of ReadReq MSHR hits 777system.cpu.dcache.WriteReq_mshr_hits::cpu.data 866472 # number of WriteReq MSHR hits 778system.cpu.dcache.WriteReq_mshr_hits::total 866472 # number of WriteReq MSHR hits 779system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5 # number of LoadLockedReq MSHR hits 780system.cpu.dcache.LoadLockedReq_mshr_hits::total 5 # number of LoadLockedReq MSHR hits 781system.cpu.dcache.demand_mshr_hits::cpu.data 2325971 # number of demand (read+write) MSHR hits 782system.cpu.dcache.demand_mshr_hits::total 2325971 # number of demand (read+write) MSHR hits 783system.cpu.dcache.overall_mshr_hits::cpu.data 2325971 # number of overall MSHR hits 784system.cpu.dcache.overall_mshr_hits::total 2325971 # number of overall MSHR hits 785system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1313714 # number of ReadReq MSHR misses 786system.cpu.dcache.ReadReq_mshr_misses::total 1313714 # number of ReadReq MSHR misses 787system.cpu.dcache.WriteReq_mshr_misses::cpu.data 220645 # number of WriteReq MSHR misses 788system.cpu.dcache.WriteReq_mshr_misses::total 220645 # number of WriteReq MSHR misses 789system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 11 # number of SoftPFReq MSHR misses 790system.cpu.dcache.SoftPFReq_mshr_misses::total 11 # number of SoftPFReq MSHR misses 791system.cpu.dcache.demand_mshr_misses::cpu.data 1534359 # number of demand (read+write) MSHR misses 792system.cpu.dcache.demand_mshr_misses::total 1534359 # number of demand (read+write) MSHR misses 793system.cpu.dcache.overall_mshr_misses::cpu.data 1534370 # number of overall MSHR misses 794system.cpu.dcache.overall_mshr_misses::total 1534370 # number of overall MSHR misses 795system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9969290033 # number of ReadReq MSHR miss cycles 796system.cpu.dcache.ReadReq_mshr_miss_latency::total 9969290033 # number of ReadReq MSHR miss cycles 797system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1717345064 # number of WriteReq MSHR miss cycles 798system.cpu.dcache.WriteReq_mshr_miss_latency::total 1717345064 # number of WriteReq MSHR miss cycles 799system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1161750 # number of SoftPFReq MSHR miss cycles 800system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1161750 # number of SoftPFReq MSHR miss cycles 801system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11686635097 # number of demand (read+write) MSHR miss cycles 802system.cpu.dcache.demand_mshr_miss_latency::total 11686635097 # number of demand (read+write) MSHR miss cycles 803system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11687796847 # number of overall MSHR miss cycles 804system.cpu.dcache.overall_mshr_miss_latency::total 11687796847 # number of overall MSHR miss cycles 805system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015382 # mshr miss rate for ReadReq accesses 806system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015382 # mshr miss rate for ReadReq accesses 807system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002689 # mshr miss rate for WriteReq accesses 808system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002689 # mshr miss rate for WriteReq accesses 809system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.000156 # mshr miss rate for SoftPFReq accesses 810system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.000156 # mshr miss rate for SoftPFReq accesses 811system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.009163 # mshr miss rate for demand accesses 812system.cpu.dcache.demand_mshr_miss_rate::total 0.009163 # mshr miss rate for demand accesses 813system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.009159 # mshr miss rate for overall accesses 814system.cpu.dcache.overall_mshr_miss_rate::total 0.009159 # mshr miss rate for overall accesses 815system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7588.630427 # average ReadReq mshr miss latency 816system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 7588.630427 # average ReadReq mshr miss latency 817system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 7783.294722 # average WriteReq mshr miss latency 818system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 7783.294722 # average WriteReq mshr miss latency 819system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 105613.636364 # average SoftPFReq mshr miss latency 820system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 105613.636364 # average SoftPFReq mshr miss latency 821system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 7616.623683 # average overall mshr miss latency 822system.cpu.dcache.demand_avg_mshr_miss_latency::total 7616.623683 # average overall mshr miss latency 823system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 7617.326230 # average overall mshr miss latency 824system.cpu.dcache.overall_avg_mshr_miss_latency::total 7617.326230 # average overall mshr miss latency 825system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 826system.cpu.icache.tags.replacements 715719 # number of replacements 827system.cpu.icache.tags.tagsinuse 511.828705 # Cycle average of tags in use 828system.cpu.icache.tags.total_refs 88373879 # Total number of references to valid blocks. 829system.cpu.icache.tags.sampled_refs 716231 # Sample count of references to valid blocks. 830system.cpu.icache.tags.avg_refs 123.387397 # Average number of references to valid blocks. 831system.cpu.icache.tags.warmup_cycle 326261250 # Cycle when the warmup percentage was hit. 832system.cpu.icache.tags.occ_blocks::cpu.inst 511.828705 # Average occupied blocks per requestor 833system.cpu.icache.tags.occ_percent::cpu.inst 0.999665 # Average percentage of cache occupancy 834system.cpu.icache.tags.occ_percent::total 0.999665 # Average percentage of cache occupancy 835system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 836system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id 837system.cpu.icache.tags.age_task_id_blocks_1024::1 131 # Occupied blocks per task id 838system.cpu.icache.tags.age_task_id_blocks_1024::2 244 # Occupied blocks per task id 839system.cpu.icache.tags.age_task_id_blocks_1024::3 13 # Occupied blocks per task id 840system.cpu.icache.tags.age_task_id_blocks_1024::4 69 # Occupied blocks per task id 841system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 842system.cpu.icache.tags.tag_accesses 178906226 # Number of tag accesses 843system.cpu.icache.tags.data_accesses 178906226 # Number of data accesses 844system.cpu.icache.ReadReq_hits::cpu.inst 88373879 # number of ReadReq hits 845system.cpu.icache.ReadReq_hits::total 88373879 # number of ReadReq hits 846system.cpu.icache.demand_hits::cpu.inst 88373879 # number of demand (read+write) hits 847system.cpu.icache.demand_hits::total 88373879 # number of demand (read+write) hits 848system.cpu.icache.overall_hits::cpu.inst 88373879 # number of overall hits 849system.cpu.icache.overall_hits::total 88373879 # number of overall hits 850system.cpu.icache.ReadReq_misses::cpu.inst 721118 # number of ReadReq misses 851system.cpu.icache.ReadReq_misses::total 721118 # number of ReadReq misses 852system.cpu.icache.demand_misses::cpu.inst 721118 # number of demand (read+write) misses 853system.cpu.icache.demand_misses::total 721118 # number of demand (read+write) misses 854system.cpu.icache.overall_misses::cpu.inst 721118 # number of overall misses 855system.cpu.icache.overall_misses::total 721118 # number of overall misses 856system.cpu.icache.ReadReq_miss_latency::cpu.inst 5972962690 # number of ReadReq miss cycles 857system.cpu.icache.ReadReq_miss_latency::total 5972962690 # number of ReadReq miss cycles 858system.cpu.icache.demand_miss_latency::cpu.inst 5972962690 # number of demand (read+write) miss cycles 859system.cpu.icache.demand_miss_latency::total 5972962690 # number of demand (read+write) miss cycles 860system.cpu.icache.overall_miss_latency::cpu.inst 5972962690 # number of overall miss cycles 861system.cpu.icache.overall_miss_latency::total 5972962690 # number of overall miss cycles 862system.cpu.icache.ReadReq_accesses::cpu.inst 89094997 # number of ReadReq accesses(hits+misses) 863system.cpu.icache.ReadReq_accesses::total 89094997 # number of ReadReq accesses(hits+misses) 864system.cpu.icache.demand_accesses::cpu.inst 89094997 # number of demand (read+write) accesses 865system.cpu.icache.demand_accesses::total 89094997 # number of demand (read+write) accesses 866system.cpu.icache.overall_accesses::cpu.inst 89094997 # number of overall (read+write) accesses 867system.cpu.icache.overall_accesses::total 89094997 # number of overall (read+write) accesses 868system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.008094 # miss rate for ReadReq accesses 869system.cpu.icache.ReadReq_miss_rate::total 0.008094 # miss rate for ReadReq accesses 870system.cpu.icache.demand_miss_rate::cpu.inst 0.008094 # miss rate for demand accesses 871system.cpu.icache.demand_miss_rate::total 0.008094 # miss rate for demand accesses 872system.cpu.icache.overall_miss_rate::cpu.inst 0.008094 # miss rate for overall accesses 873system.cpu.icache.overall_miss_rate::total 0.008094 # miss rate for overall accesses 874system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8282.919980 # average ReadReq miss latency 875system.cpu.icache.ReadReq_avg_miss_latency::total 8282.919980 # average ReadReq miss latency 876system.cpu.icache.demand_avg_miss_latency::cpu.inst 8282.919980 # average overall miss latency 877system.cpu.icache.demand_avg_miss_latency::total 8282.919980 # average overall miss latency 878system.cpu.icache.overall_avg_miss_latency::cpu.inst 8282.919980 # average overall miss latency 879system.cpu.icache.overall_avg_miss_latency::total 8282.919980 # average overall miss latency 880system.cpu.icache.blocked_cycles::no_mshrs 60262 # number of cycles access was blocked 881system.cpu.icache.blocked_cycles::no_targets 95 # number of cycles access was blocked 882system.cpu.icache.blocked::no_mshrs 2026 # number of cycles access was blocked 883system.cpu.icache.blocked::no_targets 3 # number of cycles access was blocked 884system.cpu.icache.avg_blocked_cycles::no_mshrs 29.744324 # average number of cycles each access was blocked 885system.cpu.icache.avg_blocked_cycles::no_targets 31.666667 # average number of cycles each access was blocked 886system.cpu.icache.fast_writes 0 # number of fast writes performed 887system.cpu.icache.cache_copies 0 # number of cache copies performed 888system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4886 # number of ReadReq MSHR hits 889system.cpu.icache.ReadReq_mshr_hits::total 4886 # number of ReadReq MSHR hits 890system.cpu.icache.demand_mshr_hits::cpu.inst 4886 # number of demand (read+write) MSHR hits 891system.cpu.icache.demand_mshr_hits::total 4886 # number of demand (read+write) MSHR hits 892system.cpu.icache.overall_mshr_hits::cpu.inst 4886 # number of overall MSHR hits 893system.cpu.icache.overall_mshr_hits::total 4886 # number of overall MSHR hits 894system.cpu.icache.ReadReq_mshr_misses::cpu.inst 716232 # number of ReadReq MSHR misses 895system.cpu.icache.ReadReq_mshr_misses::total 716232 # number of ReadReq MSHR misses 896system.cpu.icache.demand_mshr_misses::cpu.inst 716232 # number of demand (read+write) MSHR misses 897system.cpu.icache.demand_mshr_misses::total 716232 # number of demand (read+write) MSHR misses 898system.cpu.icache.overall_mshr_misses::cpu.inst 716232 # number of overall MSHR misses 899system.cpu.icache.overall_mshr_misses::total 716232 # number of overall MSHR misses 900system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 5192936459 # number of ReadReq MSHR miss cycles 901system.cpu.icache.ReadReq_mshr_miss_latency::total 5192936459 # number of ReadReq MSHR miss cycles 902system.cpu.icache.demand_mshr_miss_latency::cpu.inst 5192936459 # number of demand (read+write) MSHR miss cycles 903system.cpu.icache.demand_mshr_miss_latency::total 5192936459 # number of demand (read+write) MSHR miss cycles 904system.cpu.icache.overall_mshr_miss_latency::cpu.inst 5192936459 # number of overall MSHR miss cycles 905system.cpu.icache.overall_mshr_miss_latency::total 5192936459 # number of overall MSHR miss cycles 906system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.008039 # mshr miss rate for ReadReq accesses 907system.cpu.icache.ReadReq_mshr_miss_rate::total 0.008039 # mshr miss rate for ReadReq accesses 908system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.008039 # mshr miss rate for demand accesses 909system.cpu.icache.demand_mshr_miss_rate::total 0.008039 # mshr miss rate for demand accesses 910system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.008039 # mshr miss rate for overall accesses 911system.cpu.icache.overall_mshr_miss_rate::total 0.008039 # mshr miss rate for overall accesses 912system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 7250.355275 # average ReadReq mshr miss latency 913system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 7250.355275 # average ReadReq mshr miss latency 914system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 7250.355275 # average overall mshr miss latency 915system.cpu.icache.demand_avg_mshr_miss_latency::total 7250.355275 # average overall mshr miss latency 916system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 7250.355275 # average overall mshr miss latency 917system.cpu.icache.overall_avg_mshr_miss_latency::total 7250.355275 # average overall mshr miss latency 918system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 919system.cpu.l2cache.prefetcher.num_hwpf_issued 404550 # number of hwpf issued 920system.cpu.l2cache.prefetcher.pfIdentified 404804 # number of prefetch candidates identified 921system.cpu.l2cache.prefetcher.pfBufferHit 188 # number of redundant prefetches already in prefetch queue 922system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 923system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 924system.cpu.l2cache.prefetcher.pfSpanPage 28140 # number of prefetches not generated due to page crossing 925system.cpu.l2cache.tags.replacements 0 # number of replacements 926system.cpu.l2cache.tags.tagsinuse 5993.813794 # Cycle average of tags in use 927system.cpu.l2cache.tags.total_refs 2806615 # Total number of references to valid blocks. 928system.cpu.l2cache.tags.sampled_refs 7301 # Sample count of references to valid blocks. 929system.cpu.l2cache.tags.avg_refs 384.415149 # Average number of references to valid blocks. 930system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 931system.cpu.l2cache.tags.occ_blocks::writebacks 2575.149913 # Average occupied blocks per requestor 932system.cpu.l2cache.tags.occ_blocks::cpu.inst 2681.614006 # Average occupied blocks per requestor 933system.cpu.l2cache.tags.occ_blocks::cpu.data 610.589138 # Average occupied blocks per requestor 934system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 126.460737 # Average occupied blocks per requestor 935system.cpu.l2cache.tags.occ_percent::writebacks 0.157175 # Average percentage of cache occupancy 936system.cpu.l2cache.tags.occ_percent::cpu.inst 0.163673 # Average percentage of cache occupancy 937system.cpu.l2cache.tags.occ_percent::cpu.data 0.037267 # Average percentage of cache occupancy 938system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.007719 # Average percentage of cache occupancy 939system.cpu.l2cache.tags.occ_percent::total 0.365833 # Average percentage of cache occupancy 940system.cpu.l2cache.tags.occ_task_id_blocks::1022 517 # Occupied blocks per task id 941system.cpu.l2cache.tags.occ_task_id_blocks::1024 6784 # Occupied blocks per task id 942system.cpu.l2cache.tags.age_task_id_blocks_1022::0 16 # Occupied blocks per task id 943system.cpu.l2cache.tags.age_task_id_blocks_1022::1 22 # Occupied blocks per task id 944system.cpu.l2cache.tags.age_task_id_blocks_1022::2 344 # Occupied blocks per task id 945system.cpu.l2cache.tags.age_task_id_blocks_1022::4 135 # Occupied blocks per task id 946system.cpu.l2cache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id 947system.cpu.l2cache.tags.age_task_id_blocks_1024::1 83 # Occupied blocks per task id 948system.cpu.l2cache.tags.age_task_id_blocks_1024::2 775 # Occupied blocks per task id 949system.cpu.l2cache.tags.age_task_id_blocks_1024::3 126 # Occupied blocks per task id 950system.cpu.l2cache.tags.age_task_id_blocks_1024::4 5743 # Occupied blocks per task id 951system.cpu.l2cache.tags.occ_task_id_percent::1022 0.031555 # Percentage of cache occupancy per task id 952system.cpu.l2cache.tags.occ_task_id_percent::1024 0.414062 # Percentage of cache occupancy per task id 953system.cpu.l2cache.tags.tag_accesses 51684538 # Number of tag accesses 954system.cpu.l2cache.tags.data_accesses 51684538 # Number of data accesses 955system.cpu.l2cache.ReadReq_hits::cpu.inst 712391 # number of ReadReq hits 956system.cpu.l2cache.ReadReq_hits::cpu.data 1312672 # number of ReadReq hits 957system.cpu.l2cache.ReadReq_hits::total 2025063 # number of ReadReq hits 958system.cpu.l2cache.Writeback_hits::writebacks 966341 # number of Writeback hits 959system.cpu.l2cache.Writeback_hits::total 966341 # number of Writeback hits 960system.cpu.l2cache.UpgradeReq_hits::cpu.data 1 # number of UpgradeReq hits 961system.cpu.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits 962system.cpu.l2cache.ReadExReq_hits::cpu.data 219831 # number of ReadExReq hits 963system.cpu.l2cache.ReadExReq_hits::total 219831 # number of ReadExReq hits 964system.cpu.l2cache.demand_hits::cpu.inst 712391 # number of demand (read+write) hits 965system.cpu.l2cache.demand_hits::cpu.data 1532503 # number of demand (read+write) hits 966system.cpu.l2cache.demand_hits::total 2244894 # number of demand (read+write) hits 967system.cpu.l2cache.overall_hits::cpu.inst 712391 # number of overall hits 968system.cpu.l2cache.overall_hits::cpu.data 1532503 # number of overall hits 969system.cpu.l2cache.overall_hits::total 2244894 # number of overall hits 970system.cpu.l2cache.ReadReq_misses::cpu.inst 2935 # number of ReadReq misses 971system.cpu.l2cache.ReadReq_misses::cpu.data 1053 # number of ReadReq misses 972system.cpu.l2cache.ReadReq_misses::total 3988 # number of ReadReq misses 973system.cpu.l2cache.UpgradeReq_misses::cpu.data 1 # number of UpgradeReq misses 974system.cpu.l2cache.UpgradeReq_misses::total 1 # number of UpgradeReq misses 975system.cpu.l2cache.ReadExReq_misses::cpu.data 812 # number of ReadExReq misses 976system.cpu.l2cache.ReadExReq_misses::total 812 # number of ReadExReq misses 977system.cpu.l2cache.demand_misses::cpu.inst 2935 # number of demand (read+write) misses 978system.cpu.l2cache.demand_misses::cpu.data 1865 # number of demand (read+write) misses 979system.cpu.l2cache.demand_misses::total 4800 # number of demand (read+write) misses 980system.cpu.l2cache.overall_misses::cpu.inst 2935 # number of overall misses 981system.cpu.l2cache.overall_misses::cpu.data 1865 # number of overall misses 982system.cpu.l2cache.overall_misses::total 4800 # number of overall misses 983system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 200800474 # number of ReadReq miss cycles 984system.cpu.l2cache.ReadReq_miss_latency::cpu.data 76846248 # number of ReadReq miss cycles 985system.cpu.l2cache.ReadReq_miss_latency::total 277646722 # number of ReadReq miss cycles 986system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 23499 # number of UpgradeReq miss cycles 987system.cpu.l2cache.UpgradeReq_miss_latency::total 23499 # number of UpgradeReq miss cycles 988system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 57691250 # number of ReadExReq miss cycles 989system.cpu.l2cache.ReadExReq_miss_latency::total 57691250 # number of ReadExReq miss cycles 990system.cpu.l2cache.demand_miss_latency::cpu.inst 200800474 # number of demand (read+write) miss cycles 991system.cpu.l2cache.demand_miss_latency::cpu.data 134537498 # number of demand (read+write) miss cycles 992system.cpu.l2cache.demand_miss_latency::total 335337972 # number of demand (read+write) miss cycles 993system.cpu.l2cache.overall_miss_latency::cpu.inst 200800474 # number of overall miss cycles 994system.cpu.l2cache.overall_miss_latency::cpu.data 134537498 # number of overall miss cycles 995system.cpu.l2cache.overall_miss_latency::total 335337972 # number of overall miss cycles 996system.cpu.l2cache.ReadReq_accesses::cpu.inst 715326 # number of ReadReq accesses(hits+misses) 997system.cpu.l2cache.ReadReq_accesses::cpu.data 1313725 # number of ReadReq accesses(hits+misses) 998system.cpu.l2cache.ReadReq_accesses::total 2029051 # number of ReadReq accesses(hits+misses) 999system.cpu.l2cache.Writeback_accesses::writebacks 966341 # number of Writeback accesses(hits+misses) 1000system.cpu.l2cache.Writeback_accesses::total 966341 # number of Writeback accesses(hits+misses) 1001system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2 # number of UpgradeReq accesses(hits+misses) 1002system.cpu.l2cache.UpgradeReq_accesses::total 2 # number of UpgradeReq accesses(hits+misses) 1003system.cpu.l2cache.ReadExReq_accesses::cpu.data 220643 # number of ReadExReq accesses(hits+misses) 1004system.cpu.l2cache.ReadExReq_accesses::total 220643 # number of ReadExReq accesses(hits+misses) 1005system.cpu.l2cache.demand_accesses::cpu.inst 715326 # number of demand (read+write) accesses 1006system.cpu.l2cache.demand_accesses::cpu.data 1534368 # number of demand (read+write) accesses 1007system.cpu.l2cache.demand_accesses::total 2249694 # number of demand (read+write) accesses 1008system.cpu.l2cache.overall_accesses::cpu.inst 715326 # number of overall (read+write) accesses 1009system.cpu.l2cache.overall_accesses::cpu.data 1534368 # number of overall (read+write) accesses 1010system.cpu.l2cache.overall_accesses::total 2249694 # number of overall (read+write) accesses 1011system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.004103 # miss rate for ReadReq accesses 1012system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000802 # miss rate for ReadReq accesses 1013system.cpu.l2cache.ReadReq_miss_rate::total 0.001965 # miss rate for ReadReq accesses 1014system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.500000 # miss rate for UpgradeReq accesses 1015system.cpu.l2cache.UpgradeReq_miss_rate::total 0.500000 # miss rate for UpgradeReq accesses 1016system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.003680 # miss rate for ReadExReq accesses 1017system.cpu.l2cache.ReadExReq_miss_rate::total 0.003680 # miss rate for ReadExReq accesses 1018system.cpu.l2cache.demand_miss_rate::cpu.inst 0.004103 # miss rate for demand accesses 1019system.cpu.l2cache.demand_miss_rate::cpu.data 0.001215 # miss rate for demand accesses 1020system.cpu.l2cache.demand_miss_rate::total 0.002134 # miss rate for demand accesses 1021system.cpu.l2cache.overall_miss_rate::cpu.inst 0.004103 # miss rate for overall accesses 1022system.cpu.l2cache.overall_miss_rate::cpu.data 0.001215 # miss rate for overall accesses 1023system.cpu.l2cache.overall_miss_rate::total 0.002134 # miss rate for overall accesses 1024system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68415.834412 # average ReadReq miss latency 1025system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 72978.393162 # average ReadReq miss latency 1026system.cpu.l2cache.ReadReq_avg_miss_latency::total 69620.542126 # average ReadReq miss latency 1027system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 23499 # average UpgradeReq miss latency 1028system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 23499 # average UpgradeReq miss latency 1029system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71048.337438 # average ReadExReq miss latency 1030system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71048.337438 # average ReadExReq miss latency 1031system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68415.834412 # average overall miss latency 1032system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72138.068633 # average overall miss latency 1033system.cpu.l2cache.demand_avg_miss_latency::total 69862.077500 # average overall miss latency 1034system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68415.834412 # average overall miss latency 1035system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72138.068633 # average overall miss latency 1036system.cpu.l2cache.overall_avg_miss_latency::total 69862.077500 # average overall miss latency 1037system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1038system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1039system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1040system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1041system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1042system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1043system.cpu.l2cache.fast_writes 0 # number of fast writes performed 1044system.cpu.l2cache.cache_copies 0 # number of cache copies performed 1045system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 11 # number of ReadReq MSHR hits 1046system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 34 # number of ReadReq MSHR hits 1047system.cpu.l2cache.ReadReq_mshr_hits::total 45 # number of ReadReq MSHR hits 1048system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 47 # number of ReadExReq MSHR hits 1049system.cpu.l2cache.ReadExReq_mshr_hits::total 47 # number of ReadExReq MSHR hits 1050system.cpu.l2cache.demand_mshr_hits::cpu.inst 11 # number of demand (read+write) MSHR hits 1051system.cpu.l2cache.demand_mshr_hits::cpu.data 81 # number of demand (read+write) MSHR hits 1052system.cpu.l2cache.demand_mshr_hits::total 92 # number of demand (read+write) MSHR hits 1053system.cpu.l2cache.overall_mshr_hits::cpu.inst 11 # number of overall MSHR hits 1054system.cpu.l2cache.overall_mshr_hits::cpu.data 81 # number of overall MSHR hits 1055system.cpu.l2cache.overall_mshr_hits::total 92 # number of overall MSHR hits 1056system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2924 # number of ReadReq MSHR misses 1057system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1019 # number of ReadReq MSHR misses 1058system.cpu.l2cache.ReadReq_mshr_misses::total 3943 # number of ReadReq MSHR misses 1059system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 30395 # number of HardPFReq MSHR misses 1060system.cpu.l2cache.HardPFReq_mshr_misses::total 30395 # number of HardPFReq MSHR misses 1061system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1 # number of UpgradeReq MSHR misses 1062system.cpu.l2cache.UpgradeReq_mshr_misses::total 1 # number of UpgradeReq MSHR misses 1063system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 765 # number of ReadExReq MSHR misses 1064system.cpu.l2cache.ReadExReq_mshr_misses::total 765 # number of ReadExReq MSHR misses 1065system.cpu.l2cache.demand_mshr_misses::cpu.inst 2924 # number of demand (read+write) MSHR misses 1066system.cpu.l2cache.demand_mshr_misses::cpu.data 1784 # number of demand (read+write) MSHR misses 1067system.cpu.l2cache.demand_mshr_misses::total 4708 # number of demand (read+write) MSHR misses 1068system.cpu.l2cache.overall_mshr_misses::cpu.inst 2924 # number of overall MSHR misses 1069system.cpu.l2cache.overall_mshr_misses::cpu.data 1784 # number of overall MSHR misses 1070system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 30395 # number of overall MSHR misses 1071system.cpu.l2cache.overall_mshr_misses::total 35103 # number of overall MSHR misses 1072system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 175338026 # number of ReadReq MSHR miss cycles 1073system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 66096002 # number of ReadReq MSHR miss cycles 1074system.cpu.l2cache.ReadReq_mshr_miss_latency::total 241434028 # number of ReadReq MSHR miss cycles 1075system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 176500042 # number of HardPFReq MSHR miss cycles 1076system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 176500042 # number of HardPFReq MSHR miss cycles 1077system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 14001 # number of UpgradeReq MSHR miss cycles 1078system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 14001 # number of UpgradeReq MSHR miss cycles 1079system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 49863251 # number of ReadExReq MSHR miss cycles 1080system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 49863251 # number of ReadExReq MSHR miss cycles 1081system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 175338026 # number of demand (read+write) MSHR miss cycles 1082system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 115959253 # number of demand (read+write) MSHR miss cycles 1083system.cpu.l2cache.demand_mshr_miss_latency::total 291297279 # number of demand (read+write) MSHR miss cycles 1084system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 175338026 # number of overall MSHR miss cycles 1085system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 115959253 # number of overall MSHR miss cycles 1086system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 176500042 # number of overall MSHR miss cycles 1087system.cpu.l2cache.overall_mshr_miss_latency::total 467797321 # number of overall MSHR miss cycles 1088system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.004088 # mshr miss rate for ReadReq accesses 1089system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000776 # mshr miss rate for ReadReq accesses 1090system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001943 # mshr miss rate for ReadReq accesses 1091system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1092system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 1093system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for UpgradeReq accesses 1094system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.500000 # mshr miss rate for UpgradeReq accesses 1095system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.003467 # mshr miss rate for ReadExReq accesses 1096system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.003467 # mshr miss rate for ReadExReq accesses 1097system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.004088 # mshr miss rate for demand accesses 1098system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.001163 # mshr miss rate for demand accesses 1099system.cpu.l2cache.demand_mshr_miss_rate::total 0.002093 # mshr miss rate for demand accesses 1100system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.004088 # mshr miss rate for overall accesses 1101system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.001163 # mshr miss rate for overall accesses 1102system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses 1103system.cpu.l2cache.overall_mshr_miss_rate::total 0.015603 # mshr miss rate for overall accesses 1104system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59965.125171 # average ReadReq mshr miss latency 1105system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64863.593719 # average ReadReq mshr miss latency 1106system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61231.049455 # average ReadReq mshr miss latency 1107system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 5806.877513 # average HardPFReq mshr miss latency 1108system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 5806.877513 # average HardPFReq mshr miss latency 1109system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14001 # average UpgradeReq mshr miss latency 1110system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14001 # average UpgradeReq mshr miss latency 1111system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65180.720261 # average ReadExReq mshr miss latency 1112system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65180.720261 # average ReadExReq mshr miss latency 1113system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59965.125171 # average overall mshr miss latency 1114system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64999.581278 # average overall mshr miss latency 1115system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61872.829014 # average overall mshr miss latency 1116system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59965.125171 # average overall mshr miss latency 1117system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64999.581278 # average overall mshr miss latency 1118system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 5806.877513 # average overall mshr miss latency 1119system.cpu.l2cache.overall_avg_mshr_miss_latency::total 13326.419993 # average overall mshr miss latency 1120system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1121system.cpu.toL2Bus.trans_dist::ReadReq 2029957 # Transaction distribution 1122system.cpu.toL2Bus.trans_dist::ReadResp 2029957 # Transaction distribution 1123system.cpu.toL2Bus.trans_dist::Writeback 966341 # Transaction distribution 1124system.cpu.toL2Bus.trans_dist::HardPFReq 31800 # Transaction distribution 1125system.cpu.toL2Bus.trans_dist::UpgradeReq 2 # Transaction distribution 1126system.cpu.toL2Bus.trans_dist::UpgradeResp 2 # Transaction distribution 1127system.cpu.toL2Bus.trans_dist::ReadExReq 220643 # Transaction distribution 1128system.cpu.toL2Bus.trans_dist::ReadExResp 220643 # Transaction distribution 1129system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1431558 # Packet count per connected master and slave (bytes) 1130system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4035081 # Packet count per connected master and slave (bytes) 1131system.cpu.toL2Bus.pkt_count::total 5466639 # Packet count per connected master and slave (bytes) 1132system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45780864 # Cumulative packet size per connected master and slave (bytes) 1133system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 160045376 # Cumulative packet size per connected master and slave (bytes) 1134system.cpu.toL2Bus.pkt_size::total 205826240 # Cumulative packet size per connected master and slave (bytes) 1135system.cpu.toL2Bus.snoops 32706 # Total snoops (count) 1136system.cpu.toL2Bus.snoop_fanout::samples 3248743 # Request fanout histogram 1137system.cpu.toL2Bus.snoop_fanout::mean 3.009788 # Request fanout histogram 1138system.cpu.toL2Bus.snoop_fanout::stdev 0.098451 # Request fanout histogram 1139system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1140system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1141system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 1142system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 1143system.cpu.toL2Bus.snoop_fanout::3 3216943 99.02% 99.02% # Request fanout histogram 1144system.cpu.toL2Bus.snoop_fanout::4 31800 0.98% 100.00% # Request fanout histogram 1145system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1146system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram 1147system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram 1148system.cpu.toL2Bus.snoop_fanout::total 3248743 # Request fanout histogram 1149system.cpu.toL2Bus.reqLayer0.occupancy 2574812500 # Layer occupancy (ticks) 1150system.cpu.toL2Bus.reqLayer0.utilization 2.3 # Layer utilization (%) 1151system.cpu.toL2Bus.respLayer0.occupancy 1075185997 # Layer occupancy (ticks) 1152system.cpu.toL2Bus.respLayer0.utilization 1.0 # Layer utilization (%) 1153system.cpu.toL2Bus.respLayer1.occupancy 2301792968 # Layer occupancy (ticks) 1154system.cpu.toL2Bus.respLayer1.utilization 2.0 # Layer utilization (%) 1155system.membus.trans_dist::ReadReq 6562 # Transaction distribution 1156system.membus.trans_dist::ReadResp 6562 # Transaction distribution 1157system.membus.trans_dist::UpgradeReq 1 # Transaction distribution 1158system.membus.trans_dist::UpgradeResp 1 # Transaction distribution 1159system.membus.trans_dist::ReadExReq 765 # Transaction distribution 1160system.membus.trans_dist::ReadExResp 765 # Transaction distribution 1161system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14656 # Packet count per connected master and slave (bytes) 1162system.membus.pkt_count::total 14656 # Packet count per connected master and slave (bytes) 1163system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 468928 # Cumulative packet size per connected master and slave (bytes) 1164system.membus.pkt_size::total 468928 # Cumulative packet size per connected master and slave (bytes) 1165system.membus.snoops 0 # Total snoops (count) 1166system.membus.snoop_fanout::samples 7328 # Request fanout histogram 1167system.membus.snoop_fanout::mean 0 # Request fanout histogram 1168system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1169system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1170system.membus.snoop_fanout::0 7328 100.00% 100.00% # Request fanout histogram 1171system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 1172system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1173system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1174system.membus.snoop_fanout::max_value 0 # Request fanout histogram 1175system.membus.snoop_fanout::total 7328 # Request fanout histogram 1176system.membus.reqLayer0.occupancy 9247379 # Layer occupancy (ticks) 1177system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 1178system.membus.respLayer1.occupancy 38369962 # Layer occupancy (ticks) 1179system.membus.respLayer1.utilization 0.0 # Layer utilization (%) 1180 1181---------- End Simulation Statistics ---------- 1182