stats.txt revision 10352:5f1f92bf76ee
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.058843 # Number of seconds simulated 4sim_ticks 58842982000 # Number of ticks simulated 5final_tick 58842982000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 157851 # Simulator instruction rate (inst/s) 8host_op_rate 189517 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 34018873 # Simulator tick rate (ticks/s) 10host_mem_usage 327492 # Number of bytes of host memory used 11host_seconds 1729.72 # Real time elapsed on the host 12sim_insts 273036656 # Number of instructions simulated 13sim_ops 327810999 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 189376 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 272128 # Number of bytes read from this memory 18system.physmem.bytes_read::total 461504 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 189376 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 189376 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 2959 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 4252 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 7211 # Number of read requests responded to by this memory 24system.physmem.bw_read::cpu.inst 3218328 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 4624647 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 7842974 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 3218328 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 3218328 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 3218328 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 4624647 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 7842974 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.readReqs 7211 # Number of read requests accepted 33system.physmem.writeReqs 0 # Number of write requests accepted 34system.physmem.readBursts 7211 # Number of DRAM read bursts, including those serviced by the write queue 35system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 36system.physmem.bytesReadDRAM 461504 # Total number of bytes read from DRAM 37system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 38system.physmem.bytesWritten 0 # Total number of bytes written to DRAM 39system.physmem.bytesReadSys 461504 # Total read bytes from the system interface side 40system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 41system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 42system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 43system.physmem.neitherReadNorWriteReqs 11 # Number of requests that are neither read nor write 44system.physmem.perBankRdBursts::0 592 # Per bank write bursts 45system.physmem.perBankRdBursts::1 792 # Per bank write bursts 46system.physmem.perBankRdBursts::2 603 # Per bank write bursts 47system.physmem.perBankRdBursts::3 519 # Per bank write bursts 48system.physmem.perBankRdBursts::4 437 # Per bank write bursts 49system.physmem.perBankRdBursts::5 342 # Per bank write bursts 50system.physmem.perBankRdBursts::6 159 # Per bank write bursts 51system.physmem.perBankRdBursts::7 228 # Per bank write bursts 52system.physmem.perBankRdBursts::8 208 # Per bank write bursts 53system.physmem.perBankRdBursts::9 292 # Per bank write bursts 54system.physmem.perBankRdBursts::10 317 # Per bank write bursts 55system.physmem.perBankRdBursts::11 409 # Per bank write bursts 56system.physmem.perBankRdBursts::12 526 # Per bank write bursts 57system.physmem.perBankRdBursts::13 671 # Per bank write bursts 58system.physmem.perBankRdBursts::14 612 # Per bank write bursts 59system.physmem.perBankRdBursts::15 504 # Per bank write bursts 60system.physmem.perBankWrBursts::0 0 # Per bank write bursts 61system.physmem.perBankWrBursts::1 0 # Per bank write bursts 62system.physmem.perBankWrBursts::2 0 # Per bank write bursts 63system.physmem.perBankWrBursts::3 0 # Per bank write bursts 64system.physmem.perBankWrBursts::4 0 # Per bank write bursts 65system.physmem.perBankWrBursts::5 0 # Per bank write bursts 66system.physmem.perBankWrBursts::6 0 # Per bank write bursts 67system.physmem.perBankWrBursts::7 0 # Per bank write bursts 68system.physmem.perBankWrBursts::8 0 # Per bank write bursts 69system.physmem.perBankWrBursts::9 0 # Per bank write bursts 70system.physmem.perBankWrBursts::10 0 # Per bank write bursts 71system.physmem.perBankWrBursts::11 0 # Per bank write bursts 72system.physmem.perBankWrBursts::12 0 # Per bank write bursts 73system.physmem.perBankWrBursts::13 0 # Per bank write bursts 74system.physmem.perBankWrBursts::14 0 # Per bank write bursts 75system.physmem.perBankWrBursts::15 0 # Per bank write bursts 76system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 77system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 78system.physmem.totGap 58842848000 # Total gap between requests 79system.physmem.readPktSize::0 0 # Read request sizes (log2) 80system.physmem.readPktSize::1 0 # Read request sizes (log2) 81system.physmem.readPktSize::2 0 # Read request sizes (log2) 82system.physmem.readPktSize::3 0 # Read request sizes (log2) 83system.physmem.readPktSize::4 0 # Read request sizes (log2) 84system.physmem.readPktSize::5 0 # Read request sizes (log2) 85system.physmem.readPktSize::6 7211 # Read request sizes (log2) 86system.physmem.writePktSize::0 0 # Write request sizes (log2) 87system.physmem.writePktSize::1 0 # Write request sizes (log2) 88system.physmem.writePktSize::2 0 # Write request sizes (log2) 89system.physmem.writePktSize::3 0 # Write request sizes (log2) 90system.physmem.writePktSize::4 0 # Write request sizes (log2) 91system.physmem.writePktSize::5 0 # Write request sizes (log2) 92system.physmem.writePktSize::6 0 # Write request sizes (log2) 93system.physmem.rdQLenPdf::0 4240 # What read queue length does an incoming req see 94system.physmem.rdQLenPdf::1 2012 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::2 646 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::3 244 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::4 68 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 125system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 126system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 127system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 128system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 129system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 130system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 131system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 132system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 133system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 134system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 189system.physmem.bytesPerActivate::samples 1405 # Bytes accessed per row activation 190system.physmem.bytesPerActivate::mean 327.288256 # Bytes accessed per row activation 191system.physmem.bytesPerActivate::gmean 191.332764 # Bytes accessed per row activation 192system.physmem.bytesPerActivate::stdev 342.731237 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::0-127 492 35.02% 35.02% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::128-255 350 24.91% 59.93% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::256-383 132 9.40% 69.32% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::384-511 82 5.84% 75.16% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::512-639 53 3.77% 78.93% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::640-767 47 3.35% 82.28% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::768-895 27 1.92% 84.20% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::896-1023 22 1.57% 85.77% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::1024-1151 200 14.23% 100.00% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::total 1405 # Bytes accessed per row activation 203system.physmem.totQLat 59614750 # Total ticks spent queuing 204system.physmem.totMemAccLat 194821000 # Total ticks spent from burst creation until serviced by the DRAM 205system.physmem.totBusLat 36055000 # Total ticks spent in databus transfers 206system.physmem.avgQLat 8267.20 # Average queueing delay per DRAM burst 207system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 208system.physmem.avgMemAccLat 27017.20 # Average memory access latency per DRAM burst 209system.physmem.avgRdBW 7.84 # Average DRAM read bandwidth in MiByte/s 210system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 211system.physmem.avgRdBWSys 7.84 # Average system read bandwidth in MiByte/s 212system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 213system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 214system.physmem.busUtil 0.06 # Data bus utilization in percentage 215system.physmem.busUtilRead 0.06 # Data bus utilization in percentage for reads 216system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 217system.physmem.avgRdQLen 1.12 # Average read queue length when enqueuing 218system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 219system.physmem.readRowHits 5798 # Number of row buffer hits during reads 220system.physmem.writeRowHits 0 # Number of row buffer hits during writes 221system.physmem.readRowHitRate 80.40 # Row buffer hit rate for reads 222system.physmem.writeRowHitRate nan # Row buffer hit rate for writes 223system.physmem.avgGap 8160150.88 # Average gap between requests 224system.physmem.pageHitRate 80.40 # Row buffer hit rate, read and write combined 225system.physmem.memoryStateTime::IDLE 55121576750 # Time in different power states 226system.physmem.memoryStateTime::REF 1964820000 # Time in different power states 227system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states 228system.physmem.memoryStateTime::ACT 1754568250 # Time in different power states 229system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states 230system.membus.throughput 7842974 # Throughput (bytes/s) 231system.membus.trans_dist::ReadReq 4381 # Transaction distribution 232system.membus.trans_dist::ReadResp 4381 # Transaction distribution 233system.membus.trans_dist::UpgradeReq 11 # Transaction distribution 234system.membus.trans_dist::UpgradeResp 11 # Transaction distribution 235system.membus.trans_dist::ReadExReq 2830 # Transaction distribution 236system.membus.trans_dist::ReadExResp 2830 # Transaction distribution 237system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14444 # Packet count per connected master and slave (bytes) 238system.membus.pkt_count::total 14444 # Packet count per connected master and slave (bytes) 239system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 461504 # Cumulative packet size per connected master and slave (bytes) 240system.membus.tot_pkt_size::total 461504 # Cumulative packet size per connected master and slave (bytes) 241system.membus.data_through_bus 461504 # Total data (bytes) 242system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 243system.membus.reqLayer0.occupancy 8714000 # Layer occupancy (ticks) 244system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 245system.membus.respLayer1.occupancy 67059990 # Layer occupancy (ticks) 246system.membus.respLayer1.utilization 0.1 # Layer utilization (%) 247system.cpu_clk_domain.clock 500 # Clock period in ticks 248system.cpu.branchPred.lookups 36678579 # Number of BP lookups 249system.cpu.branchPred.condPredicted 19369962 # Number of conditional branches predicted 250system.cpu.branchPred.condIncorrect 1628976 # Number of conditional branches incorrect 251system.cpu.branchPred.BTBLookups 19217639 # Number of BTB lookups 252system.cpu.branchPred.BTBHits 17291098 # Number of BTB hits 253system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 254system.cpu.branchPred.BTBHitPct 89.975142 # BTB Hit Percentage 255system.cpu.branchPred.usedRAS 7036393 # Number of times the RAS was used to get a target. 256system.cpu.branchPred.RASInCorrect 5252 # Number of incorrect RAS predictions. 257system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 258system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 259system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 260system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 261system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 262system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 263system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 264system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 265system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 266system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 267system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 268system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 269system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 270system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 271system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 272system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 273system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 274system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 275system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 276system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 277system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 278system.cpu.dtb.inst_hits 0 # ITB inst hits 279system.cpu.dtb.inst_misses 0 # ITB inst misses 280system.cpu.dtb.read_hits 0 # DTB read hits 281system.cpu.dtb.read_misses 0 # DTB read misses 282system.cpu.dtb.write_hits 0 # DTB write hits 283system.cpu.dtb.write_misses 0 # DTB write misses 284system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 285system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 286system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 287system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 288system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 289system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 290system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 291system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 292system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 293system.cpu.dtb.read_accesses 0 # DTB read accesses 294system.cpu.dtb.write_accesses 0 # DTB write accesses 295system.cpu.dtb.inst_accesses 0 # ITB inst accesses 296system.cpu.dtb.hits 0 # DTB hits 297system.cpu.dtb.misses 0 # DTB misses 298system.cpu.dtb.accesses 0 # DTB accesses 299system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 300system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 301system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 302system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 303system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 304system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 305system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 306system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 307system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 308system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 309system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 310system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 311system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 312system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 313system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 314system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 315system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 316system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 317system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 318system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 319system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 320system.cpu.itb.inst_hits 0 # ITB inst hits 321system.cpu.itb.inst_misses 0 # ITB inst misses 322system.cpu.itb.read_hits 0 # DTB read hits 323system.cpu.itb.read_misses 0 # DTB read misses 324system.cpu.itb.write_hits 0 # DTB write hits 325system.cpu.itb.write_misses 0 # DTB write misses 326system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 327system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 328system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 329system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 330system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 331system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 332system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 333system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 334system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 335system.cpu.itb.read_accesses 0 # DTB read accesses 336system.cpu.itb.write_accesses 0 # DTB write accesses 337system.cpu.itb.inst_accesses 0 # ITB inst accesses 338system.cpu.itb.hits 0 # DTB hits 339system.cpu.itb.misses 0 # DTB misses 340system.cpu.itb.accesses 0 # DTB accesses 341system.cpu.workload.num_syscalls 191 # Number of system calls 342system.cpu.numCycles 117685965 # number of cpu cycles simulated 343system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 344system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 345system.cpu.fetch.icacheStallCycles 40172132 # Number of cycles fetch is stalled on an Icache miss 346system.cpu.fetch.Insts 329927106 # Number of instructions fetch has processed 347system.cpu.fetch.Branches 36678579 # Number of branches that fetch encountered 348system.cpu.fetch.predictedBranches 24327491 # Number of branches that fetch has predicted taken 349system.cpu.fetch.Cycles 75600101 # Number of cycles fetch has run and was not squashing or blocked 350system.cpu.fetch.SquashCycles 3327960 # Number of cycles fetch has spent squashing 351system.cpu.fetch.MiscStallCycles 175 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 352system.cpu.fetch.PendingTrapStallCycles 2800 # Number of stall cycles due to pending traps 353system.cpu.fetch.IcacheWaitRetryStallCycles 41 # Number of stall cycles due to full MSHR 354system.cpu.fetch.CacheLines 38768855 # Number of cache lines fetched 355system.cpu.fetch.IcacheSquashes 530996 # Number of outstanding Icache misses that were squashed 356system.cpu.fetch.rateDist::samples 117439229 # Number of instructions fetched each cycle (Total) 357system.cpu.fetch.rateDist::mean 3.389931 # Number of instructions fetched each cycle (Total) 358system.cpu.fetch.rateDist::stdev 3.437439 # Number of instructions fetched each cycle (Total) 359system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 360system.cpu.fetch.rateDist::0 46731814 39.79% 39.79% # Number of instructions fetched each cycle (Total) 361system.cpu.fetch.rateDist::1 7329854 6.24% 46.03% # Number of instructions fetched each cycle (Total) 362system.cpu.fetch.rateDist::2 6574514 5.60% 51.63% # Number of instructions fetched each cycle (Total) 363system.cpu.fetch.rateDist::3 6398088 5.45% 57.08% # Number of instructions fetched each cycle (Total) 364system.cpu.fetch.rateDist::4 4252484 3.62% 60.70% # Number of instructions fetched each cycle (Total) 365system.cpu.fetch.rateDist::5 5520861 4.70% 65.40% # Number of instructions fetched each cycle (Total) 366system.cpu.fetch.rateDist::6 3987559 3.40% 68.80% # Number of instructions fetched each cycle (Total) 367system.cpu.fetch.rateDist::7 3254311 2.77% 71.57% # Number of instructions fetched each cycle (Total) 368system.cpu.fetch.rateDist::8 33389744 28.43% 100.00% # Number of instructions fetched each cycle (Total) 369system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 370system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 371system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 372system.cpu.fetch.rateDist::total 117439229 # Number of instructions fetched each cycle (Total) 373system.cpu.fetch.branchRate 0.311665 # Number of branch fetches per cycle 374system.cpu.fetch.rate 2.803453 # Number of inst fetches per cycle 375system.cpu.decode.IdleCycles 34271331 # Number of cycles decode is idle 376system.cpu.decode.BlockedCycles 16148849 # Number of cycles decode is blocked 377system.cpu.decode.RunCycles 61039844 # Number of cycles decode is running 378system.cpu.decode.UnblockCycles 4384832 # Number of cycles decode is unblocking 379system.cpu.decode.SquashCycles 1594373 # Number of cycles decode is squashing 380system.cpu.decode.BranchResolved 7530126 # Number of times decode resolved a branch 381system.cpu.decode.BranchMispred 70364 # Number of times decode detected a branch misprediction 382system.cpu.decode.DecodedInsts 389722126 # Number of instructions handled by decode 383system.cpu.decode.SquashedInsts 437543 # Number of squashed instructions handled by decode 384system.cpu.rename.SquashCycles 1594373 # Number of cycles rename is squashing 385system.cpu.rename.IdleCycles 37031203 # Number of cycles rename is idle 386system.cpu.rename.BlockCycles 5569218 # Number of cycles rename is blocking 387system.cpu.rename.serializeStallCycles 387986 # count of cycles rename stalled for serializing inst 388system.cpu.rename.RunCycles 62601924 # Number of cycles rename is running 389system.cpu.rename.UnblockCycles 10254525 # Number of cycles rename is unblocking 390system.cpu.rename.RenamedInsts 382340457 # Number of instructions processed by rename 391system.cpu.rename.ROBFullEvents 36 # Number of times rename has blocked due to ROB full 392system.cpu.rename.IQFullEvents 4583661 # Number of times rename has blocked due to IQ full 393system.cpu.rename.LQFullEvents 2043172 # Number of times rename has blocked due to LQ full 394system.cpu.rename.SQFullEvents 2989050 # Number of times rename has blocked due to SQ full 395system.cpu.rename.FullRegisterEvents 65700 # Number of times there has been no free registers 396system.cpu.rename.RenamedOperands 432935056 # Number of destination operands rename has renamed 397system.cpu.rename.RenameLookups 2729953830 # Number of register rename lookups that rename has made 398system.cpu.rename.int_rename_lookups 376601971 # Number of integer rename lookups 399system.cpu.rename.fp_rename_lookups 209126886 # Number of floating rename lookups 400system.cpu.rename.CommittedMaps 372229219 # Number of HB maps that are committed 401system.cpu.rename.UndoneMaps 60705837 # Number of HB maps that are undone due to squashing 402system.cpu.rename.serializingInsts 14453 # count of serializing insts renamed 403system.cpu.rename.tempSerializingInsts 15060 # count of temporary serializing insts renamed 404system.cpu.rename.skidInsts 19856485 # count of insts added to the skid buffer 405system.cpu.memDep0.insertedLoads 96101144 # Number of loads inserted to the mem dependence unit. 406system.cpu.memDep0.insertedStores 93882304 # Number of stores inserted to the mem dependence unit. 407system.cpu.memDep0.conflictingLoads 9920575 # Number of conflicting loads. 408system.cpu.memDep0.conflictingStores 10878783 # Number of conflicting stores. 409system.cpu.iq.iqInstsAdded 370378331 # Number of instructions added to the IQ (excludes non-spec) 410system.cpu.iq.iqNonSpecInstsAdded 25182 # Number of non-speculative instructions added to the IQ 411system.cpu.iq.iqInstsIssued 358744041 # Number of instructions issued 412system.cpu.iq.iqSquashedInstsIssued 1234352 # Number of squashed instructions issued 413system.cpu.iq.iqSquashedInstsExamined 42331510 # Number of squashed instructions iterated over during squash; mainly for profiling 414system.cpu.iq.iqSquashedOperandsExamined 132428138 # Number of squashed operands that are examined and possibly removed from graph 415system.cpu.iq.iqSquashedNonSpecRemoved 3062 # Number of squashed non-spec instructions that were removed 416system.cpu.iq.issued_per_cycle::samples 117439229 # Number of insts issued each cycle 417system.cpu.iq.issued_per_cycle::mean 3.054721 # Number of insts issued each cycle 418system.cpu.iq.issued_per_cycle::stdev 2.223263 # Number of insts issued each cycle 419system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 420system.cpu.iq.issued_per_cycle::0 21274018 18.11% 18.11% # Number of insts issued each cycle 421system.cpu.iq.issued_per_cycle::1 14280801 12.16% 30.28% # Number of insts issued each cycle 422system.cpu.iq.issued_per_cycle::2 14869023 12.66% 42.94% # Number of insts issued each cycle 423system.cpu.iq.issued_per_cycle::3 13830819 11.78% 54.71% # Number of insts issued each cycle 424system.cpu.iq.issued_per_cycle::4 20620243 17.56% 72.27% # Number of insts issued each cycle 425system.cpu.iq.issued_per_cycle::5 15076681 12.84% 85.11% # Number of insts issued each cycle 426system.cpu.iq.issued_per_cycle::6 10030176 8.54% 93.65% # Number of insts issued each cycle 427system.cpu.iq.issued_per_cycle::7 4472440 3.81% 97.46% # Number of insts issued each cycle 428system.cpu.iq.issued_per_cycle::8 2985028 2.54% 100.00% # Number of insts issued each cycle 429system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 430system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 431system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 432system.cpu.iq.issued_per_cycle::total 117439229 # Number of insts issued each cycle 433system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 434system.cpu.iq.fu_full::IntAlu 30566 0.13% 0.13% # attempts to use FU when none available 435system.cpu.iq.fu_full::IntMult 5035 0.02% 0.15% # attempts to use FU when none available 436system.cpu.iq.fu_full::IntDiv 0 0.00% 0.15% # attempts to use FU when none available 437system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.15% # attempts to use FU when none available 438system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.15% # attempts to use FU when none available 439system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.15% # attempts to use FU when none available 440system.cpu.iq.fu_full::FloatMult 0 0.00% 0.15% # attempts to use FU when none available 441system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.15% # attempts to use FU when none available 442system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.15% # attempts to use FU when none available 443system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.15% # attempts to use FU when none available 444system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.15% # attempts to use FU when none available 445system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.15% # attempts to use FU when none available 446system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.15% # attempts to use FU when none available 447system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.15% # attempts to use FU when none available 448system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.15% # attempts to use FU when none available 449system.cpu.iq.fu_full::SimdMult 0 0.00% 0.15% # attempts to use FU when none available 450system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.15% # attempts to use FU when none available 451system.cpu.iq.fu_full::SimdShift 0 0.00% 0.15% # attempts to use FU when none available 452system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.15% # attempts to use FU when none available 453system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.15% # attempts to use FU when none available 454system.cpu.iq.fu_full::SimdFloatAdd 218902 0.91% 1.06% # attempts to use FU when none available 455system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.06% # attempts to use FU when none available 456system.cpu.iq.fu_full::SimdFloatCmp 207576 0.86% 1.92% # attempts to use FU when none available 457system.cpu.iq.fu_full::SimdFloatCvt 15328 0.06% 1.98% # attempts to use FU when none available 458system.cpu.iq.fu_full::SimdFloatDiv 1824 0.01% 1.99% # attempts to use FU when none available 459system.cpu.iq.fu_full::SimdFloatMisc 338916 1.41% 3.39% # attempts to use FU when none available 460system.cpu.iq.fu_full::SimdFloatMult 30886 0.13% 3.52% # attempts to use FU when none available 461system.cpu.iq.fu_full::SimdFloatMultAcc 130712 0.54% 4.07% # attempts to use FU when none available 462system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.07% # attempts to use FU when none available 463system.cpu.iq.fu_full::MemRead 13684069 56.78% 60.84% # attempts to use FU when none available 464system.cpu.iq.fu_full::MemWrite 9438097 39.16% 100.00% # attempts to use FU when none available 465system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 466system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 467system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 468system.cpu.iq.FU_type_0::IntAlu 114997382 32.06% 32.06% # Type of FU issued 469system.cpu.iq.FU_type_0::IntMult 2177572 0.61% 32.66% # Type of FU issued 470system.cpu.iq.FU_type_0::IntDiv 0 0.00% 32.66% # Type of FU issued 471system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 32.66% # Type of FU issued 472system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 32.66% # Type of FU issued 473system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 32.66% # Type of FU issued 474system.cpu.iq.FU_type_0::FloatMult 0 0.00% 32.66% # Type of FU issued 475system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 32.66% # Type of FU issued 476system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 32.66% # Type of FU issued 477system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 32.66% # Type of FU issued 478system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 32.66% # Type of FU issued 479system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 32.66% # Type of FU issued 480system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 32.66% # Type of FU issued 481system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 32.66% # Type of FU issued 482system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 32.66% # Type of FU issued 483system.cpu.iq.FU_type_0::SimdMult 0 0.00% 32.66% # Type of FU issued 484system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 32.66% # Type of FU issued 485system.cpu.iq.FU_type_0::SimdShift 0 0.00% 32.66% # Type of FU issued 486system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 32.66% # Type of FU issued 487system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 32.66% # Type of FU issued 488system.cpu.iq.FU_type_0::SimdFloatAdd 6789188 1.89% 34.56% # Type of FU issued 489system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 34.56% # Type of FU issued 490system.cpu.iq.FU_type_0::SimdFloatCmp 8562613 2.39% 36.94% # Type of FU issued 491system.cpu.iq.FU_type_0::SimdFloatCvt 3491505 0.97% 37.92% # Type of FU issued 492system.cpu.iq.FU_type_0::SimdFloatDiv 1605361 0.45% 38.36% # Type of FU issued 493system.cpu.iq.FU_type_0::SimdFloatMisc 21185799 5.91% 44.27% # Type of FU issued 494system.cpu.iq.FU_type_0::SimdFloatMult 7196318 2.01% 46.27% # Type of FU issued 495system.cpu.iq.FU_type_0::SimdFloatMultAcc 7147739 1.99% 48.27% # Type of FU issued 496system.cpu.iq.FU_type_0::SimdFloatSqrt 183217 0.05% 48.32% # Type of FU issued 497system.cpu.iq.FU_type_0::MemRead 95472748 26.61% 74.93% # Type of FU issued 498system.cpu.iq.FU_type_0::MemWrite 89934599 25.07% 100.00% # Type of FU issued 499system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 500system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 501system.cpu.iq.FU_type_0::total 358744041 # Type of FU issued 502system.cpu.iq.rate 3.048316 # Inst issue rate 503system.cpu.iq.fu_busy_cnt 24101911 # FU busy when requested 504system.cpu.iq.fu_busy_rate 0.067184 # FU busy rate (busy events/executed inst) 505system.cpu.iq.int_inst_queue_reads 600140343 # Number of integer instruction queue reads 506system.cpu.iq.int_inst_queue_writes 274631052 # Number of integer instruction queue writes 507system.cpu.iq.int_inst_queue_wakeup_accesses 231134438 # Number of integer instruction queue wakeup accesses 508system.cpu.iq.fp_inst_queue_reads 260123231 # Number of floating instruction queue reads 509system.cpu.iq.fp_inst_queue_writes 138160310 # Number of floating instruction queue writes 510system.cpu.iq.fp_inst_queue_wakeup_accesses 119811956 # Number of floating instruction queue wakeup accesses 511system.cpu.iq.int_alu_accesses 246702850 # Number of integer alu accesses 512system.cpu.iq.fp_alu_accesses 136143102 # Number of floating point alu accesses 513system.cpu.iew.lsq.thread0.forwLoads 13691987 # Number of loads that had data forwarded from stores 514system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 515system.cpu.iew.lsq.thread0.squashedLoads 10368919 # Number of loads squashed 516system.cpu.iew.lsq.thread0.ignoredResponses 114059 # Number of memory responses ignored because the instruction is squashed 517system.cpu.iew.lsq.thread0.memOrderViolation 68397 # Number of memory ordering violations 518system.cpu.iew.lsq.thread0.squashedStores 11506726 # Number of stores squashed 519system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 520system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 521system.cpu.iew.lsq.thread0.rescheduledLoads 1395971 # Number of loads that were rescheduled 522system.cpu.iew.lsq.thread0.cacheBlocked 850 # Number of times an access to memory failed due to the cache being blocked 523system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 524system.cpu.iew.iewSquashCycles 1594373 # Number of cycles IEW is squashing 525system.cpu.iew.iewBlockCycles 4558099 # Number of cycles IEW is blocking 526system.cpu.iew.iewUnblockCycles 129859 # Number of cycles IEW is unblocking 527system.cpu.iew.iewDispatchedInsts 370404619 # Number of instructions dispatched to IQ 528system.cpu.iew.iewDispSquashedInsts 1080086 # Number of squashed instructions skipped by dispatch 529system.cpu.iew.iewDispLoadInsts 96101144 # Number of dispatched load instructions 530system.cpu.iew.iewDispStoreInsts 93882304 # Number of dispatched store instructions 531system.cpu.iew.iewDispNonSpecInsts 14149 # Number of dispatched non-speculative instructions 532system.cpu.iew.iewIQFullEvents 21825 # Number of times the IQ has become full, causing a stall 533system.cpu.iew.iewLSQFullEvents 109033 # Number of times the LSQ has become full, causing a stall 534system.cpu.iew.memOrderViolationEvents 68397 # Number of memory order violations 535system.cpu.iew.predictedTakenIncorrect 1241378 # Number of branches that were predicted taken incorrectly 536system.cpu.iew.predictedNotTakenIncorrect 435662 # Number of branches that were predicted not taken incorrectly 537system.cpu.iew.branchMispredicts 1677040 # Number of branch mispredicts detected at execute 538system.cpu.iew.iewExecutedInsts 354745077 # Number of executed instructions 539system.cpu.iew.iewExecLoadInsts 94263609 # Number of load instructions executed 540system.cpu.iew.iewExecSquashedInsts 3998964 # Number of squashed instructions skipped in execute 541system.cpu.iew.exec_swp 0 # number of swp insts executed 542system.cpu.iew.exec_nop 1106 # number of nop insts executed 543system.cpu.iew.exec_refs 182843438 # number of memory reference insts executed 544system.cpu.iew.exec_branches 32405794 # Number of branches executed 545system.cpu.iew.exec_stores 88579829 # Number of stores executed 546system.cpu.iew.exec_rate 3.014336 # Inst execution rate 547system.cpu.iew.wb_sent 352024494 # cumulative count of insts sent to commit 548system.cpu.iew.wb_count 350946394 # cumulative count of insts written-back 549system.cpu.iew.wb_producers 175212964 # num instructions producing a value 550system.cpu.iew.wb_consumers 355804607 # num instructions consuming a value 551system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 552system.cpu.iew.wb_rate 2.982058 # insts written-back per cycle 553system.cpu.iew.wb_fanout 0.492442 # average fanout of values written-back 554system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 555system.cpu.commit.commitSquashedInsts 42598489 # The number of squashed insts skipped by commit 556system.cpu.commit.commitNonSpecStalls 22120 # The number of times commit has been forced to stall to communicate backwards 557system.cpu.commit.branchMispredicts 1559369 # The number of times a branch was mispredicted 558system.cpu.commit.committed_per_cycle::samples 111323846 # Number of insts commited each cycle 559system.cpu.commit.committed_per_cycle::mean 2.944667 # Number of insts commited each cycle 560system.cpu.commit.committed_per_cycle::stdev 2.904010 # Number of insts commited each cycle 561system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 562system.cpu.commit.committed_per_cycle::0 29334492 26.35% 26.35% # Number of insts commited each cycle 563system.cpu.commit.committed_per_cycle::1 21002495 18.87% 45.22% # Number of insts commited each cycle 564system.cpu.commit.committed_per_cycle::2 12438899 11.17% 56.39% # Number of insts commited each cycle 565system.cpu.commit.committed_per_cycle::3 8843852 7.94% 64.33% # Number of insts commited each cycle 566system.cpu.commit.committed_per_cycle::4 8943359 8.03% 72.37% # Number of insts commited each cycle 567system.cpu.commit.committed_per_cycle::5 5286497 4.75% 77.12% # Number of insts commited each cycle 568system.cpu.commit.committed_per_cycle::6 3580965 3.22% 80.33% # Number of insts commited each cycle 569system.cpu.commit.committed_per_cycle::7 3438245 3.09% 83.42% # Number of insts commited each cycle 570system.cpu.commit.committed_per_cycle::8 18455042 16.58% 100.00% # Number of insts commited each cycle 571system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 572system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 573system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 574system.cpu.commit.committed_per_cycle::total 111323846 # Number of insts commited each cycle 575system.cpu.commit.committedInsts 273037268 # Number of instructions committed 576system.cpu.commit.committedOps 327811611 # Number of ops (including micro ops) committed 577system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 578system.cpu.commit.refs 168107803 # Number of memory references committed 579system.cpu.commit.loads 85732225 # Number of loads committed 580system.cpu.commit.membars 11033 # Number of memory barriers committed 581system.cpu.commit.branches 30563485 # Number of branches committed 582system.cpu.commit.fp_insts 114216705 # Number of committed floating point instructions. 583system.cpu.commit.int_insts 258331174 # Number of committed integer instructions. 584system.cpu.commit.function_calls 6225112 # Number of function calls committed. 585system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 586system.cpu.commit.op_class_0::IntAlu 104312045 31.82% 31.82% # Class of committed instruction 587system.cpu.commit.op_class_0::IntMult 2145845 0.65% 32.48% # Class of committed instruction 588system.cpu.commit.op_class_0::IntDiv 0 0.00% 32.48% # Class of committed instruction 589system.cpu.commit.op_class_0::FloatAdd 0 0.00% 32.48% # Class of committed instruction 590system.cpu.commit.op_class_0::FloatCmp 0 0.00% 32.48% # Class of committed instruction 591system.cpu.commit.op_class_0::FloatCvt 0 0.00% 32.48% # Class of committed instruction 592system.cpu.commit.op_class_0::FloatMult 0 0.00% 32.48% # Class of committed instruction 593system.cpu.commit.op_class_0::FloatDiv 0 0.00% 32.48% # Class of committed instruction 594system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 32.48% # Class of committed instruction 595system.cpu.commit.op_class_0::SimdAdd 0 0.00% 32.48% # Class of committed instruction 596system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 32.48% # Class of committed instruction 597system.cpu.commit.op_class_0::SimdAlu 0 0.00% 32.48% # Class of committed instruction 598system.cpu.commit.op_class_0::SimdCmp 0 0.00% 32.48% # Class of committed instruction 599system.cpu.commit.op_class_0::SimdCvt 0 0.00% 32.48% # Class of committed instruction 600system.cpu.commit.op_class_0::SimdMisc 0 0.00% 32.48% # Class of committed instruction 601system.cpu.commit.op_class_0::SimdMult 0 0.00% 32.48% # Class of committed instruction 602system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 32.48% # Class of committed instruction 603system.cpu.commit.op_class_0::SimdShift 0 0.00% 32.48% # Class of committed instruction 604system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 32.48% # Class of committed instruction 605system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 32.48% # Class of committed instruction 606system.cpu.commit.op_class_0::SimdFloatAdd 6594343 2.01% 34.49% # Class of committed instruction 607system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 34.49% # Class of committed instruction 608system.cpu.commit.op_class_0::SimdFloatCmp 7943502 2.42% 36.91% # Class of committed instruction 609system.cpu.commit.op_class_0::SimdFloatCvt 3118180 0.95% 37.86% # Class of committed instruction 610system.cpu.commit.op_class_0::SimdFloatDiv 1563217 0.48% 38.34% # Class of committed instruction 611system.cpu.commit.op_class_0::SimdFloatMisc 19652356 6.00% 44.33% # Class of committed instruction 612system.cpu.commit.op_class_0::SimdFloatMult 7136937 2.18% 46.51% # Class of committed instruction 613system.cpu.commit.op_class_0::SimdFloatMultAcc 7062098 2.15% 48.66% # Class of committed instruction 614system.cpu.commit.op_class_0::SimdFloatSqrt 175285 0.05% 48.72% # Class of committed instruction 615system.cpu.commit.op_class_0::MemRead 85732225 26.15% 74.87% # Class of committed instruction 616system.cpu.commit.op_class_0::MemWrite 82375578 25.13% 100.00% # Class of committed instruction 617system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 618system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 619system.cpu.commit.op_class_0::total 327811611 # Class of committed instruction 620system.cpu.commit.bw_lim_events 18455042 # number cycles where commit BW limit reached 621system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 622system.cpu.rob.rob_reads 463276381 # The number of ROB reads 623system.cpu.rob.rob_writes 746948197 # The number of ROB writes 624system.cpu.timesIdled 5570 # Number of times that the entire CPU went into an idle state and unscheduled itself 625system.cpu.idleCycles 246736 # Total number of cycles that the CPU has spent unscheduled due to idling 626system.cpu.committedInsts 273036656 # Number of Instructions Simulated 627system.cpu.committedOps 327810999 # Number of Ops (including micro ops) Simulated 628system.cpu.cpi 0.431026 # CPI: Cycles Per Instruction 629system.cpu.cpi_total 0.431026 # CPI: Total CPI of All Threads 630system.cpu.ipc 2.320044 # IPC: Instructions Per Cycle 631system.cpu.ipc_total 2.320044 # IPC: Total IPC of All Threads 632system.cpu.int_regfile_reads 344698387 # number of integer regfile reads 633system.cpu.int_regfile_writes 141985623 # number of integer regfile writes 634system.cpu.fp_regfile_reads 189510679 # number of floating regfile reads 635system.cpu.fp_regfile_writes 134618624 # number of floating regfile writes 636system.cpu.cc_regfile_reads 1340695625 # number of cc regfile reads 637system.cpu.cc_regfile_writes 80827327 # number of cc regfile writes 638system.cpu.misc_regfile_reads 1216328122 # number of misc regfile reads 639system.cpu.misc_regfile_writes 34421755 # number of misc regfile writes 640system.cpu.toL2Bus.throughput 23209157 # Throughput (bytes/s) 641system.cpu.toL2Bus.trans_dist::ReadReq 17471 # Transaction distribution 642system.cpu.toL2Bus.trans_dist::ReadResp 17471 # Transaction distribution 643system.cpu.toL2Bus.trans_dist::Writeback 1022 # Transaction distribution 644system.cpu.toL2Bus.trans_dist::UpgradeReq 12 # Transaction distribution 645system.cpu.toL2Bus.trans_dist::UpgradeResp 12 # Transaction distribution 646system.cpu.toL2Bus.trans_dist::ReadExReq 2846 # Transaction distribution 647system.cpu.toL2Bus.trans_dist::ReadExResp 2846 # Transaction distribution 648system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 31432 # Packet count per connected master and slave (bytes) 649system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10234 # Packet count per connected master and slave (bytes) 650system.cpu.toL2Bus.pkt_count::total 41666 # Packet count per connected master and slave (bytes) 651system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1005376 # Cumulative packet size per connected master and slave (bytes) 652system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 359424 # Cumulative packet size per connected master and slave (bytes) 653system.cpu.toL2Bus.tot_pkt_size::total 1364800 # Cumulative packet size per connected master and slave (bytes) 654system.cpu.toL2Bus.data_through_bus 1364800 # Total data (bytes) 655system.cpu.toL2Bus.snoop_data_through_bus 896 # Total snoop data (bytes) 656system.cpu.toL2Bus.reqLayer0.occupancy 11697999 # Layer occupancy (ticks) 657system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 658system.cpu.toL2Bus.respLayer0.occupancy 24104992 # Layer occupancy (ticks) 659system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 660system.cpu.toL2Bus.respLayer1.occupancy 7380470 # Layer occupancy (ticks) 661system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 662system.cpu.icache.tags.replacements 13841 # number of replacements 663system.cpu.icache.tags.tagsinuse 1830.861112 # Cycle average of tags in use 664system.cpu.icache.tags.total_refs 38751311 # Total number of references to valid blocks. 665system.cpu.icache.tags.sampled_refs 15711 # Sample count of references to valid blocks. 666system.cpu.icache.tags.avg_refs 2466.508243 # Average number of references to valid blocks. 667system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 668system.cpu.icache.tags.occ_blocks::cpu.inst 1830.861112 # Average occupied blocks per requestor 669system.cpu.icache.tags.occ_percent::cpu.inst 0.893975 # Average percentage of cache occupancy 670system.cpu.icache.tags.occ_percent::total 0.893975 # Average percentage of cache occupancy 671system.cpu.icache.tags.occ_task_id_blocks::1024 1870 # Occupied blocks per task id 672system.cpu.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id 673system.cpu.icache.tags.age_task_id_blocks_1024::1 92 # Occupied blocks per task id 674system.cpu.icache.tags.age_task_id_blocks_1024::2 194 # Occupied blocks per task id 675system.cpu.icache.tags.age_task_id_blocks_1024::3 9 # Occupied blocks per task id 676system.cpu.icache.tags.age_task_id_blocks_1024::4 1522 # Occupied blocks per task id 677system.cpu.icache.tags.occ_task_id_percent::1024 0.913086 # Percentage of cache occupancy per task id 678system.cpu.icache.tags.tag_accesses 77553427 # Number of tag accesses 679system.cpu.icache.tags.data_accesses 77553427 # Number of data accesses 680system.cpu.icache.ReadReq_hits::cpu.inst 38751328 # number of ReadReq hits 681system.cpu.icache.ReadReq_hits::total 38751328 # number of ReadReq hits 682system.cpu.icache.demand_hits::cpu.inst 38751328 # number of demand (read+write) hits 683system.cpu.icache.demand_hits::total 38751328 # number of demand (read+write) hits 684system.cpu.icache.overall_hits::cpu.inst 38751328 # number of overall hits 685system.cpu.icache.overall_hits::total 38751328 # number of overall hits 686system.cpu.icache.ReadReq_misses::cpu.inst 17524 # number of ReadReq misses 687system.cpu.icache.ReadReq_misses::total 17524 # number of ReadReq misses 688system.cpu.icache.demand_misses::cpu.inst 17524 # number of demand (read+write) misses 689system.cpu.icache.demand_misses::total 17524 # number of demand (read+write) misses 690system.cpu.icache.overall_misses::cpu.inst 17524 # number of overall misses 691system.cpu.icache.overall_misses::total 17524 # number of overall misses 692system.cpu.icache.ReadReq_miss_latency::cpu.inst 439561740 # number of ReadReq miss cycles 693system.cpu.icache.ReadReq_miss_latency::total 439561740 # number of ReadReq miss cycles 694system.cpu.icache.demand_miss_latency::cpu.inst 439561740 # number of demand (read+write) miss cycles 695system.cpu.icache.demand_miss_latency::total 439561740 # number of demand (read+write) miss cycles 696system.cpu.icache.overall_miss_latency::cpu.inst 439561740 # number of overall miss cycles 697system.cpu.icache.overall_miss_latency::total 439561740 # number of overall miss cycles 698system.cpu.icache.ReadReq_accesses::cpu.inst 38768852 # number of ReadReq accesses(hits+misses) 699system.cpu.icache.ReadReq_accesses::total 38768852 # number of ReadReq accesses(hits+misses) 700system.cpu.icache.demand_accesses::cpu.inst 38768852 # number of demand (read+write) accesses 701system.cpu.icache.demand_accesses::total 38768852 # number of demand (read+write) accesses 702system.cpu.icache.overall_accesses::cpu.inst 38768852 # number of overall (read+write) accesses 703system.cpu.icache.overall_accesses::total 38768852 # number of overall (read+write) accesses 704system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000452 # miss rate for ReadReq accesses 705system.cpu.icache.ReadReq_miss_rate::total 0.000452 # miss rate for ReadReq accesses 706system.cpu.icache.demand_miss_rate::cpu.inst 0.000452 # miss rate for demand accesses 707system.cpu.icache.demand_miss_rate::total 0.000452 # miss rate for demand accesses 708system.cpu.icache.overall_miss_rate::cpu.inst 0.000452 # miss rate for overall accesses 709system.cpu.icache.overall_miss_rate::total 0.000452 # miss rate for overall accesses 710system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25083.413604 # average ReadReq miss latency 711system.cpu.icache.ReadReq_avg_miss_latency::total 25083.413604 # average ReadReq miss latency 712system.cpu.icache.demand_avg_miss_latency::cpu.inst 25083.413604 # average overall miss latency 713system.cpu.icache.demand_avg_miss_latency::total 25083.413604 # average overall miss latency 714system.cpu.icache.overall_avg_miss_latency::cpu.inst 25083.413604 # average overall miss latency 715system.cpu.icache.overall_avg_miss_latency::total 25083.413604 # average overall miss latency 716system.cpu.icache.blocked_cycles::no_mshrs 684 # number of cycles access was blocked 717system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 718system.cpu.icache.blocked::no_mshrs 12 # number of cycles access was blocked 719system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 720system.cpu.icache.avg_blocked_cycles::no_mshrs 57 # average number of cycles each access was blocked 721system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 722system.cpu.icache.fast_writes 0 # number of fast writes performed 723system.cpu.icache.cache_copies 0 # number of cache copies performed 724system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1801 # number of ReadReq MSHR hits 725system.cpu.icache.ReadReq_mshr_hits::total 1801 # number of ReadReq MSHR hits 726system.cpu.icache.demand_mshr_hits::cpu.inst 1801 # number of demand (read+write) MSHR hits 727system.cpu.icache.demand_mshr_hits::total 1801 # number of demand (read+write) MSHR hits 728system.cpu.icache.overall_mshr_hits::cpu.inst 1801 # number of overall MSHR hits 729system.cpu.icache.overall_mshr_hits::total 1801 # number of overall MSHR hits 730system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15723 # number of ReadReq MSHR misses 731system.cpu.icache.ReadReq_mshr_misses::total 15723 # number of ReadReq MSHR misses 732system.cpu.icache.demand_mshr_misses::cpu.inst 15723 # number of demand (read+write) MSHR misses 733system.cpu.icache.demand_mshr_misses::total 15723 # number of demand (read+write) MSHR misses 734system.cpu.icache.overall_mshr_misses::cpu.inst 15723 # number of overall MSHR misses 735system.cpu.icache.overall_mshr_misses::total 15723 # number of overall MSHR misses 736system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 350218008 # number of ReadReq MSHR miss cycles 737system.cpu.icache.ReadReq_mshr_miss_latency::total 350218008 # number of ReadReq MSHR miss cycles 738system.cpu.icache.demand_mshr_miss_latency::cpu.inst 350218008 # number of demand (read+write) MSHR miss cycles 739system.cpu.icache.demand_mshr_miss_latency::total 350218008 # number of demand (read+write) MSHR miss cycles 740system.cpu.icache.overall_mshr_miss_latency::cpu.inst 350218008 # number of overall MSHR miss cycles 741system.cpu.icache.overall_mshr_miss_latency::total 350218008 # number of overall MSHR miss cycles 742system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000406 # mshr miss rate for ReadReq accesses 743system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000406 # mshr miss rate for ReadReq accesses 744system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000406 # mshr miss rate for demand accesses 745system.cpu.icache.demand_mshr_miss_rate::total 0.000406 # mshr miss rate for demand accesses 746system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000406 # mshr miss rate for overall accesses 747system.cpu.icache.overall_mshr_miss_rate::total 0.000406 # mshr miss rate for overall accesses 748system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22274.248426 # average ReadReq mshr miss latency 749system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22274.248426 # average ReadReq mshr miss latency 750system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22274.248426 # average overall mshr miss latency 751system.cpu.icache.demand_avg_mshr_miss_latency::total 22274.248426 # average overall mshr miss latency 752system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22274.248426 # average overall mshr miss latency 753system.cpu.icache.overall_avg_mshr_miss_latency::total 22274.248426 # average overall mshr miss latency 754system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 755system.cpu.l2cache.tags.replacements 0 # number of replacements 756system.cpu.l2cache.tags.tagsinuse 3837.051468 # Cycle average of tags in use 757system.cpu.l2cache.tags.total_refs 13121 # Total number of references to valid blocks. 758system.cpu.l2cache.tags.sampled_refs 5294 # Sample count of references to valid blocks. 759system.cpu.l2cache.tags.avg_refs 2.478466 # Average number of references to valid blocks. 760system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 761system.cpu.l2cache.tags.occ_blocks::writebacks 357.151307 # Average occupied blocks per requestor 762system.cpu.l2cache.tags.occ_blocks::cpu.inst 2707.112582 # Average occupied blocks per requestor 763system.cpu.l2cache.tags.occ_blocks::cpu.data 772.787579 # Average occupied blocks per requestor 764system.cpu.l2cache.tags.occ_percent::writebacks 0.010899 # Average percentage of cache occupancy 765system.cpu.l2cache.tags.occ_percent::cpu.inst 0.082615 # Average percentage of cache occupancy 766system.cpu.l2cache.tags.occ_percent::cpu.data 0.023584 # Average percentage of cache occupancy 767system.cpu.l2cache.tags.occ_percent::total 0.117098 # Average percentage of cache occupancy 768system.cpu.l2cache.tags.occ_task_id_blocks::1024 5294 # Occupied blocks per task id 769system.cpu.l2cache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id 770system.cpu.l2cache.tags.age_task_id_blocks_1024::1 69 # Occupied blocks per task id 771system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1246 # Occupied blocks per task id 772system.cpu.l2cache.tags.age_task_id_blocks_1024::3 12 # Occupied blocks per task id 773system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3911 # Occupied blocks per task id 774system.cpu.l2cache.tags.occ_task_id_percent::1024 0.161560 # Percentage of cache occupancy per task id 775system.cpu.l2cache.tags.tag_accesses 178837 # Number of tag accesses 776system.cpu.l2cache.tags.data_accesses 178837 # Number of data accesses 777system.cpu.l2cache.ReadReq_hits::cpu.inst 12742 # number of ReadReq hits 778system.cpu.l2cache.ReadReq_hits::cpu.data 286 # number of ReadReq hits 779system.cpu.l2cache.ReadReq_hits::total 13028 # number of ReadReq hits 780system.cpu.l2cache.Writeback_hits::writebacks 1022 # number of Writeback hits 781system.cpu.l2cache.Writeback_hits::total 1022 # number of Writeback hits 782system.cpu.l2cache.UpgradeReq_hits::cpu.data 1 # number of UpgradeReq hits 783system.cpu.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits 784system.cpu.l2cache.ReadExReq_hits::cpu.data 16 # number of ReadExReq hits 785system.cpu.l2cache.ReadExReq_hits::total 16 # number of ReadExReq hits 786system.cpu.l2cache.demand_hits::cpu.inst 12742 # number of demand (read+write) hits 787system.cpu.l2cache.demand_hits::cpu.data 302 # number of demand (read+write) hits 788system.cpu.l2cache.demand_hits::total 13044 # number of demand (read+write) hits 789system.cpu.l2cache.overall_hits::cpu.inst 12742 # number of overall hits 790system.cpu.l2cache.overall_hits::cpu.data 302 # number of overall hits 791system.cpu.l2cache.overall_hits::total 13044 # number of overall hits 792system.cpu.l2cache.ReadReq_misses::cpu.inst 2967 # number of ReadReq misses 793system.cpu.l2cache.ReadReq_misses::cpu.data 1462 # number of ReadReq misses 794system.cpu.l2cache.ReadReq_misses::total 4429 # number of ReadReq misses 795system.cpu.l2cache.UpgradeReq_misses::cpu.data 11 # number of UpgradeReq misses 796system.cpu.l2cache.UpgradeReq_misses::total 11 # number of UpgradeReq misses 797system.cpu.l2cache.ReadExReq_misses::cpu.data 2830 # number of ReadExReq misses 798system.cpu.l2cache.ReadExReq_misses::total 2830 # number of ReadExReq misses 799system.cpu.l2cache.demand_misses::cpu.inst 2967 # number of demand (read+write) misses 800system.cpu.l2cache.demand_misses::cpu.data 4292 # number of demand (read+write) misses 801system.cpu.l2cache.demand_misses::total 7259 # number of demand (read+write) misses 802system.cpu.l2cache.overall_misses::cpu.inst 2967 # number of overall misses 803system.cpu.l2cache.overall_misses::cpu.data 4292 # number of overall misses 804system.cpu.l2cache.overall_misses::total 7259 # number of overall misses 805system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 207032250 # number of ReadReq miss cycles 806system.cpu.l2cache.ReadReq_miss_latency::cpu.data 106837750 # number of ReadReq miss cycles 807system.cpu.l2cache.ReadReq_miss_latency::total 313870000 # number of ReadReq miss cycles 808system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 202417250 # number of ReadExReq miss cycles 809system.cpu.l2cache.ReadExReq_miss_latency::total 202417250 # number of ReadExReq miss cycles 810system.cpu.l2cache.demand_miss_latency::cpu.inst 207032250 # number of demand (read+write) miss cycles 811system.cpu.l2cache.demand_miss_latency::cpu.data 309255000 # number of demand (read+write) miss cycles 812system.cpu.l2cache.demand_miss_latency::total 516287250 # number of demand (read+write) miss cycles 813system.cpu.l2cache.overall_miss_latency::cpu.inst 207032250 # number of overall miss cycles 814system.cpu.l2cache.overall_miss_latency::cpu.data 309255000 # number of overall miss cycles 815system.cpu.l2cache.overall_miss_latency::total 516287250 # number of overall miss cycles 816system.cpu.l2cache.ReadReq_accesses::cpu.inst 15709 # number of ReadReq accesses(hits+misses) 817system.cpu.l2cache.ReadReq_accesses::cpu.data 1748 # number of ReadReq accesses(hits+misses) 818system.cpu.l2cache.ReadReq_accesses::total 17457 # number of ReadReq accesses(hits+misses) 819system.cpu.l2cache.Writeback_accesses::writebacks 1022 # number of Writeback accesses(hits+misses) 820system.cpu.l2cache.Writeback_accesses::total 1022 # number of Writeback accesses(hits+misses) 821system.cpu.l2cache.UpgradeReq_accesses::cpu.data 12 # number of UpgradeReq accesses(hits+misses) 822system.cpu.l2cache.UpgradeReq_accesses::total 12 # number of UpgradeReq accesses(hits+misses) 823system.cpu.l2cache.ReadExReq_accesses::cpu.data 2846 # number of ReadExReq accesses(hits+misses) 824system.cpu.l2cache.ReadExReq_accesses::total 2846 # number of ReadExReq accesses(hits+misses) 825system.cpu.l2cache.demand_accesses::cpu.inst 15709 # number of demand (read+write) accesses 826system.cpu.l2cache.demand_accesses::cpu.data 4594 # number of demand (read+write) accesses 827system.cpu.l2cache.demand_accesses::total 20303 # number of demand (read+write) accesses 828system.cpu.l2cache.overall_accesses::cpu.inst 15709 # number of overall (read+write) accesses 829system.cpu.l2cache.overall_accesses::cpu.data 4594 # number of overall (read+write) accesses 830system.cpu.l2cache.overall_accesses::total 20303 # number of overall (read+write) accesses 831system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.188873 # miss rate for ReadReq accesses 832system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.836384 # miss rate for ReadReq accesses 833system.cpu.l2cache.ReadReq_miss_rate::total 0.253709 # miss rate for ReadReq accesses 834system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.916667 # miss rate for UpgradeReq accesses 835system.cpu.l2cache.UpgradeReq_miss_rate::total 0.916667 # miss rate for UpgradeReq accesses 836system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.994378 # miss rate for ReadExReq accesses 837system.cpu.l2cache.ReadExReq_miss_rate::total 0.994378 # miss rate for ReadExReq accesses 838system.cpu.l2cache.demand_miss_rate::cpu.inst 0.188873 # miss rate for demand accesses 839system.cpu.l2cache.demand_miss_rate::cpu.data 0.934262 # miss rate for demand accesses 840system.cpu.l2cache.demand_miss_rate::total 0.357533 # miss rate for demand accesses 841system.cpu.l2cache.overall_miss_rate::cpu.inst 0.188873 # miss rate for overall accesses 842system.cpu.l2cache.overall_miss_rate::cpu.data 0.934262 # miss rate for overall accesses 843system.cpu.l2cache.overall_miss_rate::total 0.357533 # miss rate for overall accesses 844system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69778.311426 # average ReadReq miss latency 845system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 73076.436389 # average ReadReq miss latency 846system.cpu.l2cache.ReadReq_avg_miss_latency::total 70867.012870 # average ReadReq miss latency 847system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71525.530035 # average ReadExReq miss latency 848system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71525.530035 # average ReadExReq miss latency 849system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69778.311426 # average overall miss latency 850system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72053.821062 # average overall miss latency 851system.cpu.l2cache.demand_avg_miss_latency::total 71123.742940 # average overall miss latency 852system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69778.311426 # average overall miss latency 853system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72053.821062 # average overall miss latency 854system.cpu.l2cache.overall_avg_miss_latency::total 71123.742940 # average overall miss latency 855system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 856system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 857system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 858system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 859system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 860system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 861system.cpu.l2cache.fast_writes 0 # number of fast writes performed 862system.cpu.l2cache.cache_copies 0 # number of cache copies performed 863system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 8 # number of ReadReq MSHR hits 864system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 40 # number of ReadReq MSHR hits 865system.cpu.l2cache.ReadReq_mshr_hits::total 48 # number of ReadReq MSHR hits 866system.cpu.l2cache.demand_mshr_hits::cpu.inst 8 # number of demand (read+write) MSHR hits 867system.cpu.l2cache.demand_mshr_hits::cpu.data 40 # number of demand (read+write) MSHR hits 868system.cpu.l2cache.demand_mshr_hits::total 48 # number of demand (read+write) MSHR hits 869system.cpu.l2cache.overall_mshr_hits::cpu.inst 8 # number of overall MSHR hits 870system.cpu.l2cache.overall_mshr_hits::cpu.data 40 # number of overall MSHR hits 871system.cpu.l2cache.overall_mshr_hits::total 48 # number of overall MSHR hits 872system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2959 # number of ReadReq MSHR misses 873system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1422 # number of ReadReq MSHR misses 874system.cpu.l2cache.ReadReq_mshr_misses::total 4381 # number of ReadReq MSHR misses 875system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 11 # number of UpgradeReq MSHR misses 876system.cpu.l2cache.UpgradeReq_mshr_misses::total 11 # number of UpgradeReq MSHR misses 877system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 2830 # number of ReadExReq MSHR misses 878system.cpu.l2cache.ReadExReq_mshr_misses::total 2830 # number of ReadExReq MSHR misses 879system.cpu.l2cache.demand_mshr_misses::cpu.inst 2959 # number of demand (read+write) MSHR misses 880system.cpu.l2cache.demand_mshr_misses::cpu.data 4252 # number of demand (read+write) MSHR misses 881system.cpu.l2cache.demand_mshr_misses::total 7211 # number of demand (read+write) MSHR misses 882system.cpu.l2cache.overall_mshr_misses::cpu.inst 2959 # number of overall MSHR misses 883system.cpu.l2cache.overall_mshr_misses::cpu.data 4252 # number of overall MSHR misses 884system.cpu.l2cache.overall_mshr_misses::total 7211 # number of overall MSHR misses 885system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 169394250 # number of ReadReq MSHR miss cycles 886system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 86707000 # number of ReadReq MSHR miss cycles 887system.cpu.l2cache.ReadReq_mshr_miss_latency::total 256101250 # number of ReadReq MSHR miss cycles 888system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 112009 # number of UpgradeReq MSHR miss cycles 889system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 112009 # number of UpgradeReq MSHR miss cycles 890system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 167488250 # number of ReadExReq MSHR miss cycles 891system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 167488250 # number of ReadExReq MSHR miss cycles 892system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 169394250 # number of demand (read+write) MSHR miss cycles 893system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 254195250 # number of demand (read+write) MSHR miss cycles 894system.cpu.l2cache.demand_mshr_miss_latency::total 423589500 # number of demand (read+write) MSHR miss cycles 895system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 169394250 # number of overall MSHR miss cycles 896system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 254195250 # number of overall MSHR miss cycles 897system.cpu.l2cache.overall_mshr_miss_latency::total 423589500 # number of overall MSHR miss cycles 898system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.188363 # mshr miss rate for ReadReq accesses 899system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.813501 # mshr miss rate for ReadReq accesses 900system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.250960 # mshr miss rate for ReadReq accesses 901system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.916667 # mshr miss rate for UpgradeReq accesses 902system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.916667 # mshr miss rate for UpgradeReq accesses 903system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994378 # mshr miss rate for ReadExReq accesses 904system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994378 # mshr miss rate for ReadExReq accesses 905system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.188363 # mshr miss rate for demand accesses 906system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.925555 # mshr miss rate for demand accesses 907system.cpu.l2cache.demand_mshr_miss_rate::total 0.355169 # mshr miss rate for demand accesses 908system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.188363 # mshr miss rate for overall accesses 909system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.925555 # mshr miss rate for overall accesses 910system.cpu.l2cache.overall_mshr_miss_rate::total 0.355169 # mshr miss rate for overall accesses 911system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57247.127408 # average ReadReq mshr miss latency 912system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60975.386779 # average ReadReq mshr miss latency 913system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58457.258617 # average ReadReq mshr miss latency 914system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10182.636364 # average UpgradeReq mshr miss latency 915system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10182.636364 # average UpgradeReq mshr miss latency 916system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59183.127208 # average ReadExReq mshr miss latency 917system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59183.127208 # average ReadExReq mshr miss latency 918system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57247.127408 # average overall mshr miss latency 919system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59782.514111 # average overall mshr miss latency 920system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58742.130079 # average overall mshr miss latency 921system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57247.127408 # average overall mshr miss latency 922system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59782.514111 # average overall mshr miss latency 923system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58742.130079 # average overall mshr miss latency 924system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 925system.cpu.dcache.tags.replacements 1384 # number of replacements 926system.cpu.dcache.tags.tagsinuse 3114.575432 # Cycle average of tags in use 927system.cpu.dcache.tags.total_refs 161730326 # Total number of references to valid blocks. 928system.cpu.dcache.tags.sampled_refs 4594 # Sample count of references to valid blocks. 929system.cpu.dcache.tags.avg_refs 35204.685677 # Average number of references to valid blocks. 930system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 931system.cpu.dcache.tags.occ_blocks::cpu.data 3114.575432 # Average occupied blocks per requestor 932system.cpu.dcache.tags.occ_percent::cpu.data 0.760394 # Average percentage of cache occupancy 933system.cpu.dcache.tags.occ_percent::total 0.760394 # Average percentage of cache occupancy 934system.cpu.dcache.tags.occ_task_id_blocks::1024 3210 # Occupied blocks per task id 935system.cpu.dcache.tags.age_task_id_blocks_1024::0 23 # Occupied blocks per task id 936system.cpu.dcache.tags.age_task_id_blocks_1024::1 27 # Occupied blocks per task id 937system.cpu.dcache.tags.age_task_id_blocks_1024::2 686 # Occupied blocks per task id 938system.cpu.dcache.tags.age_task_id_blocks_1024::3 12 # Occupied blocks per task id 939system.cpu.dcache.tags.age_task_id_blocks_1024::4 2462 # Occupied blocks per task id 940system.cpu.dcache.tags.occ_task_id_percent::1024 0.783691 # Percentage of cache occupancy per task id 941system.cpu.dcache.tags.tag_accesses 323517792 # Number of tag accesses 942system.cpu.dcache.tags.data_accesses 323517792 # Number of data accesses 943system.cpu.dcache.ReadReq_hits::cpu.data 79590771 # number of ReadReq hits 944system.cpu.dcache.ReadReq_hits::total 79590771 # number of ReadReq hits 945system.cpu.dcache.WriteReq_hits::cpu.data 82030417 # number of WriteReq hits 946system.cpu.dcache.WriteReq_hits::total 82030417 # number of WriteReq hits 947system.cpu.dcache.SoftPFReq_hits::cpu.data 87045 # number of SoftPFReq hits 948system.cpu.dcache.SoftPFReq_hits::total 87045 # number of SoftPFReq hits 949system.cpu.dcache.LoadLockedReq_hits::cpu.data 11127 # number of LoadLockedReq hits 950system.cpu.dcache.LoadLockedReq_hits::total 11127 # number of LoadLockedReq hits 951system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits 952system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits 953system.cpu.dcache.demand_hits::cpu.data 161621188 # number of demand (read+write) hits 954system.cpu.dcache.demand_hits::total 161621188 # number of demand (read+write) hits 955system.cpu.dcache.overall_hits::cpu.data 161708233 # number of overall hits 956system.cpu.dcache.overall_hits::total 161708233 # number of overall hits 957system.cpu.dcache.ReadReq_misses::cpu.data 4059 # number of ReadReq misses 958system.cpu.dcache.ReadReq_misses::total 4059 # number of ReadReq misses 959system.cpu.dcache.WriteReq_misses::cpu.data 22243 # number of WriteReq misses 960system.cpu.dcache.WriteReq_misses::total 22243 # number of WriteReq misses 961system.cpu.dcache.SoftPFReq_misses::cpu.data 40 # number of SoftPFReq misses 962system.cpu.dcache.SoftPFReq_misses::total 40 # number of SoftPFReq misses 963system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses 964system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses 965system.cpu.dcache.demand_misses::cpu.data 26302 # number of demand (read+write) misses 966system.cpu.dcache.demand_misses::total 26302 # number of demand (read+write) misses 967system.cpu.dcache.overall_misses::cpu.data 26342 # number of overall misses 968system.cpu.dcache.overall_misses::total 26342 # number of overall misses 969system.cpu.dcache.ReadReq_miss_latency::cpu.data 234715222 # number of ReadReq miss cycles 970system.cpu.dcache.ReadReq_miss_latency::total 234715222 # number of ReadReq miss cycles 971system.cpu.dcache.WriteReq_miss_latency::cpu.data 1291834537 # number of WriteReq miss cycles 972system.cpu.dcache.WriteReq_miss_latency::total 1291834537 # number of WriteReq miss cycles 973system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 170250 # number of LoadLockedReq miss cycles 974system.cpu.dcache.LoadLockedReq_miss_latency::total 170250 # number of LoadLockedReq miss cycles 975system.cpu.dcache.demand_miss_latency::cpu.data 1526549759 # number of demand (read+write) miss cycles 976system.cpu.dcache.demand_miss_latency::total 1526549759 # number of demand (read+write) miss cycles 977system.cpu.dcache.overall_miss_latency::cpu.data 1526549759 # number of overall miss cycles 978system.cpu.dcache.overall_miss_latency::total 1526549759 # number of overall miss cycles 979system.cpu.dcache.ReadReq_accesses::cpu.data 79594830 # number of ReadReq accesses(hits+misses) 980system.cpu.dcache.ReadReq_accesses::total 79594830 # number of ReadReq accesses(hits+misses) 981system.cpu.dcache.WriteReq_accesses::cpu.data 82052660 # number of WriteReq accesses(hits+misses) 982system.cpu.dcache.WriteReq_accesses::total 82052660 # number of WriteReq accesses(hits+misses) 983system.cpu.dcache.SoftPFReq_accesses::cpu.data 87085 # number of SoftPFReq accesses(hits+misses) 984system.cpu.dcache.SoftPFReq_accesses::total 87085 # number of SoftPFReq accesses(hits+misses) 985system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11129 # number of LoadLockedReq accesses(hits+misses) 986system.cpu.dcache.LoadLockedReq_accesses::total 11129 # number of LoadLockedReq accesses(hits+misses) 987system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses) 988system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) 989system.cpu.dcache.demand_accesses::cpu.data 161647490 # number of demand (read+write) accesses 990system.cpu.dcache.demand_accesses::total 161647490 # number of demand (read+write) accesses 991system.cpu.dcache.overall_accesses::cpu.data 161734575 # number of overall (read+write) accesses 992system.cpu.dcache.overall_accesses::total 161734575 # number of overall (read+write) accesses 993system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000051 # miss rate for ReadReq accesses 994system.cpu.dcache.ReadReq_miss_rate::total 0.000051 # miss rate for ReadReq accesses 995system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000271 # miss rate for WriteReq accesses 996system.cpu.dcache.WriteReq_miss_rate::total 0.000271 # miss rate for WriteReq accesses 997system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000459 # miss rate for SoftPFReq accesses 998system.cpu.dcache.SoftPFReq_miss_rate::total 0.000459 # miss rate for SoftPFReq accesses 999system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000180 # miss rate for LoadLockedReq accesses 1000system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000180 # miss rate for LoadLockedReq accesses 1001system.cpu.dcache.demand_miss_rate::cpu.data 0.000163 # miss rate for demand accesses 1002system.cpu.dcache.demand_miss_rate::total 0.000163 # miss rate for demand accesses 1003system.cpu.dcache.overall_miss_rate::cpu.data 0.000163 # miss rate for overall accesses 1004system.cpu.dcache.overall_miss_rate::total 0.000163 # miss rate for overall accesses 1005system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 57825.873861 # average ReadReq miss latency 1006system.cpu.dcache.ReadReq_avg_miss_latency::total 57825.873861 # average ReadReq miss latency 1007system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 58078.251000 # average WriteReq miss latency 1008system.cpu.dcache.WriteReq_avg_miss_latency::total 58078.251000 # average WriteReq miss latency 1009system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 85125 # average LoadLockedReq miss latency 1010system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 85125 # average LoadLockedReq miss latency 1011system.cpu.dcache.demand_avg_miss_latency::cpu.data 58039.303437 # average overall miss latency 1012system.cpu.dcache.demand_avg_miss_latency::total 58039.303437 # average overall miss latency 1013system.cpu.dcache.overall_avg_miss_latency::cpu.data 57951.171475 # average overall miss latency 1014system.cpu.dcache.overall_avg_miss_latency::total 57951.171475 # average overall miss latency 1015system.cpu.dcache.blocked_cycles::no_mshrs 32404 # number of cycles access was blocked 1016system.cpu.dcache.blocked_cycles::no_targets 1444 # number of cycles access was blocked 1017system.cpu.dcache.blocked::no_mshrs 548 # number of cycles access was blocked 1018system.cpu.dcache.blocked::no_targets 14 # number of cycles access was blocked 1019system.cpu.dcache.avg_blocked_cycles::no_mshrs 59.131387 # average number of cycles each access was blocked 1020system.cpu.dcache.avg_blocked_cycles::no_targets 103.142857 # average number of cycles each access was blocked 1021system.cpu.dcache.fast_writes 0 # number of fast writes performed 1022system.cpu.dcache.cache_copies 0 # number of cache copies performed 1023system.cpu.dcache.writebacks::writebacks 1022 # number of writebacks 1024system.cpu.dcache.writebacks::total 1022 # number of writebacks 1025system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2332 # number of ReadReq MSHR hits 1026system.cpu.dcache.ReadReq_mshr_hits::total 2332 # number of ReadReq MSHR hits 1027system.cpu.dcache.WriteReq_mshr_hits::cpu.data 19388 # number of WriteReq MSHR hits 1028system.cpu.dcache.WriteReq_mshr_hits::total 19388 # number of WriteReq MSHR hits 1029system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits 1030system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits 1031system.cpu.dcache.demand_mshr_hits::cpu.data 21720 # number of demand (read+write) MSHR hits 1032system.cpu.dcache.demand_mshr_hits::total 21720 # number of demand (read+write) MSHR hits 1033system.cpu.dcache.overall_mshr_hits::cpu.data 21720 # number of overall MSHR hits 1034system.cpu.dcache.overall_mshr_hits::total 21720 # number of overall MSHR hits 1035system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1727 # number of ReadReq MSHR misses 1036system.cpu.dcache.ReadReq_mshr_misses::total 1727 # number of ReadReq MSHR misses 1037system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2855 # number of WriteReq MSHR misses 1038system.cpu.dcache.WriteReq_mshr_misses::total 2855 # number of WriteReq MSHR misses 1039system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 24 # number of SoftPFReq MSHR misses 1040system.cpu.dcache.SoftPFReq_mshr_misses::total 24 # number of SoftPFReq MSHR misses 1041system.cpu.dcache.demand_mshr_misses::cpu.data 4582 # number of demand (read+write) MSHR misses 1042system.cpu.dcache.demand_mshr_misses::total 4582 # number of demand (read+write) MSHR misses 1043system.cpu.dcache.overall_mshr_misses::cpu.data 4606 # number of overall MSHR misses 1044system.cpu.dcache.overall_mshr_misses::total 4606 # number of overall MSHR misses 1045system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 109924790 # number of ReadReq MSHR miss cycles 1046system.cpu.dcache.ReadReq_mshr_miss_latency::total 109924790 # number of ReadReq MSHR miss cycles 1047system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 205574740 # number of WriteReq MSHR miss cycles 1048system.cpu.dcache.WriteReq_mshr_miss_latency::total 205574740 # number of WriteReq MSHR miss cycles 1049system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1745000 # number of SoftPFReq MSHR miss cycles 1050system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1745000 # number of SoftPFReq MSHR miss cycles 1051system.cpu.dcache.demand_mshr_miss_latency::cpu.data 315499530 # number of demand (read+write) MSHR miss cycles 1052system.cpu.dcache.demand_mshr_miss_latency::total 315499530 # number of demand (read+write) MSHR miss cycles 1053system.cpu.dcache.overall_mshr_miss_latency::cpu.data 317244530 # number of overall MSHR miss cycles 1054system.cpu.dcache.overall_mshr_miss_latency::total 317244530 # number of overall MSHR miss cycles 1055system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000022 # mshr miss rate for ReadReq accesses 1056system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000022 # mshr miss rate for ReadReq accesses 1057system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses 1058system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000035 # mshr miss rate for WriteReq accesses 1059system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.000276 # mshr miss rate for SoftPFReq accesses 1060system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.000276 # mshr miss rate for SoftPFReq accesses 1061system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000028 # mshr miss rate for demand accesses 1062system.cpu.dcache.demand_mshr_miss_rate::total 0.000028 # mshr miss rate for demand accesses 1063system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000028 # mshr miss rate for overall accesses 1064system.cpu.dcache.overall_mshr_miss_rate::total 0.000028 # mshr miss rate for overall accesses 1065system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 63650.718008 # average ReadReq mshr miss latency 1066system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 63650.718008 # average ReadReq mshr miss latency 1067system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72005.162872 # average WriteReq mshr miss latency 1068system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72005.162872 # average WriteReq mshr miss latency 1069system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 72708.333333 # average SoftPFReq mshr miss latency 1070system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 72708.333333 # average SoftPFReq mshr miss latency 1071system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68856.292012 # average overall mshr miss latency 1072system.cpu.dcache.demand_avg_mshr_miss_latency::total 68856.292012 # average overall mshr miss latency 1073system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68876.363439 # average overall mshr miss latency 1074system.cpu.dcache.overall_avg_mshr_miss_latency::total 68876.363439 # average overall mshr miss latency 1075system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1076 1077---------- End Simulation Statistics ---------- 1078