stats.txt revision 10220:9eab5efc02e8
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.068540 # Number of seconds simulated 4sim_ticks 68540241500 # Number of ticks simulated 5final_tick 68540241500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 122061 # Simulator instruction rate (inst/s) 8host_op_rate 156050 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 30641006 # Simulator tick rate (ticks/s) 10host_mem_usage 321880 # Number of bytes of host memory used 11host_seconds 2236.88 # Real time elapsed on the host 12sim_insts 273036725 # Number of instructions simulated 13sim_ops 349064449 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 193920 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 272448 # Number of bytes read from this memory 18system.physmem.bytes_read::total 466368 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 193920 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 193920 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 3030 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 4257 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 7287 # Number of read requests responded to by this memory 24system.physmem.bw_read::cpu.inst 2829287 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 3975008 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 6804295 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 2829287 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 2829287 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 2829287 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 3975008 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 6804295 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.readReqs 7287 # Number of read requests accepted 33system.physmem.writeReqs 0 # Number of write requests accepted 34system.physmem.readBursts 7287 # Number of DRAM read bursts, including those serviced by the write queue 35system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 36system.physmem.bytesReadDRAM 466368 # Total number of bytes read from DRAM 37system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 38system.physmem.bytesWritten 0 # Total number of bytes written to DRAM 39system.physmem.bytesReadSys 466368 # Total read bytes from the system interface side 40system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 41system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 42system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 43system.physmem.neitherReadNorWriteReqs 2 # Number of requests that are neither read nor write 44system.physmem.perBankRdBursts::0 604 # Per bank write bursts 45system.physmem.perBankRdBursts::1 802 # Per bank write bursts 46system.physmem.perBankRdBursts::2 607 # Per bank write bursts 47system.physmem.perBankRdBursts::3 525 # Per bank write bursts 48system.physmem.perBankRdBursts::4 444 # Per bank write bursts 49system.physmem.perBankRdBursts::5 349 # Per bank write bursts 50system.physmem.perBankRdBursts::6 161 # Per bank write bursts 51system.physmem.perBankRdBursts::7 221 # Per bank write bursts 52system.physmem.perBankRdBursts::8 206 # Per bank write bursts 53system.physmem.perBankRdBursts::9 292 # Per bank write bursts 54system.physmem.perBankRdBursts::10 324 # Per bank write bursts 55system.physmem.perBankRdBursts::11 416 # Per bank write bursts 56system.physmem.perBankRdBursts::12 533 # Per bank write bursts 57system.physmem.perBankRdBursts::13 685 # Per bank write bursts 58system.physmem.perBankRdBursts::14 612 # Per bank write bursts 59system.physmem.perBankRdBursts::15 506 # Per bank write bursts 60system.physmem.perBankWrBursts::0 0 # Per bank write bursts 61system.physmem.perBankWrBursts::1 0 # Per bank write bursts 62system.physmem.perBankWrBursts::2 0 # Per bank write bursts 63system.physmem.perBankWrBursts::3 0 # Per bank write bursts 64system.physmem.perBankWrBursts::4 0 # Per bank write bursts 65system.physmem.perBankWrBursts::5 0 # Per bank write bursts 66system.physmem.perBankWrBursts::6 0 # Per bank write bursts 67system.physmem.perBankWrBursts::7 0 # Per bank write bursts 68system.physmem.perBankWrBursts::8 0 # Per bank write bursts 69system.physmem.perBankWrBursts::9 0 # Per bank write bursts 70system.physmem.perBankWrBursts::10 0 # Per bank write bursts 71system.physmem.perBankWrBursts::11 0 # Per bank write bursts 72system.physmem.perBankWrBursts::12 0 # Per bank write bursts 73system.physmem.perBankWrBursts::13 0 # Per bank write bursts 74system.physmem.perBankWrBursts::14 0 # Per bank write bursts 75system.physmem.perBankWrBursts::15 0 # Per bank write bursts 76system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 77system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 78system.physmem.totGap 68540041000 # Total gap between requests 79system.physmem.readPktSize::0 0 # Read request sizes (log2) 80system.physmem.readPktSize::1 0 # Read request sizes (log2) 81system.physmem.readPktSize::2 0 # Read request sizes (log2) 82system.physmem.readPktSize::3 0 # Read request sizes (log2) 83system.physmem.readPktSize::4 0 # Read request sizes (log2) 84system.physmem.readPktSize::5 0 # Read request sizes (log2) 85system.physmem.readPktSize::6 7287 # Read request sizes (log2) 86system.physmem.writePktSize::0 0 # Write request sizes (log2) 87system.physmem.writePktSize::1 0 # Write request sizes (log2) 88system.physmem.writePktSize::2 0 # Write request sizes (log2) 89system.physmem.writePktSize::3 0 # Write request sizes (log2) 90system.physmem.writePktSize::4 0 # Write request sizes (log2) 91system.physmem.writePktSize::5 0 # Write request sizes (log2) 92system.physmem.writePktSize::6 0 # Write request sizes (log2) 93system.physmem.rdQLenPdf::0 4301 # What read queue length does an incoming req see 94system.physmem.rdQLenPdf::1 2168 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::2 588 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::3 170 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::4 60 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 125system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 126system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 127system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 128system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 129system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 130system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 131system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 132system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 133system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 134system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 189system.physmem.bytesPerActivate::samples 1441 # Bytes accessed per row activation 190system.physmem.bytesPerActivate::mean 322.087439 # Bytes accessed per row activation 191system.physmem.bytesPerActivate::gmean 187.561369 # Bytes accessed per row activation 192system.physmem.bytesPerActivate::stdev 340.705535 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::0-127 517 35.88% 35.88% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::128-255 362 25.12% 61.00% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::256-383 132 9.16% 70.16% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::384-511 71 4.93% 75.09% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::512-639 61 4.23% 79.32% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::640-767 42 2.91% 82.23% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::768-895 35 2.43% 84.66% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::896-1023 26 1.80% 86.47% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::1024-1151 195 13.53% 100.00% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::total 1441 # Bytes accessed per row activation 203system.physmem.totQLat 60227500 # Total ticks spent queuing 204system.physmem.totMemAccLat 196858750 # Total ticks spent from burst creation until serviced by the DRAM 205system.physmem.totBusLat 36435000 # Total ticks spent in databus transfers 206system.physmem.avgQLat 8265.06 # Average queueing delay per DRAM burst 207system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 208system.physmem.avgMemAccLat 27015.06 # Average memory access latency per DRAM burst 209system.physmem.avgRdBW 6.80 # Average DRAM read bandwidth in MiByte/s 210system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 211system.physmem.avgRdBWSys 6.80 # Average system read bandwidth in MiByte/s 212system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 213system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 214system.physmem.busUtil 0.05 # Data bus utilization in percentage 215system.physmem.busUtilRead 0.05 # Data bus utilization in percentage for reads 216system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 217system.physmem.avgRdQLen 1.17 # Average read queue length when enqueuing 218system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 219system.physmem.readRowHits 5834 # Number of row buffer hits during reads 220system.physmem.writeRowHits 0 # Number of row buffer hits during writes 221system.physmem.readRowHitRate 80.06 # Row buffer hit rate for reads 222system.physmem.writeRowHitRate nan # Row buffer hit rate for writes 223system.physmem.avgGap 9405796.76 # Average gap between requests 224system.physmem.pageHitRate 80.06 # Row buffer hit rate, read and write combined 225system.physmem.memoryStateTime::IDLE 64419207500 # Time in different power states 226system.physmem.memoryStateTime::REF 2288520000 # Time in different power states 227system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states 228system.physmem.memoryStateTime::ACT 1827118750 # Time in different power states 229system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states 230system.membus.throughput 6804295 # Throughput (bytes/s) 231system.membus.trans_dist::ReadReq 4468 # Transaction distribution 232system.membus.trans_dist::ReadResp 4468 # Transaction distribution 233system.membus.trans_dist::UpgradeReq 2 # Transaction distribution 234system.membus.trans_dist::UpgradeResp 2 # Transaction distribution 235system.membus.trans_dist::ReadExReq 2819 # Transaction distribution 236system.membus.trans_dist::ReadExResp 2819 # Transaction distribution 237system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14578 # Packet count per connected master and slave (bytes) 238system.membus.pkt_count::total 14578 # Packet count per connected master and slave (bytes) 239system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 466368 # Cumulative packet size per connected master and slave (bytes) 240system.membus.tot_pkt_size::total 466368 # Cumulative packet size per connected master and slave (bytes) 241system.membus.data_through_bus 466368 # Total data (bytes) 242system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 243system.membus.reqLayer0.occupancy 8924000 # Layer occupancy (ticks) 244system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 245system.membus.respLayer1.occupancy 67911998 # Layer occupancy (ticks) 246system.membus.respLayer1.utilization 0.1 # Layer utilization (%) 247system.cpu_clk_domain.clock 500 # Clock period in ticks 248system.cpu.branchPred.lookups 35427097 # Number of BP lookups 249system.cpu.branchPred.condPredicted 21222481 # Number of conditional branches predicted 250system.cpu.branchPred.condIncorrect 1662305 # Number of conditional branches incorrect 251system.cpu.branchPred.BTBLookups 19504890 # Number of BTB lookups 252system.cpu.branchPred.BTBHits 16830620 # Number of BTB hits 253system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 254system.cpu.branchPred.BTBHitPct 86.289233 # BTB Hit Percentage 255system.cpu.branchPred.usedRAS 6785276 # Number of times the RAS was used to get a target. 256system.cpu.branchPred.RASInCorrect 8391 # Number of incorrect RAS predictions. 257system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 258system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 259system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 260system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 261system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 262system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 263system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 264system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 265system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 266system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 267system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 268system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 269system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 270system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 271system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 272system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 273system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 274system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 275system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 276system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 277system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 278system.cpu.dtb.inst_hits 0 # ITB inst hits 279system.cpu.dtb.inst_misses 0 # ITB inst misses 280system.cpu.dtb.read_hits 0 # DTB read hits 281system.cpu.dtb.read_misses 0 # DTB read misses 282system.cpu.dtb.write_hits 0 # DTB write hits 283system.cpu.dtb.write_misses 0 # DTB write misses 284system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 285system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 286system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 287system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 288system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 289system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 290system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 291system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 292system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 293system.cpu.dtb.read_accesses 0 # DTB read accesses 294system.cpu.dtb.write_accesses 0 # DTB write accesses 295system.cpu.dtb.inst_accesses 0 # ITB inst accesses 296system.cpu.dtb.hits 0 # DTB hits 297system.cpu.dtb.misses 0 # DTB misses 298system.cpu.dtb.accesses 0 # DTB accesses 299system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 300system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 301system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 302system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 303system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 304system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 305system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 306system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 307system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 308system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 309system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 310system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 311system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 312system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 313system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 314system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 315system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 316system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 317system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 318system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 319system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 320system.cpu.itb.inst_hits 0 # ITB inst hits 321system.cpu.itb.inst_misses 0 # ITB inst misses 322system.cpu.itb.read_hits 0 # DTB read hits 323system.cpu.itb.read_misses 0 # DTB read misses 324system.cpu.itb.write_hits 0 # DTB write hits 325system.cpu.itb.write_misses 0 # DTB write misses 326system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 327system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 328system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 329system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 330system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 331system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 332system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 333system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 334system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 335system.cpu.itb.read_accesses 0 # DTB read accesses 336system.cpu.itb.write_accesses 0 # DTB write accesses 337system.cpu.itb.inst_accesses 0 # ITB inst accesses 338system.cpu.itb.hits 0 # DTB hits 339system.cpu.itb.misses 0 # DTB misses 340system.cpu.itb.accesses 0 # DTB accesses 341system.cpu.workload.num_syscalls 191 # Number of system calls 342system.cpu.numCycles 137080484 # number of cpu cycles simulated 343system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 344system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 345system.cpu.fetch.icacheStallCycles 39013094 # Number of cycles fetch is stalled on an Icache miss 346system.cpu.fetch.Insts 318011666 # Number of instructions fetch has processed 347system.cpu.fetch.Branches 35427097 # Number of branches that fetch encountered 348system.cpu.fetch.predictedBranches 23615896 # Number of branches that fetch has predicted taken 349system.cpu.fetch.Cycles 70957700 # Number of cycles fetch has run and was not squashing or blocked 350system.cpu.fetch.SquashCycles 6891338 # Number of cycles fetch has spent squashing 351system.cpu.fetch.BlockedCycles 21536315 # Number of cycles fetch has spent blocked 352system.cpu.fetch.MiscStallCycles 110 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 353system.cpu.fetch.PendingTrapStallCycles 1697 # Number of stall cycles due to pending traps 354system.cpu.fetch.IcacheWaitRetryStallCycles 56 # Number of stall cycles due to full MSHR 355system.cpu.fetch.CacheLines 37608451 # Number of cache lines fetched 356system.cpu.fetch.IcacheSquashes 511125 # Number of outstanding Icache misses that were squashed 357system.cpu.fetch.rateDist::samples 136726497 # Number of instructions fetched each cycle (Total) 358system.cpu.fetch.rateDist::mean 2.983044 # Number of instructions fetched each cycle (Total) 359system.cpu.fetch.rateDist::stdev 3.454276 # Number of instructions fetched each cycle (Total) 360system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 361system.cpu.fetch.rateDist::0 66399200 48.56% 48.56% # Number of instructions fetched each cycle (Total) 362system.cpu.fetch.rateDist::1 6788638 4.97% 53.53% # Number of instructions fetched each cycle (Total) 363system.cpu.fetch.rateDist::2 5707530 4.17% 57.70% # Number of instructions fetched each cycle (Total) 364system.cpu.fetch.rateDist::3 6111990 4.47% 62.17% # Number of instructions fetched each cycle (Total) 365system.cpu.fetch.rateDist::4 4922665 3.60% 65.77% # Number of instructions fetched each cycle (Total) 366system.cpu.fetch.rateDist::5 4080012 2.98% 68.76% # Number of instructions fetched each cycle (Total) 367system.cpu.fetch.rateDist::6 3180881 2.33% 71.08% # Number of instructions fetched each cycle (Total) 368system.cpu.fetch.rateDist::7 4139139 3.03% 74.11% # Number of instructions fetched each cycle (Total) 369system.cpu.fetch.rateDist::8 35396442 25.89% 100.00% # Number of instructions fetched each cycle (Total) 370system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 371system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 372system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 373system.cpu.fetch.rateDist::total 136726497 # Number of instructions fetched each cycle (Total) 374system.cpu.fetch.branchRate 0.258440 # Number of branch fetches per cycle 375system.cpu.fetch.rate 2.319890 # Number of inst fetches per cycle 376system.cpu.decode.IdleCycles 45526376 # Number of cycles decode is idle 377system.cpu.decode.BlockedCycles 16684464 # Number of cycles decode is blocked 378system.cpu.decode.RunCycles 66829825 # Number of cycles decode is running 379system.cpu.decode.UnblockCycles 2537018 # Number of cycles decode is unblocking 380system.cpu.decode.SquashCycles 5148814 # Number of cycles decode is squashing 381system.cpu.decode.BranchResolved 7346336 # Number of times decode resolved a branch 382system.cpu.decode.BranchMispred 69128 # Number of times decode detected a branch misprediction 383system.cpu.decode.DecodedInsts 401912579 # Number of instructions handled by decode 384system.cpu.decode.SquashedInsts 214046 # Number of squashed instructions handled by decode 385system.cpu.rename.SquashCycles 5148814 # Number of cycles rename is squashing 386system.cpu.rename.IdleCycles 51079671 # Number of cycles rename is idle 387system.cpu.rename.BlockCycles 1913308 # Number of cycles rename is blocking 388system.cpu.rename.serializeStallCycles 333807 # count of cycles rename stalled for serializing inst 389system.cpu.rename.RunCycles 63753347 # Number of cycles rename is running 390system.cpu.rename.UnblockCycles 14497550 # Number of cycles rename is unblocking 391system.cpu.rename.RenamedInsts 394307650 # Number of instructions processed by rename 392system.cpu.rename.ROBFullEvents 25 # Number of times rename has blocked due to ROB full 393system.cpu.rename.IQFullEvents 1657315 # Number of times rename has blocked due to IQ full 394system.cpu.rename.LSQFullEvents 10195595 # Number of times rename has blocked due to LSQ full 395system.cpu.rename.FullRegisterEvents 22429 # Number of times there has been no free registers 396system.cpu.rename.RenamedOperands 432708181 # Number of destination operands rename has renamed 397system.cpu.rename.RenameLookups 2738145852 # Number of register rename lookups that rename has made 398system.cpu.rename.int_rename_lookups 1575813049 # Number of integer rename lookups 399system.cpu.rename.fp_rename_lookups 200323476 # Number of floating rename lookups 400system.cpu.rename.CommittedMaps 384566193 # Number of HB maps that are committed 401system.cpu.rename.UndoneMaps 48141988 # Number of HB maps that are undone due to squashing 402system.cpu.rename.serializingInsts 11963 # count of serializing insts renamed 403system.cpu.rename.tempSerializingInsts 11962 # count of temporary serializing insts renamed 404system.cpu.rename.skidInsts 36553940 # count of insts added to the skid buffer 405system.cpu.memDep0.insertedLoads 103619662 # Number of loads inserted to the mem dependence unit. 406system.cpu.memDep0.insertedStores 91398989 # Number of stores inserted to the mem dependence unit. 407system.cpu.memDep0.conflictingLoads 4293575 # Number of conflicting loads. 408system.cpu.memDep0.conflictingStores 5309451 # Number of conflicting stores. 409system.cpu.iq.iqInstsAdded 384641768 # Number of instructions added to the IQ (excludes non-spec) 410system.cpu.iq.iqNonSpecInstsAdded 22898 # Number of non-speculative instructions added to the IQ 411system.cpu.iq.iqInstsIssued 374271543 # Number of instructions issued 412system.cpu.iq.iqSquashedInstsIssued 1203075 # Number of squashed instructions issued 413system.cpu.iq.iqSquashedInstsExamined 34859337 # Number of squashed instructions iterated over during squash; mainly for profiling 414system.cpu.iq.iqSquashedOperandsExamined 100548351 # Number of squashed operands that are examined and possibly removed from graph 415system.cpu.iq.iqSquashedNonSpecRemoved 778 # Number of squashed non-spec instructions that were removed 416system.cpu.iq.issued_per_cycle::samples 136726497 # Number of insts issued each cycle 417system.cpu.iq.issued_per_cycle::mean 2.737374 # Number of insts issued each cycle 418system.cpu.iq.issued_per_cycle::stdev 2.024550 # Number of insts issued each cycle 419system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 420system.cpu.iq.issued_per_cycle::0 25150398 18.39% 18.39% # Number of insts issued each cycle 421system.cpu.iq.issued_per_cycle::1 19938048 14.58% 32.98% # Number of insts issued each cycle 422system.cpu.iq.issued_per_cycle::2 20598425 15.07% 48.04% # Number of insts issued each cycle 423system.cpu.iq.issued_per_cycle::3 18168946 13.29% 61.33% # Number of insts issued each cycle 424system.cpu.iq.issued_per_cycle::4 24025170 17.57% 78.90% # Number of insts issued each cycle 425system.cpu.iq.issued_per_cycle::5 15741501 11.51% 90.42% # Number of insts issued each cycle 426system.cpu.iq.issued_per_cycle::6 8821837 6.45% 96.87% # Number of insts issued each cycle 427system.cpu.iq.issued_per_cycle::7 3366776 2.46% 99.33% # Number of insts issued each cycle 428system.cpu.iq.issued_per_cycle::8 915396 0.67% 100.00% # Number of insts issued each cycle 429system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 430system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 431system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 432system.cpu.iq.issued_per_cycle::total 136726497 # Number of insts issued each cycle 433system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 434system.cpu.iq.fu_full::IntAlu 8454 0.05% 0.05% # attempts to use FU when none available 435system.cpu.iq.fu_full::IntMult 4686 0.03% 0.07% # attempts to use FU when none available 436system.cpu.iq.fu_full::IntDiv 0 0.00% 0.07% # attempts to use FU when none available 437system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.07% # attempts to use FU when none available 438system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.07% # attempts to use FU when none available 439system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.07% # attempts to use FU when none available 440system.cpu.iq.fu_full::FloatMult 0 0.00% 0.07% # attempts to use FU when none available 441system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.07% # attempts to use FU when none available 442system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.07% # attempts to use FU when none available 443system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.07% # attempts to use FU when none available 444system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.07% # attempts to use FU when none available 445system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.07% # attempts to use FU when none available 446system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.07% # attempts to use FU when none available 447system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.07% # attempts to use FU when none available 448system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.07% # attempts to use FU when none available 449system.cpu.iq.fu_full::SimdMult 0 0.00% 0.07% # attempts to use FU when none available 450system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.07% # attempts to use FU when none available 451system.cpu.iq.fu_full::SimdShift 0 0.00% 0.07% # attempts to use FU when none available 452system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.07% # attempts to use FU when none available 453system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.07% # attempts to use FU when none available 454system.cpu.iq.fu_full::SimdFloatAdd 46141 0.26% 0.33% # attempts to use FU when none available 455system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.33% # attempts to use FU when none available 456system.cpu.iq.fu_full::SimdFloatCmp 3549 0.02% 0.35% # attempts to use FU when none available 457system.cpu.iq.fu_full::SimdFloatCvt 438 0.00% 0.36% # attempts to use FU when none available 458system.cpu.iq.fu_full::SimdFloatDiv 3 0.00% 0.36% # attempts to use FU when none available 459system.cpu.iq.fu_full::SimdFloatMisc 186673 1.05% 1.41% # attempts to use FU when none available 460system.cpu.iq.fu_full::SimdFloatMult 3981 0.02% 1.43% # attempts to use FU when none available 461system.cpu.iq.fu_full::SimdFloatMultAcc 241129 1.36% 2.80% # attempts to use FU when none available 462system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.80% # attempts to use FU when none available 463system.cpu.iq.fu_full::MemRead 9262679 52.30% 55.10% # attempts to use FU when none available 464system.cpu.iq.fu_full::MemWrite 7952866 44.90% 100.00% # attempts to use FU when none available 465system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 466system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 467system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 468system.cpu.iq.FU_type_0::IntAlu 126495771 33.80% 33.80% # Type of FU issued 469system.cpu.iq.FU_type_0::IntMult 2175574 0.58% 34.38% # Type of FU issued 470system.cpu.iq.FU_type_0::IntDiv 0 0.00% 34.38% # Type of FU issued 471system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 34.38% # Type of FU issued 472system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 34.38% # Type of FU issued 473system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 34.38% # Type of FU issued 474system.cpu.iq.FU_type_0::FloatMult 0 0.00% 34.38% # Type of FU issued 475system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 34.38% # Type of FU issued 476system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 34.38% # Type of FU issued 477system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 34.38% # Type of FU issued 478system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 34.38% # Type of FU issued 479system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 34.38% # Type of FU issued 480system.cpu.iq.FU_type_0::SimdCmp 1 0.00% 34.38% # Type of FU issued 481system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 34.38% # Type of FU issued 482system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 34.38% # Type of FU issued 483system.cpu.iq.FU_type_0::SimdMult 0 0.00% 34.38% # Type of FU issued 484system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 34.38% # Type of FU issued 485system.cpu.iq.FU_type_0::SimdShift 0 0.00% 34.38% # Type of FU issued 486system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 34.38% # Type of FU issued 487system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 34.38% # Type of FU issued 488system.cpu.iq.FU_type_0::SimdFloatAdd 6778108 1.81% 36.19% # Type of FU issued 489system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 36.19% # Type of FU issued 490system.cpu.iq.FU_type_0::SimdFloatCmp 8473024 2.26% 38.45% # Type of FU issued 491system.cpu.iq.FU_type_0::SimdFloatCvt 3429632 0.92% 39.37% # Type of FU issued 492system.cpu.iq.FU_type_0::SimdFloatDiv 1595745 0.43% 39.80% # Type of FU issued 493system.cpu.iq.FU_type_0::SimdFloatMisc 20862309 5.57% 45.37% # Type of FU issued 494system.cpu.iq.FU_type_0::SimdFloatMult 7172511 1.92% 47.29% # Type of FU issued 495system.cpu.iq.FU_type_0::SimdFloatMultAcc 7129172 1.90% 49.19% # Type of FU issued 496system.cpu.iq.FU_type_0::SimdFloatSqrt 175286 0.05% 49.24% # Type of FU issued 497system.cpu.iq.FU_type_0::MemRead 101679299 27.17% 76.41% # Type of FU issued 498system.cpu.iq.FU_type_0::MemWrite 88305111 23.59% 100.00% # Type of FU issued 499system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 500system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 501system.cpu.iq.FU_type_0::total 374271543 # Type of FU issued 502system.cpu.iq.rate 2.730305 # Inst issue rate 503system.cpu.iq.fu_busy_cnt 17710599 # FU busy when requested 504system.cpu.iq.fu_busy_rate 0.047320 # FU busy rate (busy events/executed inst) 505system.cpu.iq.int_inst_queue_reads 654796096 # Number of integer instruction queue reads 506system.cpu.iq.int_inst_queue_writes 289211293 # Number of integer instruction queue writes 507system.cpu.iq.int_inst_queue_wakeup_accesses 250149926 # Number of integer instruction queue wakeup accesses 508system.cpu.iq.fp_inst_queue_reads 249387161 # Number of floating instruction queue reads 509system.cpu.iq.fp_inst_queue_writes 130326745 # Number of floating instruction queue writes 510system.cpu.iq.fp_inst_queue_wakeup_accesses 118060008 # Number of floating instruction queue wakeup accesses 511system.cpu.iq.int_alu_accesses 263377407 # Number of integer alu accesses 512system.cpu.iq.fp_alu_accesses 128604735 # Number of floating point alu accesses 513system.cpu.iew.lsq.thread0.forwLoads 11093990 # Number of loads that had data forwarded from stores 514system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 515system.cpu.iew.lsq.thread0.squashedLoads 8970914 # Number of loads squashed 516system.cpu.iew.lsq.thread0.ignoredResponses 108859 # Number of memory responses ignored because the instruction is squashed 517system.cpu.iew.lsq.thread0.memOrderViolation 14127 # Number of memory ordering violations 518system.cpu.iew.lsq.thread0.squashedStores 9023406 # Number of stores squashed 519system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 520system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 521system.cpu.iew.lsq.thread0.rescheduledLoads 175522 # Number of loads that were rescheduled 522system.cpu.iew.lsq.thread0.cacheBlocked 1863 # Number of times an access to memory failed due to the cache being blocked 523system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 524system.cpu.iew.iewSquashCycles 5148814 # Number of cycles IEW is squashing 525system.cpu.iew.iewBlockCycles 279698 # Number of cycles IEW is blocking 526system.cpu.iew.iewUnblockCycles 35585 # Number of cycles IEW is unblocking 527system.cpu.iew.iewDispatchedInsts 384666248 # Number of instructions dispatched to IQ 528system.cpu.iew.iewDispSquashedInsts 872586 # Number of squashed instructions skipped by dispatch 529system.cpu.iew.iewDispLoadInsts 103619662 # Number of dispatched load instructions 530system.cpu.iew.iewDispStoreInsts 91398989 # Number of dispatched store instructions 531system.cpu.iew.iewDispNonSpecInsts 11864 # Number of dispatched non-speculative instructions 532system.cpu.iew.iewIQFullEvents 344 # Number of times the IQ has become full, causing a stall 533system.cpu.iew.iewLSQFullEvents 288 # Number of times the LSQ has become full, causing a stall 534system.cpu.iew.memOrderViolationEvents 14127 # Number of memory order violations 535system.cpu.iew.predictedTakenIncorrect 1301679 # Number of branches that were predicted taken incorrectly 536system.cpu.iew.predictedNotTakenIncorrect 370144 # Number of branches that were predicted not taken incorrectly 537system.cpu.iew.branchMispredicts 1671823 # Number of branch mispredicts detected at execute 538system.cpu.iew.iewExecutedInsts 370317109 # Number of executed instructions 539system.cpu.iew.iewExecLoadInsts 100386827 # Number of load instructions executed 540system.cpu.iew.iewExecSquashedInsts 3954434 # Number of squashed instructions skipped in execute 541system.cpu.iew.exec_swp 0 # number of swp insts executed 542system.cpu.iew.exec_nop 1582 # number of nop insts executed 543system.cpu.iew.exec_refs 187618668 # number of memory reference insts executed 544system.cpu.iew.exec_branches 32015275 # Number of branches executed 545system.cpu.iew.exec_stores 87231841 # Number of stores executed 546system.cpu.iew.exec_rate 2.701458 # Inst execution rate 547system.cpu.iew.wb_sent 368883883 # cumulative count of insts sent to commit 548system.cpu.iew.wb_count 368209934 # cumulative count of insts written-back 549system.cpu.iew.wb_producers 183051685 # num instructions producing a value 550system.cpu.iew.wb_consumers 363776414 # num instructions consuming a value 551system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 552system.cpu.iew.wb_rate 2.686086 # insts written-back per cycle 553system.cpu.iew.wb_fanout 0.503198 # average fanout of values written-back 554system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 555system.cpu.commit.commitSquashedInsts 35601258 # The number of squashed insts skipped by commit 556system.cpu.commit.commitNonSpecStalls 22120 # The number of times commit has been forced to stall to communicate backwards 557system.cpu.commit.branchMispredicts 1593594 # The number of times a branch was mispredicted 558system.cpu.commit.committed_per_cycle::samples 131577683 # Number of insts commited each cycle 559system.cpu.commit.committed_per_cycle::mean 2.652920 # Number of insts commited each cycle 560system.cpu.commit.committed_per_cycle::stdev 2.658674 # Number of insts commited each cycle 561system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 562system.cpu.commit.committed_per_cycle::0 34743119 26.41% 26.41% # Number of insts commited each cycle 563system.cpu.commit.committed_per_cycle::1 28469178 21.64% 48.04% # Number of insts commited each cycle 564system.cpu.commit.committed_per_cycle::2 13363377 10.16% 58.20% # Number of insts commited each cycle 565system.cpu.commit.committed_per_cycle::3 11438386 8.69% 66.89% # Number of insts commited each cycle 566system.cpu.commit.committed_per_cycle::4 13773451 10.47% 77.36% # Number of insts commited each cycle 567system.cpu.commit.committed_per_cycle::5 7412867 5.63% 82.99% # Number of insts commited each cycle 568system.cpu.commit.committed_per_cycle::6 3865563 2.94% 85.93% # Number of insts commited each cycle 569system.cpu.commit.committed_per_cycle::7 3891482 2.96% 88.89% # Number of insts commited each cycle 570system.cpu.commit.committed_per_cycle::8 14620260 11.11% 100.00% # Number of insts commited each cycle 571system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 572system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 573system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 574system.cpu.commit.committed_per_cycle::total 131577683 # Number of insts commited each cycle 575system.cpu.commit.committedInsts 273037337 # Number of instructions committed 576system.cpu.commit.committedOps 349065061 # Number of ops (including micro ops) committed 577system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 578system.cpu.commit.refs 177024331 # Number of memory references committed 579system.cpu.commit.loads 94648748 # Number of loads committed 580system.cpu.commit.membars 11033 # Number of memory barriers committed 581system.cpu.commit.branches 30563497 # Number of branches committed 582system.cpu.commit.fp_insts 114216705 # Number of committed floating point instructions. 583system.cpu.commit.int_insts 279584611 # Number of committed integer instructions. 584system.cpu.commit.function_calls 6225112 # Number of function calls committed. 585system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 586system.cpu.commit.op_class_0::IntAlu 116648967 33.42% 33.42% # Class of committed instruction 587system.cpu.commit.op_class_0::IntMult 2145845 0.61% 34.03% # Class of committed instruction 588system.cpu.commit.op_class_0::IntDiv 0 0.00% 34.03% # Class of committed instruction 589system.cpu.commit.op_class_0::FloatAdd 0 0.00% 34.03% # Class of committed instruction 590system.cpu.commit.op_class_0::FloatCmp 0 0.00% 34.03% # Class of committed instruction 591system.cpu.commit.op_class_0::FloatCvt 0 0.00% 34.03% # Class of committed instruction 592system.cpu.commit.op_class_0::FloatMult 0 0.00% 34.03% # Class of committed instruction 593system.cpu.commit.op_class_0::FloatDiv 0 0.00% 34.03% # Class of committed instruction 594system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 34.03% # Class of committed instruction 595system.cpu.commit.op_class_0::SimdAdd 0 0.00% 34.03% # Class of committed instruction 596system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 34.03% # Class of committed instruction 597system.cpu.commit.op_class_0::SimdAlu 0 0.00% 34.03% # Class of committed instruction 598system.cpu.commit.op_class_0::SimdCmp 0 0.00% 34.03% # Class of committed instruction 599system.cpu.commit.op_class_0::SimdCvt 0 0.00% 34.03% # Class of committed instruction 600system.cpu.commit.op_class_0::SimdMisc 0 0.00% 34.03% # Class of committed instruction 601system.cpu.commit.op_class_0::SimdMult 0 0.00% 34.03% # Class of committed instruction 602system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 34.03% # Class of committed instruction 603system.cpu.commit.op_class_0::SimdShift 0 0.00% 34.03% # Class of committed instruction 604system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 34.03% # Class of committed instruction 605system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 34.03% # Class of committed instruction 606system.cpu.commit.op_class_0::SimdFloatAdd 6594343 1.89% 35.92% # Class of committed instruction 607system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 35.92% # Class of committed instruction 608system.cpu.commit.op_class_0::SimdFloatCmp 7943502 2.28% 38.20% # Class of committed instruction 609system.cpu.commit.op_class_0::SimdFloatCvt 3118180 0.89% 39.09% # Class of committed instruction 610system.cpu.commit.op_class_0::SimdFloatDiv 1563217 0.45% 39.54% # Class of committed instruction 611system.cpu.commit.op_class_0::SimdFloatMisc 19652356 5.63% 45.17% # Class of committed instruction 612system.cpu.commit.op_class_0::SimdFloatMult 7136937 2.04% 47.21% # Class of committed instruction 613system.cpu.commit.op_class_0::SimdFloatMultAcc 7062098 2.02% 49.24% # Class of committed instruction 614system.cpu.commit.op_class_0::SimdFloatSqrt 175285 0.05% 49.29% # Class of committed instruction 615system.cpu.commit.op_class_0::MemRead 94648748 27.11% 76.40% # Class of committed instruction 616system.cpu.commit.op_class_0::MemWrite 82375583 23.60% 100.00% # Class of committed instruction 617system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 618system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 619system.cpu.commit.op_class_0::total 349065061 # Class of committed instruction 620system.cpu.commit.bw_lim_events 14620260 # number cycles where commit BW limit reached 621system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 622system.cpu.rob.rob_reads 501621219 # The number of ROB reads 623system.cpu.rob.rob_writes 774485510 # The number of ROB writes 624system.cpu.timesIdled 6746 # Number of times that the entire CPU went into an idle state and unscheduled itself 625system.cpu.idleCycles 353987 # Total number of cycles that the CPU has spent unscheduled due to idling 626system.cpu.committedInsts 273036725 # Number of Instructions Simulated 627system.cpu.committedOps 349064449 # Number of Ops (including micro ops) Simulated 628system.cpu.committedInsts_total 273036725 # Number of Instructions Simulated 629system.cpu.cpi 0.502059 # CPI: Cycles Per Instruction 630system.cpu.cpi_total 0.502059 # CPI: Total CPI of All Threads 631system.cpu.ipc 1.991799 # IPC: Instructions Per Cycle 632system.cpu.ipc_total 1.991799 # IPC: Total IPC of All Threads 633system.cpu.int_regfile_reads 1770130874 # number of integer regfile reads 634system.cpu.int_regfile_writes 233038396 # number of integer regfile writes 635system.cpu.fp_regfile_reads 188133896 # number of floating regfile reads 636system.cpu.fp_regfile_writes 132498519 # number of floating regfile writes 637system.cpu.misc_regfile_reads 1201060026 # number of misc regfile reads 638system.cpu.misc_regfile_writes 34421755 # number of misc regfile writes 639system.cpu.toL2Bus.throughput 20063659 # Throughput (bytes/s) 640system.cpu.toL2Bus.trans_dist::ReadReq 17609 # Transaction distribution 641system.cpu.toL2Bus.trans_dist::ReadResp 17609 # Transaction distribution 642system.cpu.toL2Bus.trans_dist::Writeback 1041 # Transaction distribution 643system.cpu.toL2Bus.trans_dist::UpgradeReq 2 # Transaction distribution 644system.cpu.toL2Bus.trans_dist::UpgradeResp 2 # Transaction distribution 645system.cpu.toL2Bus.trans_dist::ReadExReq 2837 # Transaction distribution 646system.cpu.toL2Bus.trans_dist::ReadExResp 2837 # Transaction distribution 647system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 31648 # Packet count per connected master and slave (bytes) 648system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10285 # Packet count per connected master and slave (bytes) 649system.cpu.toL2Bus.pkt_count::total 41933 # Packet count per connected master and slave (bytes) 650system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1012608 # Cumulative packet size per connected master and slave (bytes) 651system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 362304 # Cumulative packet size per connected master and slave (bytes) 652system.cpu.toL2Bus.tot_pkt_size::total 1374912 # Cumulative packet size per connected master and slave (bytes) 653system.cpu.toL2Bus.data_through_bus 1374912 # Total data (bytes) 654system.cpu.toL2Bus.snoop_data_through_bus 256 # Total snoop data (bytes) 655system.cpu.toL2Bus.reqLayer0.occupancy 11785500 # Layer occupancy (ticks) 656system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 657system.cpu.toL2Bus.respLayer0.occupancy 24279239 # Layer occupancy (ticks) 658system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 659system.cpu.toL2Bus.respLayer1.occupancy 7466709 # Layer occupancy (ticks) 660system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 661system.cpu.icache.tags.replacements 13936 # number of replacements 662system.cpu.icache.tags.tagsinuse 1847.607729 # Cycle average of tags in use 663system.cpu.icache.tags.total_refs 37591137 # Total number of references to valid blocks. 664system.cpu.icache.tags.sampled_refs 15825 # Sample count of references to valid blocks. 665system.cpu.icache.tags.avg_refs 2375.427299 # Average number of references to valid blocks. 666system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 667system.cpu.icache.tags.occ_blocks::cpu.inst 1847.607729 # Average occupied blocks per requestor 668system.cpu.icache.tags.occ_percent::cpu.inst 0.902152 # Average percentage of cache occupancy 669system.cpu.icache.tags.occ_percent::total 0.902152 # Average percentage of cache occupancy 670system.cpu.icache.tags.occ_task_id_blocks::1024 1889 # Occupied blocks per task id 671system.cpu.icache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id 672system.cpu.icache.tags.age_task_id_blocks_1024::1 89 # Occupied blocks per task id 673system.cpu.icache.tags.age_task_id_blocks_1024::2 210 # Occupied blocks per task id 674system.cpu.icache.tags.age_task_id_blocks_1024::3 9 # Occupied blocks per task id 675system.cpu.icache.tags.age_task_id_blocks_1024::4 1525 # Occupied blocks per task id 676system.cpu.icache.tags.occ_task_id_percent::1024 0.922363 # Percentage of cache occupancy per task id 677system.cpu.icache.tags.tag_accesses 75232724 # Number of tag accesses 678system.cpu.icache.tags.data_accesses 75232724 # Number of data accesses 679system.cpu.icache.ReadReq_hits::cpu.inst 37591137 # number of ReadReq hits 680system.cpu.icache.ReadReq_hits::total 37591137 # number of ReadReq hits 681system.cpu.icache.demand_hits::cpu.inst 37591137 # number of demand (read+write) hits 682system.cpu.icache.demand_hits::total 37591137 # number of demand (read+write) hits 683system.cpu.icache.overall_hits::cpu.inst 37591137 # number of overall hits 684system.cpu.icache.overall_hits::total 37591137 # number of overall hits 685system.cpu.icache.ReadReq_misses::cpu.inst 17312 # number of ReadReq misses 686system.cpu.icache.ReadReq_misses::total 17312 # number of ReadReq misses 687system.cpu.icache.demand_misses::cpu.inst 17312 # number of demand (read+write) misses 688system.cpu.icache.demand_misses::total 17312 # number of demand (read+write) misses 689system.cpu.icache.overall_misses::cpu.inst 17312 # number of overall misses 690system.cpu.icache.overall_misses::total 17312 # number of overall misses 691system.cpu.icache.ReadReq_miss_latency::cpu.inst 452091985 # number of ReadReq miss cycles 692system.cpu.icache.ReadReq_miss_latency::total 452091985 # number of ReadReq miss cycles 693system.cpu.icache.demand_miss_latency::cpu.inst 452091985 # number of demand (read+write) miss cycles 694system.cpu.icache.demand_miss_latency::total 452091985 # number of demand (read+write) miss cycles 695system.cpu.icache.overall_miss_latency::cpu.inst 452091985 # number of overall miss cycles 696system.cpu.icache.overall_miss_latency::total 452091985 # number of overall miss cycles 697system.cpu.icache.ReadReq_accesses::cpu.inst 37608449 # number of ReadReq accesses(hits+misses) 698system.cpu.icache.ReadReq_accesses::total 37608449 # number of ReadReq accesses(hits+misses) 699system.cpu.icache.demand_accesses::cpu.inst 37608449 # number of demand (read+write) accesses 700system.cpu.icache.demand_accesses::total 37608449 # number of demand (read+write) accesses 701system.cpu.icache.overall_accesses::cpu.inst 37608449 # number of overall (read+write) accesses 702system.cpu.icache.overall_accesses::total 37608449 # number of overall (read+write) accesses 703system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000460 # miss rate for ReadReq accesses 704system.cpu.icache.ReadReq_miss_rate::total 0.000460 # miss rate for ReadReq accesses 705system.cpu.icache.demand_miss_rate::cpu.inst 0.000460 # miss rate for demand accesses 706system.cpu.icache.demand_miss_rate::total 0.000460 # miss rate for demand accesses 707system.cpu.icache.overall_miss_rate::cpu.inst 0.000460 # miss rate for overall accesses 708system.cpu.icache.overall_miss_rate::total 0.000460 # miss rate for overall accesses 709system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 26114.370668 # average ReadReq miss latency 710system.cpu.icache.ReadReq_avg_miss_latency::total 26114.370668 # average ReadReq miss latency 711system.cpu.icache.demand_avg_miss_latency::cpu.inst 26114.370668 # average overall miss latency 712system.cpu.icache.demand_avg_miss_latency::total 26114.370668 # average overall miss latency 713system.cpu.icache.overall_avg_miss_latency::cpu.inst 26114.370668 # average overall miss latency 714system.cpu.icache.overall_avg_miss_latency::total 26114.370668 # average overall miss latency 715system.cpu.icache.blocked_cycles::no_mshrs 970 # number of cycles access was blocked 716system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 717system.cpu.icache.blocked::no_mshrs 19 # number of cycles access was blocked 718system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 719system.cpu.icache.avg_blocked_cycles::no_mshrs 51.052632 # average number of cycles each access was blocked 720system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 721system.cpu.icache.fast_writes 0 # number of fast writes performed 722system.cpu.icache.cache_copies 0 # number of cache copies performed 723system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1486 # number of ReadReq MSHR hits 724system.cpu.icache.ReadReq_mshr_hits::total 1486 # number of ReadReq MSHR hits 725system.cpu.icache.demand_mshr_hits::cpu.inst 1486 # number of demand (read+write) MSHR hits 726system.cpu.icache.demand_mshr_hits::total 1486 # number of demand (read+write) MSHR hits 727system.cpu.icache.overall_mshr_hits::cpu.inst 1486 # number of overall MSHR hits 728system.cpu.icache.overall_mshr_hits::total 1486 # number of overall MSHR hits 729system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15826 # number of ReadReq MSHR misses 730system.cpu.icache.ReadReq_mshr_misses::total 15826 # number of ReadReq MSHR misses 731system.cpu.icache.demand_mshr_misses::cpu.inst 15826 # number of demand (read+write) MSHR misses 732system.cpu.icache.demand_mshr_misses::total 15826 # number of demand (read+write) MSHR misses 733system.cpu.icache.overall_mshr_misses::cpu.inst 15826 # number of overall MSHR misses 734system.cpu.icache.overall_mshr_misses::total 15826 # number of overall MSHR misses 735system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 356931509 # number of ReadReq MSHR miss cycles 736system.cpu.icache.ReadReq_mshr_miss_latency::total 356931509 # number of ReadReq MSHR miss cycles 737system.cpu.icache.demand_mshr_miss_latency::cpu.inst 356931509 # number of demand (read+write) MSHR miss cycles 738system.cpu.icache.demand_mshr_miss_latency::total 356931509 # number of demand (read+write) MSHR miss cycles 739system.cpu.icache.overall_mshr_miss_latency::cpu.inst 356931509 # number of overall MSHR miss cycles 740system.cpu.icache.overall_mshr_miss_latency::total 356931509 # number of overall MSHR miss cycles 741system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000421 # mshr miss rate for ReadReq accesses 742system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000421 # mshr miss rate for ReadReq accesses 743system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000421 # mshr miss rate for demand accesses 744system.cpu.icache.demand_mshr_miss_rate::total 0.000421 # mshr miss rate for demand accesses 745system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000421 # mshr miss rate for overall accesses 746system.cpu.icache.overall_mshr_miss_rate::total 0.000421 # mshr miss rate for overall accesses 747system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22553.488500 # average ReadReq mshr miss latency 748system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22553.488500 # average ReadReq mshr miss latency 749system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22553.488500 # average overall mshr miss latency 750system.cpu.icache.demand_avg_mshr_miss_latency::total 22553.488500 # average overall mshr miss latency 751system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22553.488500 # average overall mshr miss latency 752system.cpu.icache.overall_avg_mshr_miss_latency::total 22553.488500 # average overall mshr miss latency 753system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 754system.cpu.l2cache.tags.replacements 0 # number of replacements 755system.cpu.l2cache.tags.tagsinuse 3938.278477 # Cycle average of tags in use 756system.cpu.l2cache.tags.total_refs 13178 # Total number of references to valid blocks. 757system.cpu.l2cache.tags.sampled_refs 5394 # Sample count of references to valid blocks. 758system.cpu.l2cache.tags.avg_refs 2.443085 # Average number of references to valid blocks. 759system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 760system.cpu.l2cache.tags.occ_blocks::writebacks 377.930800 # Average occupied blocks per requestor 761system.cpu.l2cache.tags.occ_blocks::cpu.inst 2772.496816 # Average occupied blocks per requestor 762system.cpu.l2cache.tags.occ_blocks::cpu.data 787.850861 # Average occupied blocks per requestor 763system.cpu.l2cache.tags.occ_percent::writebacks 0.011534 # Average percentage of cache occupancy 764system.cpu.l2cache.tags.occ_percent::cpu.inst 0.084610 # Average percentage of cache occupancy 765system.cpu.l2cache.tags.occ_percent::cpu.data 0.024043 # Average percentage of cache occupancy 766system.cpu.l2cache.tags.occ_percent::total 0.120187 # Average percentage of cache occupancy 767system.cpu.l2cache.tags.occ_task_id_blocks::1024 5394 # Occupied blocks per task id 768system.cpu.l2cache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id 769system.cpu.l2cache.tags.age_task_id_blocks_1024::1 68 # Occupied blocks per task id 770system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1247 # Occupied blocks per task id 771system.cpu.l2cache.tags.age_task_id_blocks_1024::3 11 # Occupied blocks per task id 772system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4004 # Occupied blocks per task id 773system.cpu.l2cache.tags.occ_task_id_percent::1024 0.164612 # Percentage of cache occupancy per task id 774system.cpu.l2cache.tags.tag_accesses 180111 # Number of tag accesses 775system.cpu.l2cache.tags.data_accesses 180111 # Number of data accesses 776system.cpu.l2cache.ReadReq_hits::cpu.inst 12781 # number of ReadReq hits 777system.cpu.l2cache.ReadReq_hits::cpu.data 302 # number of ReadReq hits 778system.cpu.l2cache.ReadReq_hits::total 13083 # number of ReadReq hits 779system.cpu.l2cache.Writeback_hits::writebacks 1041 # number of Writeback hits 780system.cpu.l2cache.Writeback_hits::total 1041 # number of Writeback hits 781system.cpu.l2cache.ReadExReq_hits::cpu.data 18 # number of ReadExReq hits 782system.cpu.l2cache.ReadExReq_hits::total 18 # number of ReadExReq hits 783system.cpu.l2cache.demand_hits::cpu.inst 12781 # number of demand (read+write) hits 784system.cpu.l2cache.demand_hits::cpu.data 320 # number of demand (read+write) hits 785system.cpu.l2cache.demand_hits::total 13101 # number of demand (read+write) hits 786system.cpu.l2cache.overall_hits::cpu.inst 12781 # number of overall hits 787system.cpu.l2cache.overall_hits::cpu.data 320 # number of overall hits 788system.cpu.l2cache.overall_hits::total 13101 # number of overall hits 789system.cpu.l2cache.ReadReq_misses::cpu.inst 3041 # number of ReadReq misses 790system.cpu.l2cache.ReadReq_misses::cpu.data 1481 # number of ReadReq misses 791system.cpu.l2cache.ReadReq_misses::total 4522 # number of ReadReq misses 792system.cpu.l2cache.UpgradeReq_misses::cpu.data 2 # number of UpgradeReq misses 793system.cpu.l2cache.UpgradeReq_misses::total 2 # number of UpgradeReq misses 794system.cpu.l2cache.ReadExReq_misses::cpu.data 2819 # number of ReadExReq misses 795system.cpu.l2cache.ReadExReq_misses::total 2819 # number of ReadExReq misses 796system.cpu.l2cache.demand_misses::cpu.inst 3041 # number of demand (read+write) misses 797system.cpu.l2cache.demand_misses::cpu.data 4300 # number of demand (read+write) misses 798system.cpu.l2cache.demand_misses::total 7341 # number of demand (read+write) misses 799system.cpu.l2cache.overall_misses::cpu.inst 3041 # number of overall misses 800system.cpu.l2cache.overall_misses::cpu.data 4300 # number of overall misses 801system.cpu.l2cache.overall_misses::total 7341 # number of overall misses 802system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 213267000 # number of ReadReq miss cycles 803system.cpu.l2cache.ReadReq_miss_latency::cpu.data 109185750 # number of ReadReq miss cycles 804system.cpu.l2cache.ReadReq_miss_latency::total 322452750 # number of ReadReq miss cycles 805system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 198902000 # number of ReadExReq miss cycles 806system.cpu.l2cache.ReadExReq_miss_latency::total 198902000 # number of ReadExReq miss cycles 807system.cpu.l2cache.demand_miss_latency::cpu.inst 213267000 # number of demand (read+write) miss cycles 808system.cpu.l2cache.demand_miss_latency::cpu.data 308087750 # number of demand (read+write) miss cycles 809system.cpu.l2cache.demand_miss_latency::total 521354750 # number of demand (read+write) miss cycles 810system.cpu.l2cache.overall_miss_latency::cpu.inst 213267000 # number of overall miss cycles 811system.cpu.l2cache.overall_miss_latency::cpu.data 308087750 # number of overall miss cycles 812system.cpu.l2cache.overall_miss_latency::total 521354750 # number of overall miss cycles 813system.cpu.l2cache.ReadReq_accesses::cpu.inst 15822 # number of ReadReq accesses(hits+misses) 814system.cpu.l2cache.ReadReq_accesses::cpu.data 1783 # number of ReadReq accesses(hits+misses) 815system.cpu.l2cache.ReadReq_accesses::total 17605 # number of ReadReq accesses(hits+misses) 816system.cpu.l2cache.Writeback_accesses::writebacks 1041 # number of Writeback accesses(hits+misses) 817system.cpu.l2cache.Writeback_accesses::total 1041 # number of Writeback accesses(hits+misses) 818system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2 # number of UpgradeReq accesses(hits+misses) 819system.cpu.l2cache.UpgradeReq_accesses::total 2 # number of UpgradeReq accesses(hits+misses) 820system.cpu.l2cache.ReadExReq_accesses::cpu.data 2837 # number of ReadExReq accesses(hits+misses) 821system.cpu.l2cache.ReadExReq_accesses::total 2837 # number of ReadExReq accesses(hits+misses) 822system.cpu.l2cache.demand_accesses::cpu.inst 15822 # number of demand (read+write) accesses 823system.cpu.l2cache.demand_accesses::cpu.data 4620 # number of demand (read+write) accesses 824system.cpu.l2cache.demand_accesses::total 20442 # number of demand (read+write) accesses 825system.cpu.l2cache.overall_accesses::cpu.inst 15822 # number of overall (read+write) accesses 826system.cpu.l2cache.overall_accesses::cpu.data 4620 # number of overall (read+write) accesses 827system.cpu.l2cache.overall_accesses::total 20442 # number of overall (read+write) accesses 828system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.192201 # miss rate for ReadReq accesses 829system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.830623 # miss rate for ReadReq accesses 830system.cpu.l2cache.ReadReq_miss_rate::total 0.256859 # miss rate for ReadReq accesses 831system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses 832system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses 833system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.993655 # miss rate for ReadExReq accesses 834system.cpu.l2cache.ReadExReq_miss_rate::total 0.993655 # miss rate for ReadExReq accesses 835system.cpu.l2cache.demand_miss_rate::cpu.inst 0.192201 # miss rate for demand accesses 836system.cpu.l2cache.demand_miss_rate::cpu.data 0.930736 # miss rate for demand accesses 837system.cpu.l2cache.demand_miss_rate::total 0.359114 # miss rate for demand accesses 838system.cpu.l2cache.overall_miss_rate::cpu.inst 0.192201 # miss rate for overall accesses 839system.cpu.l2cache.overall_miss_rate::cpu.data 0.930736 # miss rate for overall accesses 840system.cpu.l2cache.overall_miss_rate::total 0.359114 # miss rate for overall accesses 841system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70130.549161 # average ReadReq miss latency 842system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 73724.341661 # average ReadReq miss latency 843system.cpu.l2cache.ReadReq_avg_miss_latency::total 71307.551968 # average ReadReq miss latency 844system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70557.644555 # average ReadExReq miss latency 845system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70557.644555 # average ReadExReq miss latency 846system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70130.549161 # average overall miss latency 847system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71648.313953 # average overall miss latency 848system.cpu.l2cache.demand_avg_miss_latency::total 71019.581801 # average overall miss latency 849system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70130.549161 # average overall miss latency 850system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71648.313953 # average overall miss latency 851system.cpu.l2cache.overall_avg_miss_latency::total 71019.581801 # average overall miss latency 852system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 853system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 854system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 855system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 856system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 857system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 858system.cpu.l2cache.fast_writes 0 # number of fast writes performed 859system.cpu.l2cache.cache_copies 0 # number of cache copies performed 860system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 11 # number of ReadReq MSHR hits 861system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 43 # number of ReadReq MSHR hits 862system.cpu.l2cache.ReadReq_mshr_hits::total 54 # number of ReadReq MSHR hits 863system.cpu.l2cache.demand_mshr_hits::cpu.inst 11 # number of demand (read+write) MSHR hits 864system.cpu.l2cache.demand_mshr_hits::cpu.data 43 # number of demand (read+write) MSHR hits 865system.cpu.l2cache.demand_mshr_hits::total 54 # number of demand (read+write) MSHR hits 866system.cpu.l2cache.overall_mshr_hits::cpu.inst 11 # number of overall MSHR hits 867system.cpu.l2cache.overall_mshr_hits::cpu.data 43 # number of overall MSHR hits 868system.cpu.l2cache.overall_mshr_hits::total 54 # number of overall MSHR hits 869system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3030 # number of ReadReq MSHR misses 870system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1438 # number of ReadReq MSHR misses 871system.cpu.l2cache.ReadReq_mshr_misses::total 4468 # number of ReadReq MSHR misses 872system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2 # number of UpgradeReq MSHR misses 873system.cpu.l2cache.UpgradeReq_mshr_misses::total 2 # number of UpgradeReq MSHR misses 874system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 2819 # number of ReadExReq MSHR misses 875system.cpu.l2cache.ReadExReq_mshr_misses::total 2819 # number of ReadExReq MSHR misses 876system.cpu.l2cache.demand_mshr_misses::cpu.inst 3030 # number of demand (read+write) MSHR misses 877system.cpu.l2cache.demand_mshr_misses::cpu.data 4257 # number of demand (read+write) MSHR misses 878system.cpu.l2cache.demand_mshr_misses::total 7287 # number of demand (read+write) MSHR misses 879system.cpu.l2cache.overall_mshr_misses::cpu.inst 3030 # number of overall MSHR misses 880system.cpu.l2cache.overall_mshr_misses::cpu.data 4257 # number of overall MSHR misses 881system.cpu.l2cache.overall_mshr_misses::total 7287 # number of overall MSHR misses 882system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 174561000 # number of ReadReq MSHR miss cycles 883system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 88459500 # number of ReadReq MSHR miss cycles 884system.cpu.l2cache.ReadReq_mshr_miss_latency::total 263020500 # number of ReadReq MSHR miss cycles 885system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 20002 # number of UpgradeReq MSHR miss cycles 886system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 20002 # number of UpgradeReq MSHR miss cycles 887system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 163883500 # number of ReadExReq MSHR miss cycles 888system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 163883500 # number of ReadExReq MSHR miss cycles 889system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 174561000 # number of demand (read+write) MSHR miss cycles 890system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 252343000 # number of demand (read+write) MSHR miss cycles 891system.cpu.l2cache.demand_mshr_miss_latency::total 426904000 # number of demand (read+write) MSHR miss cycles 892system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 174561000 # number of overall MSHR miss cycles 893system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 252343000 # number of overall MSHR miss cycles 894system.cpu.l2cache.overall_mshr_miss_latency::total 426904000 # number of overall MSHR miss cycles 895system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.191505 # mshr miss rate for ReadReq accesses 896system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.806506 # mshr miss rate for ReadReq accesses 897system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.253792 # mshr miss rate for ReadReq accesses 898system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses 899system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses 900system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.993655 # mshr miss rate for ReadExReq accesses 901system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.993655 # mshr miss rate for ReadExReq accesses 902system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.191505 # mshr miss rate for demand accesses 903system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.921429 # mshr miss rate for demand accesses 904system.cpu.l2cache.demand_mshr_miss_rate::total 0.356472 # mshr miss rate for demand accesses 905system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.191505 # mshr miss rate for overall accesses 906system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.921429 # mshr miss rate for overall accesses 907system.cpu.l2cache.overall_mshr_miss_rate::total 0.356472 # mshr miss rate for overall accesses 908system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57610.891089 # average ReadReq mshr miss latency 909system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 61515.646732 # average ReadReq mshr miss latency 910system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58867.614145 # average ReadReq mshr miss latency 911system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency 912system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency 913system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58135.331678 # average ReadExReq mshr miss latency 914system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58135.331678 # average ReadExReq mshr miss latency 915system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57610.891089 # average overall mshr miss latency 916system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59277.190510 # average overall mshr miss latency 917system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58584.328256 # average overall mshr miss latency 918system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57610.891089 # average overall mshr miss latency 919system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59277.190510 # average overall mshr miss latency 920system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58584.328256 # average overall mshr miss latency 921system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 922system.cpu.dcache.tags.replacements 1423 # number of replacements 923system.cpu.dcache.tags.tagsinuse 3106.690369 # Cycle average of tags in use 924system.cpu.dcache.tags.total_refs 170987022 # Total number of references to valid blocks. 925system.cpu.dcache.tags.sampled_refs 4620 # Sample count of references to valid blocks. 926system.cpu.dcache.tags.avg_refs 37010.177922 # Average number of references to valid blocks. 927system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 928system.cpu.dcache.tags.occ_blocks::cpu.data 3106.690369 # Average occupied blocks per requestor 929system.cpu.dcache.tags.occ_percent::cpu.data 0.758469 # Average percentage of cache occupancy 930system.cpu.dcache.tags.occ_percent::total 0.758469 # Average percentage of cache occupancy 931system.cpu.dcache.tags.occ_task_id_blocks::1024 3197 # Occupied blocks per task id 932system.cpu.dcache.tags.age_task_id_blocks_1024::0 25 # Occupied blocks per task id 933system.cpu.dcache.tags.age_task_id_blocks_1024::1 30 # Occupied blocks per task id 934system.cpu.dcache.tags.age_task_id_blocks_1024::2 683 # Occupied blocks per task id 935system.cpu.dcache.tags.age_task_id_blocks_1024::3 11 # Occupied blocks per task id 936system.cpu.dcache.tags.age_task_id_blocks_1024::4 2448 # Occupied blocks per task id 937system.cpu.dcache.tags.occ_task_id_percent::1024 0.780518 # Percentage of cache occupancy per task id 938system.cpu.dcache.tags.tag_accesses 342028974 # Number of tag accesses 939system.cpu.dcache.tags.data_accesses 342028974 # Number of data accesses 940system.cpu.dcache.ReadReq_hits::cpu.data 88933648 # number of ReadReq hits 941system.cpu.dcache.ReadReq_hits::total 88933648 # number of ReadReq hits 942system.cpu.dcache.WriteReq_hits::cpu.data 82031473 # number of WriteReq hits 943system.cpu.dcache.WriteReq_hits::total 82031473 # number of WriteReq hits 944system.cpu.dcache.LoadLockedReq_hits::cpu.data 10994 # number of LoadLockedReq hits 945system.cpu.dcache.LoadLockedReq_hits::total 10994 # number of LoadLockedReq hits 946system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits 947system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits 948system.cpu.dcache.demand_hits::cpu.data 170965121 # number of demand (read+write) hits 949system.cpu.dcache.demand_hits::total 170965121 # number of demand (read+write) hits 950system.cpu.dcache.overall_hits::cpu.data 170965121 # number of overall hits 951system.cpu.dcache.overall_hits::total 170965121 # number of overall hits 952system.cpu.dcache.ReadReq_misses::cpu.data 3973 # number of ReadReq misses 953system.cpu.dcache.ReadReq_misses::total 3973 # number of ReadReq misses 954system.cpu.dcache.WriteReq_misses::cpu.data 21192 # number of WriteReq misses 955system.cpu.dcache.WriteReq_misses::total 21192 # number of WriteReq misses 956system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses 957system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses 958system.cpu.dcache.demand_misses::cpu.data 25165 # number of demand (read+write) misses 959system.cpu.dcache.demand_misses::total 25165 # number of demand (read+write) misses 960system.cpu.dcache.overall_misses::cpu.data 25165 # number of overall misses 961system.cpu.dcache.overall_misses::total 25165 # number of overall misses 962system.cpu.dcache.ReadReq_miss_latency::cpu.data 236002703 # number of ReadReq miss cycles 963system.cpu.dcache.ReadReq_miss_latency::total 236002703 # number of ReadReq miss cycles 964system.cpu.dcache.WriteReq_miss_latency::cpu.data 1249306876 # number of WriteReq miss cycles 965system.cpu.dcache.WriteReq_miss_latency::total 1249306876 # number of WriteReq miss cycles 966system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 170250 # number of LoadLockedReq miss cycles 967system.cpu.dcache.LoadLockedReq_miss_latency::total 170250 # number of LoadLockedReq miss cycles 968system.cpu.dcache.demand_miss_latency::cpu.data 1485309579 # number of demand (read+write) miss cycles 969system.cpu.dcache.demand_miss_latency::total 1485309579 # number of demand (read+write) miss cycles 970system.cpu.dcache.overall_miss_latency::cpu.data 1485309579 # number of overall miss cycles 971system.cpu.dcache.overall_miss_latency::total 1485309579 # number of overall miss cycles 972system.cpu.dcache.ReadReq_accesses::cpu.data 88937621 # number of ReadReq accesses(hits+misses) 973system.cpu.dcache.ReadReq_accesses::total 88937621 # number of ReadReq accesses(hits+misses) 974system.cpu.dcache.WriteReq_accesses::cpu.data 82052665 # number of WriteReq accesses(hits+misses) 975system.cpu.dcache.WriteReq_accesses::total 82052665 # number of WriteReq accesses(hits+misses) 976system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10996 # number of LoadLockedReq accesses(hits+misses) 977system.cpu.dcache.LoadLockedReq_accesses::total 10996 # number of LoadLockedReq accesses(hits+misses) 978system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses) 979system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) 980system.cpu.dcache.demand_accesses::cpu.data 170990286 # number of demand (read+write) accesses 981system.cpu.dcache.demand_accesses::total 170990286 # number of demand (read+write) accesses 982system.cpu.dcache.overall_accesses::cpu.data 170990286 # number of overall (read+write) accesses 983system.cpu.dcache.overall_accesses::total 170990286 # number of overall (read+write) accesses 984system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000045 # miss rate for ReadReq accesses 985system.cpu.dcache.ReadReq_miss_rate::total 0.000045 # miss rate for ReadReq accesses 986system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000258 # miss rate for WriteReq accesses 987system.cpu.dcache.WriteReq_miss_rate::total 0.000258 # miss rate for WriteReq accesses 988system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000182 # miss rate for LoadLockedReq accesses 989system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000182 # miss rate for LoadLockedReq accesses 990system.cpu.dcache.demand_miss_rate::cpu.data 0.000147 # miss rate for demand accesses 991system.cpu.dcache.demand_miss_rate::total 0.000147 # miss rate for demand accesses 992system.cpu.dcache.overall_miss_rate::cpu.data 0.000147 # miss rate for overall accesses 993system.cpu.dcache.overall_miss_rate::total 0.000147 # miss rate for overall accesses 994system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 59401.636798 # average ReadReq miss latency 995system.cpu.dcache.ReadReq_avg_miss_latency::total 59401.636798 # average ReadReq miss latency 996system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 58951.815591 # average WriteReq miss latency 997system.cpu.dcache.WriteReq_avg_miss_latency::total 58951.815591 # average WriteReq miss latency 998system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 85125 # average LoadLockedReq miss latency 999system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 85125 # average LoadLockedReq miss latency 1000system.cpu.dcache.demand_avg_miss_latency::cpu.data 59022.832466 # average overall miss latency 1001system.cpu.dcache.demand_avg_miss_latency::total 59022.832466 # average overall miss latency 1002system.cpu.dcache.overall_avg_miss_latency::cpu.data 59022.832466 # average overall miss latency 1003system.cpu.dcache.overall_avg_miss_latency::total 59022.832466 # average overall miss latency 1004system.cpu.dcache.blocked_cycles::no_mshrs 25911 # number of cycles access was blocked 1005system.cpu.dcache.blocked_cycles::no_targets 1248 # number of cycles access was blocked 1006system.cpu.dcache.blocked::no_mshrs 444 # number of cycles access was blocked 1007system.cpu.dcache.blocked::no_targets 13 # number of cycles access was blocked 1008system.cpu.dcache.avg_blocked_cycles::no_mshrs 58.358108 # average number of cycles each access was blocked 1009system.cpu.dcache.avg_blocked_cycles::no_targets 96 # average number of cycles each access was blocked 1010system.cpu.dcache.fast_writes 0 # number of fast writes performed 1011system.cpu.dcache.cache_copies 0 # number of cache copies performed 1012system.cpu.dcache.writebacks::writebacks 1041 # number of writebacks 1013system.cpu.dcache.writebacks::total 1041 # number of writebacks 1014system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2189 # number of ReadReq MSHR hits 1015system.cpu.dcache.ReadReq_mshr_hits::total 2189 # number of ReadReq MSHR hits 1016system.cpu.dcache.WriteReq_mshr_hits::cpu.data 18354 # number of WriteReq MSHR hits 1017system.cpu.dcache.WriteReq_mshr_hits::total 18354 # number of WriteReq MSHR hits 1018system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits 1019system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits 1020system.cpu.dcache.demand_mshr_hits::cpu.data 20543 # number of demand (read+write) MSHR hits 1021system.cpu.dcache.demand_mshr_hits::total 20543 # number of demand (read+write) MSHR hits 1022system.cpu.dcache.overall_mshr_hits::cpu.data 20543 # number of overall MSHR hits 1023system.cpu.dcache.overall_mshr_hits::total 20543 # number of overall MSHR hits 1024system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1784 # number of ReadReq MSHR misses 1025system.cpu.dcache.ReadReq_mshr_misses::total 1784 # number of ReadReq MSHR misses 1026system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2838 # number of WriteReq MSHR misses 1027system.cpu.dcache.WriteReq_mshr_misses::total 2838 # number of WriteReq MSHR misses 1028system.cpu.dcache.demand_mshr_misses::cpu.data 4622 # number of demand (read+write) MSHR misses 1029system.cpu.dcache.demand_mshr_misses::total 4622 # number of demand (read+write) MSHR misses 1030system.cpu.dcache.overall_mshr_misses::cpu.data 4622 # number of overall MSHR misses 1031system.cpu.dcache.overall_mshr_misses::total 4622 # number of overall MSHR misses 1032system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 114103043 # number of ReadReq MSHR miss cycles 1033system.cpu.dcache.ReadReq_mshr_miss_latency::total 114103043 # number of ReadReq MSHR miss cycles 1034system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 201967248 # number of WriteReq MSHR miss cycles 1035system.cpu.dcache.WriteReq_mshr_miss_latency::total 201967248 # number of WriteReq MSHR miss cycles 1036system.cpu.dcache.demand_mshr_miss_latency::cpu.data 316070291 # number of demand (read+write) MSHR miss cycles 1037system.cpu.dcache.demand_mshr_miss_latency::total 316070291 # number of demand (read+write) MSHR miss cycles 1038system.cpu.dcache.overall_mshr_miss_latency::cpu.data 316070291 # number of overall MSHR miss cycles 1039system.cpu.dcache.overall_mshr_miss_latency::total 316070291 # number of overall MSHR miss cycles 1040system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000020 # mshr miss rate for ReadReq accesses 1041system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000020 # mshr miss rate for ReadReq accesses 1042system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses 1043system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000035 # mshr miss rate for WriteReq accesses 1044system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for demand accesses 1045system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses 1046system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses 1047system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses 1048system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 63959.104821 # average ReadReq mshr miss latency 1049system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 63959.104821 # average ReadReq mshr miss latency 1050system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71165.344609 # average WriteReq mshr miss latency 1051system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71165.344609 # average WriteReq mshr miss latency 1052system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68383.879489 # average overall mshr miss latency 1053system.cpu.dcache.demand_avg_mshr_miss_latency::total 68383.879489 # average overall mshr miss latency 1054system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68383.879489 # average overall mshr miss latency 1055system.cpu.dcache.overall_avg_mshr_miss_latency::total 68383.879489 # average overall mshr miss latency 1056system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1057 1058---------- End Simulation Statistics ---------- 1059