stats.txt revision 10148:4574d5882066
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.068245 # Number of seconds simulated 4sim_ticks 68245472000 # Number of ticks simulated 5final_tick 68245472000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 123424 # Simulator instruction rate (inst/s) 8host_op_rate 157791 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 30849723 # Simulator tick rate (ticks/s) 10host_mem_usage 321440 # Number of bytes of host memory used 11host_seconds 2212.19 # Real time elapsed on the host 12sim_insts 273036725 # Number of instructions simulated 13sim_ops 349064449 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 193792 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 272576 # Number of bytes read from this memory 18system.physmem.bytes_read::total 466368 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 193792 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 193792 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 3028 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 4259 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 7287 # Number of read requests responded to by this memory 24system.physmem.bw_read::cpu.inst 2839632 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 3994053 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 6833684 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 2839632 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 2839632 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 2839632 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 3994053 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 6833684 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.readReqs 7288 # Number of read requests accepted 33system.physmem.writeReqs 0 # Number of write requests accepted 34system.physmem.readBursts 7288 # Number of DRAM read bursts, including those serviced by the write queue 35system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 36system.physmem.bytesReadDRAM 466432 # Total number of bytes read from DRAM 37system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 38system.physmem.bytesWritten 0 # Total number of bytes written to DRAM 39system.physmem.bytesReadSys 466432 # Total read bytes from the system interface side 40system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 41system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 42system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 43system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 44system.physmem.perBankRdBursts::0 606 # Per bank write bursts 45system.physmem.perBankRdBursts::1 802 # Per bank write bursts 46system.physmem.perBankRdBursts::2 608 # Per bank write bursts 47system.physmem.perBankRdBursts::3 526 # Per bank write bursts 48system.physmem.perBankRdBursts::4 441 # Per bank write bursts 49system.physmem.perBankRdBursts::5 356 # Per bank write bursts 50system.physmem.perBankRdBursts::6 162 # Per bank write bursts 51system.physmem.perBankRdBursts::7 220 # Per bank write bursts 52system.physmem.perBankRdBursts::8 205 # Per bank write bursts 53system.physmem.perBankRdBursts::9 290 # Per bank write bursts 54system.physmem.perBankRdBursts::10 324 # Per bank write bursts 55system.physmem.perBankRdBursts::11 417 # Per bank write bursts 56system.physmem.perBankRdBursts::12 531 # Per bank write bursts 57system.physmem.perBankRdBursts::13 687 # Per bank write bursts 58system.physmem.perBankRdBursts::14 611 # Per bank write bursts 59system.physmem.perBankRdBursts::15 502 # Per bank write bursts 60system.physmem.perBankWrBursts::0 0 # Per bank write bursts 61system.physmem.perBankWrBursts::1 0 # Per bank write bursts 62system.physmem.perBankWrBursts::2 0 # Per bank write bursts 63system.physmem.perBankWrBursts::3 0 # Per bank write bursts 64system.physmem.perBankWrBursts::4 0 # Per bank write bursts 65system.physmem.perBankWrBursts::5 0 # Per bank write bursts 66system.physmem.perBankWrBursts::6 0 # Per bank write bursts 67system.physmem.perBankWrBursts::7 0 # Per bank write bursts 68system.physmem.perBankWrBursts::8 0 # Per bank write bursts 69system.physmem.perBankWrBursts::9 0 # Per bank write bursts 70system.physmem.perBankWrBursts::10 0 # Per bank write bursts 71system.physmem.perBankWrBursts::11 0 # Per bank write bursts 72system.physmem.perBankWrBursts::12 0 # Per bank write bursts 73system.physmem.perBankWrBursts::13 0 # Per bank write bursts 74system.physmem.perBankWrBursts::14 0 # Per bank write bursts 75system.physmem.perBankWrBursts::15 0 # Per bank write bursts 76system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 77system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 78system.physmem.totGap 68245446000 # Total gap between requests 79system.physmem.readPktSize::0 0 # Read request sizes (log2) 80system.physmem.readPktSize::1 0 # Read request sizes (log2) 81system.physmem.readPktSize::2 0 # Read request sizes (log2) 82system.physmem.readPktSize::3 0 # Read request sizes (log2) 83system.physmem.readPktSize::4 0 # Read request sizes (log2) 84system.physmem.readPktSize::5 0 # Read request sizes (log2) 85system.physmem.readPktSize::6 7288 # Read request sizes (log2) 86system.physmem.writePktSize::0 0 # Write request sizes (log2) 87system.physmem.writePktSize::1 0 # Write request sizes (log2) 88system.physmem.writePktSize::2 0 # Write request sizes (log2) 89system.physmem.writePktSize::3 0 # Write request sizes (log2) 90system.physmem.writePktSize::4 0 # Write request sizes (log2) 91system.physmem.writePktSize::5 0 # Write request sizes (log2) 92system.physmem.writePktSize::6 0 # Write request sizes (log2) 93system.physmem.rdQLenPdf::0 4342 # What read queue length does an incoming req see 94system.physmem.rdQLenPdf::1 2121 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::2 590 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::3 174 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::4 61 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 125system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 126system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 127system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 128system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 129system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 130system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 131system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 132system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 133system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 134system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 189system.physmem.bytesPerActivate::samples 580 # Bytes accessed per row activation 190system.physmem.bytesPerActivate::mean 479.779310 # Bytes accessed per row activation 191system.physmem.bytesPerActivate::gmean 274.986956 # Bytes accessed per row activation 192system.physmem.bytesPerActivate::stdev 421.744260 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::0-127 159 27.41% 27.41% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::128-255 117 20.17% 47.59% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::256-383 45 7.76% 55.34% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::384-511 23 3.97% 59.31% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::512-639 14 2.41% 61.72% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::640-767 13 2.24% 63.97% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::768-895 6 1.03% 65.00% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::896-1023 2 0.34% 65.34% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::1024-1151 201 34.66% 100.00% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::total 580 # Bytes accessed per row activation 203system.physmem.totQLat 57907000 # Total ticks spent queuing 204system.physmem.totMemAccLat 195684500 # Total ticks spent from burst creation until serviced by the DRAM 205system.physmem.totBusLat 36440000 # Total ticks spent in databus transfers 206system.physmem.totBankLat 101337500 # Total ticks spent accessing banks 207system.physmem.avgQLat 7945.53 # Average queueing delay per DRAM burst 208system.physmem.avgBankLat 13904.71 # Average bank access latency per DRAM burst 209system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 210system.physmem.avgMemAccLat 26850.23 # Average memory access latency per DRAM burst 211system.physmem.avgRdBW 6.83 # Average DRAM read bandwidth in MiByte/s 212system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 213system.physmem.avgRdBWSys 6.83 # Average system read bandwidth in MiByte/s 214system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 215system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 216system.physmem.busUtil 0.05 # Data bus utilization in percentage 217system.physmem.busUtilRead 0.05 # Data bus utilization in percentage for reads 218system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 219system.physmem.avgRdQLen 1.16 # Average read queue length when enqueuing 220system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 221system.physmem.readRowHits 5839 # Number of row buffer hits during reads 222system.physmem.writeRowHits 0 # Number of row buffer hits during writes 223system.physmem.readRowHitRate 80.12 # Row buffer hit rate for reads 224system.physmem.writeRowHitRate nan # Row buffer hit rate for writes 225system.physmem.avgGap 9364084.25 # Average gap between requests 226system.physmem.pageHitRate 80.12 # Row buffer hit rate, read and write combined 227system.physmem.prechargeAllPercent 1.16 # Percentage of time for which DRAM has all the banks in precharge state 228system.membus.throughput 6833684 # Throughput (bytes/s) 229system.membus.trans_dist::ReadReq 4468 # Transaction distribution 230system.membus.trans_dist::ReadResp 4467 # Transaction distribution 231system.membus.trans_dist::ReadExReq 2820 # Transaction distribution 232system.membus.trans_dist::ReadExResp 2820 # Transaction distribution 233system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14575 # Packet count per connected master and slave (bytes) 234system.membus.pkt_count::total 14575 # Packet count per connected master and slave (bytes) 235system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 466368 # Cumulative packet size per connected master and slave (bytes) 236system.membus.tot_pkt_size::total 466368 # Cumulative packet size per connected master and slave (bytes) 237system.membus.data_through_bus 466368 # Total data (bytes) 238system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 239system.membus.reqLayer0.occupancy 8915000 # Layer occupancy (ticks) 240system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 241system.membus.respLayer1.occupancy 67732500 # Layer occupancy (ticks) 242system.membus.respLayer1.utilization 0.1 # Layer utilization (%) 243system.cpu_clk_domain.clock 500 # Clock period in ticks 244system.cpu.branchPred.lookups 35342667 # Number of BP lookups 245system.cpu.branchPred.condPredicted 21189046 # Number of conditional branches predicted 246system.cpu.branchPred.condIncorrect 1621967 # Number of conditional branches incorrect 247system.cpu.branchPred.BTBLookups 18355176 # Number of BTB lookups 248system.cpu.branchPred.BTBHits 16729462 # Number of BTB hits 249system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 250system.cpu.branchPred.BTBHitPct 91.143021 # BTB Hit Percentage 251system.cpu.branchPred.usedRAS 6774978 # Number of times the RAS was used to get a target. 252system.cpu.branchPred.RASInCorrect 8404 # Number of incorrect RAS predictions. 253system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 254system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 255system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 256system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 257system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 258system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 259system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 260system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 261system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 262system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 263system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 264system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 265system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 266system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 267system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 268system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 269system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 270system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 271system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 272system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 273system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 274system.cpu.dtb.inst_hits 0 # ITB inst hits 275system.cpu.dtb.inst_misses 0 # ITB inst misses 276system.cpu.dtb.read_hits 0 # DTB read hits 277system.cpu.dtb.read_misses 0 # DTB read misses 278system.cpu.dtb.write_hits 0 # DTB write hits 279system.cpu.dtb.write_misses 0 # DTB write misses 280system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 281system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 282system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 283system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 284system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 285system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 286system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 287system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 288system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 289system.cpu.dtb.read_accesses 0 # DTB read accesses 290system.cpu.dtb.write_accesses 0 # DTB write accesses 291system.cpu.dtb.inst_accesses 0 # ITB inst accesses 292system.cpu.dtb.hits 0 # DTB hits 293system.cpu.dtb.misses 0 # DTB misses 294system.cpu.dtb.accesses 0 # DTB accesses 295system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 296system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 297system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 298system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 299system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 300system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 301system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 302system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 303system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 304system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 305system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 306system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 307system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 308system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 309system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 310system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 311system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 312system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 313system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 314system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 315system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 316system.cpu.itb.inst_hits 0 # ITB inst hits 317system.cpu.itb.inst_misses 0 # ITB inst misses 318system.cpu.itb.read_hits 0 # DTB read hits 319system.cpu.itb.read_misses 0 # DTB read misses 320system.cpu.itb.write_hits 0 # DTB write hits 321system.cpu.itb.write_misses 0 # DTB write misses 322system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 323system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 324system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 325system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 326system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 327system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 328system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 329system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 330system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 331system.cpu.itb.read_accesses 0 # DTB read accesses 332system.cpu.itb.write_accesses 0 # DTB write accesses 333system.cpu.itb.inst_accesses 0 # ITB inst accesses 334system.cpu.itb.hits 0 # DTB hits 335system.cpu.itb.misses 0 # DTB misses 336system.cpu.itb.accesses 0 # DTB accesses 337system.cpu.workload.num_syscalls 191 # Number of system calls 338system.cpu.numCycles 136490945 # number of cpu cycles simulated 339system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 340system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 341system.cpu.fetch.icacheStallCycles 38825213 # Number of cycles fetch is stalled on an Icache miss 342system.cpu.fetch.Insts 317051968 # Number of instructions fetch has processed 343system.cpu.fetch.Branches 35342667 # Number of branches that fetch encountered 344system.cpu.fetch.predictedBranches 23504440 # Number of branches that fetch has predicted taken 345system.cpu.fetch.Cycles 70679896 # Number of cycles fetch has run and was not squashing or blocked 346system.cpu.fetch.SquashCycles 6716000 # Number of cycles fetch has spent squashing 347system.cpu.fetch.BlockedCycles 21545367 # Number of cycles fetch has spent blocked 348system.cpu.fetch.MiscStallCycles 106 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 349system.cpu.fetch.PendingTrapStallCycles 1322 # Number of stall cycles due to pending traps 350system.cpu.fetch.IcacheWaitRetryStallCycles 66 # Number of stall cycles due to full MSHR 351system.cpu.fetch.CacheLines 37451719 # Number of cache lines fetched 352system.cpu.fetch.IcacheSquashes 502899 # Number of outstanding Icache misses that were squashed 353system.cpu.fetch.rateDist::samples 136134435 # Number of instructions fetched each cycle (Total) 354system.cpu.fetch.rateDist::mean 2.985255 # Number of instructions fetched each cycle (Total) 355system.cpu.fetch.rateDist::stdev 3.454681 # Number of instructions fetched each cycle (Total) 356system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 357system.cpu.fetch.rateDist::0 66077496 48.54% 48.54% # Number of instructions fetched each cycle (Total) 358system.cpu.fetch.rateDist::1 6747770 4.96% 53.50% # Number of instructions fetched each cycle (Total) 359system.cpu.fetch.rateDist::2 5691244 4.18% 57.68% # Number of instructions fetched each cycle (Total) 360system.cpu.fetch.rateDist::3 6070617 4.46% 62.13% # Number of instructions fetched each cycle (Total) 361system.cpu.fetch.rateDist::4 4899295 3.60% 65.73% # Number of instructions fetched each cycle (Total) 362system.cpu.fetch.rateDist::5 4080163 3.00% 68.73% # Number of instructions fetched each cycle (Total) 363system.cpu.fetch.rateDist::6 3177720 2.33% 71.07% # Number of instructions fetched each cycle (Total) 364system.cpu.fetch.rateDist::7 4131471 3.03% 74.10% # Number of instructions fetched each cycle (Total) 365system.cpu.fetch.rateDist::8 35258659 25.90% 100.00% # Number of instructions fetched each cycle (Total) 366system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 367system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 368system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 369system.cpu.fetch.rateDist::total 136134435 # Number of instructions fetched each cycle (Total) 370system.cpu.fetch.branchRate 0.258938 # Number of branch fetches per cycle 371system.cpu.fetch.rate 2.322879 # Number of inst fetches per cycle 372system.cpu.decode.IdleCycles 45319095 # Number of cycles decode is idle 373system.cpu.decode.BlockedCycles 16701200 # Number of cycles decode is blocked 374system.cpu.decode.RunCycles 66547822 # Number of cycles decode is running 375system.cpu.decode.UnblockCycles 2552537 # Number of cycles decode is unblocking 376system.cpu.decode.SquashCycles 5013781 # Number of cycles decode is squashing 377system.cpu.decode.BranchResolved 7320658 # Number of times decode resolved a branch 378system.cpu.decode.BranchMispred 69067 # Number of times decode detected a branch misprediction 379system.cpu.decode.DecodedInsts 400437341 # Number of instructions handled by decode 380system.cpu.decode.SquashedInsts 211449 # Number of squashed instructions handled by decode 381system.cpu.rename.SquashCycles 5013781 # Number of cycles rename is squashing 382system.cpu.rename.IdleCycles 50843684 # Number of cycles rename is idle 383system.cpu.rename.BlockCycles 1928767 # Number of cycles rename is blocking 384system.cpu.rename.serializeStallCycles 335631 # count of cycles rename stalled for serializing inst 385system.cpu.rename.RunCycles 63516277 # Number of cycles rename is running 386system.cpu.rename.UnblockCycles 14496295 # Number of cycles rename is unblocking 387system.cpu.rename.RenamedInsts 392925979 # Number of instructions processed by rename 388system.cpu.rename.ROBFullEvents 32 # Number of times rename has blocked due to ROB full 389system.cpu.rename.IQFullEvents 1658279 # Number of times rename has blocked due to IQ full 390system.cpu.rename.LSQFullEvents 10203172 # Number of times rename has blocked due to LSQ full 391system.cpu.rename.FullRegisterEvents 22306 # Number of times there has been no free registers 392system.cpu.rename.RenamedOperands 431444746 # Number of destination operands rename has renamed 393system.cpu.rename.RenameLookups 2730832248 # Number of register rename lookups that rename has made 394system.cpu.rename.int_rename_lookups 1570013245 # Number of integer rename lookups 395system.cpu.rename.fp_rename_lookups 200164445 # Number of floating rename lookups 396system.cpu.rename.CommittedMaps 384566193 # Number of HB maps that are committed 397system.cpu.rename.UndoneMaps 46878553 # Number of HB maps that are undone due to squashing 398system.cpu.rename.serializingInsts 11940 # count of serializing insts renamed 399system.cpu.rename.tempSerializingInsts 11939 # count of temporary serializing insts renamed 400system.cpu.rename.skidInsts 36493417 # count of insts added to the skid buffer 401system.cpu.memDep0.insertedLoads 103352368 # Number of loads inserted to the mem dependence unit. 402system.cpu.memDep0.insertedStores 91160183 # Number of stores inserted to the mem dependence unit. 403system.cpu.memDep0.conflictingLoads 4261604 # Number of conflicting loads. 404system.cpu.memDep0.conflictingStores 5303451 # Number of conflicting stores. 405system.cpu.iq.iqInstsAdded 383671023 # Number of instructions added to the IQ (excludes non-spec) 406system.cpu.iq.iqNonSpecInstsAdded 22900 # Number of non-speculative instructions added to the IQ 407system.cpu.iq.iqInstsIssued 373754233 # Number of instructions issued 408system.cpu.iq.iqSquashedInstsIssued 1199031 # Number of squashed instructions issued 409system.cpu.iq.iqSquashedInstsExamined 33881433 # Number of squashed instructions iterated over during squash; mainly for profiling 410system.cpu.iq.iqSquashedOperandsExamined 97712598 # Number of squashed operands that are examined and possibly removed from graph 411system.cpu.iq.iqSquashedNonSpecRemoved 780 # Number of squashed non-spec instructions that were removed 412system.cpu.iq.issued_per_cycle::samples 136134435 # Number of insts issued each cycle 413system.cpu.iq.issued_per_cycle::mean 2.745479 # Number of insts issued each cycle 414system.cpu.iq.issued_per_cycle::stdev 2.022556 # Number of insts issued each cycle 415system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 416system.cpu.iq.issued_per_cycle::0 24740289 18.17% 18.17% # Number of insts issued each cycle 417system.cpu.iq.issued_per_cycle::1 19905513 14.62% 32.80% # Number of insts issued each cycle 418system.cpu.iq.issued_per_cycle::2 20515084 15.07% 47.87% # Number of insts issued each cycle 419system.cpu.iq.issued_per_cycle::3 18158642 13.34% 61.20% # Number of insts issued each cycle 420system.cpu.iq.issued_per_cycle::4 24030824 17.65% 78.86% # Number of insts issued each cycle 421system.cpu.iq.issued_per_cycle::5 15691878 11.53% 90.38% # Number of insts issued each cycle 422system.cpu.iq.issued_per_cycle::6 8802431 6.47% 96.85% # Number of insts issued each cycle 423system.cpu.iq.issued_per_cycle::7 3372838 2.48% 99.33% # Number of insts issued each cycle 424system.cpu.iq.issued_per_cycle::8 916936 0.67% 100.00% # Number of insts issued each cycle 425system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 426system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 427system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 428system.cpu.iq.issued_per_cycle::total 136134435 # Number of insts issued each cycle 429system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 430system.cpu.iq.fu_full::IntAlu 8938 0.05% 0.05% # attempts to use FU when none available 431system.cpu.iq.fu_full::IntMult 4692 0.03% 0.08% # attempts to use FU when none available 432system.cpu.iq.fu_full::IntDiv 0 0.00% 0.08% # attempts to use FU when none available 433system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.08% # attempts to use FU when none available 434system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.08% # attempts to use FU when none available 435system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.08% # attempts to use FU when none available 436system.cpu.iq.fu_full::FloatMult 0 0.00% 0.08% # attempts to use FU when none available 437system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.08% # attempts to use FU when none available 438system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.08% # attempts to use FU when none available 439system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.08% # attempts to use FU when none available 440system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.08% # attempts to use FU when none available 441system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.08% # attempts to use FU when none available 442system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.08% # attempts to use FU when none available 443system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.08% # attempts to use FU when none available 444system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.08% # attempts to use FU when none available 445system.cpu.iq.fu_full::SimdMult 0 0.00% 0.08% # attempts to use FU when none available 446system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.08% # attempts to use FU when none available 447system.cpu.iq.fu_full::SimdShift 0 0.00% 0.08% # attempts to use FU when none available 448system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.08% # attempts to use FU when none available 449system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.08% # attempts to use FU when none available 450system.cpu.iq.fu_full::SimdFloatAdd 46049 0.26% 0.34% # attempts to use FU when none available 451system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.34% # attempts to use FU when none available 452system.cpu.iq.fu_full::SimdFloatCmp 3482 0.02% 0.36% # attempts to use FU when none available 453system.cpu.iq.fu_full::SimdFloatCvt 434 0.00% 0.36% # attempts to use FU when none available 454system.cpu.iq.fu_full::SimdFloatDiv 2 0.00% 0.36% # attempts to use FU when none available 455system.cpu.iq.fu_full::SimdFloatMisc 186470 1.05% 1.41% # attempts to use FU when none available 456system.cpu.iq.fu_full::SimdFloatMult 3938 0.02% 1.43% # attempts to use FU when none available 457system.cpu.iq.fu_full::SimdFloatMultAcc 241178 1.36% 2.80% # attempts to use FU when none available 458system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.80% # attempts to use FU when none available 459system.cpu.iq.fu_full::MemRead 9277159 52.37% 55.16% # attempts to use FU when none available 460system.cpu.iq.fu_full::MemWrite 7942822 44.84% 100.00% # attempts to use FU when none available 461system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 462system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 463system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 464system.cpu.iq.FU_type_0::IntAlu 126226981 33.77% 33.77% # Type of FU issued 465system.cpu.iq.FU_type_0::IntMult 2175715 0.58% 34.35% # Type of FU issued 466system.cpu.iq.FU_type_0::IntDiv 0 0.00% 34.35% # Type of FU issued 467system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 34.35% # Type of FU issued 468system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 34.35% # Type of FU issued 469system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 34.35% # Type of FU issued 470system.cpu.iq.FU_type_0::FloatMult 0 0.00% 34.35% # Type of FU issued 471system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 34.35% # Type of FU issued 472system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 34.35% # Type of FU issued 473system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 34.35% # Type of FU issued 474system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 34.35% # Type of FU issued 475system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 34.35% # Type of FU issued 476system.cpu.iq.FU_type_0::SimdCmp 4 0.00% 34.35% # Type of FU issued 477system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 34.35% # Type of FU issued 478system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 34.35% # Type of FU issued 479system.cpu.iq.FU_type_0::SimdMult 0 0.00% 34.35% # Type of FU issued 480system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 34.35% # Type of FU issued 481system.cpu.iq.FU_type_0::SimdShift 0 0.00% 34.35% # Type of FU issued 482system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 34.35% # Type of FU issued 483system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 34.35% # Type of FU issued 484system.cpu.iq.FU_type_0::SimdFloatAdd 6775957 1.81% 36.17% # Type of FU issued 485system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 36.17% # Type of FU issued 486system.cpu.iq.FU_type_0::SimdFloatCmp 8464752 2.26% 38.43% # Type of FU issued 487system.cpu.iq.FU_type_0::SimdFloatCvt 3426733 0.92% 39.35% # Type of FU issued 488system.cpu.iq.FU_type_0::SimdFloatDiv 1595441 0.43% 39.78% # Type of FU issued 489system.cpu.iq.FU_type_0::SimdFloatMisc 20845390 5.58% 45.35% # Type of FU issued 490system.cpu.iq.FU_type_0::SimdFloatMult 7170609 1.92% 47.27% # Type of FU issued 491system.cpu.iq.FU_type_0::SimdFloatMultAcc 7125607 1.91% 49.18% # Type of FU issued 492system.cpu.iq.FU_type_0::SimdFloatSqrt 175287 0.05% 49.23% # Type of FU issued 493system.cpu.iq.FU_type_0::MemRead 101514689 27.16% 76.39% # Type of FU issued 494system.cpu.iq.FU_type_0::MemWrite 88257068 23.61% 100.00% # Type of FU issued 495system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 496system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 497system.cpu.iq.FU_type_0::total 373754233 # Type of FU issued 498system.cpu.iq.rate 2.738308 # Inst issue rate 499system.cpu.iq.fu_busy_cnt 17715164 # FU busy when requested 500system.cpu.iq.fu_busy_rate 0.047398 # FU busy rate (busy events/executed inst) 501system.cpu.iq.int_inst_queue_reads 653197592 # Number of integer instruction queue reads 502system.cpu.iq.int_inst_queue_writes 287339977 # Number of integer instruction queue writes 503system.cpu.iq.int_inst_queue_wakeup_accesses 249810515 # Number of integer instruction queue wakeup accesses 504system.cpu.iq.fp_inst_queue_reads 249359504 # Number of floating instruction queue reads 505system.cpu.iq.fp_inst_queue_writes 130249499 # Number of floating instruction queue writes 506system.cpu.iq.fp_inst_queue_wakeup_accesses 118015221 # Number of floating instruction queue wakeup accesses 507system.cpu.iq.int_alu_accesses 262881293 # Number of integer alu accesses 508system.cpu.iq.fp_alu_accesses 128588104 # Number of floating point alu accesses 509system.cpu.iew.lsq.thread0.forwLoads 11104968 # Number of loads that had data forwarded from stores 510system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 511system.cpu.iew.lsq.thread0.squashedLoads 8703620 # Number of loads squashed 512system.cpu.iew.lsq.thread0.ignoredResponses 109542 # Number of memory responses ignored because the instruction is squashed 513system.cpu.iew.lsq.thread0.memOrderViolation 14223 # Number of memory ordering violations 514system.cpu.iew.lsq.thread0.squashedStores 8784600 # Number of stores squashed 515system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 516system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 517system.cpu.iew.lsq.thread0.rescheduledLoads 184473 # Number of loads that were rescheduled 518system.cpu.iew.lsq.thread0.cacheBlocked 1790 # Number of times an access to memory failed due to the cache being blocked 519system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 520system.cpu.iew.iewSquashCycles 5013781 # Number of cycles IEW is squashing 521system.cpu.iew.iewBlockCycles 291002 # Number of cycles IEW is blocking 522system.cpu.iew.iewUnblockCycles 36408 # Number of cycles IEW is unblocking 523system.cpu.iew.iewDispatchedInsts 383695470 # Number of instructions dispatched to IQ 524system.cpu.iew.iewDispSquashedInsts 852736 # Number of squashed instructions skipped by dispatch 525system.cpu.iew.iewDispLoadInsts 103352368 # Number of dispatched load instructions 526system.cpu.iew.iewDispStoreInsts 91160183 # Number of dispatched store instructions 527system.cpu.iew.iewDispNonSpecInsts 11866 # Number of dispatched non-speculative instructions 528system.cpu.iew.iewIQFullEvents 327 # Number of times the IQ has become full, causing a stall 529system.cpu.iew.iewLSQFullEvents 282 # Number of times the LSQ has become full, causing a stall 530system.cpu.iew.memOrderViolationEvents 14223 # Number of memory order violations 531system.cpu.iew.predictedTakenIncorrect 1256888 # Number of branches that were predicted taken incorrectly 532system.cpu.iew.predictedNotTakenIncorrect 362770 # Number of branches that were predicted not taken incorrectly 533system.cpu.iew.branchMispredicts 1619658 # Number of branch mispredicts detected at execute 534system.cpu.iew.iewExecutedInsts 369836414 # Number of executed instructions 535system.cpu.iew.iewExecLoadInsts 100211998 # Number of load instructions executed 536system.cpu.iew.iewExecSquashedInsts 3917819 # Number of squashed instructions skipped in execute 537system.cpu.iew.exec_swp 0 # number of swp insts executed 538system.cpu.iew.exec_nop 1547 # number of nop insts executed 539system.cpu.iew.exec_refs 187429987 # number of memory reference insts executed 540system.cpu.iew.exec_branches 31988466 # Number of branches executed 541system.cpu.iew.exec_stores 87217989 # Number of stores executed 542system.cpu.iew.exec_rate 2.709604 # Inst execution rate 543system.cpu.iew.wb_sent 368475660 # cumulative count of insts sent to commit 544system.cpu.iew.wb_count 367825736 # cumulative count of insts written-back 545system.cpu.iew.wb_producers 182824140 # num instructions producing a value 546system.cpu.iew.wb_consumers 363330392 # num instructions consuming a value 547system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 548system.cpu.iew.wb_rate 2.694873 # insts written-back per cycle 549system.cpu.iew.wb_fanout 0.503190 # average fanout of values written-back 550system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 551system.cpu.commit.commitSquashedInsts 34630475 # The number of squashed insts skipped by commit 552system.cpu.commit.commitNonSpecStalls 22120 # The number of times commit has been forced to stall to communicate backwards 553system.cpu.commit.branchMispredicts 1553283 # The number of times a branch was mispredicted 554system.cpu.commit.committed_per_cycle::samples 131120654 # Number of insts commited each cycle 555system.cpu.commit.committed_per_cycle::mean 2.662167 # Number of insts commited each cycle 556system.cpu.commit.committed_per_cycle::stdev 2.659302 # Number of insts commited each cycle 557system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 558system.cpu.commit.committed_per_cycle::0 34358811 26.20% 26.20% # Number of insts commited each cycle 559system.cpu.commit.committed_per_cycle::1 28410916 21.67% 47.87% # Number of insts commited each cycle 560system.cpu.commit.committed_per_cycle::2 13299289 10.14% 58.01% # Number of insts commited each cycle 561system.cpu.commit.committed_per_cycle::3 11469684 8.75% 66.76% # Number of insts commited each cycle 562system.cpu.commit.committed_per_cycle::4 13783827 10.51% 77.27% # Number of insts commited each cycle 563system.cpu.commit.committed_per_cycle::5 7406623 5.65% 82.92% # Number of insts commited each cycle 564system.cpu.commit.committed_per_cycle::6 3875247 2.96% 85.88% # Number of insts commited each cycle 565system.cpu.commit.committed_per_cycle::7 3903446 2.98% 88.86% # Number of insts commited each cycle 566system.cpu.commit.committed_per_cycle::8 14612811 11.14% 100.00% # Number of insts commited each cycle 567system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 568system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 569system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 570system.cpu.commit.committed_per_cycle::total 131120654 # Number of insts commited each cycle 571system.cpu.commit.committedInsts 273037337 # Number of instructions committed 572system.cpu.commit.committedOps 349065061 # Number of ops (including micro ops) committed 573system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 574system.cpu.commit.refs 177024331 # Number of memory references committed 575system.cpu.commit.loads 94648748 # Number of loads committed 576system.cpu.commit.membars 11033 # Number of memory barriers committed 577system.cpu.commit.branches 30563497 # Number of branches committed 578system.cpu.commit.fp_insts 114216705 # Number of committed floating point instructions. 579system.cpu.commit.int_insts 279584611 # Number of committed integer instructions. 580system.cpu.commit.function_calls 6225112 # Number of function calls committed. 581system.cpu.commit.bw_lim_events 14612811 # number cycles where commit BW limit reached 582system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 583system.cpu.rob.rob_reads 500200856 # The number of ROB reads 584system.cpu.rob.rob_writes 772408679 # The number of ROB writes 585system.cpu.timesIdled 6691 # Number of times that the entire CPU went into an idle state and unscheduled itself 586system.cpu.idleCycles 356510 # Total number of cycles that the CPU has spent unscheduled due to idling 587system.cpu.committedInsts 273036725 # Number of Instructions Simulated 588system.cpu.committedOps 349064449 # Number of Ops (including micro ops) Simulated 589system.cpu.committedInsts_total 273036725 # Number of Instructions Simulated 590system.cpu.cpi 0.499900 # CPI: Cycles Per Instruction 591system.cpu.cpi_total 0.499900 # CPI: Total CPI of All Threads 592system.cpu.ipc 2.000402 # IPC: Instructions Per Cycle 593system.cpu.ipc_total 2.000402 # IPC: Total IPC of All Threads 594system.cpu.int_regfile_reads 1768035388 # number of integer regfile reads 595system.cpu.int_regfile_writes 232615737 # number of integer regfile writes 596system.cpu.fp_regfile_reads 188041949 # number of floating regfile reads 597system.cpu.fp_regfile_writes 132439422 # number of floating regfile writes 598system.cpu.misc_regfile_reads 1200568638 # number of misc regfile reads 599system.cpu.misc_regfile_writes 34421755 # number of misc regfile writes 600system.cpu.toL2Bus.throughput 20175639 # Throughput (bytes/s) 601system.cpu.toL2Bus.trans_dist::ReadReq 17638 # Transaction distribution 602system.cpu.toL2Bus.trans_dist::ReadResp 17637 # Transaction distribution 603system.cpu.toL2Bus.trans_dist::Writeback 1039 # Transaction distribution 604system.cpu.toL2Bus.trans_dist::ReadExReq 2838 # Transaction distribution 605system.cpu.toL2Bus.trans_dist::ReadExResp 2838 # Transaction distribution 606system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 31713 # Packet count per connected master and slave (bytes) 607system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10277 # Packet count per connected master and slave (bytes) 608system.cpu.toL2Bus.pkt_count::total 41990 # Packet count per connected master and slave (bytes) 609system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1014784 # Cumulative packet size per connected master and slave (bytes) 610system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 362112 # Cumulative packet size per connected master and slave (bytes) 611system.cpu.toL2Bus.tot_pkt_size::total 1376896 # Cumulative packet size per connected master and slave (bytes) 612system.cpu.toL2Bus.data_through_bus 1376896 # Total data (bytes) 613system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) 614system.cpu.toL2Bus.reqLayer0.occupancy 11796500 # Layer occupancy (ticks) 615system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 616system.cpu.toL2Bus.respLayer0.occupancy 24305488 # Layer occupancy (ticks) 617system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 618system.cpu.toL2Bus.respLayer1.occupancy 7381711 # Layer occupancy (ticks) 619system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 620system.cpu.icache.tags.replacements 13966 # number of replacements 621system.cpu.icache.tags.tagsinuse 1849.581585 # Cycle average of tags in use 622system.cpu.icache.tags.total_refs 37434387 # Total number of references to valid blocks. 623system.cpu.icache.tags.sampled_refs 15856 # Sample count of references to valid blocks. 624system.cpu.icache.tags.avg_refs 2360.897263 # Average number of references to valid blocks. 625system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 626system.cpu.icache.tags.occ_blocks::cpu.inst 1849.581585 # Average occupied blocks per requestor 627system.cpu.icache.tags.occ_percent::cpu.inst 0.903116 # Average percentage of cache occupancy 628system.cpu.icache.tags.occ_percent::total 0.903116 # Average percentage of cache occupancy 629system.cpu.icache.tags.occ_task_id_blocks::1024 1890 # Occupied blocks per task id 630system.cpu.icache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id 631system.cpu.icache.tags.age_task_id_blocks_1024::1 92 # Occupied blocks per task id 632system.cpu.icache.tags.age_task_id_blocks_1024::2 206 # Occupied blocks per task id 633system.cpu.icache.tags.age_task_id_blocks_1024::3 9 # Occupied blocks per task id 634system.cpu.icache.tags.age_task_id_blocks_1024::4 1531 # Occupied blocks per task id 635system.cpu.icache.tags.occ_task_id_percent::1024 0.922852 # Percentage of cache occupancy per task id 636system.cpu.icache.tags.tag_accesses 74919290 # Number of tag accesses 637system.cpu.icache.tags.data_accesses 74919290 # Number of data accesses 638system.cpu.icache.ReadReq_hits::cpu.inst 37434387 # number of ReadReq hits 639system.cpu.icache.ReadReq_hits::total 37434387 # number of ReadReq hits 640system.cpu.icache.demand_hits::cpu.inst 37434387 # number of demand (read+write) hits 641system.cpu.icache.demand_hits::total 37434387 # number of demand (read+write) hits 642system.cpu.icache.overall_hits::cpu.inst 37434387 # number of overall hits 643system.cpu.icache.overall_hits::total 37434387 # number of overall hits 644system.cpu.icache.ReadReq_misses::cpu.inst 17330 # number of ReadReq misses 645system.cpu.icache.ReadReq_misses::total 17330 # number of ReadReq misses 646system.cpu.icache.demand_misses::cpu.inst 17330 # number of demand (read+write) misses 647system.cpu.icache.demand_misses::total 17330 # number of demand (read+write) misses 648system.cpu.icache.overall_misses::cpu.inst 17330 # number of overall misses 649system.cpu.icache.overall_misses::total 17330 # number of overall misses 650system.cpu.icache.ReadReq_miss_latency::cpu.inst 451723484 # number of ReadReq miss cycles 651system.cpu.icache.ReadReq_miss_latency::total 451723484 # number of ReadReq miss cycles 652system.cpu.icache.demand_miss_latency::cpu.inst 451723484 # number of demand (read+write) miss cycles 653system.cpu.icache.demand_miss_latency::total 451723484 # number of demand (read+write) miss cycles 654system.cpu.icache.overall_miss_latency::cpu.inst 451723484 # number of overall miss cycles 655system.cpu.icache.overall_miss_latency::total 451723484 # number of overall miss cycles 656system.cpu.icache.ReadReq_accesses::cpu.inst 37451717 # number of ReadReq accesses(hits+misses) 657system.cpu.icache.ReadReq_accesses::total 37451717 # number of ReadReq accesses(hits+misses) 658system.cpu.icache.demand_accesses::cpu.inst 37451717 # number of demand (read+write) accesses 659system.cpu.icache.demand_accesses::total 37451717 # number of demand (read+write) accesses 660system.cpu.icache.overall_accesses::cpu.inst 37451717 # number of overall (read+write) accesses 661system.cpu.icache.overall_accesses::total 37451717 # number of overall (read+write) accesses 662system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000463 # miss rate for ReadReq accesses 663system.cpu.icache.ReadReq_miss_rate::total 0.000463 # miss rate for ReadReq accesses 664system.cpu.icache.demand_miss_rate::cpu.inst 0.000463 # miss rate for demand accesses 665system.cpu.icache.demand_miss_rate::total 0.000463 # miss rate for demand accesses 666system.cpu.icache.overall_miss_rate::cpu.inst 0.000463 # miss rate for overall accesses 667system.cpu.icache.overall_miss_rate::total 0.000463 # miss rate for overall accesses 668system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 26065.982920 # average ReadReq miss latency 669system.cpu.icache.ReadReq_avg_miss_latency::total 26065.982920 # average ReadReq miss latency 670system.cpu.icache.demand_avg_miss_latency::cpu.inst 26065.982920 # average overall miss latency 671system.cpu.icache.demand_avg_miss_latency::total 26065.982920 # average overall miss latency 672system.cpu.icache.overall_avg_miss_latency::cpu.inst 26065.982920 # average overall miss latency 673system.cpu.icache.overall_avg_miss_latency::total 26065.982920 # average overall miss latency 674system.cpu.icache.blocked_cycles::no_mshrs 1035 # number of cycles access was blocked 675system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 676system.cpu.icache.blocked::no_mshrs 26 # number of cycles access was blocked 677system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 678system.cpu.icache.avg_blocked_cycles::no_mshrs 39.807692 # average number of cycles each access was blocked 679system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 680system.cpu.icache.fast_writes 0 # number of fast writes performed 681system.cpu.icache.cache_copies 0 # number of cache copies performed 682system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1473 # number of ReadReq MSHR hits 683system.cpu.icache.ReadReq_mshr_hits::total 1473 # number of ReadReq MSHR hits 684system.cpu.icache.demand_mshr_hits::cpu.inst 1473 # number of demand (read+write) MSHR hits 685system.cpu.icache.demand_mshr_hits::total 1473 # number of demand (read+write) MSHR hits 686system.cpu.icache.overall_mshr_hits::cpu.inst 1473 # number of overall MSHR hits 687system.cpu.icache.overall_mshr_hits::total 1473 # number of overall MSHR hits 688system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15857 # number of ReadReq MSHR misses 689system.cpu.icache.ReadReq_mshr_misses::total 15857 # number of ReadReq MSHR misses 690system.cpu.icache.demand_mshr_misses::cpu.inst 15857 # number of demand (read+write) MSHR misses 691system.cpu.icache.demand_mshr_misses::total 15857 # number of demand (read+write) MSHR misses 692system.cpu.icache.overall_mshr_misses::cpu.inst 15857 # number of overall MSHR misses 693system.cpu.icache.overall_mshr_misses::total 15857 # number of overall MSHR misses 694system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 359348009 # number of ReadReq MSHR miss cycles 695system.cpu.icache.ReadReq_mshr_miss_latency::total 359348009 # number of ReadReq MSHR miss cycles 696system.cpu.icache.demand_mshr_miss_latency::cpu.inst 359348009 # number of demand (read+write) MSHR miss cycles 697system.cpu.icache.demand_mshr_miss_latency::total 359348009 # number of demand (read+write) MSHR miss cycles 698system.cpu.icache.overall_mshr_miss_latency::cpu.inst 359348009 # number of overall MSHR miss cycles 699system.cpu.icache.overall_mshr_miss_latency::total 359348009 # number of overall MSHR miss cycles 700system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000423 # mshr miss rate for ReadReq accesses 701system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000423 # mshr miss rate for ReadReq accesses 702system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000423 # mshr miss rate for demand accesses 703system.cpu.icache.demand_mshr_miss_rate::total 0.000423 # mshr miss rate for demand accesses 704system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000423 # mshr miss rate for overall accesses 705system.cpu.icache.overall_mshr_miss_rate::total 0.000423 # mshr miss rate for overall accesses 706system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22661.790313 # average ReadReq mshr miss latency 707system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22661.790313 # average ReadReq mshr miss latency 708system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22661.790313 # average overall mshr miss latency 709system.cpu.icache.demand_avg_mshr_miss_latency::total 22661.790313 # average overall mshr miss latency 710system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22661.790313 # average overall mshr miss latency 711system.cpu.icache.overall_avg_mshr_miss_latency::total 22661.790313 # average overall mshr miss latency 712system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 713system.cpu.l2cache.tags.replacements 0 # number of replacements 714system.cpu.l2cache.tags.tagsinuse 3939.930856 # Cycle average of tags in use 715system.cpu.l2cache.tags.total_refs 13213 # Total number of references to valid blocks. 716system.cpu.l2cache.tags.sampled_refs 5393 # Sample count of references to valid blocks. 717system.cpu.l2cache.tags.avg_refs 2.450028 # Average number of references to valid blocks. 718system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 719system.cpu.l2cache.tags.occ_blocks::writebacks 375.867414 # Average occupied blocks per requestor 720system.cpu.l2cache.tags.occ_blocks::cpu.inst 2777.143346 # Average occupied blocks per requestor 721system.cpu.l2cache.tags.occ_blocks::cpu.data 786.920096 # Average occupied blocks per requestor 722system.cpu.l2cache.tags.occ_percent::writebacks 0.011471 # Average percentage of cache occupancy 723system.cpu.l2cache.tags.occ_percent::cpu.inst 0.084752 # Average percentage of cache occupancy 724system.cpu.l2cache.tags.occ_percent::cpu.data 0.024015 # Average percentage of cache occupancy 725system.cpu.l2cache.tags.occ_percent::total 0.120237 # Average percentage of cache occupancy 726system.cpu.l2cache.tags.occ_task_id_blocks::1024 5393 # Occupied blocks per task id 727system.cpu.l2cache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id 728system.cpu.l2cache.tags.age_task_id_blocks_1024::1 71 # Occupied blocks per task id 729system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1243 # Occupied blocks per task id 730system.cpu.l2cache.tags.age_task_id_blocks_1024::3 10 # Occupied blocks per task id 731system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4011 # Occupied blocks per task id 732system.cpu.l2cache.tags.occ_task_id_percent::1024 0.164581 # Percentage of cache occupancy per task id 733system.cpu.l2cache.tags.tag_accesses 180351 # Number of tag accesses 734system.cpu.l2cache.tags.data_accesses 180351 # Number of data accesses 735system.cpu.l2cache.ReadReq_hits::cpu.inst 12816 # number of ReadReq hits 736system.cpu.l2cache.ReadReq_hits::cpu.data 303 # number of ReadReq hits 737system.cpu.l2cache.ReadReq_hits::total 13119 # number of ReadReq hits 738system.cpu.l2cache.Writeback_hits::writebacks 1039 # number of Writeback hits 739system.cpu.l2cache.Writeback_hits::total 1039 # number of Writeback hits 740system.cpu.l2cache.ReadExReq_hits::cpu.data 18 # number of ReadExReq hits 741system.cpu.l2cache.ReadExReq_hits::total 18 # number of ReadExReq hits 742system.cpu.l2cache.demand_hits::cpu.inst 12816 # number of demand (read+write) hits 743system.cpu.l2cache.demand_hits::cpu.data 321 # number of demand (read+write) hits 744system.cpu.l2cache.demand_hits::total 13137 # number of demand (read+write) hits 745system.cpu.l2cache.overall_hits::cpu.inst 12816 # number of overall hits 746system.cpu.l2cache.overall_hits::cpu.data 321 # number of overall hits 747system.cpu.l2cache.overall_hits::total 13137 # number of overall hits 748system.cpu.l2cache.ReadReq_misses::cpu.inst 3041 # number of ReadReq misses 749system.cpu.l2cache.ReadReq_misses::cpu.data 1478 # number of ReadReq misses 750system.cpu.l2cache.ReadReq_misses::total 4519 # number of ReadReq misses 751system.cpu.l2cache.ReadExReq_misses::cpu.data 2820 # number of ReadExReq misses 752system.cpu.l2cache.ReadExReq_misses::total 2820 # number of ReadExReq misses 753system.cpu.l2cache.demand_misses::cpu.inst 3041 # number of demand (read+write) misses 754system.cpu.l2cache.demand_misses::cpu.data 4298 # number of demand (read+write) misses 755system.cpu.l2cache.demand_misses::total 7339 # number of demand (read+write) misses 756system.cpu.l2cache.overall_misses::cpu.inst 3041 # number of overall misses 757system.cpu.l2cache.overall_misses::cpu.data 4298 # number of overall misses 758system.cpu.l2cache.overall_misses::total 7339 # number of overall misses 759system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 215304250 # number of ReadReq miss cycles 760system.cpu.l2cache.ReadReq_miss_latency::cpu.data 106779500 # number of ReadReq miss cycles 761system.cpu.l2cache.ReadReq_miss_latency::total 322083750 # number of ReadReq miss cycles 762system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 200114250 # number of ReadExReq miss cycles 763system.cpu.l2cache.ReadExReq_miss_latency::total 200114250 # number of ReadExReq miss cycles 764system.cpu.l2cache.demand_miss_latency::cpu.inst 215304250 # number of demand (read+write) miss cycles 765system.cpu.l2cache.demand_miss_latency::cpu.data 306893750 # number of demand (read+write) miss cycles 766system.cpu.l2cache.demand_miss_latency::total 522198000 # number of demand (read+write) miss cycles 767system.cpu.l2cache.overall_miss_latency::cpu.inst 215304250 # number of overall miss cycles 768system.cpu.l2cache.overall_miss_latency::cpu.data 306893750 # number of overall miss cycles 769system.cpu.l2cache.overall_miss_latency::total 522198000 # number of overall miss cycles 770system.cpu.l2cache.ReadReq_accesses::cpu.inst 15857 # number of ReadReq accesses(hits+misses) 771system.cpu.l2cache.ReadReq_accesses::cpu.data 1781 # number of ReadReq accesses(hits+misses) 772system.cpu.l2cache.ReadReq_accesses::total 17638 # number of ReadReq accesses(hits+misses) 773system.cpu.l2cache.Writeback_accesses::writebacks 1039 # number of Writeback accesses(hits+misses) 774system.cpu.l2cache.Writeback_accesses::total 1039 # number of Writeback accesses(hits+misses) 775system.cpu.l2cache.ReadExReq_accesses::cpu.data 2838 # number of ReadExReq accesses(hits+misses) 776system.cpu.l2cache.ReadExReq_accesses::total 2838 # number of ReadExReq accesses(hits+misses) 777system.cpu.l2cache.demand_accesses::cpu.inst 15857 # number of demand (read+write) accesses 778system.cpu.l2cache.demand_accesses::cpu.data 4619 # number of demand (read+write) accesses 779system.cpu.l2cache.demand_accesses::total 20476 # number of demand (read+write) accesses 780system.cpu.l2cache.overall_accesses::cpu.inst 15857 # number of overall (read+write) accesses 781system.cpu.l2cache.overall_accesses::cpu.data 4619 # number of overall (read+write) accesses 782system.cpu.l2cache.overall_accesses::total 20476 # number of overall (read+write) accesses 783system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.191777 # miss rate for ReadReq accesses 784system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.829871 # miss rate for ReadReq accesses 785system.cpu.l2cache.ReadReq_miss_rate::total 0.256208 # miss rate for ReadReq accesses 786system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.993658 # miss rate for ReadExReq accesses 787system.cpu.l2cache.ReadExReq_miss_rate::total 0.993658 # miss rate for ReadExReq accesses 788system.cpu.l2cache.demand_miss_rate::cpu.inst 0.191777 # miss rate for demand accesses 789system.cpu.l2cache.demand_miss_rate::cpu.data 0.930504 # miss rate for demand accesses 790system.cpu.l2cache.demand_miss_rate::total 0.358420 # miss rate for demand accesses 791system.cpu.l2cache.overall_miss_rate::cpu.inst 0.191777 # miss rate for overall accesses 792system.cpu.l2cache.overall_miss_rate::cpu.data 0.930504 # miss rate for overall accesses 793system.cpu.l2cache.overall_miss_rate::total 0.358420 # miss rate for overall accesses 794system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70800.476817 # average ReadReq miss latency 795system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 72245.940460 # average ReadReq miss latency 796system.cpu.l2cache.ReadReq_avg_miss_latency::total 71273.235229 # average ReadReq miss latency 797system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70962.500000 # average ReadExReq miss latency 798system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70962.500000 # average ReadExReq miss latency 799system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70800.476817 # average overall miss latency 800system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71403.850628 # average overall miss latency 801system.cpu.l2cache.demand_avg_miss_latency::total 71153.835672 # average overall miss latency 802system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70800.476817 # average overall miss latency 803system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71403.850628 # average overall miss latency 804system.cpu.l2cache.overall_avg_miss_latency::total 71153.835672 # average overall miss latency 805system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 806system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 807system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 808system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 809system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 810system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 811system.cpu.l2cache.fast_writes 0 # number of fast writes performed 812system.cpu.l2cache.cache_copies 0 # number of cache copies performed 813system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 12 # number of ReadReq MSHR hits 814system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 39 # number of ReadReq MSHR hits 815system.cpu.l2cache.ReadReq_mshr_hits::total 51 # number of ReadReq MSHR hits 816system.cpu.l2cache.demand_mshr_hits::cpu.inst 12 # number of demand (read+write) MSHR hits 817system.cpu.l2cache.demand_mshr_hits::cpu.data 39 # number of demand (read+write) MSHR hits 818system.cpu.l2cache.demand_mshr_hits::total 51 # number of demand (read+write) MSHR hits 819system.cpu.l2cache.overall_mshr_hits::cpu.inst 12 # number of overall MSHR hits 820system.cpu.l2cache.overall_mshr_hits::cpu.data 39 # number of overall MSHR hits 821system.cpu.l2cache.overall_mshr_hits::total 51 # number of overall MSHR hits 822system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3029 # number of ReadReq MSHR misses 823system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1439 # number of ReadReq MSHR misses 824system.cpu.l2cache.ReadReq_mshr_misses::total 4468 # number of ReadReq MSHR misses 825system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 2820 # number of ReadExReq MSHR misses 826system.cpu.l2cache.ReadExReq_mshr_misses::total 2820 # number of ReadExReq MSHR misses 827system.cpu.l2cache.demand_mshr_misses::cpu.inst 3029 # number of demand (read+write) MSHR misses 828system.cpu.l2cache.demand_mshr_misses::cpu.data 4259 # number of demand (read+write) MSHR misses 829system.cpu.l2cache.demand_mshr_misses::total 7288 # number of demand (read+write) MSHR misses 830system.cpu.l2cache.overall_mshr_misses::cpu.inst 3029 # number of overall MSHR misses 831system.cpu.l2cache.overall_mshr_misses::cpu.data 4259 # number of overall MSHR misses 832system.cpu.l2cache.overall_mshr_misses::total 7288 # number of overall MSHR misses 833system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 176626500 # number of ReadReq MSHR miss cycles 834system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 86490250 # number of ReadReq MSHR miss cycles 835system.cpu.l2cache.ReadReq_mshr_miss_latency::total 263116750 # number of ReadReq MSHR miss cycles 836system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 165285750 # number of ReadExReq MSHR miss cycles 837system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 165285750 # number of ReadExReq MSHR miss cycles 838system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 176626500 # number of demand (read+write) MSHR miss cycles 839system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 251776000 # number of demand (read+write) MSHR miss cycles 840system.cpu.l2cache.demand_mshr_miss_latency::total 428402500 # number of demand (read+write) MSHR miss cycles 841system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 176626500 # number of overall MSHR miss cycles 842system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 251776000 # number of overall MSHR miss cycles 843system.cpu.l2cache.overall_mshr_miss_latency::total 428402500 # number of overall MSHR miss cycles 844system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.191020 # mshr miss rate for ReadReq accesses 845system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.807973 # mshr miss rate for ReadReq accesses 846system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.253317 # mshr miss rate for ReadReq accesses 847system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.993658 # mshr miss rate for ReadExReq accesses 848system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.993658 # mshr miss rate for ReadExReq accesses 849system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.191020 # mshr miss rate for demand accesses 850system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.922061 # mshr miss rate for demand accesses 851system.cpu.l2cache.demand_mshr_miss_rate::total 0.355929 # mshr miss rate for demand accesses 852system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.191020 # mshr miss rate for overall accesses 853system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.922061 # mshr miss rate for overall accesses 854system.cpu.l2cache.overall_mshr_miss_rate::total 0.355929 # mshr miss rate for overall accesses 855system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58311.819082 # average ReadReq mshr miss latency 856system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60104.412787 # average ReadReq mshr miss latency 857system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58889.156222 # average ReadReq mshr miss latency 858system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58611.968085 # average ReadExReq mshr miss latency 859system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58611.968085 # average ReadExReq mshr miss latency 860system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58311.819082 # average overall mshr miss latency 861system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59116.224466 # average overall mshr miss latency 862system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58781.901756 # average overall mshr miss latency 863system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58311.819082 # average overall mshr miss latency 864system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59116.224466 # average overall mshr miss latency 865system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58781.901756 # average overall mshr miss latency 866system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 867system.cpu.dcache.tags.replacements 1416 # number of replacements 868system.cpu.dcache.tags.tagsinuse 3111.494128 # Cycle average of tags in use 869system.cpu.dcache.tags.total_refs 170791722 # Total number of references to valid blocks. 870system.cpu.dcache.tags.sampled_refs 4619 # Sample count of references to valid blocks. 871system.cpu.dcache.tags.avg_refs 36975.908638 # Average number of references to valid blocks. 872system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 873system.cpu.dcache.tags.occ_blocks::cpu.data 3111.494128 # Average occupied blocks per requestor 874system.cpu.dcache.tags.occ_percent::cpu.data 0.759642 # Average percentage of cache occupancy 875system.cpu.dcache.tags.occ_percent::total 0.759642 # Average percentage of cache occupancy 876system.cpu.dcache.tags.occ_task_id_blocks::1024 3203 # Occupied blocks per task id 877system.cpu.dcache.tags.age_task_id_blocks_1024::0 23 # Occupied blocks per task id 878system.cpu.dcache.tags.age_task_id_blocks_1024::1 34 # Occupied blocks per task id 879system.cpu.dcache.tags.age_task_id_blocks_1024::2 686 # Occupied blocks per task id 880system.cpu.dcache.tags.age_task_id_blocks_1024::3 10 # Occupied blocks per task id 881system.cpu.dcache.tags.age_task_id_blocks_1024::4 2450 # Occupied blocks per task id 882system.cpu.dcache.tags.occ_task_id_percent::1024 0.781982 # Percentage of cache occupancy per task id 883system.cpu.dcache.tags.tag_accesses 341638239 # Number of tag accesses 884system.cpu.dcache.tags.data_accesses 341638239 # Number of data accesses 885system.cpu.dcache.ReadReq_hits::cpu.data 88738255 # number of ReadReq hits 886system.cpu.dcache.ReadReq_hits::total 88738255 # number of ReadReq hits 887system.cpu.dcache.WriteReq_hits::cpu.data 82031563 # number of WriteReq hits 888system.cpu.dcache.WriteReq_hits::total 82031563 # number of WriteReq hits 889system.cpu.dcache.LoadLockedReq_hits::cpu.data 11009 # number of LoadLockedReq hits 890system.cpu.dcache.LoadLockedReq_hits::total 11009 # number of LoadLockedReq hits 891system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits 892system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits 893system.cpu.dcache.demand_hits::cpu.data 170769818 # number of demand (read+write) hits 894system.cpu.dcache.demand_hits::total 170769818 # number of demand (read+write) hits 895system.cpu.dcache.overall_hits::cpu.data 170769818 # number of overall hits 896system.cpu.dcache.overall_hits::total 170769818 # number of overall hits 897system.cpu.dcache.ReadReq_misses::cpu.data 3984 # number of ReadReq misses 898system.cpu.dcache.ReadReq_misses::total 3984 # number of ReadReq misses 899system.cpu.dcache.WriteReq_misses::cpu.data 21102 # number of WriteReq misses 900system.cpu.dcache.WriteReq_misses::total 21102 # number of WriteReq misses 901system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses 902system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses 903system.cpu.dcache.demand_misses::cpu.data 25086 # number of demand (read+write) misses 904system.cpu.dcache.demand_misses::total 25086 # number of demand (read+write) misses 905system.cpu.dcache.overall_misses::cpu.data 25086 # number of overall misses 906system.cpu.dcache.overall_misses::total 25086 # number of overall misses 907system.cpu.dcache.ReadReq_miss_latency::cpu.data 232475203 # number of ReadReq miss cycles 908system.cpu.dcache.ReadReq_miss_latency::total 232475203 # number of ReadReq miss cycles 909system.cpu.dcache.WriteReq_miss_latency::cpu.data 1255700879 # number of WriteReq miss cycles 910system.cpu.dcache.WriteReq_miss_latency::total 1255700879 # number of WriteReq miss cycles 911system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 170250 # number of LoadLockedReq miss cycles 912system.cpu.dcache.LoadLockedReq_miss_latency::total 170250 # number of LoadLockedReq miss cycles 913system.cpu.dcache.demand_miss_latency::cpu.data 1488176082 # number of demand (read+write) miss cycles 914system.cpu.dcache.demand_miss_latency::total 1488176082 # number of demand (read+write) miss cycles 915system.cpu.dcache.overall_miss_latency::cpu.data 1488176082 # number of overall miss cycles 916system.cpu.dcache.overall_miss_latency::total 1488176082 # number of overall miss cycles 917system.cpu.dcache.ReadReq_accesses::cpu.data 88742239 # number of ReadReq accesses(hits+misses) 918system.cpu.dcache.ReadReq_accesses::total 88742239 # number of ReadReq accesses(hits+misses) 919system.cpu.dcache.WriteReq_accesses::cpu.data 82052665 # number of WriteReq accesses(hits+misses) 920system.cpu.dcache.WriteReq_accesses::total 82052665 # number of WriteReq accesses(hits+misses) 921system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11011 # number of LoadLockedReq accesses(hits+misses) 922system.cpu.dcache.LoadLockedReq_accesses::total 11011 # number of LoadLockedReq accesses(hits+misses) 923system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses) 924system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) 925system.cpu.dcache.demand_accesses::cpu.data 170794904 # number of demand (read+write) accesses 926system.cpu.dcache.demand_accesses::total 170794904 # number of demand (read+write) accesses 927system.cpu.dcache.overall_accesses::cpu.data 170794904 # number of overall (read+write) accesses 928system.cpu.dcache.overall_accesses::total 170794904 # number of overall (read+write) accesses 929system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000045 # miss rate for ReadReq accesses 930system.cpu.dcache.ReadReq_miss_rate::total 0.000045 # miss rate for ReadReq accesses 931system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000257 # miss rate for WriteReq accesses 932system.cpu.dcache.WriteReq_miss_rate::total 0.000257 # miss rate for WriteReq accesses 933system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000182 # miss rate for LoadLockedReq accesses 934system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000182 # miss rate for LoadLockedReq accesses 935system.cpu.dcache.demand_miss_rate::cpu.data 0.000147 # miss rate for demand accesses 936system.cpu.dcache.demand_miss_rate::total 0.000147 # miss rate for demand accesses 937system.cpu.dcache.overall_miss_rate::cpu.data 0.000147 # miss rate for overall accesses 938system.cpu.dcache.overall_miss_rate::total 0.000147 # miss rate for overall accesses 939system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 58352.209588 # average ReadReq miss latency 940system.cpu.dcache.ReadReq_avg_miss_latency::total 58352.209588 # average ReadReq miss latency 941system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59506.249597 # average WriteReq miss latency 942system.cpu.dcache.WriteReq_avg_miss_latency::total 59506.249597 # average WriteReq miss latency 943system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 85125 # average LoadLockedReq miss latency 944system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 85125 # average LoadLockedReq miss latency 945system.cpu.dcache.demand_avg_miss_latency::cpu.data 59322.972255 # average overall miss latency 946system.cpu.dcache.demand_avg_miss_latency::total 59322.972255 # average overall miss latency 947system.cpu.dcache.overall_avg_miss_latency::cpu.data 59322.972255 # average overall miss latency 948system.cpu.dcache.overall_avg_miss_latency::total 59322.972255 # average overall miss latency 949system.cpu.dcache.blocked_cycles::no_mshrs 26768 # number of cycles access was blocked 950system.cpu.dcache.blocked_cycles::no_targets 1267 # number of cycles access was blocked 951system.cpu.dcache.blocked::no_mshrs 424 # number of cycles access was blocked 952system.cpu.dcache.blocked::no_targets 13 # number of cycles access was blocked 953system.cpu.dcache.avg_blocked_cycles::no_mshrs 63.132075 # average number of cycles each access was blocked 954system.cpu.dcache.avg_blocked_cycles::no_targets 97.461538 # average number of cycles each access was blocked 955system.cpu.dcache.fast_writes 0 # number of fast writes performed 956system.cpu.dcache.cache_copies 0 # number of cache copies performed 957system.cpu.dcache.writebacks::writebacks 1039 # number of writebacks 958system.cpu.dcache.writebacks::total 1039 # number of writebacks 959system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2202 # number of ReadReq MSHR hits 960system.cpu.dcache.ReadReq_mshr_hits::total 2202 # number of ReadReq MSHR hits 961system.cpu.dcache.WriteReq_mshr_hits::cpu.data 18265 # number of WriteReq MSHR hits 962system.cpu.dcache.WriteReq_mshr_hits::total 18265 # number of WriteReq MSHR hits 963system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits 964system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits 965system.cpu.dcache.demand_mshr_hits::cpu.data 20467 # number of demand (read+write) MSHR hits 966system.cpu.dcache.demand_mshr_hits::total 20467 # number of demand (read+write) MSHR hits 967system.cpu.dcache.overall_mshr_hits::cpu.data 20467 # number of overall MSHR hits 968system.cpu.dcache.overall_mshr_hits::total 20467 # number of overall MSHR hits 969system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1782 # number of ReadReq MSHR misses 970system.cpu.dcache.ReadReq_mshr_misses::total 1782 # number of ReadReq MSHR misses 971system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2837 # number of WriteReq MSHR misses 972system.cpu.dcache.WriteReq_mshr_misses::total 2837 # number of WriteReq MSHR misses 973system.cpu.dcache.demand_mshr_misses::cpu.data 4619 # number of demand (read+write) MSHR misses 974system.cpu.dcache.demand_mshr_misses::total 4619 # number of demand (read+write) MSHR misses 975system.cpu.dcache.overall_mshr_misses::cpu.data 4619 # number of overall MSHR misses 976system.cpu.dcache.overall_mshr_misses::total 4619 # number of overall MSHR misses 977system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 111706789 # number of ReadReq MSHR miss cycles 978system.cpu.dcache.ReadReq_mshr_miss_latency::total 111706789 # number of ReadReq MSHR miss cycles 979system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 203137000 # number of WriteReq MSHR miss cycles 980system.cpu.dcache.WriteReq_mshr_miss_latency::total 203137000 # number of WriteReq MSHR miss cycles 981system.cpu.dcache.demand_mshr_miss_latency::cpu.data 314843789 # number of demand (read+write) MSHR miss cycles 982system.cpu.dcache.demand_mshr_miss_latency::total 314843789 # number of demand (read+write) MSHR miss cycles 983system.cpu.dcache.overall_mshr_miss_latency::cpu.data 314843789 # number of overall MSHR miss cycles 984system.cpu.dcache.overall_mshr_miss_latency::total 314843789 # number of overall MSHR miss cycles 985system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000020 # mshr miss rate for ReadReq accesses 986system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000020 # mshr miss rate for ReadReq accesses 987system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses 988system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000035 # mshr miss rate for WriteReq accesses 989system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for demand accesses 990system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses 991system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses 992system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses 993system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 62686.189113 # average ReadReq mshr miss latency 994system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 62686.189113 # average ReadReq mshr miss latency 995system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71602.749383 # average WriteReq mshr miss latency 996system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71602.749383 # average WriteReq mshr miss latency 997system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68162.760121 # average overall mshr miss latency 998system.cpu.dcache.demand_avg_mshr_miss_latency::total 68162.760121 # average overall mshr miss latency 999system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68162.760121 # average overall mshr miss latency 1000system.cpu.dcache.overall_avg_mshr_miss_latency::total 68162.760121 # average overall mshr miss latency 1001system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1002 1003---------- End Simulation Statistics ---------- 1004