config.ini revision 11515:c48c7cc5a522
1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=System 13children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain 17eventq_index=0 18exit_on_work_items=false 19init_param=0 20kernel= 21kernel_addr_check=true 22load_addr_mask=1099511627775 23load_offset=0 24mem_mode=timing 25mem_ranges= 26memories=system.physmem 27mmap_using_noreserve=false 28multi_thread=false 29num_work_ids=16 30readfile= 31symbolfile= 32thermal_components= 33thermal_model=Null 34work_begin_ckpt_count=0 35work_begin_cpu_id_exit=-1 36work_begin_exit_count=0 37work_cpus_ckpt_count=0 38work_end_ckpt_count=0 39work_end_exit_count=0 40work_item_id=-1 41system_port=system.membus.slave[0] 42 43[system.clk_domain] 44type=SrcClockDomain 45clock=1000 46domain_id=-1 47eventq_index=0 48init_perf_level=0 49voltage_domain=system.voltage_domain 50 51[system.cpu] 52type=DerivO3CPU 53children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload 54LFSTSize=1024 55LQEntries=16 56LSQCheckLoads=true 57LSQDepCheckShift=0 58SQEntries=16 59SSITSize=1024 60activity=0 61backComSize=5 62branchPred=system.cpu.branchPred 63cachePorts=200 64checker=Null 65clk_domain=system.cpu_clk_domain 66commitToDecodeDelay=1 67commitToFetchDelay=1 68commitToIEWDelay=1 69commitToRenameDelay=1 70commitWidth=8 71cpu_id=0 72decodeToFetchDelay=1 73decodeToRenameDelay=2 74decodeWidth=3 75dispatchWidth=6 76do_checkpoint_insts=true 77do_quiesce=true 78do_statistics_insts=true 79dstage2_mmu=system.cpu.dstage2_mmu 80dtb=system.cpu.dtb 81eventq_index=0 82fetchBufferSize=16 83fetchQueueSize=32 84fetchToDecodeDelay=3 85fetchTrapLatency=1 86fetchWidth=3 87forwardComSize=5 88fuPool=system.cpu.fuPool 89function_trace=false 90function_trace_start=0 91iewToCommitDelay=1 92iewToDecodeDelay=1 93iewToFetchDelay=1 94iewToRenameDelay=1 95interrupts=system.cpu.interrupts 96isa=system.cpu.isa 97issueToExecuteDelay=1 98issueWidth=8 99istage2_mmu=system.cpu.istage2_mmu 100itb=system.cpu.itb 101max_insts_all_threads=0 102max_insts_any_thread=0 103max_loads_all_threads=0 104max_loads_any_thread=0 105needsTSO=false 106numIQEntries=32 107numPhysCCRegs=640 108numPhysFloatRegs=192 109numPhysIntRegs=128 110numROBEntries=40 111numRobs=1 112numThreads=1 113profile=0 114progress_interval=0 115renameToDecodeDelay=1 116renameToFetchDelay=1 117renameToIEWDelay=1 118renameToROBDelay=1 119renameWidth=3 120simpoint_start_insts= 121smtCommitPolicy=RoundRobin 122smtFetchPolicy=SingleThread 123smtIQPolicy=Partitioned 124smtIQThreshold=100 125smtLSQPolicy=Partitioned 126smtLSQThreshold=100 127smtNumFetchingThreads=1 128smtROBPolicy=Partitioned 129smtROBThreshold=100 130socket_id=0 131squashWidth=8 132store_set_clear_period=250000 133switched_out=false 134system=system 135tracer=system.cpu.tracer 136trapLatency=13 137wbWidth=8 138workload=system.cpu.workload 139dcache_port=system.cpu.dcache.cpu_side 140icache_port=system.cpu.icache.cpu_side 141 142[system.cpu.branchPred] 143type=BiModeBP 144BTBEntries=2048 145BTBTagSize=18 146RASSize=16 147choiceCtrBits=2 148choicePredictorSize=8192 149eventq_index=0 150globalCtrBits=2 151globalPredictorSize=8192 152indirectHashGHR=true 153indirectHashTargets=true 154indirectPathLength=3 155indirectSets=256 156indirectTagSize=16 157indirectWays=2 158instShiftAmt=2 159numThreads=1 160useIndirect=true 161 162[system.cpu.dcache] 163type=Cache 164children=tags 165addr_ranges=0:18446744073709551615 166assoc=2 167clk_domain=system.cpu_clk_domain 168clusivity=mostly_incl 169demand_mshr_reserve=1 170eventq_index=0 171hit_latency=2 172is_read_only=false 173max_miss_count=0 174mshrs=6 175prefetch_on_access=false 176prefetcher=Null 177response_latency=2 178sequential_access=false 179size=32768 180system=system 181tags=system.cpu.dcache.tags 182tgts_per_mshr=8 183write_buffers=16 184writeback_clean=true 185cpu_side=system.cpu.dcache_port 186mem_side=system.cpu.toL2Bus.slave[1] 187 188[system.cpu.dcache.tags] 189type=LRU 190assoc=2 191block_size=64 192clk_domain=system.cpu_clk_domain 193eventq_index=0 194hit_latency=2 195sequential_access=false 196size=32768 197 198[system.cpu.dstage2_mmu] 199type=ArmStage2MMU 200children=stage2_tlb 201eventq_index=0 202stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb 203sys=system 204tlb=system.cpu.dtb 205 206[system.cpu.dstage2_mmu.stage2_tlb] 207type=ArmTLB 208children=walker 209eventq_index=0 210is_stage2=true 211size=32 212walker=system.cpu.dstage2_mmu.stage2_tlb.walker 213 214[system.cpu.dstage2_mmu.stage2_tlb.walker] 215type=ArmTableWalker 216clk_domain=system.cpu_clk_domain 217eventq_index=0 218is_stage2=true 219num_squash_per_cycle=2 220sys=system 221 222[system.cpu.dtb] 223type=ArmTLB 224children=walker 225eventq_index=0 226is_stage2=false 227size=64 228walker=system.cpu.dtb.walker 229 230[system.cpu.dtb.walker] 231type=ArmTableWalker 232clk_domain=system.cpu_clk_domain 233eventq_index=0 234is_stage2=false 235num_squash_per_cycle=2 236sys=system 237port=system.cpu.toL2Bus.slave[3] 238 239[system.cpu.fuPool] 240type=FUPool 241children=FUList0 FUList1 FUList2 FUList3 FUList4 242FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 243eventq_index=0 244 245[system.cpu.fuPool.FUList0] 246type=FUDesc 247children=opList 248count=2 249eventq_index=0 250opList=system.cpu.fuPool.FUList0.opList 251 252[system.cpu.fuPool.FUList0.opList] 253type=OpDesc 254eventq_index=0 255opClass=IntAlu 256opLat=1 257pipelined=true 258 259[system.cpu.fuPool.FUList1] 260type=FUDesc 261children=opList0 opList1 opList2 262count=1 263eventq_index=0 264opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 system.cpu.fuPool.FUList1.opList2 265 266[system.cpu.fuPool.FUList1.opList0] 267type=OpDesc 268eventq_index=0 269opClass=IntMult 270opLat=3 271pipelined=true 272 273[system.cpu.fuPool.FUList1.opList1] 274type=OpDesc 275eventq_index=0 276opClass=IntDiv 277opLat=12 278pipelined=false 279 280[system.cpu.fuPool.FUList1.opList2] 281type=OpDesc 282eventq_index=0 283opClass=IprAccess 284opLat=3 285pipelined=true 286 287[system.cpu.fuPool.FUList2] 288type=FUDesc 289children=opList 290count=1 291eventq_index=0 292opList=system.cpu.fuPool.FUList2.opList 293 294[system.cpu.fuPool.FUList2.opList] 295type=OpDesc 296eventq_index=0 297opClass=MemRead 298opLat=2 299pipelined=true 300 301[system.cpu.fuPool.FUList3] 302type=FUDesc 303children=opList 304count=1 305eventq_index=0 306opList=system.cpu.fuPool.FUList3.opList 307 308[system.cpu.fuPool.FUList3.opList] 309type=OpDesc 310eventq_index=0 311opClass=MemWrite 312opLat=2 313pipelined=true 314 315[system.cpu.fuPool.FUList4] 316type=FUDesc 317children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25 318count=2 319eventq_index=0 320opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 system.cpu.fuPool.FUList4.opList02 system.cpu.fuPool.FUList4.opList03 system.cpu.fuPool.FUList4.opList04 system.cpu.fuPool.FUList4.opList05 system.cpu.fuPool.FUList4.opList06 system.cpu.fuPool.FUList4.opList07 system.cpu.fuPool.FUList4.opList08 system.cpu.fuPool.FUList4.opList09 system.cpu.fuPool.FUList4.opList10 system.cpu.fuPool.FUList4.opList11 system.cpu.fuPool.FUList4.opList12 system.cpu.fuPool.FUList4.opList13 system.cpu.fuPool.FUList4.opList14 system.cpu.fuPool.FUList4.opList15 system.cpu.fuPool.FUList4.opList16 system.cpu.fuPool.FUList4.opList17 system.cpu.fuPool.FUList4.opList18 system.cpu.fuPool.FUList4.opList19 system.cpu.fuPool.FUList4.opList20 system.cpu.fuPool.FUList4.opList21 system.cpu.fuPool.FUList4.opList22 system.cpu.fuPool.FUList4.opList23 system.cpu.fuPool.FUList4.opList24 system.cpu.fuPool.FUList4.opList25 321 322[system.cpu.fuPool.FUList4.opList00] 323type=OpDesc 324eventq_index=0 325opClass=SimdAdd 326opLat=4 327pipelined=true 328 329[system.cpu.fuPool.FUList4.opList01] 330type=OpDesc 331eventq_index=0 332opClass=SimdAddAcc 333opLat=4 334pipelined=true 335 336[system.cpu.fuPool.FUList4.opList02] 337type=OpDesc 338eventq_index=0 339opClass=SimdAlu 340opLat=4 341pipelined=true 342 343[system.cpu.fuPool.FUList4.opList03] 344type=OpDesc 345eventq_index=0 346opClass=SimdCmp 347opLat=4 348pipelined=true 349 350[system.cpu.fuPool.FUList4.opList04] 351type=OpDesc 352eventq_index=0 353opClass=SimdCvt 354opLat=3 355pipelined=true 356 357[system.cpu.fuPool.FUList4.opList05] 358type=OpDesc 359eventq_index=0 360opClass=SimdMisc 361opLat=3 362pipelined=true 363 364[system.cpu.fuPool.FUList4.opList06] 365type=OpDesc 366eventq_index=0 367opClass=SimdMult 368opLat=5 369pipelined=true 370 371[system.cpu.fuPool.FUList4.opList07] 372type=OpDesc 373eventq_index=0 374opClass=SimdMultAcc 375opLat=5 376pipelined=true 377 378[system.cpu.fuPool.FUList4.opList08] 379type=OpDesc 380eventq_index=0 381opClass=SimdShift 382opLat=3 383pipelined=true 384 385[system.cpu.fuPool.FUList4.opList09] 386type=OpDesc 387eventq_index=0 388opClass=SimdShiftAcc 389opLat=3 390pipelined=true 391 392[system.cpu.fuPool.FUList4.opList10] 393type=OpDesc 394eventq_index=0 395opClass=SimdSqrt 396opLat=9 397pipelined=true 398 399[system.cpu.fuPool.FUList4.opList11] 400type=OpDesc 401eventq_index=0 402opClass=SimdFloatAdd 403opLat=5 404pipelined=true 405 406[system.cpu.fuPool.FUList4.opList12] 407type=OpDesc 408eventq_index=0 409opClass=SimdFloatAlu 410opLat=5 411pipelined=true 412 413[system.cpu.fuPool.FUList4.opList13] 414type=OpDesc 415eventq_index=0 416opClass=SimdFloatCmp 417opLat=3 418pipelined=true 419 420[system.cpu.fuPool.FUList4.opList14] 421type=OpDesc 422eventq_index=0 423opClass=SimdFloatCvt 424opLat=3 425pipelined=true 426 427[system.cpu.fuPool.FUList4.opList15] 428type=OpDesc 429eventq_index=0 430opClass=SimdFloatDiv 431opLat=3 432pipelined=true 433 434[system.cpu.fuPool.FUList4.opList16] 435type=OpDesc 436eventq_index=0 437opClass=SimdFloatMisc 438opLat=3 439pipelined=true 440 441[system.cpu.fuPool.FUList4.opList17] 442type=OpDesc 443eventq_index=0 444opClass=SimdFloatMult 445opLat=3 446pipelined=true 447 448[system.cpu.fuPool.FUList4.opList18] 449type=OpDesc 450eventq_index=0 451opClass=SimdFloatMultAcc 452opLat=1 453pipelined=true 454 455[system.cpu.fuPool.FUList4.opList19] 456type=OpDesc 457eventq_index=0 458opClass=SimdFloatSqrt 459opLat=9 460pipelined=true 461 462[system.cpu.fuPool.FUList4.opList20] 463type=OpDesc 464eventq_index=0 465opClass=FloatAdd 466opLat=5 467pipelined=true 468 469[system.cpu.fuPool.FUList4.opList21] 470type=OpDesc 471eventq_index=0 472opClass=FloatCmp 473opLat=5 474pipelined=true 475 476[system.cpu.fuPool.FUList4.opList22] 477type=OpDesc 478eventq_index=0 479opClass=FloatCvt 480opLat=5 481pipelined=true 482 483[system.cpu.fuPool.FUList4.opList23] 484type=OpDesc 485eventq_index=0 486opClass=FloatDiv 487opLat=9 488pipelined=false 489 490[system.cpu.fuPool.FUList4.opList24] 491type=OpDesc 492eventq_index=0 493opClass=FloatSqrt 494opLat=33 495pipelined=false 496 497[system.cpu.fuPool.FUList4.opList25] 498type=OpDesc 499eventq_index=0 500opClass=FloatMult 501opLat=4 502pipelined=true 503 504[system.cpu.icache] 505type=Cache 506children=tags 507addr_ranges=0:18446744073709551615 508assoc=2 509clk_domain=system.cpu_clk_domain 510clusivity=mostly_incl 511demand_mshr_reserve=1 512eventq_index=0 513hit_latency=1 514is_read_only=true 515max_miss_count=0 516mshrs=2 517prefetch_on_access=false 518prefetcher=Null 519response_latency=1 520sequential_access=false 521size=32768 522system=system 523tags=system.cpu.icache.tags 524tgts_per_mshr=8 525write_buffers=8 526writeback_clean=true 527cpu_side=system.cpu.icache_port 528mem_side=system.cpu.toL2Bus.slave[0] 529 530[system.cpu.icache.tags] 531type=LRU 532assoc=2 533block_size=64 534clk_domain=system.cpu_clk_domain 535eventq_index=0 536hit_latency=1 537sequential_access=false 538size=32768 539 540[system.cpu.interrupts] 541type=ArmInterrupts 542eventq_index=0 543 544[system.cpu.isa] 545type=ArmISA 546decoderFlavour=Generic 547eventq_index=0 548fpsid=1090793632 549id_aa64afr0_el1=0 550id_aa64afr1_el1=0 551id_aa64dfr0_el1=1052678 552id_aa64dfr1_el1=0 553id_aa64isar0_el1=0 554id_aa64isar1_el1=0 555id_aa64mmfr0_el1=15728642 556id_aa64mmfr1_el1=0 557id_aa64pfr0_el1=17 558id_aa64pfr1_el1=0 559id_isar0=34607377 560id_isar1=34677009 561id_isar2=555950401 562id_isar3=17899825 563id_isar4=268501314 564id_isar5=0 565id_mmfr0=270536963 566id_mmfr1=0 567id_mmfr2=19070976 568id_mmfr3=34611729 569id_pfr0=49 570id_pfr1=4113 571midr=1091551472 572pmu=Null 573system=system 574 575[system.cpu.istage2_mmu] 576type=ArmStage2MMU 577children=stage2_tlb 578eventq_index=0 579stage2_tlb=system.cpu.istage2_mmu.stage2_tlb 580sys=system 581tlb=system.cpu.itb 582 583[system.cpu.istage2_mmu.stage2_tlb] 584type=ArmTLB 585children=walker 586eventq_index=0 587is_stage2=true 588size=32 589walker=system.cpu.istage2_mmu.stage2_tlb.walker 590 591[system.cpu.istage2_mmu.stage2_tlb.walker] 592type=ArmTableWalker 593clk_domain=system.cpu_clk_domain 594eventq_index=0 595is_stage2=true 596num_squash_per_cycle=2 597sys=system 598 599[system.cpu.itb] 600type=ArmTLB 601children=walker 602eventq_index=0 603is_stage2=false 604size=64 605walker=system.cpu.itb.walker 606 607[system.cpu.itb.walker] 608type=ArmTableWalker 609clk_domain=system.cpu_clk_domain 610eventq_index=0 611is_stage2=false 612num_squash_per_cycle=2 613sys=system 614port=system.cpu.toL2Bus.slave[2] 615 616[system.cpu.l2cache] 617type=Cache 618children=prefetcher tags 619addr_ranges=0:18446744073709551615 620assoc=16 621clk_domain=system.cpu_clk_domain 622clusivity=mostly_excl 623demand_mshr_reserve=1 624eventq_index=0 625hit_latency=12 626is_read_only=false 627max_miss_count=0 628mshrs=16 629prefetch_on_access=true 630prefetcher=system.cpu.l2cache.prefetcher 631response_latency=12 632sequential_access=false 633size=1048576 634system=system 635tags=system.cpu.l2cache.tags 636tgts_per_mshr=8 637write_buffers=8 638writeback_clean=false 639cpu_side=system.cpu.toL2Bus.master[0] 640mem_side=system.membus.slave[1] 641 642[system.cpu.l2cache.prefetcher] 643type=StridePrefetcher 644cache_snoop=false 645clk_domain=system.cpu_clk_domain 646degree=8 647eventq_index=0 648latency=1 649max_conf=7 650min_conf=0 651on_data=true 652on_inst=true 653on_miss=false 654on_read=true 655on_write=true 656queue_filter=true 657queue_size=32 658queue_squash=true 659start_conf=4 660sys=system 661table_assoc=4 662table_sets=16 663tag_prefetch=true 664thresh_conf=4 665use_master_id=true 666 667[system.cpu.l2cache.tags] 668type=RandomRepl 669assoc=16 670block_size=64 671clk_domain=system.cpu_clk_domain 672eventq_index=0 673hit_latency=12 674sequential_access=false 675size=1048576 676 677[system.cpu.toL2Bus] 678type=CoherentXBar 679children=snoop_filter 680clk_domain=system.cpu_clk_domain 681eventq_index=0 682forward_latency=0 683frontend_latency=1 684point_of_coherency=false 685response_latency=1 686snoop_filter=system.cpu.toL2Bus.snoop_filter 687snoop_response_latency=1 688system=system 689use_default_range=false 690width=32 691master=system.cpu.l2cache.cpu_side 692slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port 693 694[system.cpu.toL2Bus.snoop_filter] 695type=SnoopFilter 696eventq_index=0 697lookup_latency=0 698max_capacity=8388608 699system=system 700 701[system.cpu.tracer] 702type=ExeTracer 703eventq_index=0 704 705[system.cpu.workload] 706type=LiveProcess 707cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook 708cwd=build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing 709drivers= 710egid=100 711env= 712errout=cerr 713euid=100 714eventq_index=0 715executable=/dist/m5/cpu2000/binaries/arm/linux/eon 716gid=100 717input=cin 718kvmInSE=false 719max_stack_size=67108864 720output=cout 721pid=100 722ppid=99 723simpoint=0 724system=system 725uid=100 726useArchPT=false 727 728[system.cpu_clk_domain] 729type=SrcClockDomain 730clock=500 731domain_id=-1 732eventq_index=0 733init_perf_level=0 734voltage_domain=system.voltage_domain 735 736[system.dvfs_handler] 737type=DVFSHandler 738domains= 739enable=false 740eventq_index=0 741sys_clk_domain=system.clk_domain 742transition_latency=100000000 743 744[system.membus] 745type=CoherentXBar 746clk_domain=system.clk_domain 747eventq_index=0 748forward_latency=4 749frontend_latency=3 750point_of_coherency=true 751response_latency=2 752snoop_filter=Null 753snoop_response_latency=4 754system=system 755use_default_range=false 756width=16 757master=system.physmem.port 758slave=system.system_port system.cpu.l2cache.mem_side 759 760[system.physmem] 761type=DRAMCtrl 762IDD0=0.075000 763IDD02=0.000000 764IDD2N=0.050000 765IDD2N2=0.000000 766IDD2P0=0.000000 767IDD2P02=0.000000 768IDD2P1=0.000000 769IDD2P12=0.000000 770IDD3N=0.057000 771IDD3N2=0.000000 772IDD3P0=0.000000 773IDD3P02=0.000000 774IDD3P1=0.000000 775IDD3P12=0.000000 776IDD4R=0.187000 777IDD4R2=0.000000 778IDD4W=0.165000 779IDD4W2=0.000000 780IDD5=0.220000 781IDD52=0.000000 782IDD6=0.000000 783IDD62=0.000000 784VDD=1.500000 785VDD2=0.000000 786activation_limit=4 787addr_mapping=RoRaBaCoCh 788bank_groups_per_rank=0 789banks_per_rank=8 790burst_length=8 791channels=1 792clk_domain=system.clk_domain 793conf_table_reported=true 794device_bus_width=8 795device_rowbuffer_size=1024 796device_size=536870912 797devices_per_rank=8 798dll=true 799eventq_index=0 800in_addr_map=true 801max_accesses_per_row=16 802mem_sched_policy=frfcfs 803min_writes_per_switch=16 804null=false 805page_policy=open_adaptive 806range=0:134217727 807ranks_per_channel=2 808read_buffer_size=32 809static_backend_latency=10000 810static_frontend_latency=10000 811tBURST=5000 812tCCD_L=0 813tCK=1250 814tCL=13750 815tCS=2500 816tRAS=35000 817tRCD=13750 818tREFI=7800000 819tRFC=260000 820tRP=13750 821tRRD=6000 822tRRD_L=0 823tRTP=7500 824tRTW=2500 825tWR=15000 826tWTR=7500 827tXAW=30000 828tXP=0 829tXPDLL=0 830tXS=0 831tXSDLL=0 832write_buffer_size=64 833write_high_thresh_perc=85 834write_low_thresh_perc=50 835port=system.membus.master[0] 836 837[system.voltage_domain] 838type=VoltageDomain 839eventq_index=0 840voltage=1.000000 841 842