stats.txt revision 9481:b0fa6b872f40
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.647873 # Number of seconds simulated 4sim_ticks 1647872848000 # Number of ticks simulated 5final_tick 1647872848000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 579757 # Simulator instruction rate (inst/s) 8host_op_rate 1072035 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1155389699 # Simulator tick rate (ticks/s) 10host_mem_usage 301076 # Number of bytes of host memory used 11host_seconds 1426.25 # Real time elapsed on the host 12sim_insts 826877110 # Number of instructions simulated 13sim_ops 1528988701 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 120704 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 24272448 # Number of bytes read from this memory 16system.physmem.bytes_read::total 24393152 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 120704 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 120704 # Number of instructions bytes read from this memory 19system.physmem.bytes_written::writebacks 18706304 # Number of bytes written to this memory 20system.physmem.bytes_written::total 18706304 # Number of bytes written to this memory 21system.physmem.num_reads::cpu.inst 1886 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 379257 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 381143 # Number of read requests responded to by this memory 24system.physmem.num_writes::writebacks 292286 # Number of write requests responded to by this memory 25system.physmem.num_writes::total 292286 # Number of write requests responded to by this memory 26system.physmem.bw_read::cpu.inst 73248 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::cpu.data 14729564 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_read::total 14802812 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::cpu.inst 73248 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_inst_read::total 73248 # Instruction read bandwidth from this memory (bytes/s) 31system.physmem.bw_write::writebacks 11351788 # Write bandwidth from this memory (bytes/s) 32system.physmem.bw_write::total 11351788 # Write bandwidth from this memory (bytes/s) 33system.physmem.bw_total::writebacks 11351788 # Total bandwidth to/from this memory (bytes/s) 34system.physmem.bw_total::cpu.inst 73248 # Total bandwidth to/from this memory (bytes/s) 35system.physmem.bw_total::cpu.data 14729564 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::total 26154600 # Total bandwidth to/from this memory (bytes/s) 37system.cpu.workload.num_syscalls 551 # Number of system calls 38system.cpu.numCycles 3295745696 # number of cpu cycles simulated 39system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 40system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 41system.cpu.committedInsts 826877110 # Number of instructions committed 42system.cpu.committedOps 1528988701 # Number of ops (including micro ops) committed 43system.cpu.num_int_alu_accesses 1528317560 # Number of integer alu accesses 44system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses 45system.cpu.num_func_calls 0 # number of times a function call or return occured 46system.cpu.num_conditional_control_insts 92658795 # number of instructions that are conditional controls 47system.cpu.num_int_insts 1528317560 # number of integer instructions 48system.cpu.num_fp_insts 0 # number of float instructions 49system.cpu.num_int_register_reads 3855106255 # number of times the integer registers were read 50system.cpu.num_int_register_writes 1614040852 # number of times the integer registers were written 51system.cpu.num_fp_register_reads 0 # number of times the floating registers were read 52system.cpu.num_fp_register_writes 0 # number of times the floating registers were written 53system.cpu.num_mem_refs 533262342 # number of memory refs 54system.cpu.num_load_insts 384102156 # Number of load instructions 55system.cpu.num_store_insts 149160186 # Number of store instructions 56system.cpu.num_idle_cycles 0 # Number of idle cycles 57system.cpu.num_busy_cycles 3295745696 # Number of busy cycles 58system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles 59system.cpu.idle_fraction 0 # Percentage of idle cycles 60system.cpu.icache.replacements 1253 # number of replacements 61system.cpu.icache.tagsinuse 881.356491 # Cycle average of tags in use 62system.cpu.icache.total_refs 1068344252 # Total number of references to valid blocks. 63system.cpu.icache.sampled_refs 2814 # Sample count of references to valid blocks. 64system.cpu.icache.avg_refs 379653.252310 # Average number of references to valid blocks. 65system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 66system.cpu.icache.occ_blocks::cpu.inst 881.356491 # Average occupied blocks per requestor 67system.cpu.icache.occ_percent::cpu.inst 0.430350 # Average percentage of cache occupancy 68system.cpu.icache.occ_percent::total 0.430350 # Average percentage of cache occupancy 69system.cpu.icache.ReadReq_hits::cpu.inst 1068344252 # number of ReadReq hits 70system.cpu.icache.ReadReq_hits::total 1068344252 # number of ReadReq hits 71system.cpu.icache.demand_hits::cpu.inst 1068344252 # number of demand (read+write) hits 72system.cpu.icache.demand_hits::total 1068344252 # number of demand (read+write) hits 73system.cpu.icache.overall_hits::cpu.inst 1068344252 # number of overall hits 74system.cpu.icache.overall_hits::total 1068344252 # number of overall hits 75system.cpu.icache.ReadReq_misses::cpu.inst 2814 # number of ReadReq misses 76system.cpu.icache.ReadReq_misses::total 2814 # number of ReadReq misses 77system.cpu.icache.demand_misses::cpu.inst 2814 # number of demand (read+write) misses 78system.cpu.icache.demand_misses::total 2814 # number of demand (read+write) misses 79system.cpu.icache.overall_misses::cpu.inst 2814 # number of overall misses 80system.cpu.icache.overall_misses::total 2814 # number of overall misses 81system.cpu.icache.ReadReq_miss_latency::cpu.inst 115806000 # number of ReadReq miss cycles 82system.cpu.icache.ReadReq_miss_latency::total 115806000 # number of ReadReq miss cycles 83system.cpu.icache.demand_miss_latency::cpu.inst 115806000 # number of demand (read+write) miss cycles 84system.cpu.icache.demand_miss_latency::total 115806000 # number of demand (read+write) miss cycles 85system.cpu.icache.overall_miss_latency::cpu.inst 115806000 # number of overall miss cycles 86system.cpu.icache.overall_miss_latency::total 115806000 # number of overall miss cycles 87system.cpu.icache.ReadReq_accesses::cpu.inst 1068347066 # number of ReadReq accesses(hits+misses) 88system.cpu.icache.ReadReq_accesses::total 1068347066 # number of ReadReq accesses(hits+misses) 89system.cpu.icache.demand_accesses::cpu.inst 1068347066 # number of demand (read+write) accesses 90system.cpu.icache.demand_accesses::total 1068347066 # number of demand (read+write) accesses 91system.cpu.icache.overall_accesses::cpu.inst 1068347066 # number of overall (read+write) accesses 92system.cpu.icache.overall_accesses::total 1068347066 # number of overall (read+write) accesses 93system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000003 # miss rate for ReadReq accesses 94system.cpu.icache.ReadReq_miss_rate::total 0.000003 # miss rate for ReadReq accesses 95system.cpu.icache.demand_miss_rate::cpu.inst 0.000003 # miss rate for demand accesses 96system.cpu.icache.demand_miss_rate::total 0.000003 # miss rate for demand accesses 97system.cpu.icache.overall_miss_rate::cpu.inst 0.000003 # miss rate for overall accesses 98system.cpu.icache.overall_miss_rate::total 0.000003 # miss rate for overall accesses 99system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 41153.518124 # average ReadReq miss latency 100system.cpu.icache.ReadReq_avg_miss_latency::total 41153.518124 # average ReadReq miss latency 101system.cpu.icache.demand_avg_miss_latency::cpu.inst 41153.518124 # average overall miss latency 102system.cpu.icache.demand_avg_miss_latency::total 41153.518124 # average overall miss latency 103system.cpu.icache.overall_avg_miss_latency::cpu.inst 41153.518124 # average overall miss latency 104system.cpu.icache.overall_avg_miss_latency::total 41153.518124 # average overall miss latency 105system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 106system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 107system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 108system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 109system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 110system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 111system.cpu.icache.fast_writes 0 # number of fast writes performed 112system.cpu.icache.cache_copies 0 # number of cache copies performed 113system.cpu.icache.ReadReq_mshr_misses::cpu.inst 2814 # number of ReadReq MSHR misses 114system.cpu.icache.ReadReq_mshr_misses::total 2814 # number of ReadReq MSHR misses 115system.cpu.icache.demand_mshr_misses::cpu.inst 2814 # number of demand (read+write) MSHR misses 116system.cpu.icache.demand_mshr_misses::total 2814 # number of demand (read+write) MSHR misses 117system.cpu.icache.overall_mshr_misses::cpu.inst 2814 # number of overall MSHR misses 118system.cpu.icache.overall_mshr_misses::total 2814 # number of overall MSHR misses 119system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 110178000 # number of ReadReq MSHR miss cycles 120system.cpu.icache.ReadReq_mshr_miss_latency::total 110178000 # number of ReadReq MSHR miss cycles 121system.cpu.icache.demand_mshr_miss_latency::cpu.inst 110178000 # number of demand (read+write) MSHR miss cycles 122system.cpu.icache.demand_mshr_miss_latency::total 110178000 # number of demand (read+write) MSHR miss cycles 123system.cpu.icache.overall_mshr_miss_latency::cpu.inst 110178000 # number of overall MSHR miss cycles 124system.cpu.icache.overall_mshr_miss_latency::total 110178000 # number of overall MSHR miss cycles 125system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for ReadReq accesses 126system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000003 # mshr miss rate for ReadReq accesses 127system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for demand accesses 128system.cpu.icache.demand_mshr_miss_rate::total 0.000003 # mshr miss rate for demand accesses 129system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for overall accesses 130system.cpu.icache.overall_mshr_miss_rate::total 0.000003 # mshr miss rate for overall accesses 131system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 39153.518124 # average ReadReq mshr miss latency 132system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 39153.518124 # average ReadReq mshr miss latency 133system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 39153.518124 # average overall mshr miss latency 134system.cpu.icache.demand_avg_mshr_miss_latency::total 39153.518124 # average overall mshr miss latency 135system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 39153.518124 # average overall mshr miss latency 136system.cpu.icache.overall_avg_mshr_miss_latency::total 39153.518124 # average overall mshr miss latency 137system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 138system.cpu.l2cache.replacements 348459 # number of replacements 139system.cpu.l2cache.tagsinuse 29286.402681 # Cycle average of tags in use 140system.cpu.l2cache.total_refs 3655011 # Total number of references to valid blocks. 141system.cpu.l2cache.sampled_refs 380814 # Sample count of references to valid blocks. 142system.cpu.l2cache.avg_refs 9.597890 # Average number of references to valid blocks. 143system.cpu.l2cache.warmup_cycle 755936430000 # Cycle when the warmup percentage was hit. 144system.cpu.l2cache.occ_blocks::writebacks 21041.299350 # Average occupied blocks per requestor 145system.cpu.l2cache.occ_blocks::cpu.inst 139.758520 # Average occupied blocks per requestor 146system.cpu.l2cache.occ_blocks::cpu.data 8105.344812 # Average occupied blocks per requestor 147system.cpu.l2cache.occ_percent::writebacks 0.642129 # Average percentage of cache occupancy 148system.cpu.l2cache.occ_percent::cpu.inst 0.004265 # Average percentage of cache occupancy 149system.cpu.l2cache.occ_percent::cpu.data 0.247355 # Average percentage of cache occupancy 150system.cpu.l2cache.occ_percent::total 0.893750 # Average percentage of cache occupancy 151system.cpu.l2cache.ReadReq_hits::cpu.inst 928 # number of ReadReq hits 152system.cpu.l2cache.ReadReq_hits::cpu.data 1554848 # number of ReadReq hits 153system.cpu.l2cache.ReadReq_hits::total 1555776 # number of ReadReq hits 154system.cpu.l2cache.Writeback_hits::writebacks 2323523 # number of Writeback hits 155system.cpu.l2cache.Writeback_hits::total 2323523 # number of Writeback hits 156system.cpu.l2cache.ReadExReq_hits::cpu.data 584353 # number of ReadExReq hits 157system.cpu.l2cache.ReadExReq_hits::total 584353 # number of ReadExReq hits 158system.cpu.l2cache.demand_hits::cpu.inst 928 # number of demand (read+write) hits 159system.cpu.l2cache.demand_hits::cpu.data 2139201 # number of demand (read+write) hits 160system.cpu.l2cache.demand_hits::total 2140129 # number of demand (read+write) hits 161system.cpu.l2cache.overall_hits::cpu.inst 928 # number of overall hits 162system.cpu.l2cache.overall_hits::cpu.data 2139201 # number of overall hits 163system.cpu.l2cache.overall_hits::total 2140129 # number of overall hits 164system.cpu.l2cache.ReadReq_misses::cpu.inst 1886 # number of ReadReq misses 165system.cpu.l2cache.ReadReq_misses::cpu.data 172566 # number of ReadReq misses 166system.cpu.l2cache.ReadReq_misses::total 174452 # number of ReadReq misses 167system.cpu.l2cache.ReadExReq_misses::cpu.data 206691 # number of ReadExReq misses 168system.cpu.l2cache.ReadExReq_misses::total 206691 # number of ReadExReq misses 169system.cpu.l2cache.demand_misses::cpu.inst 1886 # number of demand (read+write) misses 170system.cpu.l2cache.demand_misses::cpu.data 379257 # number of demand (read+write) misses 171system.cpu.l2cache.demand_misses::total 381143 # number of demand (read+write) misses 172system.cpu.l2cache.overall_misses::cpu.inst 1886 # number of overall misses 173system.cpu.l2cache.overall_misses::cpu.data 379257 # number of overall misses 174system.cpu.l2cache.overall_misses::total 381143 # number of overall misses 175system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 98084000 # number of ReadReq miss cycles 176system.cpu.l2cache.ReadReq_miss_latency::cpu.data 8973561000 # number of ReadReq miss cycles 177system.cpu.l2cache.ReadReq_miss_latency::total 9071645000 # number of ReadReq miss cycles 178system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10747939500 # number of ReadExReq miss cycles 179system.cpu.l2cache.ReadExReq_miss_latency::total 10747939500 # number of ReadExReq miss cycles 180system.cpu.l2cache.demand_miss_latency::cpu.inst 98084000 # number of demand (read+write) miss cycles 181system.cpu.l2cache.demand_miss_latency::cpu.data 19721500500 # number of demand (read+write) miss cycles 182system.cpu.l2cache.demand_miss_latency::total 19819584500 # number of demand (read+write) miss cycles 183system.cpu.l2cache.overall_miss_latency::cpu.inst 98084000 # number of overall miss cycles 184system.cpu.l2cache.overall_miss_latency::cpu.data 19721500500 # number of overall miss cycles 185system.cpu.l2cache.overall_miss_latency::total 19819584500 # number of overall miss cycles 186system.cpu.l2cache.ReadReq_accesses::cpu.inst 2814 # number of ReadReq accesses(hits+misses) 187system.cpu.l2cache.ReadReq_accesses::cpu.data 1727414 # number of ReadReq accesses(hits+misses) 188system.cpu.l2cache.ReadReq_accesses::total 1730228 # number of ReadReq accesses(hits+misses) 189system.cpu.l2cache.Writeback_accesses::writebacks 2323523 # number of Writeback accesses(hits+misses) 190system.cpu.l2cache.Writeback_accesses::total 2323523 # number of Writeback accesses(hits+misses) 191system.cpu.l2cache.ReadExReq_accesses::cpu.data 791044 # number of ReadExReq accesses(hits+misses) 192system.cpu.l2cache.ReadExReq_accesses::total 791044 # number of ReadExReq accesses(hits+misses) 193system.cpu.l2cache.demand_accesses::cpu.inst 2814 # number of demand (read+write) accesses 194system.cpu.l2cache.demand_accesses::cpu.data 2518458 # number of demand (read+write) accesses 195system.cpu.l2cache.demand_accesses::total 2521272 # number of demand (read+write) accesses 196system.cpu.l2cache.overall_accesses::cpu.inst 2814 # number of overall (read+write) accesses 197system.cpu.l2cache.overall_accesses::cpu.data 2518458 # number of overall (read+write) accesses 198system.cpu.l2cache.overall_accesses::total 2521272 # number of overall (read+write) accesses 199system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.670220 # miss rate for ReadReq accesses 200system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.099898 # miss rate for ReadReq accesses 201system.cpu.l2cache.ReadReq_miss_rate::total 0.100826 # miss rate for ReadReq accesses 202system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.261289 # miss rate for ReadExReq accesses 203system.cpu.l2cache.ReadExReq_miss_rate::total 0.261289 # miss rate for ReadExReq accesses 204system.cpu.l2cache.demand_miss_rate::cpu.inst 0.670220 # miss rate for demand accesses 205system.cpu.l2cache.demand_miss_rate::cpu.data 0.150591 # miss rate for demand accesses 206system.cpu.l2cache.demand_miss_rate::total 0.151171 # miss rate for demand accesses 207system.cpu.l2cache.overall_miss_rate::cpu.inst 0.670220 # miss rate for overall accesses 208system.cpu.l2cache.overall_miss_rate::cpu.data 0.150591 # miss rate for overall accesses 209system.cpu.l2cache.overall_miss_rate::total 0.151171 # miss rate for overall accesses 210system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52006.362672 # average ReadReq miss latency 211system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000.747540 # average ReadReq miss latency 212system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000.808245 # average ReadReq miss latency 213system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000.036286 # average ReadExReq miss latency 214system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000.036286 # average ReadExReq miss latency 215system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52006.362672 # average overall miss latency 216system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000.359914 # average overall miss latency 217system.cpu.l2cache.demand_avg_miss_latency::total 52000.389618 # average overall miss latency 218system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52006.362672 # average overall miss latency 219system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000.359914 # average overall miss latency 220system.cpu.l2cache.overall_avg_miss_latency::total 52000.389618 # average overall miss latency 221system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 222system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 223system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 224system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 225system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 226system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 227system.cpu.l2cache.fast_writes 0 # number of fast writes performed 228system.cpu.l2cache.cache_copies 0 # number of cache copies performed 229system.cpu.l2cache.writebacks::writebacks 292286 # number of writebacks 230system.cpu.l2cache.writebacks::total 292286 # number of writebacks 231system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1886 # number of ReadReq MSHR misses 232system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 172566 # number of ReadReq MSHR misses 233system.cpu.l2cache.ReadReq_mshr_misses::total 174452 # number of ReadReq MSHR misses 234system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206691 # number of ReadExReq MSHR misses 235system.cpu.l2cache.ReadExReq_mshr_misses::total 206691 # number of ReadExReq MSHR misses 236system.cpu.l2cache.demand_mshr_misses::cpu.inst 1886 # number of demand (read+write) MSHR misses 237system.cpu.l2cache.demand_mshr_misses::cpu.data 379257 # number of demand (read+write) MSHR misses 238system.cpu.l2cache.demand_mshr_misses::total 381143 # number of demand (read+write) MSHR misses 239system.cpu.l2cache.overall_mshr_misses::cpu.inst 1886 # number of overall MSHR misses 240system.cpu.l2cache.overall_mshr_misses::cpu.data 379257 # number of overall MSHR misses 241system.cpu.l2cache.overall_mshr_misses::total 381143 # number of overall MSHR misses 242system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 75452000 # number of ReadReq MSHR miss cycles 243system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6902758000 # number of ReadReq MSHR miss cycles 244system.cpu.l2cache.ReadReq_mshr_miss_latency::total 6978210000 # number of ReadReq MSHR miss cycles 245system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8267645000 # number of ReadExReq MSHR miss cycles 246system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8267645000 # number of ReadExReq MSHR miss cycles 247system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 75452000 # number of demand (read+write) MSHR miss cycles 248system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15170403000 # number of demand (read+write) MSHR miss cycles 249system.cpu.l2cache.demand_mshr_miss_latency::total 15245855000 # number of demand (read+write) MSHR miss cycles 250system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 75452000 # number of overall MSHR miss cycles 251system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15170403000 # number of overall MSHR miss cycles 252system.cpu.l2cache.overall_mshr_miss_latency::total 15245855000 # number of overall MSHR miss cycles 253system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.670220 # mshr miss rate for ReadReq accesses 254system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.099898 # mshr miss rate for ReadReq accesses 255system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.100826 # mshr miss rate for ReadReq accesses 256system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.261289 # mshr miss rate for ReadExReq accesses 257system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.261289 # mshr miss rate for ReadExReq accesses 258system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.670220 # mshr miss rate for demand accesses 259system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.150591 # mshr miss rate for demand accesses 260system.cpu.l2cache.demand_mshr_miss_rate::total 0.151171 # mshr miss rate for demand accesses 261system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.670220 # mshr miss rate for overall accesses 262system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.150591 # mshr miss rate for overall accesses 263system.cpu.l2cache.overall_mshr_miss_rate::total 0.151171 # mshr miss rate for overall accesses 264system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40006.362672 # average ReadReq mshr miss latency 265system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000.683796 # average ReadReq mshr miss latency 266system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000.745191 # average ReadReq mshr miss latency 267system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000.024191 # average ReadExReq mshr miss latency 268system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000.024191 # average ReadExReq mshr miss latency 269system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40006.362672 # average overall mshr miss latency 270system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000.324318 # average overall mshr miss latency 271system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000.354198 # average overall mshr miss latency 272system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40006.362672 # average overall mshr miss latency 273system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000.324318 # average overall mshr miss latency 274system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.354198 # average overall mshr miss latency 275system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 276system.cpu.dcache.replacements 2514362 # number of replacements 277system.cpu.dcache.tagsinuse 4086.415786 # Cycle average of tags in use 278system.cpu.dcache.total_refs 530743929 # Total number of references to valid blocks. 279system.cpu.dcache.sampled_refs 2518458 # Sample count of references to valid blocks. 280system.cpu.dcache.avg_refs 210.741624 # Average number of references to valid blocks. 281system.cpu.dcache.warmup_cycle 8211723000 # Cycle when the warmup percentage was hit. 282system.cpu.dcache.occ_blocks::cpu.data 4086.415786 # Average occupied blocks per requestor 283system.cpu.dcache.occ_percent::cpu.data 0.997660 # Average percentage of cache occupancy 284system.cpu.dcache.occ_percent::total 0.997660 # Average percentage of cache occupancy 285system.cpu.dcache.ReadReq_hits::cpu.data 382374771 # number of ReadReq hits 286system.cpu.dcache.ReadReq_hits::total 382374771 # number of ReadReq hits 287system.cpu.dcache.WriteReq_hits::cpu.data 148369158 # number of WriteReq hits 288system.cpu.dcache.WriteReq_hits::total 148369158 # number of WriteReq hits 289system.cpu.dcache.demand_hits::cpu.data 530743929 # number of demand (read+write) hits 290system.cpu.dcache.demand_hits::total 530743929 # number of demand (read+write) hits 291system.cpu.dcache.overall_hits::cpu.data 530743929 # number of overall hits 292system.cpu.dcache.overall_hits::total 530743929 # number of overall hits 293system.cpu.dcache.ReadReq_misses::cpu.data 1727414 # number of ReadReq misses 294system.cpu.dcache.ReadReq_misses::total 1727414 # number of ReadReq misses 295system.cpu.dcache.WriteReq_misses::cpu.data 791044 # number of WriteReq misses 296system.cpu.dcache.WriteReq_misses::total 791044 # number of WriteReq misses 297system.cpu.dcache.demand_misses::cpu.data 2518458 # number of demand (read+write) misses 298system.cpu.dcache.demand_misses::total 2518458 # number of demand (read+write) misses 299system.cpu.dcache.overall_misses::cpu.data 2518458 # number of overall misses 300system.cpu.dcache.overall_misses::total 2518458 # number of overall misses 301system.cpu.dcache.ReadReq_miss_latency::cpu.data 29704283000 # number of ReadReq miss cycles 302system.cpu.dcache.ReadReq_miss_latency::total 29704283000 # number of ReadReq miss cycles 303system.cpu.dcache.WriteReq_miss_latency::cpu.data 18964601500 # number of WriteReq miss cycles 304system.cpu.dcache.WriteReq_miss_latency::total 18964601500 # number of WriteReq miss cycles 305system.cpu.dcache.demand_miss_latency::cpu.data 48668884500 # number of demand (read+write) miss cycles 306system.cpu.dcache.demand_miss_latency::total 48668884500 # number of demand (read+write) miss cycles 307system.cpu.dcache.overall_miss_latency::cpu.data 48668884500 # number of overall miss cycles 308system.cpu.dcache.overall_miss_latency::total 48668884500 # number of overall miss cycles 309system.cpu.dcache.ReadReq_accesses::cpu.data 384102185 # number of ReadReq accesses(hits+misses) 310system.cpu.dcache.ReadReq_accesses::total 384102185 # number of ReadReq accesses(hits+misses) 311system.cpu.dcache.WriteReq_accesses::cpu.data 149160202 # number of WriteReq accesses(hits+misses) 312system.cpu.dcache.WriteReq_accesses::total 149160202 # number of WriteReq accesses(hits+misses) 313system.cpu.dcache.demand_accesses::cpu.data 533262387 # number of demand (read+write) accesses 314system.cpu.dcache.demand_accesses::total 533262387 # number of demand (read+write) accesses 315system.cpu.dcache.overall_accesses::cpu.data 533262387 # number of overall (read+write) accesses 316system.cpu.dcache.overall_accesses::total 533262387 # number of overall (read+write) accesses 317system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004497 # miss rate for ReadReq accesses 318system.cpu.dcache.ReadReq_miss_rate::total 0.004497 # miss rate for ReadReq accesses 319system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005303 # miss rate for WriteReq accesses 320system.cpu.dcache.WriteReq_miss_rate::total 0.005303 # miss rate for WriteReq accesses 321system.cpu.dcache.demand_miss_rate::cpu.data 0.004723 # miss rate for demand accesses 322system.cpu.dcache.demand_miss_rate::total 0.004723 # miss rate for demand accesses 323system.cpu.dcache.overall_miss_rate::cpu.data 0.004723 # miss rate for overall accesses 324system.cpu.dcache.overall_miss_rate::total 0.004723 # miss rate for overall accesses 325system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17195.810037 # average ReadReq miss latency 326system.cpu.dcache.ReadReq_avg_miss_latency::total 17195.810037 # average ReadReq miss latency 327system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 23974.142399 # average WriteReq miss latency 328system.cpu.dcache.WriteReq_avg_miss_latency::total 23974.142399 # average WriteReq miss latency 329system.cpu.dcache.demand_avg_miss_latency::cpu.data 19324.874387 # average overall miss latency 330system.cpu.dcache.demand_avg_miss_latency::total 19324.874387 # average overall miss latency 331system.cpu.dcache.overall_avg_miss_latency::cpu.data 19324.874387 # average overall miss latency 332system.cpu.dcache.overall_avg_miss_latency::total 19324.874387 # average overall miss latency 333system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 334system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 335system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 336system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 337system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 338system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 339system.cpu.dcache.fast_writes 0 # number of fast writes performed 340system.cpu.dcache.cache_copies 0 # number of cache copies performed 341system.cpu.dcache.writebacks::writebacks 2323523 # number of writebacks 342system.cpu.dcache.writebacks::total 2323523 # number of writebacks 343system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1727414 # number of ReadReq MSHR misses 344system.cpu.dcache.ReadReq_mshr_misses::total 1727414 # number of ReadReq MSHR misses 345system.cpu.dcache.WriteReq_mshr_misses::cpu.data 791044 # number of WriteReq MSHR misses 346system.cpu.dcache.WriteReq_mshr_misses::total 791044 # number of WriteReq MSHR misses 347system.cpu.dcache.demand_mshr_misses::cpu.data 2518458 # number of demand (read+write) MSHR misses 348system.cpu.dcache.demand_mshr_misses::total 2518458 # number of demand (read+write) MSHR misses 349system.cpu.dcache.overall_mshr_misses::cpu.data 2518458 # number of overall MSHR misses 350system.cpu.dcache.overall_mshr_misses::total 2518458 # number of overall MSHR misses 351system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 26249455000 # number of ReadReq MSHR miss cycles 352system.cpu.dcache.ReadReq_mshr_miss_latency::total 26249455000 # number of ReadReq MSHR miss cycles 353system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 17382513500 # number of WriteReq MSHR miss cycles 354system.cpu.dcache.WriteReq_mshr_miss_latency::total 17382513500 # number of WriteReq MSHR miss cycles 355system.cpu.dcache.demand_mshr_miss_latency::cpu.data 43631968500 # number of demand (read+write) MSHR miss cycles 356system.cpu.dcache.demand_mshr_miss_latency::total 43631968500 # number of demand (read+write) MSHR miss cycles 357system.cpu.dcache.overall_mshr_miss_latency::cpu.data 43631968500 # number of overall MSHR miss cycles 358system.cpu.dcache.overall_mshr_miss_latency::total 43631968500 # number of overall MSHR miss cycles 359system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.004497 # mshr miss rate for ReadReq accesses 360system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.004497 # mshr miss rate for ReadReq accesses 361system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005303 # mshr miss rate for WriteReq accesses 362system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005303 # mshr miss rate for WriteReq accesses 363system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.004723 # mshr miss rate for demand accesses 364system.cpu.dcache.demand_mshr_miss_rate::total 0.004723 # mshr miss rate for demand accesses 365system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.004723 # mshr miss rate for overall accesses 366system.cpu.dcache.overall_mshr_miss_rate::total 0.004723 # mshr miss rate for overall accesses 367system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15195.810037 # average ReadReq mshr miss latency 368system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15195.810037 # average ReadReq mshr miss latency 369system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 21974.142399 # average WriteReq mshr miss latency 370system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 21974.142399 # average WriteReq mshr miss latency 371system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17324.874387 # average overall mshr miss latency 372system.cpu.dcache.demand_avg_mshr_miss_latency::total 17324.874387 # average overall mshr miss latency 373system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17324.874387 # average overall mshr miss latency 374system.cpu.dcache.overall_avg_mshr_miss_latency::total 17324.874387 # average overall mshr miss latency 375system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 376 377---------- End Simulation Statistics ---------- 378