stats.txt revision 9988:0b2e590c85be
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.459341 # Number of seconds simulated 4sim_ticks 459340600000 # Number of ticks simulated 5final_tick 459340600000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 64463 # Simulator instruction rate (inst/s) 8host_op_rate 119200 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 35810129 # Simulator tick rate (ticks/s) 10host_mem_usage 391936 # Number of bytes of host memory used 11host_seconds 12827.11 # Real time elapsed on the host 12sim_insts 826877109 # Number of instructions simulated 13sim_ops 1528988701 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 203008 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 24478016 # Number of bytes read from this memory 16system.physmem.bytes_read::total 24681024 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 203008 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 203008 # Number of instructions bytes read from this memory 19system.physmem.bytes_written::writebacks 18788608 # Number of bytes written to this memory 20system.physmem.bytes_written::total 18788608 # Number of bytes written to this memory 21system.physmem.num_reads::cpu.inst 3172 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 382469 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 385641 # Number of read requests responded to by this memory 24system.physmem.num_writes::writebacks 293572 # Number of write requests responded to by this memory 25system.physmem.num_writes::total 293572 # Number of write requests responded to by this memory 26system.physmem.bw_read::cpu.inst 441955 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::cpu.data 53289468 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_read::total 53731423 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::cpu.inst 441955 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_inst_read::total 441955 # Instruction read bandwidth from this memory (bytes/s) 31system.physmem.bw_write::writebacks 40903434 # Write bandwidth from this memory (bytes/s) 32system.physmem.bw_write::total 40903434 # Write bandwidth from this memory (bytes/s) 33system.physmem.bw_total::writebacks 40903434 # Total bandwidth to/from this memory (bytes/s) 34system.physmem.bw_total::cpu.inst 441955 # Total bandwidth to/from this memory (bytes/s) 35system.physmem.bw_total::cpu.data 53289468 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::total 94634857 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.readReqs 385641 # Number of read requests accepted 38system.physmem.writeReqs 293572 # Number of write requests accepted 39system.physmem.readBursts 385641 # Number of DRAM read bursts, including those serviced by the write queue 40system.physmem.writeBursts 293572 # Number of DRAM write bursts, including those merged in the write queue 41system.physmem.bytesReadDRAM 24669632 # Total number of bytes read from DRAM 42system.physmem.bytesReadWrQ 11392 # Total number of bytes read from write queue 43system.physmem.bytesWritten 18788480 # Total number of bytes written to DRAM 44system.physmem.bytesReadSys 24681024 # Total read bytes from the system interface side 45system.physmem.bytesWrittenSys 18788608 # Total written bytes from the system interface side 46system.physmem.servicedByWrQ 178 # Number of DRAM read bursts serviced by the write queue 47system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 48system.physmem.neitherReadNorWriteReqs 135253 # Number of requests that are neither read nor write 49system.physmem.perBankRdBursts::0 24057 # Per bank write bursts 50system.physmem.perBankRdBursts::1 26446 # Per bank write bursts 51system.physmem.perBankRdBursts::2 24658 # Per bank write bursts 52system.physmem.perBankRdBursts::3 24494 # Per bank write bursts 53system.physmem.perBankRdBursts::4 23239 # Per bank write bursts 54system.physmem.perBankRdBursts::5 23672 # Per bank write bursts 55system.physmem.perBankRdBursts::6 24412 # Per bank write bursts 56system.physmem.perBankRdBursts::7 24201 # Per bank write bursts 57system.physmem.perBankRdBursts::8 23613 # Per bank write bursts 58system.physmem.perBankRdBursts::9 23828 # Per bank write bursts 59system.physmem.perBankRdBursts::10 24822 # Per bank write bursts 60system.physmem.perBankRdBursts::11 24051 # Per bank write bursts 61system.physmem.perBankRdBursts::12 23218 # Per bank write bursts 62system.physmem.perBankRdBursts::13 22963 # Per bank write bursts 63system.physmem.perBankRdBursts::14 23780 # Per bank write bursts 64system.physmem.perBankRdBursts::15 24009 # Per bank write bursts 65system.physmem.perBankWrBursts::0 18526 # Per bank write bursts 66system.physmem.perBankWrBursts::1 19824 # Per bank write bursts 67system.physmem.perBankWrBursts::2 18930 # Per bank write bursts 68system.physmem.perBankWrBursts::3 18895 # Per bank write bursts 69system.physmem.perBankWrBursts::4 18030 # Per bank write bursts 70system.physmem.perBankWrBursts::5 18409 # Per bank write bursts 71system.physmem.perBankWrBursts::6 18982 # Per bank write bursts 72system.physmem.perBankWrBursts::7 18942 # Per bank write bursts 73system.physmem.perBankWrBursts::8 18537 # Per bank write bursts 74system.physmem.perBankWrBursts::9 18120 # Per bank write bursts 75system.physmem.perBankWrBursts::10 18829 # Per bank write bursts 76system.physmem.perBankWrBursts::11 17702 # Per bank write bursts 77system.physmem.perBankWrBursts::12 17342 # Per bank write bursts 78system.physmem.perBankWrBursts::13 16954 # Per bank write bursts 79system.physmem.perBankWrBursts::14 17718 # Per bank write bursts 80system.physmem.perBankWrBursts::15 17830 # Per bank write bursts 81system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 82system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 83system.physmem.totGap 459340574000 # Total gap between requests 84system.physmem.readPktSize::0 0 # Read request sizes (log2) 85system.physmem.readPktSize::1 0 # Read request sizes (log2) 86system.physmem.readPktSize::2 0 # Read request sizes (log2) 87system.physmem.readPktSize::3 0 # Read request sizes (log2) 88system.physmem.readPktSize::4 0 # Read request sizes (log2) 89system.physmem.readPktSize::5 0 # Read request sizes (log2) 90system.physmem.readPktSize::6 385641 # Read request sizes (log2) 91system.physmem.writePktSize::0 0 # Write request sizes (log2) 92system.physmem.writePktSize::1 0 # Write request sizes (log2) 93system.physmem.writePktSize::2 0 # Write request sizes (log2) 94system.physmem.writePktSize::3 0 # Write request sizes (log2) 95system.physmem.writePktSize::4 0 # Write request sizes (log2) 96system.physmem.writePktSize::5 0 # Write request sizes (log2) 97system.physmem.writePktSize::6 293572 # Write request sizes (log2) 98system.physmem.rdQLenPdf::0 380895 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::1 4253 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::2 284 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::3 27 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 130system.physmem.wrQLenPdf::0 13203 # What write queue length does an incoming req see 131system.physmem.wrQLenPdf::1 13289 # What write queue length does an incoming req see 132system.physmem.wrQLenPdf::2 13319 # What write queue length does an incoming req see 133system.physmem.wrQLenPdf::3 13330 # What write queue length does an incoming req see 134system.physmem.wrQLenPdf::4 13323 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::5 13318 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::6 13380 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::7 13367 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::8 13383 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::9 13400 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::10 13420 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::11 13351 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::12 13361 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::13 13365 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::14 13348 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::15 13319 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::16 13314 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::17 13314 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::18 13324 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::19 13314 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::20 13479 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::21 13297 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::22 14 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::23 9 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::24 4 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::25 3 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::26 6 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::27 3 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::28 8 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::29 4 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::30 3 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 162system.physmem.bytesPerActivate::samples 147621 # Bytes accessed per row activation 163system.physmem.bytesPerActivate::mean 294.388468 # Bytes accessed per row activation 164system.physmem.bytesPerActivate::gmean 155.710774 # Bytes accessed per row activation 165system.physmem.bytesPerActivate::stdev 443.499186 # Bytes accessed per row activation 166system.physmem.bytesPerActivate::64 63823 43.23% 43.23% # Bytes accessed per row activation 167system.physmem.bytesPerActivate::128 27954 18.94% 62.17% # Bytes accessed per row activation 168system.physmem.bytesPerActivate::192 12395 8.40% 70.57% # Bytes accessed per row activation 169system.physmem.bytesPerActivate::256 7134 4.83% 75.40% # Bytes accessed per row activation 170system.physmem.bytesPerActivate::320 4845 3.28% 78.68% # Bytes accessed per row activation 171system.physmem.bytesPerActivate::384 3604 2.44% 81.12% # Bytes accessed per row activation 172system.physmem.bytesPerActivate::448 2701 1.83% 82.95% # Bytes accessed per row activation 173system.physmem.bytesPerActivate::512 2191 1.48% 84.44% # Bytes accessed per row activation 174system.physmem.bytesPerActivate::576 1897 1.29% 85.72% # Bytes accessed per row activation 175system.physmem.bytesPerActivate::640 1561 1.06% 86.78% # Bytes accessed per row activation 176system.physmem.bytesPerActivate::704 2008 1.36% 88.14% # Bytes accessed per row activation 177system.physmem.bytesPerActivate::768 1215 0.82% 88.96% # Bytes accessed per row activation 178system.physmem.bytesPerActivate::832 1176 0.80% 89.76% # Bytes accessed per row activation 179system.physmem.bytesPerActivate::896 1069 0.72% 90.48% # Bytes accessed per row activation 180system.physmem.bytesPerActivate::960 885 0.60% 91.08% # Bytes accessed per row activation 181system.physmem.bytesPerActivate::1024 912 0.62% 91.70% # Bytes accessed per row activation 182system.physmem.bytesPerActivate::1088 1043 0.71% 92.41% # Bytes accessed per row activation 183system.physmem.bytesPerActivate::1152 1161 0.79% 93.19% # Bytes accessed per row activation 184system.physmem.bytesPerActivate::1216 1134 0.77% 93.96% # Bytes accessed per row activation 185system.physmem.bytesPerActivate::1280 871 0.59% 94.55% # Bytes accessed per row activation 186system.physmem.bytesPerActivate::1344 771 0.52% 95.07% # Bytes accessed per row activation 187system.physmem.bytesPerActivate::1408 5235 3.55% 98.62% # Bytes accessed per row activation 188system.physmem.bytesPerActivate::1472 297 0.20% 98.82% # Bytes accessed per row activation 189system.physmem.bytesPerActivate::1536 223 0.15% 98.97% # Bytes accessed per row activation 190system.physmem.bytesPerActivate::1600 174 0.12% 99.09% # Bytes accessed per row activation 191system.physmem.bytesPerActivate::1664 140 0.09% 99.19% # Bytes accessed per row activation 192system.physmem.bytesPerActivate::1728 99 0.07% 99.25% # Bytes accessed per row activation 193system.physmem.bytesPerActivate::1792 107 0.07% 99.33% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::1856 67 0.05% 99.37% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::1920 49 0.03% 99.40% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::1984 50 0.03% 99.44% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::2048 49 0.03% 99.47% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::2112 40 0.03% 99.50% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::2176 28 0.02% 99.52% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::2240 31 0.02% 99.54% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::2304 21 0.01% 99.55% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::2368 22 0.01% 99.57% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::2432 31 0.02% 99.59% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::2496 30 0.02% 99.61% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::2560 18 0.01% 99.62% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::2624 24 0.02% 99.64% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::2688 16 0.01% 99.65% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::2752 18 0.01% 99.66% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::2816 20 0.01% 99.67% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::2880 17 0.01% 99.69% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::2944 18 0.01% 99.70% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::3008 17 0.01% 99.71% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::3072 21 0.01% 99.72% # Bytes accessed per row activation 214system.physmem.bytesPerActivate::3136 13 0.01% 99.73% # Bytes accessed per row activation 215system.physmem.bytesPerActivate::3200 13 0.01% 99.74% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::3264 16 0.01% 99.75% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::3328 15 0.01% 99.76% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::3392 9 0.01% 99.77% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::3456 14 0.01% 99.78% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::3520 12 0.01% 99.79% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::3584 17 0.01% 99.80% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::3648 16 0.01% 99.81% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::3712 8 0.01% 99.81% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::3776 10 0.01% 99.82% # Bytes accessed per row activation 225system.physmem.bytesPerActivate::3840 9 0.01% 99.83% # Bytes accessed per row activation 226system.physmem.bytesPerActivate::3904 11 0.01% 99.83% # Bytes accessed per row activation 227system.physmem.bytesPerActivate::3968 6 0.00% 99.84% # Bytes accessed per row activation 228system.physmem.bytesPerActivate::4032 17 0.01% 99.85% # Bytes accessed per row activation 229system.physmem.bytesPerActivate::4096 7 0.00% 99.85% # Bytes accessed per row activation 230system.physmem.bytesPerActivate::4160 17 0.01% 99.87% # Bytes accessed per row activation 231system.physmem.bytesPerActivate::4224 18 0.01% 99.88% # Bytes accessed per row activation 232system.physmem.bytesPerActivate::4288 37 0.03% 99.90% # Bytes accessed per row activation 233system.physmem.bytesPerActivate::4352 5 0.00% 99.91% # Bytes accessed per row activation 234system.physmem.bytesPerActivate::4416 5 0.00% 99.91% # Bytes accessed per row activation 235system.physmem.bytesPerActivate::4480 6 0.00% 99.91% # Bytes accessed per row activation 236system.physmem.bytesPerActivate::4544 5 0.00% 99.92% # Bytes accessed per row activation 237system.physmem.bytesPerActivate::4608 4 0.00% 99.92% # Bytes accessed per row activation 238system.physmem.bytesPerActivate::4672 3 0.00% 99.92% # Bytes accessed per row activation 239system.physmem.bytesPerActivate::4736 4 0.00% 99.92% # Bytes accessed per row activation 240system.physmem.bytesPerActivate::4800 1 0.00% 99.92% # Bytes accessed per row activation 241system.physmem.bytesPerActivate::4864 3 0.00% 99.93% # Bytes accessed per row activation 242system.physmem.bytesPerActivate::4928 5 0.00% 99.93% # Bytes accessed per row activation 243system.physmem.bytesPerActivate::4992 2 0.00% 99.93% # Bytes accessed per row activation 244system.physmem.bytesPerActivate::5056 8 0.01% 99.94% # Bytes accessed per row activation 245system.physmem.bytesPerActivate::5120 4 0.00% 99.94% # Bytes accessed per row activation 246system.physmem.bytesPerActivate::5184 3 0.00% 99.94% # Bytes accessed per row activation 247system.physmem.bytesPerActivate::5248 3 0.00% 99.94% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::5312 6 0.00% 99.95% # Bytes accessed per row activation 249system.physmem.bytesPerActivate::5376 3 0.00% 99.95% # Bytes accessed per row activation 250system.physmem.bytesPerActivate::5440 5 0.00% 99.95% # Bytes accessed per row activation 251system.physmem.bytesPerActivate::5504 5 0.00% 99.96% # Bytes accessed per row activation 252system.physmem.bytesPerActivate::5568 4 0.00% 99.96% # Bytes accessed per row activation 253system.physmem.bytesPerActivate::5632 1 0.00% 99.96% # Bytes accessed per row activation 254system.physmem.bytesPerActivate::5696 4 0.00% 99.96% # Bytes accessed per row activation 255system.physmem.bytesPerActivate::5760 1 0.00% 99.96% # Bytes accessed per row activation 256system.physmem.bytesPerActivate::5824 2 0.00% 99.96% # Bytes accessed per row activation 257system.physmem.bytesPerActivate::5888 6 0.00% 99.97% # Bytes accessed per row activation 258system.physmem.bytesPerActivate::5952 3 0.00% 99.97% # Bytes accessed per row activation 259system.physmem.bytesPerActivate::6016 14 0.01% 99.98% # Bytes accessed per row activation 260system.physmem.bytesPerActivate::6080 3 0.00% 99.98% # Bytes accessed per row activation 261system.physmem.bytesPerActivate::6144 2 0.00% 99.98% # Bytes accessed per row activation 262system.physmem.bytesPerActivate::6272 19 0.01% 100.00% # Bytes accessed per row activation 263system.physmem.bytesPerActivate::6336 3 0.00% 100.00% # Bytes accessed per row activation 264system.physmem.bytesPerActivate::6528 1 0.00% 100.00% # Bytes accessed per row activation 265system.physmem.bytesPerActivate::7552 1 0.00% 100.00% # Bytes accessed per row activation 266system.physmem.bytesPerActivate::total 147621 # Bytes accessed per row activation 267system.physmem.totQLat 3824316500 # Total ticks spent queuing 268system.physmem.totMemAccLat 12085472750 # Total ticks spent from burst creation until serviced by the DRAM 269system.physmem.totBusLat 1927315000 # Total ticks spent in databus transfers 270system.physmem.totBankLat 6333841250 # Total ticks spent accessing banks 271system.physmem.avgQLat 9921.36 # Average queueing delay per DRAM burst 272system.physmem.avgBankLat 16431.77 # Average bank access latency per DRAM burst 273system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 274system.physmem.avgMemAccLat 31353.13 # Average memory access latency per DRAM burst 275system.physmem.avgRdBW 53.71 # Average DRAM read bandwidth in MiByte/s 276system.physmem.avgWrBW 40.90 # Average achieved write bandwidth in MiByte/s 277system.physmem.avgRdBWSys 53.73 # Average system read bandwidth in MiByte/s 278system.physmem.avgWrBWSys 40.90 # Average system write bandwidth in MiByte/s 279system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 280system.physmem.busUtil 0.74 # Data bus utilization in percentage 281system.physmem.busUtilRead 0.42 # Data bus utilization in percentage for reads 282system.physmem.busUtilWrite 0.32 # Data bus utilization in percentage for writes 283system.physmem.avgRdQLen 0.03 # Average read queue length when enqueuing 284system.physmem.avgWrQLen 9.23 # Average write queue length when enqueuing 285system.physmem.readRowHits 326993 # Number of row buffer hits during reads 286system.physmem.writeRowHits 204419 # Number of row buffer hits during writes 287system.physmem.readRowHitRate 84.83 # Row buffer hit rate for reads 288system.physmem.writeRowHitRate 69.63 # Row buffer hit rate for writes 289system.physmem.avgGap 676283.54 # Average gap between requests 290system.physmem.pageHitRate 78.26 # Row buffer hit rate, read and write combined 291system.physmem.prechargeAllPercent 5.85 # Percentage of time for which DRAM has all the banks in precharge state 292system.membus.throughput 94634857 # Throughput (bytes/s) 293system.membus.trans_dist::ReadReq 178796 # Transaction distribution 294system.membus.trans_dist::ReadResp 178796 # Transaction distribution 295system.membus.trans_dist::Writeback 293572 # Transaction distribution 296system.membus.trans_dist::UpgradeReq 135253 # Transaction distribution 297system.membus.trans_dist::UpgradeResp 135253 # Transaction distribution 298system.membus.trans_dist::ReadExReq 206845 # Transaction distribution 299system.membus.trans_dist::ReadExResp 206845 # Transaction distribution 300system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1335360 # Packet count per connected master and slave (bytes) 301system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1335360 # Packet count per connected master and slave (bytes) 302system.membus.pkt_count::total 1335360 # Packet count per connected master and slave (bytes) 303system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43469632 # Cumulative packet size per connected master and slave (bytes) 304system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 43469632 # Cumulative packet size per connected master and slave (bytes) 305system.membus.tot_pkt_size::total 43469632 # Cumulative packet size per connected master and slave (bytes) 306system.membus.data_through_bus 43469632 # Total data (bytes) 307system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 308system.membus.reqLayer0.occupancy 3391724500 # Layer occupancy (ticks) 309system.membus.reqLayer0.utilization 0.7 # Layer utilization (%) 310system.membus.respLayer1.occupancy 3901051256 # Layer occupancy (ticks) 311system.membus.respLayer1.utilization 0.8 # Layer utilization (%) 312system.cpu.branchPred.lookups 205617807 # Number of BP lookups 313system.cpu.branchPred.condPredicted 205617807 # Number of conditional branches predicted 314system.cpu.branchPred.condIncorrect 9908418 # Number of conditional branches incorrect 315system.cpu.branchPred.BTBLookups 117215133 # Number of BTB lookups 316system.cpu.branchPred.BTBHits 114724662 # Number of BTB hits 317system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 318system.cpu.branchPred.BTBHitPct 97.875299 # BTB Hit Percentage 319system.cpu.branchPred.usedRAS 25059559 # Number of times the RAS was used to get a target. 320system.cpu.branchPred.RASInCorrect 1805276 # Number of incorrect RAS predictions. 321system.cpu.workload.num_syscalls 551 # Number of system calls 322system.cpu.numCycles 918840117 # number of cpu cycles simulated 323system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 324system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 325system.cpu.fetch.icacheStallCycles 167454161 # Number of cycles fetch is stalled on an Icache miss 326system.cpu.fetch.Insts 1131890109 # Number of instructions fetch has processed 327system.cpu.fetch.Branches 205617807 # Number of branches that fetch encountered 328system.cpu.fetch.predictedBranches 139784221 # Number of branches that fetch has predicted taken 329system.cpu.fetch.Cycles 352321921 # Number of cycles fetch has run and was not squashing or blocked 330system.cpu.fetch.SquashCycles 71123589 # Number of cycles fetch has spent squashing 331system.cpu.fetch.BlockedCycles 305412308 # Number of cycles fetch has spent blocked 332system.cpu.fetch.MiscStallCycles 47848 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 333system.cpu.fetch.PendingTrapStallCycles 248697 # Number of stall cycles due to pending traps 334system.cpu.fetch.IcacheWaitRetryStallCycles 51 # Number of stall cycles due to full MSHR 335system.cpu.fetch.CacheLines 162055223 # Number of cache lines fetched 336system.cpu.fetch.IcacheSquashes 2523762 # Number of outstanding Icache misses that were squashed 337system.cpu.fetch.rateDist::samples 886447009 # Number of instructions fetched each cycle (Total) 338system.cpu.fetch.rateDist::mean 2.375660 # Number of instructions fetched each cycle (Total) 339system.cpu.fetch.rateDist::stdev 3.323512 # Number of instructions fetched each cycle (Total) 340system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 341system.cpu.fetch.rateDist::0 538196407 60.71% 60.71% # Number of instructions fetched each cycle (Total) 342system.cpu.fetch.rateDist::1 23398337 2.64% 63.35% # Number of instructions fetched each cycle (Total) 343system.cpu.fetch.rateDist::2 25267875 2.85% 66.20% # Number of instructions fetched each cycle (Total) 344system.cpu.fetch.rateDist::3 27893164 3.15% 69.35% # Number of instructions fetched each cycle (Total) 345system.cpu.fetch.rateDist::4 17745237 2.00% 71.35% # Number of instructions fetched each cycle (Total) 346system.cpu.fetch.rateDist::5 22915160 2.59% 73.94% # Number of instructions fetched each cycle (Total) 347system.cpu.fetch.rateDist::6 29437572 3.32% 77.26% # Number of instructions fetched each cycle (Total) 348system.cpu.fetch.rateDist::7 26645476 3.01% 80.26% # Number of instructions fetched each cycle (Total) 349system.cpu.fetch.rateDist::8 174947781 19.74% 100.00% # Number of instructions fetched each cycle (Total) 350system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 351system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 352system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 353system.cpu.fetch.rateDist::total 886447009 # Number of instructions fetched each cycle (Total) 354system.cpu.fetch.branchRate 0.223780 # Number of branch fetches per cycle 355system.cpu.fetch.rate 1.231868 # Number of inst fetches per cycle 356system.cpu.decode.IdleCycles 222604172 # Number of cycles decode is idle 357system.cpu.decode.BlockedCycles 260544811 # Number of cycles decode is blocked 358system.cpu.decode.RunCycles 295377211 # Number of cycles decode is running 359system.cpu.decode.UnblockCycles 46958792 # Number of cycles decode is unblocking 360system.cpu.decode.SquashCycles 60962023 # Number of cycles decode is squashing 361system.cpu.decode.DecodedInsts 2071584997 # Number of instructions handled by decode 362system.cpu.decode.SquashedInsts 1 # Number of squashed instructions handled by decode 363system.cpu.rename.SquashCycles 60962023 # Number of cycles rename is squashing 364system.cpu.rename.IdleCycles 256124443 # Number of cycles rename is idle 365system.cpu.rename.BlockCycles 115849529 # Number of cycles rename is blocking 366system.cpu.rename.serializeStallCycles 18111 # count of cycles rename stalled for serializing inst 367system.cpu.rename.RunCycles 306710232 # Number of cycles rename is running 368system.cpu.rename.UnblockCycles 146782671 # Number of cycles rename is unblocking 369system.cpu.rename.RenamedInsts 2035392094 # Number of instructions processed by rename 370system.cpu.rename.ROBFullEvents 19900 # Number of times rename has blocked due to ROB full 371system.cpu.rename.IQFullEvents 24933273 # Number of times rename has blocked due to IQ full 372system.cpu.rename.LSQFullEvents 106586441 # Number of times rename has blocked due to LSQ full 373system.cpu.rename.RenamedOperands 2138335278 # Number of destination operands rename has renamed 374system.cpu.rename.RenameLookups 5151319538 # Number of register rename lookups that rename has made 375system.cpu.rename.int_rename_lookups 3273897775 # Number of integer rename lookups 376system.cpu.rename.fp_rename_lookups 39701 # Number of floating rename lookups 377system.cpu.rename.CommittedMaps 1614040854 # Number of HB maps that are committed 378system.cpu.rename.UndoneMaps 524294424 # Number of HB maps that are undone due to squashing 379system.cpu.rename.serializingInsts 1242 # count of serializing insts renamed 380system.cpu.rename.tempSerializingInsts 1171 # count of temporary serializing insts renamed 381system.cpu.rename.skidInsts 346564705 # count of insts added to the skid buffer 382system.cpu.memDep0.insertedLoads 495938130 # Number of loads inserted to the mem dependence unit. 383system.cpu.memDep0.insertedStores 194456766 # Number of stores inserted to the mem dependence unit. 384system.cpu.memDep0.conflictingLoads 195343621 # Number of conflicting loads. 385system.cpu.memDep0.conflictingStores 54992684 # Number of conflicting stores. 386system.cpu.iq.iqInstsAdded 1975627132 # Number of instructions added to the IQ (excludes non-spec) 387system.cpu.iq.iqNonSpecInstsAdded 13244 # Number of non-speculative instructions added to the IQ 388system.cpu.iq.iqInstsIssued 1772183771 # Number of instructions issued 389system.cpu.iq.iqSquashedInstsIssued 484863 # Number of squashed instructions issued 390system.cpu.iq.iqSquashedInstsExamined 441729805 # Number of squashed instructions iterated over during squash; mainly for profiling 391system.cpu.iq.iqSquashedOperandsExamined 735457697 # Number of squashed operands that are examined and possibly removed from graph 392system.cpu.iq.iqSquashedNonSpecRemoved 12692 # Number of squashed non-spec instructions that were removed 393system.cpu.iq.issued_per_cycle::samples 886447009 # Number of insts issued each cycle 394system.cpu.iq.issued_per_cycle::mean 1.999199 # Number of insts issued each cycle 395system.cpu.iq.issued_per_cycle::stdev 1.882883 # Number of insts issued each cycle 396system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 397system.cpu.iq.issued_per_cycle::0 269548828 30.41% 30.41% # Number of insts issued each cycle 398system.cpu.iq.issued_per_cycle::1 152175288 17.17% 47.57% # Number of insts issued each cycle 399system.cpu.iq.issued_per_cycle::2 137113127 15.47% 63.04% # Number of insts issued each cycle 400system.cpu.iq.issued_per_cycle::3 132050060 14.90% 77.94% # Number of insts issued each cycle 401system.cpu.iq.issued_per_cycle::4 91550725 10.33% 88.27% # Number of insts issued each cycle 402system.cpu.iq.issued_per_cycle::5 55998430 6.32% 94.58% # Number of insts issued each cycle 403system.cpu.iq.issued_per_cycle::6 34403840 3.88% 98.47% # Number of insts issued each cycle 404system.cpu.iq.issued_per_cycle::7 11839729 1.34% 99.80% # Number of insts issued each cycle 405system.cpu.iq.issued_per_cycle::8 1766982 0.20% 100.00% # Number of insts issued each cycle 406system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 407system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 408system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 409system.cpu.iq.issued_per_cycle::total 886447009 # Number of insts issued each cycle 410system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 411system.cpu.iq.fu_full::IntAlu 4936288 32.45% 32.45% # attempts to use FU when none available 412system.cpu.iq.fu_full::IntMult 0 0.00% 32.45% # attempts to use FU when none available 413system.cpu.iq.fu_full::IntDiv 0 0.00% 32.45% # attempts to use FU when none available 414system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.45% # attempts to use FU when none available 415system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.45% # attempts to use FU when none available 416system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.45% # attempts to use FU when none available 417system.cpu.iq.fu_full::FloatMult 0 0.00% 32.45% # attempts to use FU when none available 418system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.45% # attempts to use FU when none available 419system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.45% # attempts to use FU when none available 420system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.45% # attempts to use FU when none available 421system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.45% # attempts to use FU when none available 422system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.45% # attempts to use FU when none available 423system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.45% # attempts to use FU when none available 424system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.45% # attempts to use FU when none available 425system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.45% # attempts to use FU when none available 426system.cpu.iq.fu_full::SimdMult 0 0.00% 32.45% # attempts to use FU when none available 427system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.45% # attempts to use FU when none available 428system.cpu.iq.fu_full::SimdShift 0 0.00% 32.45% # attempts to use FU when none available 429system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.45% # attempts to use FU when none available 430system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.45% # attempts to use FU when none available 431system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.45% # attempts to use FU when none available 432system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.45% # attempts to use FU when none available 433system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.45% # attempts to use FU when none available 434system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.45% # attempts to use FU when none available 435system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.45% # attempts to use FU when none available 436system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.45% # attempts to use FU when none available 437system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.45% # attempts to use FU when none available 438system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.45% # attempts to use FU when none available 439system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.45% # attempts to use FU when none available 440system.cpu.iq.fu_full::MemRead 7665302 50.39% 82.85% # attempts to use FU when none available 441system.cpu.iq.fu_full::MemWrite 2609145 17.15% 100.00% # attempts to use FU when none available 442system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 443system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 444system.cpu.iq.FU_type_0::No_OpClass 2622898 0.15% 0.15% # Type of FU issued 445system.cpu.iq.FU_type_0::IntAlu 1165798232 65.78% 65.93% # Type of FU issued 446system.cpu.iq.FU_type_0::IntMult 353842 0.02% 65.95% # Type of FU issued 447system.cpu.iq.FU_type_0::IntDiv 3880856 0.22% 66.17% # Type of FU issued 448system.cpu.iq.FU_type_0::FloatAdd 5 0.00% 66.17% # Type of FU issued 449system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.17% # Type of FU issued 450system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.17% # Type of FU issued 451system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.17% # Type of FU issued 452system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.17% # Type of FU issued 453system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.17% # Type of FU issued 454system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.17% # Type of FU issued 455system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.17% # Type of FU issued 456system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.17% # Type of FU issued 457system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.17% # Type of FU issued 458system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.17% # Type of FU issued 459system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.17% # Type of FU issued 460system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.17% # Type of FU issued 461system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.17% # Type of FU issued 462system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.17% # Type of FU issued 463system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.17% # Type of FU issued 464system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.17% # Type of FU issued 465system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.17% # Type of FU issued 466system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.17% # Type of FU issued 467system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.17% # Type of FU issued 468system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.17% # Type of FU issued 469system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.17% # Type of FU issued 470system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.17% # Type of FU issued 471system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.17% # Type of FU issued 472system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.17% # Type of FU issued 473system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.17% # Type of FU issued 474system.cpu.iq.FU_type_0::MemRead 429305841 24.22% 90.39% # Type of FU issued 475system.cpu.iq.FU_type_0::MemWrite 170222097 9.61% 100.00% # Type of FU issued 476system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 477system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 478system.cpu.iq.FU_type_0::total 1772183771 # Type of FU issued 479system.cpu.iq.rate 1.928718 # Inst issue rate 480system.cpu.iq.fu_busy_cnt 15210735 # FU busy when requested 481system.cpu.iq.fu_busy_rate 0.008583 # FU busy rate (busy events/executed inst) 482system.cpu.iq.int_inst_queue_reads 4446495646 # Number of integer instruction queue reads 483system.cpu.iq.int_inst_queue_writes 2417577635 # Number of integer instruction queue writes 484system.cpu.iq.int_inst_queue_wakeup_accesses 1744952561 # Number of integer instruction queue wakeup accesses 485system.cpu.iq.fp_inst_queue_reads 14503 # Number of floating instruction queue reads 486system.cpu.iq.fp_inst_queue_writes 50594 # Number of floating instruction queue writes 487system.cpu.iq.fp_inst_queue_wakeup_accesses 3428 # Number of floating instruction queue wakeup accesses 488system.cpu.iq.int_alu_accesses 1784764794 # Number of integer alu accesses 489system.cpu.iq.fp_alu_accesses 6814 # Number of floating point alu accesses 490system.cpu.iew.lsq.thread0.forwLoads 172654482 # Number of loads that had data forwarded from stores 491system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 492system.cpu.iew.lsq.thread0.squashedLoads 111836934 # Number of loads squashed 493system.cpu.iew.lsq.thread0.ignoredResponses 389891 # Number of memory responses ignored because the instruction is squashed 494system.cpu.iew.lsq.thread0.memOrderViolation 330016 # Number of memory ordering violations 495system.cpu.iew.lsq.thread0.squashedStores 45296580 # Number of stores squashed 496system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 497system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 498system.cpu.iew.lsq.thread0.rescheduledLoads 14646 # Number of loads that were rescheduled 499system.cpu.iew.lsq.thread0.cacheBlocked 570 # Number of times an access to memory failed due to the cache being blocked 500system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 501system.cpu.iew.iewSquashCycles 60962023 # Number of cycles IEW is squashing 502system.cpu.iew.iewBlockCycles 68066484 # Number of cycles IEW is blocking 503system.cpu.iew.iewUnblockCycles 7196875 # Number of cycles IEW is unblocking 504system.cpu.iew.iewDispatchedInsts 1975640376 # Number of instructions dispatched to IQ 505system.cpu.iew.iewDispSquashedInsts 789853 # Number of squashed instructions skipped by dispatch 506system.cpu.iew.iewDispLoadInsts 495939091 # Number of dispatched load instructions 507system.cpu.iew.iewDispStoreInsts 194456766 # Number of dispatched store instructions 508system.cpu.iew.iewDispNonSpecInsts 3282 # Number of dispatched non-speculative instructions 509system.cpu.iew.iewIQFullEvents 4474777 # Number of times the IQ has become full, causing a stall 510system.cpu.iew.iewLSQFullEvents 82775 # Number of times the LSQ has become full, causing a stall 511system.cpu.iew.memOrderViolationEvents 330016 # Number of memory order violations 512system.cpu.iew.predictedTakenIncorrect 5907886 # Number of branches that were predicted taken incorrectly 513system.cpu.iew.predictedNotTakenIncorrect 4422310 # Number of branches that were predicted not taken incorrectly 514system.cpu.iew.branchMispredicts 10330196 # Number of branch mispredicts detected at execute 515system.cpu.iew.iewExecutedInsts 1753064930 # Number of executed instructions 516system.cpu.iew.iewExecLoadInsts 424170565 # Number of load instructions executed 517system.cpu.iew.iewExecSquashedInsts 19118841 # Number of squashed instructions skipped in execute 518system.cpu.iew.exec_swp 0 # number of swp insts executed 519system.cpu.iew.exec_nop 0 # number of nop insts executed 520system.cpu.iew.exec_refs 590955910 # number of memory reference insts executed 521system.cpu.iew.exec_branches 167475793 # Number of branches executed 522system.cpu.iew.exec_stores 166785345 # Number of stores executed 523system.cpu.iew.exec_rate 1.907911 # Inst execution rate 524system.cpu.iew.wb_sent 1749812928 # cumulative count of insts sent to commit 525system.cpu.iew.wb_count 1744955989 # cumulative count of insts written-back 526system.cpu.iew.wb_producers 1325071537 # num instructions producing a value 527system.cpu.iew.wb_consumers 1945900521 # num instructions consuming a value 528system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 529system.cpu.iew.wb_rate 1.899086 # insts written-back per cycle 530system.cpu.iew.wb_fanout 0.680955 # average fanout of values written-back 531system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 532system.cpu.commit.commitSquashedInsts 446680078 # The number of squashed insts skipped by commit 533system.cpu.commit.commitNonSpecStalls 552 # The number of times commit has been forced to stall to communicate backwards 534system.cpu.commit.branchMispredicts 9936737 # The number of times a branch was mispredicted 535system.cpu.commit.committed_per_cycle::samples 825484986 # Number of insts commited each cycle 536system.cpu.commit.committed_per_cycle::mean 1.852231 # Number of insts commited each cycle 537system.cpu.commit.committed_per_cycle::stdev 2.435254 # Number of insts commited each cycle 538system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 539system.cpu.commit.committed_per_cycle::0 333347760 40.38% 40.38% # Number of insts commited each cycle 540system.cpu.commit.committed_per_cycle::1 193315332 23.42% 63.80% # Number of insts commited each cycle 541system.cpu.commit.committed_per_cycle::2 63291763 7.67% 71.47% # Number of insts commited each cycle 542system.cpu.commit.committed_per_cycle::3 92551196 11.21% 82.68% # Number of insts commited each cycle 543system.cpu.commit.committed_per_cycle::4 24974559 3.03% 85.70% # Number of insts commited each cycle 544system.cpu.commit.committed_per_cycle::5 27516320 3.33% 89.04% # Number of insts commited each cycle 545system.cpu.commit.committed_per_cycle::6 9293108 1.13% 90.16% # Number of insts commited each cycle 546system.cpu.commit.committed_per_cycle::7 11361813 1.38% 91.54% # Number of insts commited each cycle 547system.cpu.commit.committed_per_cycle::8 69833135 8.46% 100.00% # Number of insts commited each cycle 548system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 549system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 550system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 551system.cpu.commit.committed_per_cycle::total 825484986 # Number of insts commited each cycle 552system.cpu.commit.committedInsts 826877109 # Number of instructions committed 553system.cpu.commit.committedOps 1528988701 # Number of ops (including micro ops) committed 554system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 555system.cpu.commit.refs 533262343 # Number of memory references committed 556system.cpu.commit.loads 384102157 # Number of loads committed 557system.cpu.commit.membars 0 # Number of memory barriers committed 558system.cpu.commit.branches 149758583 # Number of branches committed 559system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. 560system.cpu.commit.int_insts 1526605509 # Number of committed integer instructions. 561system.cpu.commit.function_calls 17673145 # Number of function calls committed. 562system.cpu.commit.bw_lim_events 69833135 # number cycles where commit BW limit reached 563system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 564system.cpu.rob.rob_reads 2731320630 # The number of ROB reads 565system.cpu.rob.rob_writes 4012461124 # The number of ROB writes 566system.cpu.timesIdled 3340699 # Number of times that the entire CPU went into an idle state and unscheduled itself 567system.cpu.idleCycles 32393108 # Total number of cycles that the CPU has spent unscheduled due to idling 568system.cpu.committedInsts 826877109 # Number of Instructions Simulated 569system.cpu.committedOps 1528988701 # Number of Ops (including micro ops) Simulated 570system.cpu.committedInsts_total 826877109 # Number of Instructions Simulated 571system.cpu.cpi 1.111217 # CPI: Cycles Per Instruction 572system.cpu.cpi_total 1.111217 # CPI: Total CPI of All Threads 573system.cpu.ipc 0.899914 # IPC: Instructions Per Cycle 574system.cpu.ipc_total 0.899914 # IPC: Total IPC of All Threads 575system.cpu.int_regfile_reads 2716389897 # number of integer regfile reads 576system.cpu.int_regfile_writes 1420532102 # number of integer regfile writes 577system.cpu.fp_regfile_reads 3421 # number of floating regfile reads 578system.cpu.fp_regfile_writes 19 # number of floating regfile writes 579system.cpu.cc_regfile_reads 597244921 # number of cc regfile reads 580system.cpu.cc_regfile_writes 405448259 # number of cc regfile writes 581system.cpu.misc_regfile_reads 964724023 # number of misc regfile reads 582system.cpu.misc_regfile_writes 1 # number of misc regfile writes 583system.cpu.toL2Bus.throughput 697845146 # Throughput (bytes/s) 584system.cpu.toL2Bus.trans_dist::ReadReq 1906044 # Transaction distribution 585system.cpu.toL2Bus.trans_dist::ReadResp 1906043 # Transaction distribution 586system.cpu.toL2Bus.trans_dist::Writeback 2330771 # Transaction distribution 587system.cpu.toL2Bus.trans_dist::UpgradeReq 136656 # Transaction distribution 588system.cpu.toL2Bus.trans_dist::UpgradeResp 136656 # Transaction distribution 589system.cpu.toL2Bus.trans_dist::ReadExReq 771758 # Transaction distribution 590system.cpu.toL2Bus.trans_dist::ReadExResp 771758 # Transaction distribution 591system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 150484 # Packet count per connected master and slave (bytes) 592system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7672451 # Packet count per connected master and slave (bytes) 593system.cpu.toL2Bus.pkt_count::total 7822935 # Packet count per connected master and slave (bytes) 594system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 439424 # Cumulative packet size per connected master and slave (bytes) 595system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 311357120 # Cumulative packet size per connected master and slave (bytes) 596system.cpu.toL2Bus.tot_pkt_size::total 311796544 # Cumulative packet size per connected master and slave (bytes) 597system.cpu.toL2Bus.data_through_bus 311796544 # Total data (bytes) 598system.cpu.toL2Bus.snoop_data_through_bus 8752064 # Total snoop data (bytes) 599system.cpu.toL2Bus.reqLayer0.occupancy 4906973310 # Layer occupancy (ticks) 600system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) 601system.cpu.toL2Bus.respLayer0.occupancy 215891495 # Layer occupancy (ticks) 602system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 603system.cpu.toL2Bus.respLayer1.occupancy 3953569925 # Layer occupancy (ticks) 604system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) 605system.cpu.icache.tags.replacements 5335 # number of replacements 606system.cpu.icache.tags.tagsinuse 1037.583647 # Cycle average of tags in use 607system.cpu.icache.tags.total_refs 161907582 # Total number of references to valid blocks. 608system.cpu.icache.tags.sampled_refs 6916 # Sample count of references to valid blocks. 609system.cpu.icache.tags.avg_refs 23410.581550 # Average number of references to valid blocks. 610system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 611system.cpu.icache.tags.occ_blocks::cpu.inst 1037.583647 # Average occupied blocks per requestor 612system.cpu.icache.tags.occ_percent::cpu.inst 0.506633 # Average percentage of cache occupancy 613system.cpu.icache.tags.occ_percent::total 0.506633 # Average percentage of cache occupancy 614system.cpu.icache.ReadReq_hits::cpu.inst 161909622 # number of ReadReq hits 615system.cpu.icache.ReadReq_hits::total 161909622 # number of ReadReq hits 616system.cpu.icache.demand_hits::cpu.inst 161909622 # number of demand (read+write) hits 617system.cpu.icache.demand_hits::total 161909622 # number of demand (read+write) hits 618system.cpu.icache.overall_hits::cpu.inst 161909622 # number of overall hits 619system.cpu.icache.overall_hits::total 161909622 # number of overall hits 620system.cpu.icache.ReadReq_misses::cpu.inst 145600 # number of ReadReq misses 621system.cpu.icache.ReadReq_misses::total 145600 # number of ReadReq misses 622system.cpu.icache.demand_misses::cpu.inst 145600 # number of demand (read+write) misses 623system.cpu.icache.demand_misses::total 145600 # number of demand (read+write) misses 624system.cpu.icache.overall_misses::cpu.inst 145600 # number of overall misses 625system.cpu.icache.overall_misses::total 145600 # number of overall misses 626system.cpu.icache.ReadReq_miss_latency::cpu.inst 941474740 # number of ReadReq miss cycles 627system.cpu.icache.ReadReq_miss_latency::total 941474740 # number of ReadReq miss cycles 628system.cpu.icache.demand_miss_latency::cpu.inst 941474740 # number of demand (read+write) miss cycles 629system.cpu.icache.demand_miss_latency::total 941474740 # number of demand (read+write) miss cycles 630system.cpu.icache.overall_miss_latency::cpu.inst 941474740 # number of overall miss cycles 631system.cpu.icache.overall_miss_latency::total 941474740 # number of overall miss cycles 632system.cpu.icache.ReadReq_accesses::cpu.inst 162055222 # number of ReadReq accesses(hits+misses) 633system.cpu.icache.ReadReq_accesses::total 162055222 # number of ReadReq accesses(hits+misses) 634system.cpu.icache.demand_accesses::cpu.inst 162055222 # number of demand (read+write) accesses 635system.cpu.icache.demand_accesses::total 162055222 # number of demand (read+write) accesses 636system.cpu.icache.overall_accesses::cpu.inst 162055222 # number of overall (read+write) accesses 637system.cpu.icache.overall_accesses::total 162055222 # number of overall (read+write) accesses 638system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000898 # miss rate for ReadReq accesses 639system.cpu.icache.ReadReq_miss_rate::total 0.000898 # miss rate for ReadReq accesses 640system.cpu.icache.demand_miss_rate::cpu.inst 0.000898 # miss rate for demand accesses 641system.cpu.icache.demand_miss_rate::total 0.000898 # miss rate for demand accesses 642system.cpu.icache.overall_miss_rate::cpu.inst 0.000898 # miss rate for overall accesses 643system.cpu.icache.overall_miss_rate::total 0.000898 # miss rate for overall accesses 644system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6466.172665 # average ReadReq miss latency 645system.cpu.icache.ReadReq_avg_miss_latency::total 6466.172665 # average ReadReq miss latency 646system.cpu.icache.demand_avg_miss_latency::cpu.inst 6466.172665 # average overall miss latency 647system.cpu.icache.demand_avg_miss_latency::total 6466.172665 # average overall miss latency 648system.cpu.icache.overall_avg_miss_latency::cpu.inst 6466.172665 # average overall miss latency 649system.cpu.icache.overall_avg_miss_latency::total 6466.172665 # average overall miss latency 650system.cpu.icache.blocked_cycles::no_mshrs 250 # number of cycles access was blocked 651system.cpu.icache.blocked_cycles::no_targets 170 # number of cycles access was blocked 652system.cpu.icache.blocked::no_mshrs 6 # number of cycles access was blocked 653system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked 654system.cpu.icache.avg_blocked_cycles::no_mshrs 41.666667 # average number of cycles each access was blocked 655system.cpu.icache.avg_blocked_cycles::no_targets 170 # average number of cycles each access was blocked 656system.cpu.icache.fast_writes 0 # number of fast writes performed 657system.cpu.icache.cache_copies 0 # number of cache copies performed 658system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1982 # number of ReadReq MSHR hits 659system.cpu.icache.ReadReq_mshr_hits::total 1982 # number of ReadReq MSHR hits 660system.cpu.icache.demand_mshr_hits::cpu.inst 1982 # number of demand (read+write) MSHR hits 661system.cpu.icache.demand_mshr_hits::total 1982 # number of demand (read+write) MSHR hits 662system.cpu.icache.overall_mshr_hits::cpu.inst 1982 # number of overall MSHR hits 663system.cpu.icache.overall_mshr_hits::total 1982 # number of overall MSHR hits 664system.cpu.icache.ReadReq_mshr_misses::cpu.inst 143618 # number of ReadReq MSHR misses 665system.cpu.icache.ReadReq_mshr_misses::total 143618 # number of ReadReq MSHR misses 666system.cpu.icache.demand_mshr_misses::cpu.inst 143618 # number of demand (read+write) MSHR misses 667system.cpu.icache.demand_mshr_misses::total 143618 # number of demand (read+write) MSHR misses 668system.cpu.icache.overall_mshr_misses::cpu.inst 143618 # number of overall MSHR misses 669system.cpu.icache.overall_mshr_misses::total 143618 # number of overall MSHR misses 670system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 562974254 # number of ReadReq MSHR miss cycles 671system.cpu.icache.ReadReq_mshr_miss_latency::total 562974254 # number of ReadReq MSHR miss cycles 672system.cpu.icache.demand_mshr_miss_latency::cpu.inst 562974254 # number of demand (read+write) MSHR miss cycles 673system.cpu.icache.demand_mshr_miss_latency::total 562974254 # number of demand (read+write) MSHR miss cycles 674system.cpu.icache.overall_mshr_miss_latency::cpu.inst 562974254 # number of overall MSHR miss cycles 675system.cpu.icache.overall_mshr_miss_latency::total 562974254 # number of overall MSHR miss cycles 676system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000886 # mshr miss rate for ReadReq accesses 677system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000886 # mshr miss rate for ReadReq accesses 678system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000886 # mshr miss rate for demand accesses 679system.cpu.icache.demand_mshr_miss_rate::total 0.000886 # mshr miss rate for demand accesses 680system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000886 # mshr miss rate for overall accesses 681system.cpu.icache.overall_mshr_miss_rate::total 0.000886 # mshr miss rate for overall accesses 682system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 3919.942166 # average ReadReq mshr miss latency 683system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 3919.942166 # average ReadReq mshr miss latency 684system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 3919.942166 # average overall mshr miss latency 685system.cpu.icache.demand_avg_mshr_miss_latency::total 3919.942166 # average overall mshr miss latency 686system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 3919.942166 # average overall mshr miss latency 687system.cpu.icache.overall_avg_mshr_miss_latency::total 3919.942166 # average overall mshr miss latency 688system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 689system.cpu.l2cache.tags.replacements 352959 # number of replacements 690system.cpu.l2cache.tags.tagsinuse 29669.713018 # Cycle average of tags in use 691system.cpu.l2cache.tags.total_refs 3697218 # Total number of references to valid blocks. 692system.cpu.l2cache.tags.sampled_refs 385325 # Sample count of references to valid blocks. 693system.cpu.l2cache.tags.avg_refs 9.595064 # Average number of references to valid blocks. 694system.cpu.l2cache.tags.warmup_cycle 199249645000 # Cycle when the warmup percentage was hit. 695system.cpu.l2cache.tags.occ_blocks::writebacks 21121.996968 # Average occupied blocks per requestor 696system.cpu.l2cache.tags.occ_blocks::cpu.inst 224.213504 # Average occupied blocks per requestor 697system.cpu.l2cache.tags.occ_blocks::cpu.data 8323.502546 # Average occupied blocks per requestor 698system.cpu.l2cache.tags.occ_percent::writebacks 0.644592 # Average percentage of cache occupancy 699system.cpu.l2cache.tags.occ_percent::cpu.inst 0.006842 # Average percentage of cache occupancy 700system.cpu.l2cache.tags.occ_percent::cpu.data 0.254013 # Average percentage of cache occupancy 701system.cpu.l2cache.tags.occ_percent::total 0.905448 # Average percentage of cache occupancy 702system.cpu.l2cache.ReadReq_hits::cpu.inst 3694 # number of ReadReq hits 703system.cpu.l2cache.ReadReq_hits::cpu.data 1586802 # number of ReadReq hits 704system.cpu.l2cache.ReadReq_hits::total 1590496 # number of ReadReq hits 705system.cpu.l2cache.Writeback_hits::writebacks 2330771 # number of Writeback hits 706system.cpu.l2cache.Writeback_hits::total 2330771 # number of Writeback hits 707system.cpu.l2cache.UpgradeReq_hits::cpu.data 1427 # number of UpgradeReq hits 708system.cpu.l2cache.UpgradeReq_hits::total 1427 # number of UpgradeReq hits 709system.cpu.l2cache.ReadExReq_hits::cpu.data 564889 # number of ReadExReq hits 710system.cpu.l2cache.ReadExReq_hits::total 564889 # number of ReadExReq hits 711system.cpu.l2cache.demand_hits::cpu.inst 3694 # number of demand (read+write) hits 712system.cpu.l2cache.demand_hits::cpu.data 2151691 # number of demand (read+write) hits 713system.cpu.l2cache.demand_hits::total 2155385 # number of demand (read+write) hits 714system.cpu.l2cache.overall_hits::cpu.inst 3694 # number of overall hits 715system.cpu.l2cache.overall_hits::cpu.data 2151691 # number of overall hits 716system.cpu.l2cache.overall_hits::total 2155385 # number of overall hits 717system.cpu.l2cache.ReadReq_misses::cpu.inst 3173 # number of ReadReq misses 718system.cpu.l2cache.ReadReq_misses::cpu.data 175624 # number of ReadReq misses 719system.cpu.l2cache.ReadReq_misses::total 178797 # number of ReadReq misses 720system.cpu.l2cache.UpgradeReq_misses::cpu.data 135229 # number of UpgradeReq misses 721system.cpu.l2cache.UpgradeReq_misses::total 135229 # number of UpgradeReq misses 722system.cpu.l2cache.ReadExReq_misses::cpu.data 206869 # number of ReadExReq misses 723system.cpu.l2cache.ReadExReq_misses::total 206869 # number of ReadExReq misses 724system.cpu.l2cache.demand_misses::cpu.inst 3173 # number of demand (read+write) misses 725system.cpu.l2cache.demand_misses::cpu.data 382493 # number of demand (read+write) misses 726system.cpu.l2cache.demand_misses::total 385666 # number of demand (read+write) misses 727system.cpu.l2cache.overall_misses::cpu.inst 3173 # number of overall misses 728system.cpu.l2cache.overall_misses::cpu.data 382493 # number of overall misses 729system.cpu.l2cache.overall_misses::total 385666 # number of overall misses 730system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 242389500 # number of ReadReq miss cycles 731system.cpu.l2cache.ReadReq_miss_latency::cpu.data 13196439955 # number of ReadReq miss cycles 732system.cpu.l2cache.ReadReq_miss_latency::total 13438829455 # number of ReadReq miss cycles 733system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 6577717 # number of UpgradeReq miss cycles 734system.cpu.l2cache.UpgradeReq_miss_latency::total 6577717 # number of UpgradeReq miss cycles 735system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 15144418976 # number of ReadExReq miss cycles 736system.cpu.l2cache.ReadExReq_miss_latency::total 15144418976 # number of ReadExReq miss cycles 737system.cpu.l2cache.demand_miss_latency::cpu.inst 242389500 # number of demand (read+write) miss cycles 738system.cpu.l2cache.demand_miss_latency::cpu.data 28340858931 # number of demand (read+write) miss cycles 739system.cpu.l2cache.demand_miss_latency::total 28583248431 # number of demand (read+write) miss cycles 740system.cpu.l2cache.overall_miss_latency::cpu.inst 242389500 # number of overall miss cycles 741system.cpu.l2cache.overall_miss_latency::cpu.data 28340858931 # number of overall miss cycles 742system.cpu.l2cache.overall_miss_latency::total 28583248431 # number of overall miss cycles 743system.cpu.l2cache.ReadReq_accesses::cpu.inst 6867 # number of ReadReq accesses(hits+misses) 744system.cpu.l2cache.ReadReq_accesses::cpu.data 1762426 # number of ReadReq accesses(hits+misses) 745system.cpu.l2cache.ReadReq_accesses::total 1769293 # number of ReadReq accesses(hits+misses) 746system.cpu.l2cache.Writeback_accesses::writebacks 2330771 # number of Writeback accesses(hits+misses) 747system.cpu.l2cache.Writeback_accesses::total 2330771 # number of Writeback accesses(hits+misses) 748system.cpu.l2cache.UpgradeReq_accesses::cpu.data 136656 # number of UpgradeReq accesses(hits+misses) 749system.cpu.l2cache.UpgradeReq_accesses::total 136656 # number of UpgradeReq accesses(hits+misses) 750system.cpu.l2cache.ReadExReq_accesses::cpu.data 771758 # number of ReadExReq accesses(hits+misses) 751system.cpu.l2cache.ReadExReq_accesses::total 771758 # number of ReadExReq accesses(hits+misses) 752system.cpu.l2cache.demand_accesses::cpu.inst 6867 # number of demand (read+write) accesses 753system.cpu.l2cache.demand_accesses::cpu.data 2534184 # number of demand (read+write) accesses 754system.cpu.l2cache.demand_accesses::total 2541051 # number of demand (read+write) accesses 755system.cpu.l2cache.overall_accesses::cpu.inst 6867 # number of overall (read+write) accesses 756system.cpu.l2cache.overall_accesses::cpu.data 2534184 # number of overall (read+write) accesses 757system.cpu.l2cache.overall_accesses::total 2541051 # number of overall (read+write) accesses 758system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.462065 # miss rate for ReadReq accesses 759system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.099649 # miss rate for ReadReq accesses 760system.cpu.l2cache.ReadReq_miss_rate::total 0.101056 # miss rate for ReadReq accesses 761system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.989558 # miss rate for UpgradeReq accesses 762system.cpu.l2cache.UpgradeReq_miss_rate::total 0.989558 # miss rate for UpgradeReq accesses 763system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.268049 # miss rate for ReadExReq accesses 764system.cpu.l2cache.ReadExReq_miss_rate::total 0.268049 # miss rate for ReadExReq accesses 765system.cpu.l2cache.demand_miss_rate::cpu.inst 0.462065 # miss rate for demand accesses 766system.cpu.l2cache.demand_miss_rate::cpu.data 0.150933 # miss rate for demand accesses 767system.cpu.l2cache.demand_miss_rate::total 0.151774 # miss rate for demand accesses 768system.cpu.l2cache.overall_miss_rate::cpu.inst 0.462065 # miss rate for overall accesses 769system.cpu.l2cache.overall_miss_rate::cpu.data 0.150933 # miss rate for overall accesses 770system.cpu.l2cache.overall_miss_rate::total 0.151774 # miss rate for overall accesses 771system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76391.270091 # average ReadReq miss latency 772system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75140.299475 # average ReadReq miss latency 773system.cpu.l2cache.ReadReq_avg_miss_latency::total 75162.499678 # average ReadReq miss latency 774system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 48.641320 # average UpgradeReq miss latency 775system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 48.641320 # average UpgradeReq miss latency 776system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73207.773886 # average ReadExReq miss latency 777system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73207.773886 # average ReadExReq miss latency 778system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76391.270091 # average overall miss latency 779system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74095.104828 # average overall miss latency 780system.cpu.l2cache.demand_avg_miss_latency::total 74113.996129 # average overall miss latency 781system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76391.270091 # average overall miss latency 782system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74095.104828 # average overall miss latency 783system.cpu.l2cache.overall_avg_miss_latency::total 74113.996129 # average overall miss latency 784system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 785system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 786system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 787system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 788system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 789system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 790system.cpu.l2cache.fast_writes 0 # number of fast writes performed 791system.cpu.l2cache.cache_copies 0 # number of cache copies performed 792system.cpu.l2cache.writebacks::writebacks 293572 # number of writebacks 793system.cpu.l2cache.writebacks::total 293572 # number of writebacks 794system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3173 # number of ReadReq MSHR misses 795system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 175624 # number of ReadReq MSHR misses 796system.cpu.l2cache.ReadReq_mshr_misses::total 178797 # number of ReadReq MSHR misses 797system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 135229 # number of UpgradeReq MSHR misses 798system.cpu.l2cache.UpgradeReq_mshr_misses::total 135229 # number of UpgradeReq MSHR misses 799system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206869 # number of ReadExReq MSHR misses 800system.cpu.l2cache.ReadExReq_mshr_misses::total 206869 # number of ReadExReq MSHR misses 801system.cpu.l2cache.demand_mshr_misses::cpu.inst 3173 # number of demand (read+write) MSHR misses 802system.cpu.l2cache.demand_mshr_misses::cpu.data 382493 # number of demand (read+write) MSHR misses 803system.cpu.l2cache.demand_mshr_misses::total 385666 # number of demand (read+write) MSHR misses 804system.cpu.l2cache.overall_mshr_misses::cpu.inst 3173 # number of overall MSHR misses 805system.cpu.l2cache.overall_mshr_misses::cpu.data 382493 # number of overall MSHR misses 806system.cpu.l2cache.overall_mshr_misses::total 385666 # number of overall MSHR misses 807system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 202707000 # number of ReadReq MSHR miss cycles 808system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 10956266955 # number of ReadReq MSHR miss cycles 809system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11158973955 # number of ReadReq MSHR miss cycles 810system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1356015260 # number of UpgradeReq MSHR miss cycles 811system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1356015260 # number of UpgradeReq MSHR miss cycles 812system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 12518797024 # number of ReadExReq MSHR miss cycles 813system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 12518797024 # number of ReadExReq MSHR miss cycles 814system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 202707000 # number of demand (read+write) MSHR miss cycles 815system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 23475063979 # number of demand (read+write) MSHR miss cycles 816system.cpu.l2cache.demand_mshr_miss_latency::total 23677770979 # number of demand (read+write) MSHR miss cycles 817system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 202707000 # number of overall MSHR miss cycles 818system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 23475063979 # number of overall MSHR miss cycles 819system.cpu.l2cache.overall_mshr_miss_latency::total 23677770979 # number of overall MSHR miss cycles 820system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.462065 # mshr miss rate for ReadReq accesses 821system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.099649 # mshr miss rate for ReadReq accesses 822system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.101056 # mshr miss rate for ReadReq accesses 823system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.989558 # mshr miss rate for UpgradeReq accesses 824system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.989558 # mshr miss rate for UpgradeReq accesses 825system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.268049 # mshr miss rate for ReadExReq accesses 826system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.268049 # mshr miss rate for ReadExReq accesses 827system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.462065 # mshr miss rate for demand accesses 828system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.150933 # mshr miss rate for demand accesses 829system.cpu.l2cache.demand_mshr_miss_rate::total 0.151774 # mshr miss rate for demand accesses 830system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.462065 # mshr miss rate for overall accesses 831system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.150933 # mshr miss rate for overall accesses 832system.cpu.l2cache.overall_mshr_miss_rate::total 0.151774 # mshr miss rate for overall accesses 833system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63884.966908 # average ReadReq mshr miss latency 834system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62384.793394 # average ReadReq mshr miss latency 835system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62411.416047 # average ReadReq mshr miss latency 836system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10027.547789 # average UpgradeReq mshr miss latency 837system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10027.547789 # average UpgradeReq mshr miss latency 838system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60515.577607 # average ReadExReq mshr miss latency 839system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60515.577607 # average ReadExReq mshr miss latency 840system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63884.966908 # average overall mshr miss latency 841system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61373.839466 # average overall mshr miss latency 842system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61394.499331 # average overall mshr miss latency 843system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63884.966908 # average overall mshr miss latency 844system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61373.839466 # average overall mshr miss latency 845system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61394.499331 # average overall mshr miss latency 846system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 847system.cpu.dcache.tags.replacements 2530088 # number of replacements 848system.cpu.dcache.tags.tagsinuse 4088.247279 # Cycle average of tags in use 849system.cpu.dcache.tags.total_refs 395994774 # Total number of references to valid blocks. 850system.cpu.dcache.tags.sampled_refs 2534184 # Sample count of references to valid blocks. 851system.cpu.dcache.tags.avg_refs 156.261256 # Average number of references to valid blocks. 852system.cpu.dcache.tags.warmup_cycle 1794365000 # Cycle when the warmup percentage was hit. 853system.cpu.dcache.tags.occ_blocks::cpu.data 4088.247279 # Average occupied blocks per requestor 854system.cpu.dcache.tags.occ_percent::cpu.data 0.998107 # Average percentage of cache occupancy 855system.cpu.dcache.tags.occ_percent::total 0.998107 # Average percentage of cache occupancy 856system.cpu.dcache.ReadReq_hits::cpu.data 247245006 # number of ReadReq hits 857system.cpu.dcache.ReadReq_hits::total 247245006 # number of ReadReq hits 858system.cpu.dcache.WriteReq_hits::cpu.data 148235012 # number of WriteReq hits 859system.cpu.dcache.WriteReq_hits::total 148235012 # number of WriteReq hits 860system.cpu.dcache.demand_hits::cpu.data 395480018 # number of demand (read+write) hits 861system.cpu.dcache.demand_hits::total 395480018 # number of demand (read+write) hits 862system.cpu.dcache.overall_hits::cpu.data 395480018 # number of overall hits 863system.cpu.dcache.overall_hits::total 395480018 # number of overall hits 864system.cpu.dcache.ReadReq_misses::cpu.data 2882280 # number of ReadReq misses 865system.cpu.dcache.ReadReq_misses::total 2882280 # number of ReadReq misses 866system.cpu.dcache.WriteReq_misses::cpu.data 925190 # number of WriteReq misses 867system.cpu.dcache.WriteReq_misses::total 925190 # number of WriteReq misses 868system.cpu.dcache.demand_misses::cpu.data 3807470 # number of demand (read+write) misses 869system.cpu.dcache.demand_misses::total 3807470 # number of demand (read+write) misses 870system.cpu.dcache.overall_misses::cpu.data 3807470 # number of overall misses 871system.cpu.dcache.overall_misses::total 3807470 # number of overall misses 872system.cpu.dcache.ReadReq_miss_latency::cpu.data 58083545125 # number of ReadReq miss cycles 873system.cpu.dcache.ReadReq_miss_latency::total 58083545125 # number of ReadReq miss cycles 874system.cpu.dcache.WriteReq_miss_latency::cpu.data 26852968678 # number of WriteReq miss cycles 875system.cpu.dcache.WriteReq_miss_latency::total 26852968678 # number of WriteReq miss cycles 876system.cpu.dcache.demand_miss_latency::cpu.data 84936513803 # number of demand (read+write) miss cycles 877system.cpu.dcache.demand_miss_latency::total 84936513803 # number of demand (read+write) miss cycles 878system.cpu.dcache.overall_miss_latency::cpu.data 84936513803 # number of overall miss cycles 879system.cpu.dcache.overall_miss_latency::total 84936513803 # number of overall miss cycles 880system.cpu.dcache.ReadReq_accesses::cpu.data 250127286 # number of ReadReq accesses(hits+misses) 881system.cpu.dcache.ReadReq_accesses::total 250127286 # number of ReadReq accesses(hits+misses) 882system.cpu.dcache.WriteReq_accesses::cpu.data 149160202 # number of WriteReq accesses(hits+misses) 883system.cpu.dcache.WriteReq_accesses::total 149160202 # number of WriteReq accesses(hits+misses) 884system.cpu.dcache.demand_accesses::cpu.data 399287488 # number of demand (read+write) accesses 885system.cpu.dcache.demand_accesses::total 399287488 # number of demand (read+write) accesses 886system.cpu.dcache.overall_accesses::cpu.data 399287488 # number of overall (read+write) accesses 887system.cpu.dcache.overall_accesses::total 399287488 # number of overall (read+write) accesses 888system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011523 # miss rate for ReadReq accesses 889system.cpu.dcache.ReadReq_miss_rate::total 0.011523 # miss rate for ReadReq accesses 890system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006203 # miss rate for WriteReq accesses 891system.cpu.dcache.WriteReq_miss_rate::total 0.006203 # miss rate for WriteReq accesses 892system.cpu.dcache.demand_miss_rate::cpu.data 0.009536 # miss rate for demand accesses 893system.cpu.dcache.demand_miss_rate::total 0.009536 # miss rate for demand accesses 894system.cpu.dcache.overall_miss_rate::cpu.data 0.009536 # miss rate for overall accesses 895system.cpu.dcache.overall_miss_rate::total 0.009536 # miss rate for overall accesses 896system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20151.943991 # average ReadReq miss latency 897system.cpu.dcache.ReadReq_avg_miss_latency::total 20151.943991 # average ReadReq miss latency 898system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29024.274666 # average WriteReq miss latency 899system.cpu.dcache.WriteReq_avg_miss_latency::total 29024.274666 # average WriteReq miss latency 900system.cpu.dcache.demand_avg_miss_latency::cpu.data 22307.861599 # average overall miss latency 901system.cpu.dcache.demand_avg_miss_latency::total 22307.861599 # average overall miss latency 902system.cpu.dcache.overall_avg_miss_latency::cpu.data 22307.861599 # average overall miss latency 903system.cpu.dcache.overall_avg_miss_latency::total 22307.861599 # average overall miss latency 904system.cpu.dcache.blocked_cycles::no_mshrs 5821 # number of cycles access was blocked 905system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 906system.cpu.dcache.blocked::no_mshrs 669 # number of cycles access was blocked 907system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 908system.cpu.dcache.avg_blocked_cycles::no_mshrs 8.701046 # average number of cycles each access was blocked 909system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 910system.cpu.dcache.fast_writes 0 # number of fast writes performed 911system.cpu.dcache.cache_copies 0 # number of cache copies performed 912system.cpu.dcache.writebacks::writebacks 2330771 # number of writebacks 913system.cpu.dcache.writebacks::total 2330771 # number of writebacks 914system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1119584 # number of ReadReq MSHR hits 915system.cpu.dcache.ReadReq_mshr_hits::total 1119584 # number of ReadReq MSHR hits 916system.cpu.dcache.WriteReq_mshr_hits::cpu.data 17046 # number of WriteReq MSHR hits 917system.cpu.dcache.WriteReq_mshr_hits::total 17046 # number of WriteReq MSHR hits 918system.cpu.dcache.demand_mshr_hits::cpu.data 1136630 # number of demand (read+write) MSHR hits 919system.cpu.dcache.demand_mshr_hits::total 1136630 # number of demand (read+write) MSHR hits 920system.cpu.dcache.overall_mshr_hits::cpu.data 1136630 # number of overall MSHR hits 921system.cpu.dcache.overall_mshr_hits::total 1136630 # number of overall MSHR hits 922system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1762696 # number of ReadReq MSHR misses 923system.cpu.dcache.ReadReq_mshr_misses::total 1762696 # number of ReadReq MSHR misses 924system.cpu.dcache.WriteReq_mshr_misses::cpu.data 908144 # number of WriteReq MSHR misses 925system.cpu.dcache.WriteReq_mshr_misses::total 908144 # number of WriteReq MSHR misses 926system.cpu.dcache.demand_mshr_misses::cpu.data 2670840 # number of demand (read+write) MSHR misses 927system.cpu.dcache.demand_mshr_misses::total 2670840 # number of demand (read+write) MSHR misses 928system.cpu.dcache.overall_mshr_misses::cpu.data 2670840 # number of overall MSHR misses 929system.cpu.dcache.overall_mshr_misses::total 2670840 # number of overall MSHR misses 930system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 30862153254 # number of ReadReq MSHR miss cycles 931system.cpu.dcache.ReadReq_mshr_miss_latency::total 30862153254 # number of ReadReq MSHR miss cycles 932system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 24727931821 # number of WriteReq MSHR miss cycles 933system.cpu.dcache.WriteReq_mshr_miss_latency::total 24727931821 # number of WriteReq MSHR miss cycles 934system.cpu.dcache.demand_mshr_miss_latency::cpu.data 55590085075 # number of demand (read+write) MSHR miss cycles 935system.cpu.dcache.demand_mshr_miss_latency::total 55590085075 # number of demand (read+write) MSHR miss cycles 936system.cpu.dcache.overall_mshr_miss_latency::cpu.data 55590085075 # number of overall MSHR miss cycles 937system.cpu.dcache.overall_mshr_miss_latency::total 55590085075 # number of overall MSHR miss cycles 938system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007047 # mshr miss rate for ReadReq accesses 939system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007047 # mshr miss rate for ReadReq accesses 940system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006088 # mshr miss rate for WriteReq accesses 941system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006088 # mshr miss rate for WriteReq accesses 942system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006689 # mshr miss rate for demand accesses 943system.cpu.dcache.demand_mshr_miss_rate::total 0.006689 # mshr miss rate for demand accesses 944system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006689 # mshr miss rate for overall accesses 945system.cpu.dcache.overall_mshr_miss_rate::total 0.006689 # mshr miss rate for overall accesses 946system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17508.494519 # average ReadReq mshr miss latency 947system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17508.494519 # average ReadReq mshr miss latency 948system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27229.086820 # average WriteReq mshr miss latency 949system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27229.086820 # average WriteReq mshr miss latency 950system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20813.708449 # average overall mshr miss latency 951system.cpu.dcache.demand_avg_mshr_miss_latency::total 20813.708449 # average overall mshr miss latency 952system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20813.708449 # average overall mshr miss latency 953system.cpu.dcache.overall_avg_mshr_miss_latency::total 20813.708449 # average overall mshr miss latency 954system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 955 956---------- End Simulation Statistics ---------- 957