stats.txt revision 9289:a31a1243a3ed
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.427481 # Number of seconds simulated 4sim_ticks 427481054500 # Number of ticks simulated 5final_tick 427481054500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 86006 # Simulator instruction rate (inst/s) 8host_op_rate 159036 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 44463827 # Simulator tick rate (ticks/s) 10host_mem_usage 261156 # Number of bytes of host memory used 11host_seconds 9614.13 # Real time elapsed on the host 12sim_insts 826877109 # Number of instructions simulated 13sim_ops 1528988699 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 222080 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 27608960 # Number of bytes read from this memory 16system.physmem.bytes_read::total 27831040 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 222080 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 222080 # Number of instructions bytes read from this memory 19system.physmem.bytes_written::writebacks 20798528 # Number of bytes written to this memory 20system.physmem.bytes_written::total 20798528 # Number of bytes written to this memory 21system.physmem.num_reads::cpu.inst 3470 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 431390 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 434860 # Number of read requests responded to by this memory 24system.physmem.num_writes::writebacks 324977 # Number of write requests responded to by this memory 25system.physmem.num_writes::total 324977 # Number of write requests responded to by this memory 26system.physmem.bw_read::cpu.inst 519508 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::cpu.data 64585225 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_read::total 65104733 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::cpu.inst 519508 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_inst_read::total 519508 # Instruction read bandwidth from this memory (bytes/s) 31system.physmem.bw_write::writebacks 48653684 # Write bandwidth from this memory (bytes/s) 32system.physmem.bw_write::total 48653684 # Write bandwidth from this memory (bytes/s) 33system.physmem.bw_total::writebacks 48653684 # Total bandwidth to/from this memory (bytes/s) 34system.physmem.bw_total::cpu.inst 519508 # Total bandwidth to/from this memory (bytes/s) 35system.physmem.bw_total::cpu.data 64585225 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::total 113758417 # Total bandwidth to/from this memory (bytes/s) 37system.cpu.workload.num_syscalls 551 # Number of system calls 38system.cpu.numCycles 854962110 # number of cpu cycles simulated 39system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 40system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 41system.cpu.BPredUnit.lookups 221542687 # Number of BP lookups 42system.cpu.BPredUnit.condPredicted 221542687 # Number of conditional branches predicted 43system.cpu.BPredUnit.condIncorrect 14424166 # Number of conditional branches incorrect 44system.cpu.BPredUnit.BTBLookups 156350035 # Number of BTB lookups 45system.cpu.BPredUnit.BTBHits 152734220 # Number of BTB hits 46system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 47system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. 48system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. 49system.cpu.fetch.icacheStallCycles 186980274 # Number of cycles fetch is stalled on an Icache miss 50system.cpu.fetch.Insts 1231567115 # Number of instructions fetch has processed 51system.cpu.fetch.Branches 221542687 # Number of branches that fetch encountered 52system.cpu.fetch.predictedBranches 152734220 # Number of branches that fetch has predicted taken 53system.cpu.fetch.Cycles 382634785 # Number of cycles fetch has run and was not squashing or blocked 54system.cpu.fetch.SquashCycles 91865959 # Number of cycles fetch has spent squashing 55system.cpu.fetch.BlockedCycles 200356865 # Number of cycles fetch has spent blocked 56system.cpu.fetch.MiscStallCycles 29611 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 57system.cpu.fetch.PendingTrapStallCycles 292723 # Number of stall cycles due to pending traps 58system.cpu.fetch.CacheLines 179385748 # Number of cache lines fetched 59system.cpu.fetch.IcacheSquashes 4126859 # Number of outstanding Icache misses that were squashed 60system.cpu.fetch.rateDist::samples 847490245 # Number of instructions fetched each cycle (Total) 61system.cpu.fetch.rateDist::mean 2.698073 # Number of instructions fetched each cycle (Total) 62system.cpu.fetch.rateDist::stdev 3.416409 # Number of instructions fetched each cycle (Total) 63system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 64system.cpu.fetch.rateDist::0 469274168 55.37% 55.37% # Number of instructions fetched each cycle (Total) 65system.cpu.fetch.rateDist::1 25456463 3.00% 58.38% # Number of instructions fetched each cycle (Total) 66system.cpu.fetch.rateDist::2 28089429 3.31% 61.69% # Number of instructions fetched each cycle (Total) 67system.cpu.fetch.rateDist::3 29452206 3.48% 65.17% # Number of instructions fetched each cycle (Total) 68system.cpu.fetch.rateDist::4 18977949 2.24% 67.40% # Number of instructions fetched each cycle (Total) 69system.cpu.fetch.rateDist::5 25085896 2.96% 70.36% # Number of instructions fetched each cycle (Total) 70system.cpu.fetch.rateDist::6 31632952 3.73% 74.10% # Number of instructions fetched each cycle (Total) 71system.cpu.fetch.rateDist::7 30710148 3.62% 77.72% # Number of instructions fetched each cycle (Total) 72system.cpu.fetch.rateDist::8 188811034 22.28% 100.00% # Number of instructions fetched each cycle (Total) 73system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 74system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 75system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 76system.cpu.fetch.rateDist::total 847490245 # Number of instructions fetched each cycle (Total) 77system.cpu.fetch.branchRate 0.259126 # Number of branch fetches per cycle 78system.cpu.fetch.rate 1.440493 # Number of inst fetches per cycle 79system.cpu.decode.IdleCycles 242064219 # Number of cycles decode is idle 80system.cpu.decode.BlockedCycles 159033007 # Number of cycles decode is blocked 81system.cpu.decode.RunCycles 325519019 # Number of cycles decode is running 82system.cpu.decode.UnblockCycles 43678013 # Number of cycles decode is unblocking 83system.cpu.decode.SquashCycles 77195987 # Number of cycles decode is squashing 84system.cpu.decode.DecodedInsts 2233248714 # Number of instructions handled by decode 85system.cpu.decode.SquashedInsts 3 # Number of squashed instructions handled by decode 86system.cpu.rename.SquashCycles 77195987 # Number of cycles rename is squashing 87system.cpu.rename.IdleCycles 275570857 # Number of cycles rename is idle 88system.cpu.rename.BlockCycles 34110306 # Number of cycles rename is blocking 89system.cpu.rename.serializeStallCycles 14758 # count of cycles rename stalled for serializing inst 90system.cpu.rename.RunCycles 334015692 # Number of cycles rename is running 91system.cpu.rename.UnblockCycles 126582645 # Number of cycles rename is unblocking 92system.cpu.rename.RenamedInsts 2180982884 # Number of instructions processed by rename 93system.cpu.rename.ROBFullEvents 23384 # Number of times rename has blocked due to ROB full 94system.cpu.rename.IQFullEvents 17625674 # Number of times rename has blocked due to IQ full 95system.cpu.rename.LSQFullEvents 93760649 # Number of times rename has blocked due to LSQ full 96system.cpu.rename.FullRegisterEvents 161 # Number of times there has been no free registers 97system.cpu.rename.RenamedOperands 2280809501 # Number of destination operands rename has renamed 98system.cpu.rename.RenameLookups 5515289668 # Number of register rename lookups that rename has made 99system.cpu.rename.int_rename_lookups 5515055744 # Number of integer rename lookups 100system.cpu.rename.fp_rename_lookups 233924 # Number of floating rename lookups 101system.cpu.rename.CommittedMaps 1614040851 # Number of HB maps that are committed 102system.cpu.rename.UndoneMaps 666768650 # Number of HB maps that are undone due to squashing 103system.cpu.rename.serializingInsts 1407 # count of serializing insts renamed 104system.cpu.rename.tempSerializingInsts 1265 # count of temporary serializing insts renamed 105system.cpu.rename.skidInsts 312542490 # count of insts added to the skid buffer 106system.cpu.memDep0.insertedLoads 527887651 # Number of loads inserted to the mem dependence unit. 107system.cpu.memDep0.insertedStores 210543369 # Number of stores inserted to the mem dependence unit. 108system.cpu.memDep0.conflictingLoads 206203596 # Number of conflicting loads. 109system.cpu.memDep0.conflictingStores 60708248 # Number of conflicting stores. 110system.cpu.iq.iqInstsAdded 2086420498 # Number of instructions added to the IQ (excludes non-spec) 111system.cpu.iq.iqNonSpecInstsAdded 33397 # Number of non-speculative instructions added to the IQ 112system.cpu.iq.iqInstsIssued 1834774344 # Number of instructions issued 113system.cpu.iq.iqSquashedInstsIssued 951947 # Number of squashed instructions issued 114system.cpu.iq.iqSquashedInstsExamined 551393168 # Number of squashed instructions iterated over during squash; mainly for profiling 115system.cpu.iq.iqSquashedOperandsExamined 912351431 # Number of squashed operands that are examined and possibly removed from graph 116system.cpu.iq.iqSquashedNonSpecRemoved 32844 # Number of squashed non-spec instructions that were removed 117system.cpu.iq.issued_per_cycle::samples 847490245 # Number of insts issued each cycle 118system.cpu.iq.issued_per_cycle::mean 2.164950 # Number of insts issued each cycle 119system.cpu.iq.issued_per_cycle::stdev 1.897317 # Number of insts issued each cycle 120system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 121system.cpu.iq.issued_per_cycle::0 226384734 26.71% 26.71% # Number of insts issued each cycle 122system.cpu.iq.issued_per_cycle::1 141456799 16.69% 43.40% # Number of insts issued each cycle 123system.cpu.iq.issued_per_cycle::2 133569524 15.76% 59.16% # Number of insts issued each cycle 124system.cpu.iq.issued_per_cycle::3 133051620 15.70% 74.86% # Number of insts issued each cycle 125system.cpu.iq.issued_per_cycle::4 103773872 12.24% 87.11% # Number of insts issued each cycle 126system.cpu.iq.issued_per_cycle::5 59584692 7.03% 94.14% # Number of insts issued each cycle 127system.cpu.iq.issued_per_cycle::6 35598450 4.20% 98.34% # Number of insts issued each cycle 128system.cpu.iq.issued_per_cycle::7 12150443 1.43% 99.77% # Number of insts issued each cycle 129system.cpu.iq.issued_per_cycle::8 1920111 0.23% 100.00% # Number of insts issued each cycle 130system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 131system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 132system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 133system.cpu.iq.issued_per_cycle::total 847490245 # Number of insts issued each cycle 134system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 135system.cpu.iq.fu_full::IntAlu 5020198 29.82% 29.82% # attempts to use FU when none available 136system.cpu.iq.fu_full::IntMult 0 0.00% 29.82% # attempts to use FU when none available 137system.cpu.iq.fu_full::IntDiv 0 0.00% 29.82% # attempts to use FU when none available 138system.cpu.iq.fu_full::FloatAdd 0 0.00% 29.82% # attempts to use FU when none available 139system.cpu.iq.fu_full::FloatCmp 0 0.00% 29.82% # attempts to use FU when none available 140system.cpu.iq.fu_full::FloatCvt 0 0.00% 29.82% # attempts to use FU when none available 141system.cpu.iq.fu_full::FloatMult 0 0.00% 29.82% # attempts to use FU when none available 142system.cpu.iq.fu_full::FloatDiv 0 0.00% 29.82% # attempts to use FU when none available 143system.cpu.iq.fu_full::FloatSqrt 0 0.00% 29.82% # attempts to use FU when none available 144system.cpu.iq.fu_full::SimdAdd 0 0.00% 29.82% # attempts to use FU when none available 145system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 29.82% # attempts to use FU when none available 146system.cpu.iq.fu_full::SimdAlu 0 0.00% 29.82% # attempts to use FU when none available 147system.cpu.iq.fu_full::SimdCmp 0 0.00% 29.82% # attempts to use FU when none available 148system.cpu.iq.fu_full::SimdCvt 0 0.00% 29.82% # attempts to use FU when none available 149system.cpu.iq.fu_full::SimdMisc 0 0.00% 29.82% # attempts to use FU when none available 150system.cpu.iq.fu_full::SimdMult 0 0.00% 29.82% # attempts to use FU when none available 151system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 29.82% # attempts to use FU when none available 152system.cpu.iq.fu_full::SimdShift 0 0.00% 29.82% # attempts to use FU when none available 153system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 29.82% # attempts to use FU when none available 154system.cpu.iq.fu_full::SimdSqrt 0 0.00% 29.82% # attempts to use FU when none available 155system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 29.82% # attempts to use FU when none available 156system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 29.82% # attempts to use FU when none available 157system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 29.82% # attempts to use FU when none available 158system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 29.82% # attempts to use FU when none available 159system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 29.82% # attempts to use FU when none available 160system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 29.82% # attempts to use FU when none available 161system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 29.82% # attempts to use FU when none available 162system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 29.82% # attempts to use FU when none available 163system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 29.82% # attempts to use FU when none available 164system.cpu.iq.fu_full::MemRead 9164809 54.44% 84.27% # attempts to use FU when none available 165system.cpu.iq.fu_full::MemWrite 2648245 15.73% 100.00% # attempts to use FU when none available 166system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 167system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 168system.cpu.iq.FU_type_0::No_OpClass 2709053 0.15% 0.15% # Type of FU issued 169system.cpu.iq.FU_type_0::IntAlu 1209921951 65.94% 66.09% # Type of FU issued 170system.cpu.iq.FU_type_0::IntMult 0 0.00% 66.09% # Type of FU issued 171system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.09% # Type of FU issued 172system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 66.09% # Type of FU issued 173system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.09% # Type of FU issued 174system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.09% # Type of FU issued 175system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.09% # Type of FU issued 176system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.09% # Type of FU issued 177system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.09% # Type of FU issued 178system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.09% # Type of FU issued 179system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.09% # Type of FU issued 180system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.09% # Type of FU issued 181system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.09% # Type of FU issued 182system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.09% # Type of FU issued 183system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.09% # Type of FU issued 184system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.09% # Type of FU issued 185system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.09% # Type of FU issued 186system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.09% # Type of FU issued 187system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.09% # Type of FU issued 188system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.09% # Type of FU issued 189system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.09% # Type of FU issued 190system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.09% # Type of FU issued 191system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.09% # Type of FU issued 192system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.09% # Type of FU issued 193system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.09% # Type of FU issued 194system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.09% # Type of FU issued 195system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.09% # Type of FU issued 196system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.09% # Type of FU issued 197system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.09% # Type of FU issued 198system.cpu.iq.FU_type_0::MemRead 444260889 24.21% 90.30% # Type of FU issued 199system.cpu.iq.FU_type_0::MemWrite 177882451 9.70% 100.00% # Type of FU issued 200system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 201system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 202system.cpu.iq.FU_type_0::total 1834774344 # Type of FU issued 203system.cpu.iq.rate 2.146030 # Inst issue rate 204system.cpu.iq.fu_busy_cnt 16833252 # FU busy when requested 205system.cpu.iq.fu_busy_rate 0.009175 # FU busy rate (busy events/executed inst) 206system.cpu.iq.int_inst_queue_reads 4534784459 # Number of integer instruction queue reads 207system.cpu.iq.int_inst_queue_writes 2638023268 # Number of integer instruction queue writes 208system.cpu.iq.int_inst_queue_wakeup_accesses 1791909670 # Number of integer instruction queue wakeup accesses 209system.cpu.iq.fp_inst_queue_reads 39673 # Number of floating instruction queue reads 210system.cpu.iq.fp_inst_queue_writes 77216 # Number of floating instruction queue writes 211system.cpu.iq.fp_inst_queue_wakeup_accesses 9185 # Number of floating instruction queue wakeup accesses 212system.cpu.iq.int_alu_accesses 1848880362 # Number of integer alu accesses 213system.cpu.iq.fp_alu_accesses 18181 # Number of floating point alu accesses 214system.cpu.iew.lsq.thread0.forwLoads 169562147 # Number of loads that had data forwarded from stores 215system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 216system.cpu.iew.lsq.thread0.squashedLoads 143785495 # Number of loads squashed 217system.cpu.iew.lsq.thread0.ignoredResponses 532532 # Number of memory responses ignored because the instruction is squashed 218system.cpu.iew.lsq.thread0.memOrderViolation 265743 # Number of memory ordering violations 219system.cpu.iew.lsq.thread0.squashedStores 61383726 # Number of stores squashed 220system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 221system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 222system.cpu.iew.lsq.thread0.rescheduledLoads 10593 # Number of loads that were rescheduled 223system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked 224system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 225system.cpu.iew.iewSquashCycles 77195987 # Number of cycles IEW is squashing 226system.cpu.iew.iewBlockCycles 3929040 # Number of cycles IEW is blocking 227system.cpu.iew.iewUnblockCycles 530860 # Number of cycles IEW is unblocking 228system.cpu.iew.iewDispatchedInsts 2086453895 # Number of instructions dispatched to IQ 229system.cpu.iew.iewDispSquashedInsts 2572498 # Number of squashed instructions skipped by dispatch 230system.cpu.iew.iewDispLoadInsts 527887651 # Number of dispatched load instructions 231system.cpu.iew.iewDispStoreInsts 210543911 # Number of dispatched store instructions 232system.cpu.iew.iewDispNonSpecInsts 5247 # Number of dispatched non-speculative instructions 233system.cpu.iew.iewIQFullEvents 306238 # Number of times the IQ has become full, causing a stall 234system.cpu.iew.iewLSQFullEvents 13529 # Number of times the LSQ has become full, causing a stall 235system.cpu.iew.memOrderViolationEvents 265743 # Number of memory order violations 236system.cpu.iew.predictedTakenIncorrect 10035586 # Number of branches that were predicted taken incorrectly 237system.cpu.iew.predictedNotTakenIncorrect 4925818 # Number of branches that were predicted not taken incorrectly 238system.cpu.iew.branchMispredicts 14961404 # Number of branch mispredicts detected at execute 239system.cpu.iew.iewExecutedInsts 1804635725 # Number of executed instructions 240system.cpu.iew.iewExecLoadInsts 435893328 # Number of load instructions executed 241system.cpu.iew.iewExecSquashedInsts 30138619 # Number of squashed instructions skipped in execute 242system.cpu.iew.exec_swp 0 # number of swp insts executed 243system.cpu.iew.exec_nop 0 # number of nop insts executed 244system.cpu.iew.exec_refs 608398138 # number of memory reference insts executed 245system.cpu.iew.exec_branches 171115964 # Number of branches executed 246system.cpu.iew.exec_stores 172504810 # Number of stores executed 247system.cpu.iew.exec_rate 2.110779 # Inst execution rate 248system.cpu.iew.wb_sent 1799306282 # cumulative count of insts sent to commit 249system.cpu.iew.wb_count 1791918855 # cumulative count of insts written-back 250system.cpu.iew.wb_producers 1361399176 # num instructions producing a value 251system.cpu.iew.wb_consumers 1998222448 # num instructions consuming a value 252system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 253system.cpu.iew.wb_rate 2.095904 # insts written-back per cycle 254system.cpu.iew.wb_fanout 0.681305 # average fanout of values written-back 255system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 256system.cpu.commit.commitSquashedInsts 557495358 # The number of squashed insts skipped by commit 257system.cpu.commit.commitNonSpecStalls 553 # The number of times commit has been forced to stall to communicate backwards 258system.cpu.commit.branchMispredicts 14453256 # The number of times a branch was mispredicted 259system.cpu.commit.committed_per_cycle::samples 770294258 # Number of insts commited each cycle 260system.cpu.commit.committed_per_cycle::mean 1.984941 # Number of insts commited each cycle 261system.cpu.commit.committed_per_cycle::stdev 2.459206 # Number of insts commited each cycle 262system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 263system.cpu.commit.committed_per_cycle::0 276893910 35.95% 35.95% # Number of insts commited each cycle 264system.cpu.commit.committed_per_cycle::1 195328257 25.36% 61.30% # Number of insts commited each cycle 265system.cpu.commit.committed_per_cycle::2 61767064 8.02% 69.32% # Number of insts commited each cycle 266system.cpu.commit.committed_per_cycle::3 90267747 11.72% 81.04% # Number of insts commited each cycle 267system.cpu.commit.committed_per_cycle::4 27669896 3.59% 84.63% # Number of insts commited each cycle 268system.cpu.commit.committed_per_cycle::5 28983308 3.76% 88.40% # Number of insts commited each cycle 269system.cpu.commit.committed_per_cycle::6 10477535 1.36% 89.76% # Number of insts commited each cycle 270system.cpu.commit.committed_per_cycle::7 10390589 1.35% 91.11% # Number of insts commited each cycle 271system.cpu.commit.committed_per_cycle::8 68515952 8.89% 100.00% # Number of insts commited each cycle 272system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 273system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 274system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 275system.cpu.commit.committed_per_cycle::total 770294258 # Number of insts commited each cycle 276system.cpu.commit.committedInsts 826877109 # Number of instructions committed 277system.cpu.commit.committedOps 1528988699 # Number of ops (including micro ops) committed 278system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 279system.cpu.commit.refs 533262341 # Number of memory references committed 280system.cpu.commit.loads 384102156 # Number of loads committed 281system.cpu.commit.membars 0 # Number of memory barriers committed 282system.cpu.commit.branches 149758583 # Number of branches committed 283system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. 284system.cpu.commit.int_insts 1528317557 # Number of committed integer instructions. 285system.cpu.commit.function_calls 0 # Number of function calls committed. 286system.cpu.commit.bw_lim_events 68515952 # number cycles where commit BW limit reached 287system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 288system.cpu.rob.rob_reads 2788262363 # The number of ROB reads 289system.cpu.rob.rob_writes 4250388650 # The number of ROB writes 290system.cpu.timesIdled 191112 # Number of times that the entire CPU went into an idle state and unscheduled itself 291system.cpu.idleCycles 7471865 # Total number of cycles that the CPU has spent unscheduled due to idling 292system.cpu.committedInsts 826877109 # Number of Instructions Simulated 293system.cpu.committedOps 1528988699 # Number of Ops (including micro ops) Simulated 294system.cpu.committedInsts_total 826877109 # Number of Instructions Simulated 295system.cpu.cpi 1.033965 # CPI: Cycles Per Instruction 296system.cpu.cpi_total 1.033965 # CPI: Total CPI of All Threads 297system.cpu.ipc 0.967151 # IPC: Instructions Per Cycle 298system.cpu.ipc_total 0.967151 # IPC: Total IPC of All Threads 299system.cpu.int_regfile_reads 3390266607 # number of integer regfile reads 300system.cpu.int_regfile_writes 1871785238 # number of integer regfile writes 301system.cpu.fp_regfile_reads 9183 # number of floating regfile reads 302system.cpu.fp_regfile_writes 2 # number of floating regfile writes 303system.cpu.misc_regfile_reads 992828832 # number of misc regfile reads 304system.cpu.icache.replacements 5688 # number of replacements 305system.cpu.icache.tagsinuse 1035.102624 # Cycle average of tags in use 306system.cpu.icache.total_refs 179169407 # Total number of references to valid blocks. 307system.cpu.icache.sampled_refs 7297 # Sample count of references to valid blocks. 308system.cpu.icache.avg_refs 24553.845005 # Average number of references to valid blocks. 309system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 310system.cpu.icache.occ_blocks::cpu.inst 1035.102624 # Average occupied blocks per requestor 311system.cpu.icache.occ_percent::cpu.inst 0.505421 # Average percentage of cache occupancy 312system.cpu.icache.occ_percent::total 0.505421 # Average percentage of cache occupancy 313system.cpu.icache.ReadReq_hits::cpu.inst 179186003 # number of ReadReq hits 314system.cpu.icache.ReadReq_hits::total 179186003 # number of ReadReq hits 315system.cpu.icache.demand_hits::cpu.inst 179186003 # number of demand (read+write) hits 316system.cpu.icache.demand_hits::total 179186003 # number of demand (read+write) hits 317system.cpu.icache.overall_hits::cpu.inst 179186003 # number of overall hits 318system.cpu.icache.overall_hits::total 179186003 # number of overall hits 319system.cpu.icache.ReadReq_misses::cpu.inst 199745 # number of ReadReq misses 320system.cpu.icache.ReadReq_misses::total 199745 # number of ReadReq misses 321system.cpu.icache.demand_misses::cpu.inst 199745 # number of demand (read+write) misses 322system.cpu.icache.demand_misses::total 199745 # number of demand (read+write) misses 323system.cpu.icache.overall_misses::cpu.inst 199745 # number of overall misses 324system.cpu.icache.overall_misses::total 199745 # number of overall misses 325system.cpu.icache.ReadReq_miss_latency::cpu.inst 1237681000 # number of ReadReq miss cycles 326system.cpu.icache.ReadReq_miss_latency::total 1237681000 # number of ReadReq miss cycles 327system.cpu.icache.demand_miss_latency::cpu.inst 1237681000 # number of demand (read+write) miss cycles 328system.cpu.icache.demand_miss_latency::total 1237681000 # number of demand (read+write) miss cycles 329system.cpu.icache.overall_miss_latency::cpu.inst 1237681000 # number of overall miss cycles 330system.cpu.icache.overall_miss_latency::total 1237681000 # number of overall miss cycles 331system.cpu.icache.ReadReq_accesses::cpu.inst 179385748 # number of ReadReq accesses(hits+misses) 332system.cpu.icache.ReadReq_accesses::total 179385748 # number of ReadReq accesses(hits+misses) 333system.cpu.icache.demand_accesses::cpu.inst 179385748 # number of demand (read+write) accesses 334system.cpu.icache.demand_accesses::total 179385748 # number of demand (read+write) accesses 335system.cpu.icache.overall_accesses::cpu.inst 179385748 # number of overall (read+write) accesses 336system.cpu.icache.overall_accesses::total 179385748 # number of overall (read+write) accesses 337system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001113 # miss rate for ReadReq accesses 338system.cpu.icache.ReadReq_miss_rate::total 0.001113 # miss rate for ReadReq accesses 339system.cpu.icache.demand_miss_rate::cpu.inst 0.001113 # miss rate for demand accesses 340system.cpu.icache.demand_miss_rate::total 0.001113 # miss rate for demand accesses 341system.cpu.icache.overall_miss_rate::cpu.inst 0.001113 # miss rate for overall accesses 342system.cpu.icache.overall_miss_rate::total 0.001113 # miss rate for overall accesses 343system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6196.305289 # average ReadReq miss latency 344system.cpu.icache.ReadReq_avg_miss_latency::total 6196.305289 # average ReadReq miss latency 345system.cpu.icache.demand_avg_miss_latency::cpu.inst 6196.305289 # average overall miss latency 346system.cpu.icache.demand_avg_miss_latency::total 6196.305289 # average overall miss latency 347system.cpu.icache.overall_avg_miss_latency::cpu.inst 6196.305289 # average overall miss latency 348system.cpu.icache.overall_avg_miss_latency::total 6196.305289 # average overall miss latency 349system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 350system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 351system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 352system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 353system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 354system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 355system.cpu.icache.fast_writes 0 # number of fast writes performed 356system.cpu.icache.cache_copies 0 # number of cache copies performed 357system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1573 # number of ReadReq MSHR hits 358system.cpu.icache.ReadReq_mshr_hits::total 1573 # number of ReadReq MSHR hits 359system.cpu.icache.demand_mshr_hits::cpu.inst 1573 # number of demand (read+write) MSHR hits 360system.cpu.icache.demand_mshr_hits::total 1573 # number of demand (read+write) MSHR hits 361system.cpu.icache.overall_mshr_hits::cpu.inst 1573 # number of overall MSHR hits 362system.cpu.icache.overall_mshr_hits::total 1573 # number of overall MSHR hits 363system.cpu.icache.ReadReq_mshr_misses::cpu.inst 198172 # number of ReadReq MSHR misses 364system.cpu.icache.ReadReq_mshr_misses::total 198172 # number of ReadReq MSHR misses 365system.cpu.icache.demand_mshr_misses::cpu.inst 198172 # number of demand (read+write) MSHR misses 366system.cpu.icache.demand_mshr_misses::total 198172 # number of demand (read+write) MSHR misses 367system.cpu.icache.overall_mshr_misses::cpu.inst 198172 # number of overall MSHR misses 368system.cpu.icache.overall_mshr_misses::total 198172 # number of overall MSHR misses 369system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 804803500 # number of ReadReq MSHR miss cycles 370system.cpu.icache.ReadReq_mshr_miss_latency::total 804803500 # number of ReadReq MSHR miss cycles 371system.cpu.icache.demand_mshr_miss_latency::cpu.inst 804803500 # number of demand (read+write) MSHR miss cycles 372system.cpu.icache.demand_mshr_miss_latency::total 804803500 # number of demand (read+write) MSHR miss cycles 373system.cpu.icache.overall_mshr_miss_latency::cpu.inst 804803500 # number of overall MSHR miss cycles 374system.cpu.icache.overall_mshr_miss_latency::total 804803500 # number of overall MSHR miss cycles 375system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001105 # mshr miss rate for ReadReq accesses 376system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001105 # mshr miss rate for ReadReq accesses 377system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001105 # mshr miss rate for demand accesses 378system.cpu.icache.demand_mshr_miss_rate::total 0.001105 # mshr miss rate for demand accesses 379system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001105 # mshr miss rate for overall accesses 380system.cpu.icache.overall_mshr_miss_rate::total 0.001105 # mshr miss rate for overall accesses 381system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 4061.136286 # average ReadReq mshr miss latency 382system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 4061.136286 # average ReadReq mshr miss latency 383system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 4061.136286 # average overall mshr miss latency 384system.cpu.icache.demand_avg_mshr_miss_latency::total 4061.136286 # average overall mshr miss latency 385system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 4061.136286 # average overall mshr miss latency 386system.cpu.icache.overall_avg_mshr_miss_latency::total 4061.136286 # average overall mshr miss latency 387system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 388system.cpu.dcache.replacements 2529003 # number of replacements 389system.cpu.dcache.tagsinuse 4087.729607 # Cycle average of tags in use 390system.cpu.dcache.total_refs 410749337 # Total number of references to valid blocks. 391system.cpu.dcache.sampled_refs 2533099 # Sample count of references to valid blocks. 392system.cpu.dcache.avg_refs 162.152895 # Average number of references to valid blocks. 393system.cpu.dcache.warmup_cycle 1774400000 # Cycle when the warmup percentage was hit. 394system.cpu.dcache.occ_blocks::cpu.data 4087.729607 # Average occupied blocks per requestor 395system.cpu.dcache.occ_percent::cpu.data 0.997981 # Average percentage of cache occupancy 396system.cpu.dcache.occ_percent::total 0.997981 # Average percentage of cache occupancy 397system.cpu.dcache.ReadReq_hits::cpu.data 261990574 # number of ReadReq hits 398system.cpu.dcache.ReadReq_hits::total 261990574 # number of ReadReq hits 399system.cpu.dcache.WriteReq_hits::cpu.data 148196003 # number of WriteReq hits 400system.cpu.dcache.WriteReq_hits::total 148196003 # number of WriteReq hits 401system.cpu.dcache.demand_hits::cpu.data 410186577 # number of demand (read+write) hits 402system.cpu.dcache.demand_hits::total 410186577 # number of demand (read+write) hits 403system.cpu.dcache.overall_hits::cpu.data 410186577 # number of overall hits 404system.cpu.dcache.overall_hits::total 410186577 # number of overall hits 405system.cpu.dcache.ReadReq_misses::cpu.data 2760947 # number of ReadReq misses 406system.cpu.dcache.ReadReq_misses::total 2760947 # number of ReadReq misses 407system.cpu.dcache.WriteReq_misses::cpu.data 964198 # number of WriteReq misses 408system.cpu.dcache.WriteReq_misses::total 964198 # number of WriteReq misses 409system.cpu.dcache.demand_misses::cpu.data 3725145 # number of demand (read+write) misses 410system.cpu.dcache.demand_misses::total 3725145 # number of demand (read+write) misses 411system.cpu.dcache.overall_misses::cpu.data 3725145 # number of overall misses 412system.cpu.dcache.overall_misses::total 3725145 # number of overall misses 413system.cpu.dcache.ReadReq_miss_latency::cpu.data 29892904500 # number of ReadReq miss cycles 414system.cpu.dcache.ReadReq_miss_latency::total 29892904500 # number of ReadReq miss cycles 415system.cpu.dcache.WriteReq_miss_latency::cpu.data 16960182000 # number of WriteReq miss cycles 416system.cpu.dcache.WriteReq_miss_latency::total 16960182000 # number of WriteReq miss cycles 417system.cpu.dcache.demand_miss_latency::cpu.data 46853086500 # number of demand (read+write) miss cycles 418system.cpu.dcache.demand_miss_latency::total 46853086500 # number of demand (read+write) miss cycles 419system.cpu.dcache.overall_miss_latency::cpu.data 46853086500 # number of overall miss cycles 420system.cpu.dcache.overall_miss_latency::total 46853086500 # number of overall miss cycles 421system.cpu.dcache.ReadReq_accesses::cpu.data 264751521 # number of ReadReq accesses(hits+misses) 422system.cpu.dcache.ReadReq_accesses::total 264751521 # number of ReadReq accesses(hits+misses) 423system.cpu.dcache.WriteReq_accesses::cpu.data 149160201 # number of WriteReq accesses(hits+misses) 424system.cpu.dcache.WriteReq_accesses::total 149160201 # number of WriteReq accesses(hits+misses) 425system.cpu.dcache.demand_accesses::cpu.data 413911722 # number of demand (read+write) accesses 426system.cpu.dcache.demand_accesses::total 413911722 # number of demand (read+write) accesses 427system.cpu.dcache.overall_accesses::cpu.data 413911722 # number of overall (read+write) accesses 428system.cpu.dcache.overall_accesses::total 413911722 # number of overall (read+write) accesses 429system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.010428 # miss rate for ReadReq accesses 430system.cpu.dcache.ReadReq_miss_rate::total 0.010428 # miss rate for ReadReq accesses 431system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006464 # miss rate for WriteReq accesses 432system.cpu.dcache.WriteReq_miss_rate::total 0.006464 # miss rate for WriteReq accesses 433system.cpu.dcache.demand_miss_rate::cpu.data 0.009000 # miss rate for demand accesses 434system.cpu.dcache.demand_miss_rate::total 0.009000 # miss rate for demand accesses 435system.cpu.dcache.overall_miss_rate::cpu.data 0.009000 # miss rate for overall accesses 436system.cpu.dcache.overall_miss_rate::total 0.009000 # miss rate for overall accesses 437system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 10827.047567 # average ReadReq miss latency 438system.cpu.dcache.ReadReq_avg_miss_latency::total 10827.047567 # average ReadReq miss latency 439system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17589.936922 # average WriteReq miss latency 440system.cpu.dcache.WriteReq_avg_miss_latency::total 17589.936922 # average WriteReq miss latency 441system.cpu.dcache.demand_avg_miss_latency::cpu.data 12577.520204 # average overall miss latency 442system.cpu.dcache.demand_avg_miss_latency::total 12577.520204 # average overall miss latency 443system.cpu.dcache.overall_avg_miss_latency::cpu.data 12577.520204 # average overall miss latency 444system.cpu.dcache.overall_avg_miss_latency::total 12577.520204 # average overall miss latency 445system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 446system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 447system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 448system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 449system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 450system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 451system.cpu.dcache.fast_writes 0 # number of fast writes performed 452system.cpu.dcache.cache_copies 0 # number of cache copies performed 453system.cpu.dcache.writebacks::writebacks 2304289 # number of writebacks 454system.cpu.dcache.writebacks::total 2304289 # number of writebacks 455system.cpu.dcache.ReadReq_mshr_hits::cpu.data 998325 # number of ReadReq MSHR hits 456system.cpu.dcache.ReadReq_mshr_hits::total 998325 # number of ReadReq MSHR hits 457system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2874 # number of WriteReq MSHR hits 458system.cpu.dcache.WriteReq_mshr_hits::total 2874 # number of WriteReq MSHR hits 459system.cpu.dcache.demand_mshr_hits::cpu.data 1001199 # number of demand (read+write) MSHR hits 460system.cpu.dcache.demand_mshr_hits::total 1001199 # number of demand (read+write) MSHR hits 461system.cpu.dcache.overall_mshr_hits::cpu.data 1001199 # number of overall MSHR hits 462system.cpu.dcache.overall_mshr_hits::total 1001199 # number of overall MSHR hits 463system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1762622 # number of ReadReq MSHR misses 464system.cpu.dcache.ReadReq_mshr_misses::total 1762622 # number of ReadReq MSHR misses 465system.cpu.dcache.WriteReq_mshr_misses::cpu.data 961324 # number of WriteReq MSHR misses 466system.cpu.dcache.WriteReq_mshr_misses::total 961324 # number of WriteReq MSHR misses 467system.cpu.dcache.demand_mshr_misses::cpu.data 2723946 # number of demand (read+write) MSHR misses 468system.cpu.dcache.demand_mshr_misses::total 2723946 # number of demand (read+write) MSHR misses 469system.cpu.dcache.overall_mshr_misses::cpu.data 2723946 # number of overall MSHR misses 470system.cpu.dcache.overall_mshr_misses::total 2723946 # number of overall MSHR misses 471system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10993099500 # number of ReadReq MSHR miss cycles 472system.cpu.dcache.ReadReq_mshr_miss_latency::total 10993099500 # number of ReadReq MSHR miss cycles 473system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14994695000 # number of WriteReq MSHR miss cycles 474system.cpu.dcache.WriteReq_mshr_miss_latency::total 14994695000 # number of WriteReq MSHR miss cycles 475system.cpu.dcache.demand_mshr_miss_latency::cpu.data 25987794500 # number of demand (read+write) MSHR miss cycles 476system.cpu.dcache.demand_mshr_miss_latency::total 25987794500 # number of demand (read+write) MSHR miss cycles 477system.cpu.dcache.overall_mshr_miss_latency::cpu.data 25987794500 # number of overall MSHR miss cycles 478system.cpu.dcache.overall_mshr_miss_latency::total 25987794500 # number of overall MSHR miss cycles 479system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006658 # mshr miss rate for ReadReq accesses 480system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006658 # mshr miss rate for ReadReq accesses 481system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006445 # mshr miss rate for WriteReq accesses 482system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006445 # mshr miss rate for WriteReq accesses 483system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006581 # mshr miss rate for demand accesses 484system.cpu.dcache.demand_mshr_miss_rate::total 0.006581 # mshr miss rate for demand accesses 485system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006581 # mshr miss rate for overall accesses 486system.cpu.dcache.overall_mshr_miss_rate::total 0.006581 # mshr miss rate for overall accesses 487system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 6236.787865 # average ReadReq mshr miss latency 488system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 6236.787865 # average ReadReq mshr miss latency 489system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 15597.961769 # average WriteReq mshr miss latency 490system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 15597.961769 # average WriteReq mshr miss latency 491system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 9540.495480 # average overall mshr miss latency 492system.cpu.dcache.demand_avg_mshr_miss_latency::total 9540.495480 # average overall mshr miss latency 493system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 9540.495480 # average overall mshr miss latency 494system.cpu.dcache.overall_avg_mshr_miss_latency::total 9540.495480 # average overall mshr miss latency 495system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 496system.cpu.l2cache.replacements 408687 # number of replacements 497system.cpu.l2cache.tagsinuse 29306.187032 # Cycle average of tags in use 498system.cpu.l2cache.total_refs 3611934 # Total number of references to valid blocks. 499system.cpu.l2cache.sampled_refs 441022 # Sample count of references to valid blocks. 500system.cpu.l2cache.avg_refs 8.189918 # Average number of references to valid blocks. 501system.cpu.l2cache.warmup_cycle 209697302000 # Cycle when the warmup percentage was hit. 502system.cpu.l2cache.occ_blocks::writebacks 21100.579684 # Average occupied blocks per requestor 503system.cpu.l2cache.occ_blocks::cpu.inst 146.976593 # Average occupied blocks per requestor 504system.cpu.l2cache.occ_blocks::cpu.data 8058.630755 # Average occupied blocks per requestor 505system.cpu.l2cache.occ_percent::writebacks 0.643939 # Average percentage of cache occupancy 506system.cpu.l2cache.occ_percent::cpu.inst 0.004485 # Average percentage of cache occupancy 507system.cpu.l2cache.occ_percent::cpu.data 0.245930 # Average percentage of cache occupancy 508system.cpu.l2cache.occ_percent::total 0.894354 # Average percentage of cache occupancy 509system.cpu.l2cache.ReadReq_hits::cpu.inst 3776 # number of ReadReq hits 510system.cpu.l2cache.ReadReq_hits::cpu.data 1539310 # number of ReadReq hits 511system.cpu.l2cache.ReadReq_hits::total 1543086 # number of ReadReq hits 512system.cpu.l2cache.Writeback_hits::writebacks 2304289 # number of Writeback hits 513system.cpu.l2cache.Writeback_hits::total 2304289 # number of Writeback hits 514system.cpu.l2cache.UpgradeReq_hits::cpu.data 1429 # number of UpgradeReq hits 515system.cpu.l2cache.UpgradeReq_hits::total 1429 # number of UpgradeReq hits 516system.cpu.l2cache.ReadExReq_hits::cpu.data 562371 # number of ReadExReq hits 517system.cpu.l2cache.ReadExReq_hits::total 562371 # number of ReadExReq hits 518system.cpu.l2cache.demand_hits::cpu.inst 3776 # number of demand (read+write) hits 519system.cpu.l2cache.demand_hits::cpu.data 2101681 # number of demand (read+write) hits 520system.cpu.l2cache.demand_hits::total 2105457 # number of demand (read+write) hits 521system.cpu.l2cache.overall_hits::cpu.inst 3776 # number of overall hits 522system.cpu.l2cache.overall_hits::cpu.data 2101681 # number of overall hits 523system.cpu.l2cache.overall_hits::total 2105457 # number of overall hits 524system.cpu.l2cache.ReadReq_misses::cpu.inst 3470 # number of ReadReq misses 525system.cpu.l2cache.ReadReq_misses::cpu.data 222202 # number of ReadReq misses 526system.cpu.l2cache.ReadReq_misses::total 225672 # number of ReadReq misses 527system.cpu.l2cache.UpgradeReq_misses::cpu.data 189416 # number of UpgradeReq misses 528system.cpu.l2cache.UpgradeReq_misses::total 189416 # number of UpgradeReq misses 529system.cpu.l2cache.ReadExReq_misses::cpu.data 209218 # number of ReadExReq misses 530system.cpu.l2cache.ReadExReq_misses::total 209218 # number of ReadExReq misses 531system.cpu.l2cache.demand_misses::cpu.inst 3470 # number of demand (read+write) misses 532system.cpu.l2cache.demand_misses::cpu.data 431420 # number of demand (read+write) misses 533system.cpu.l2cache.demand_misses::total 434890 # number of demand (read+write) misses 534system.cpu.l2cache.overall_misses::cpu.inst 3470 # number of overall misses 535system.cpu.l2cache.overall_misses::cpu.data 431420 # number of overall misses 536system.cpu.l2cache.overall_misses::total 434890 # number of overall misses 537system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 122434500 # number of ReadReq miss cycles 538system.cpu.l2cache.ReadReq_miss_latency::cpu.data 7650091930 # number of ReadReq miss cycles 539system.cpu.l2cache.ReadReq_miss_latency::total 7772526430 # number of ReadReq miss cycles 540system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 10787000 # number of UpgradeReq miss cycles 541system.cpu.l2cache.UpgradeReq_miss_latency::total 10787000 # number of UpgradeReq miss cycles 542system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7162790500 # number of ReadExReq miss cycles 543system.cpu.l2cache.ReadExReq_miss_latency::total 7162790500 # number of ReadExReq miss cycles 544system.cpu.l2cache.demand_miss_latency::cpu.inst 122434500 # number of demand (read+write) miss cycles 545system.cpu.l2cache.demand_miss_latency::cpu.data 14812882430 # number of demand (read+write) miss cycles 546system.cpu.l2cache.demand_miss_latency::total 14935316930 # number of demand (read+write) miss cycles 547system.cpu.l2cache.overall_miss_latency::cpu.inst 122434500 # number of overall miss cycles 548system.cpu.l2cache.overall_miss_latency::cpu.data 14812882430 # number of overall miss cycles 549system.cpu.l2cache.overall_miss_latency::total 14935316930 # number of overall miss cycles 550system.cpu.l2cache.ReadReq_accesses::cpu.inst 7246 # number of ReadReq accesses(hits+misses) 551system.cpu.l2cache.ReadReq_accesses::cpu.data 1761512 # number of ReadReq accesses(hits+misses) 552system.cpu.l2cache.ReadReq_accesses::total 1768758 # number of ReadReq accesses(hits+misses) 553system.cpu.l2cache.Writeback_accesses::writebacks 2304289 # number of Writeback accesses(hits+misses) 554system.cpu.l2cache.Writeback_accesses::total 2304289 # number of Writeback accesses(hits+misses) 555system.cpu.l2cache.UpgradeReq_accesses::cpu.data 190845 # number of UpgradeReq accesses(hits+misses) 556system.cpu.l2cache.UpgradeReq_accesses::total 190845 # number of UpgradeReq accesses(hits+misses) 557system.cpu.l2cache.ReadExReq_accesses::cpu.data 771589 # number of ReadExReq accesses(hits+misses) 558system.cpu.l2cache.ReadExReq_accesses::total 771589 # number of ReadExReq accesses(hits+misses) 559system.cpu.l2cache.demand_accesses::cpu.inst 7246 # number of demand (read+write) accesses 560system.cpu.l2cache.demand_accesses::cpu.data 2533101 # number of demand (read+write) accesses 561system.cpu.l2cache.demand_accesses::total 2540347 # number of demand (read+write) accesses 562system.cpu.l2cache.overall_accesses::cpu.inst 7246 # number of overall (read+write) accesses 563system.cpu.l2cache.overall_accesses::cpu.data 2533101 # number of overall (read+write) accesses 564system.cpu.l2cache.overall_accesses::total 2540347 # number of overall (read+write) accesses 565system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.478885 # miss rate for ReadReq accesses 566system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.126143 # miss rate for ReadReq accesses 567system.cpu.l2cache.ReadReq_miss_rate::total 0.127588 # miss rate for ReadReq accesses 568system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.992512 # miss rate for UpgradeReq accesses 569system.cpu.l2cache.UpgradeReq_miss_rate::total 0.992512 # miss rate for UpgradeReq accesses 570system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.271152 # miss rate for ReadExReq accesses 571system.cpu.l2cache.ReadExReq_miss_rate::total 0.271152 # miss rate for ReadExReq accesses 572system.cpu.l2cache.demand_miss_rate::cpu.inst 0.478885 # miss rate for demand accesses 573system.cpu.l2cache.demand_miss_rate::cpu.data 0.170313 # miss rate for demand accesses 574system.cpu.l2cache.demand_miss_rate::total 0.171193 # miss rate for demand accesses 575system.cpu.l2cache.overall_miss_rate::cpu.inst 0.478885 # miss rate for overall accesses 576system.cpu.l2cache.overall_miss_rate::cpu.data 0.170313 # miss rate for overall accesses 577system.cpu.l2cache.overall_miss_rate::total 0.171193 # miss rate for overall accesses 578system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35283.717579 # average ReadReq miss latency 579system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34428.546683 # average ReadReq miss latency 580system.cpu.l2cache.ReadReq_avg_miss_latency::total 34441.696046 # average ReadReq miss latency 581system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 56.948727 # average UpgradeReq miss latency 582system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 56.948727 # average UpgradeReq miss latency 583system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34236.014588 # average ReadExReq miss latency 584system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34236.014588 # average ReadExReq miss latency 585system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35283.717579 # average overall miss latency 586system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34335.177855 # average overall miss latency 587system.cpu.l2cache.demand_avg_miss_latency::total 34342.746281 # average overall miss latency 588system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35283.717579 # average overall miss latency 589system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34335.177855 # average overall miss latency 590system.cpu.l2cache.overall_avg_miss_latency::total 34342.746281 # average overall miss latency 591system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 592system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 593system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 594system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 595system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 596system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 597system.cpu.l2cache.fast_writes 0 # number of fast writes performed 598system.cpu.l2cache.cache_copies 0 # number of cache copies performed 599system.cpu.l2cache.writebacks::writebacks 324977 # number of writebacks 600system.cpu.l2cache.writebacks::total 324977 # number of writebacks 601system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3470 # number of ReadReq MSHR misses 602system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 222202 # number of ReadReq MSHR misses 603system.cpu.l2cache.ReadReq_mshr_misses::total 225672 # number of ReadReq MSHR misses 604system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 189416 # number of UpgradeReq MSHR misses 605system.cpu.l2cache.UpgradeReq_mshr_misses::total 189416 # number of UpgradeReq MSHR misses 606system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 209218 # number of ReadExReq MSHR misses 607system.cpu.l2cache.ReadExReq_mshr_misses::total 209218 # number of ReadExReq MSHR misses 608system.cpu.l2cache.demand_mshr_misses::cpu.inst 3470 # number of demand (read+write) MSHR misses 609system.cpu.l2cache.demand_mshr_misses::cpu.data 431420 # number of demand (read+write) MSHR misses 610system.cpu.l2cache.demand_mshr_misses::total 434890 # number of demand (read+write) MSHR misses 611system.cpu.l2cache.overall_mshr_misses::cpu.inst 3470 # number of overall MSHR misses 612system.cpu.l2cache.overall_mshr_misses::cpu.data 431420 # number of overall MSHR misses 613system.cpu.l2cache.overall_mshr_misses::total 434890 # number of overall MSHR misses 614system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 111424500 # number of ReadReq MSHR miss cycles 615system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6957207430 # number of ReadReq MSHR miss cycles 616system.cpu.l2cache.ReadReq_mshr_miss_latency::total 7068631930 # number of ReadReq MSHR miss cycles 617system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 5878812896 # number of UpgradeReq MSHR miss cycles 618system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 5878812896 # number of UpgradeReq MSHR miss cycles 619system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6488320000 # number of ReadExReq MSHR miss cycles 620system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6488320000 # number of ReadExReq MSHR miss cycles 621system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 111424500 # number of demand (read+write) MSHR miss cycles 622system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 13445527430 # number of demand (read+write) MSHR miss cycles 623system.cpu.l2cache.demand_mshr_miss_latency::total 13556951930 # number of demand (read+write) MSHR miss cycles 624system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 111424500 # number of overall MSHR miss cycles 625system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 13445527430 # number of overall MSHR miss cycles 626system.cpu.l2cache.overall_mshr_miss_latency::total 13556951930 # number of overall MSHR miss cycles 627system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.478885 # mshr miss rate for ReadReq accesses 628system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.126143 # mshr miss rate for ReadReq accesses 629system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.127588 # mshr miss rate for ReadReq accesses 630system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.992512 # mshr miss rate for UpgradeReq accesses 631system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.992512 # mshr miss rate for UpgradeReq accesses 632system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.271152 # mshr miss rate for ReadExReq accesses 633system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.271152 # mshr miss rate for ReadExReq accesses 634system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.478885 # mshr miss rate for demand accesses 635system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.170313 # mshr miss rate for demand accesses 636system.cpu.l2cache.demand_mshr_miss_rate::total 0.171193 # mshr miss rate for demand accesses 637system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.478885 # mshr miss rate for overall accesses 638system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.170313 # mshr miss rate for overall accesses 639system.cpu.l2cache.overall_mshr_miss_rate::total 0.171193 # mshr miss rate for overall accesses 640system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32110.806916 # average ReadReq mshr miss latency 641system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31310.282671 # average ReadReq mshr miss latency 642system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31322.591770 # average ReadReq mshr miss latency 643system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31036.516957 # average UpgradeReq mshr miss latency 644system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31036.516957 # average UpgradeReq mshr miss latency 645system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31012.245600 # average ReadExReq mshr miss latency 646system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31012.245600 # average ReadExReq mshr miss latency 647system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32110.806916 # average overall mshr miss latency 648system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31165.748992 # average overall mshr miss latency 649system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31173.289636 # average overall mshr miss latency 650system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32110.806916 # average overall mshr miss latency 651system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31165.748992 # average overall mshr miss latency 652system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31173.289636 # average overall mshr miss latency 653system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 654 655---------- End Simulation Statistics ---------- 656