stats.txt revision 9134:275232ad377d
110259SAndrew.Bardsley@arm.com 210259SAndrew.Bardsley@arm.com---------- Begin Simulation Statistics ---------- 310259SAndrew.Bardsley@arm.comsim_seconds 0.460507 # Number of seconds simulated 410259SAndrew.Bardsley@arm.comsim_ticks 460506550000 # Number of ticks simulated 510259SAndrew.Bardsley@arm.comfinal_tick 460506550000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 610259SAndrew.Bardsley@arm.comsim_freq 1000000000000 # Frequency of simulated ticks 710259SAndrew.Bardsley@arm.comhost_inst_rate 78127 # Simulator instruction rate (inst/s) 810259SAndrew.Bardsley@arm.comhost_op_rate 144467 # Simulator op (including micro ops) rate (op/s) 910259SAndrew.Bardsley@arm.comhost_tick_rate 43510964 # Simulator tick rate (ticks/s) 1010259SAndrew.Bardsley@arm.comhost_mem_usage 271484 # Number of bytes of host memory used 1110259SAndrew.Bardsley@arm.comhost_seconds 10583.69 # Real time elapsed on the host 1210259SAndrew.Bardsley@arm.comsim_insts 826877144 # Number of instructions simulated 1310259SAndrew.Bardsley@arm.comsim_ops 1528988756 # Number of ops (including micro ops) simulated 1410259SAndrew.Bardsley@arm.comsystem.physmem.bytes_read::cpu.inst 221568 # Number of bytes read from this memory 1510259SAndrew.Bardsley@arm.comsystem.physmem.bytes_read::cpu.data 27602688 # Number of bytes read from this memory 1610259SAndrew.Bardsley@arm.comsystem.physmem.bytes_read::total 27824256 # Number of bytes read from this memory 1710259SAndrew.Bardsley@arm.comsystem.physmem.bytes_inst_read::cpu.inst 221568 # Number of instructions bytes read from this memory 1810259SAndrew.Bardsley@arm.comsystem.physmem.bytes_inst_read::total 221568 # Number of instructions bytes read from this memory 1910259SAndrew.Bardsley@arm.comsystem.physmem.bytes_written::writebacks 20791168 # Number of bytes written to this memory 2010259SAndrew.Bardsley@arm.comsystem.physmem.bytes_written::total 20791168 # Number of bytes written to this memory 2110259SAndrew.Bardsley@arm.comsystem.physmem.num_reads::cpu.inst 3462 # Number of read requests responded to by this memory 2210259SAndrew.Bardsley@arm.comsystem.physmem.num_reads::cpu.data 431292 # Number of read requests responded to by this memory 2310259SAndrew.Bardsley@arm.comsystem.physmem.num_reads::total 434754 # Number of read requests responded to by this memory 2410259SAndrew.Bardsley@arm.comsystem.physmem.num_writes::writebacks 324862 # Number of write requests responded to by this memory 2510259SAndrew.Bardsley@arm.comsystem.physmem.num_writes::total 324862 # Number of write requests responded to by this memory 2610259SAndrew.Bardsley@arm.comsystem.physmem.bw_read::cpu.inst 481140 # Total read bandwidth from this memory (bytes/s) 2710259SAndrew.Bardsley@arm.comsystem.physmem.bw_read::cpu.data 59939838 # Total read bandwidth from this memory (bytes/s) 2810259SAndrew.Bardsley@arm.comsystem.physmem.bw_read::total 60420978 # Total read bandwidth from this memory (bytes/s) 2910259SAndrew.Bardsley@arm.comsystem.physmem.bw_inst_read::cpu.inst 481140 # Instruction read bandwidth from this memory (bytes/s) 3010259SAndrew.Bardsley@arm.comsystem.physmem.bw_inst_read::total 481140 # Instruction read bandwidth from this memory (bytes/s) 3110259SAndrew.Bardsley@arm.comsystem.physmem.bw_write::writebacks 45148474 # Write bandwidth from this memory (bytes/s) 3210259SAndrew.Bardsley@arm.comsystem.physmem.bw_write::total 45148474 # Write bandwidth from this memory (bytes/s) 3310259SAndrew.Bardsley@arm.comsystem.physmem.bw_total::writebacks 45148474 # Total bandwidth to/from this memory (bytes/s) 3410259SAndrew.Bardsley@arm.comsystem.physmem.bw_total::cpu.inst 481140 # Total bandwidth to/from this memory (bytes/s) 3510259SAndrew.Bardsley@arm.comsystem.physmem.bw_total::cpu.data 59939838 # Total bandwidth to/from this memory (bytes/s) 3610259SAndrew.Bardsley@arm.comsystem.physmem.bw_total::total 105569452 # Total bandwidth to/from this memory (bytes/s) 3710259SAndrew.Bardsley@arm.comsystem.cpu.workload.num_syscalls 551 # Number of system calls 3810259SAndrew.Bardsley@arm.comsystem.cpu.numCycles 921013101 # number of cpu cycles simulated 3910259SAndrew.Bardsley@arm.comsystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 4010259SAndrew.Bardsley@arm.comsystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 4110259SAndrew.Bardsley@arm.comsystem.cpu.BPredUnit.lookups 225814140 # Number of BP lookups 4210259SAndrew.Bardsley@arm.comsystem.cpu.BPredUnit.condPredicted 225814140 # Number of conditional branches predicted 4310259SAndrew.Bardsley@arm.comsystem.cpu.BPredUnit.condIncorrect 14312639 # Number of conditional branches incorrect 4410259SAndrew.Bardsley@arm.comsystem.cpu.BPredUnit.BTBLookups 160732187 # Number of BTB lookups 4510259SAndrew.Bardsley@arm.comsystem.cpu.BPredUnit.BTBHits 155963049 # Number of BTB hits 4610259SAndrew.Bardsley@arm.comsystem.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 4710259SAndrew.Bardsley@arm.comsystem.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. 4810259SAndrew.Bardsley@arm.comsystem.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. 4910259SAndrew.Bardsley@arm.comsystem.cpu.fetch.icacheStallCycles 191714211 # Number of cycles fetch is stalled on an Icache miss 5010259SAndrew.Bardsley@arm.comsystem.cpu.fetch.Insts 1263294933 # Number of instructions fetch has processed 5110259SAndrew.Bardsley@arm.comsystem.cpu.fetch.Branches 225814140 # Number of branches that fetch encountered 5210259SAndrew.Bardsley@arm.comsystem.cpu.fetch.predictedBranches 155963049 # Number of branches that fetch has predicted taken 5312334Sgabeblack@google.comsystem.cpu.fetch.Cycles 392136096 # Number of cycles fetch has run and was not squashing or blocked 5412334Sgabeblack@google.comsystem.cpu.fetch.SquashCycles 98589209 # Number of cycles fetch has spent squashing 5510259SAndrew.Bardsley@arm.comsystem.cpu.fetch.BlockedCycles 239295269 # Number of cycles fetch has spent blocked 5610259SAndrew.Bardsley@arm.comsystem.cpu.fetch.MiscStallCycles 25132 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 5710259SAndrew.Bardsley@arm.comsystem.cpu.fetch.PendingTrapStallCycles 236819 # Number of stall cycles due to pending traps 5810259SAndrew.Bardsley@arm.comsystem.cpu.fetch.CacheLines 183551766 # Number of cache lines fetched 5910259SAndrew.Bardsley@arm.comsystem.cpu.fetch.IcacheSquashes 3669107 # Number of outstanding Icache misses that were squashed 6010259SAndrew.Bardsley@arm.comsystem.cpu.fetch.rateDist::samples 907433762 # Number of instructions fetched each cycle (Total) 6110259SAndrew.Bardsley@arm.comsystem.cpu.fetch.rateDist::mean 2.580701 # Number of instructions fetched each cycle (Total) 6210259SAndrew.Bardsley@arm.comsystem.cpu.fetch.rateDist::stdev 3.385285 # Number of instructions fetched each cycle (Total) 6310259SAndrew.Bardsley@arm.comsystem.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 6410259SAndrew.Bardsley@arm.comsystem.cpu.fetch.rateDist::0 519759842 57.28% 57.28% # Number of instructions fetched each cycle (Total) 6510259SAndrew.Bardsley@arm.comsystem.cpu.fetch.rateDist::1 26004641 2.87% 60.14% # Number of instructions fetched each cycle (Total) 6610259SAndrew.Bardsley@arm.comsystem.cpu.fetch.rateDist::2 29087197 3.21% 63.35% # Number of instructions fetched each cycle (Total) 6710259SAndrew.Bardsley@arm.comsystem.cpu.fetch.rateDist::3 30312943 3.34% 66.69% # Number of instructions fetched each cycle (Total) 6810259SAndrew.Bardsley@arm.comsystem.cpu.fetch.rateDist::4 19607781 2.16% 68.85% # Number of instructions fetched each cycle (Total) 6910259SAndrew.Bardsley@arm.comsystem.cpu.fetch.rateDist::5 25619101 2.82% 71.67% # Number of instructions fetched each cycle (Total) 7010259SAndrew.Bardsley@arm.comsystem.cpu.fetch.rateDist::6 32643698 3.60% 75.27% # Number of instructions fetched each cycle (Total) 7110259SAndrew.Bardsley@arm.comsystem.cpu.fetch.rateDist::7 30879699 3.40% 78.67% # Number of instructions fetched each cycle (Total) 7210259SAndrew.Bardsley@arm.comsystem.cpu.fetch.rateDist::8 193518860 21.33% 100.00% # Number of instructions fetched each cycle (Total) 7310259SAndrew.Bardsley@arm.comsystem.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 7410259SAndrew.Bardsley@arm.comsystem.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 7510259SAndrew.Bardsley@arm.comsystem.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 7610259SAndrew.Bardsley@arm.comsystem.cpu.fetch.rateDist::total 907433762 # Number of instructions fetched each cycle (Total) 7710259SAndrew.Bardsley@arm.comsystem.cpu.fetch.branchRate 0.245180 # Number of branch fetches per cycle 7810259SAndrew.Bardsley@arm.comsystem.cpu.fetch.rate 1.371636 # Number of inst fetches per cycle 7910259SAndrew.Bardsley@arm.comsystem.cpu.decode.IdleCycles 253860681 # Number of cycles decode is idle 8010259SAndrew.Bardsley@arm.comsystem.cpu.decode.BlockedCycles 190389456 # Number of cycles decode is blocked 8110259SAndrew.Bardsley@arm.comsystem.cpu.decode.RunCycles 329095586 # Number of cycles decode is running 8210259SAndrew.Bardsley@arm.comsystem.cpu.decode.UnblockCycles 50061804 # Number of cycles decode is unblocking 8310259SAndrew.Bardsley@arm.comsystem.cpu.decode.SquashCycles 84026235 # Number of cycles decode is squashing 8410259SAndrew.Bardsley@arm.comsystem.cpu.decode.DecodedInsts 2290781397 # Number of instructions handled by decode 8510259SAndrew.Bardsley@arm.comsystem.cpu.decode.SquashedInsts 2 # Number of squashed instructions handled by decode 8610259SAndrew.Bardsley@arm.comsystem.cpu.rename.SquashCycles 84026235 # Number of cycles rename is squashing 8710259SAndrew.Bardsley@arm.comsystem.cpu.rename.IdleCycles 290493220 # Number of cycles rename is idle 8810259SAndrew.Bardsley@arm.comsystem.cpu.rename.BlockCycles 45042707 # Number of cycles rename is blocking 8910259SAndrew.Bardsley@arm.comsystem.cpu.rename.serializeStallCycles 15282 # count of cycles rename stalled for serializing inst 9010259SAndrew.Bardsley@arm.comsystem.cpu.rename.RunCycles 340016370 # Number of cycles rename is running 9110259SAndrew.Bardsley@arm.comsystem.cpu.rename.UnblockCycles 147839948 # Number of cycles rename is unblocking 9210259SAndrew.Bardsley@arm.comsystem.cpu.rename.RenamedInsts 2240790840 # Number of instructions processed by rename 9310259SAndrew.Bardsley@arm.comsystem.cpu.rename.ROBFullEvents 1987 # Number of times rename has blocked due to ROB full 9410259SAndrew.Bardsley@arm.comsystem.cpu.rename.IQFullEvents 24419621 # Number of times rename has blocked due to IQ full 9510259SAndrew.Bardsley@arm.comsystem.cpu.rename.LSQFullEvents 107426362 # Number of times rename has blocked due to LSQ full 9610259SAndrew.Bardsley@arm.comsystem.cpu.rename.FullRegisterEvents 12159 # Number of times there has been no free registers 9710259SAndrew.Bardsley@arm.comsystem.cpu.rename.RenamedOperands 2887400396 # Number of destination operands rename has renamed 9810259SAndrew.Bardsley@arm.comsystem.cpu.rename.RenameLookups 6494628948 # Number of register rename lookups that rename has made 9910259SAndrew.Bardsley@arm.comsystem.cpu.rename.int_rename_lookups 6493753174 # Number of integer rename lookups 10010259SAndrew.Bardsley@arm.comsystem.cpu.rename.fp_rename_lookups 875774 # Number of floating rename lookups 10110259SAndrew.Bardsley@arm.comsystem.cpu.rename.CommittedMaps 1993077484 # Number of HB maps that are committed 10210259SAndrew.Bardsley@arm.comsystem.cpu.rename.UndoneMaps 894322912 # Number of HB maps that are undone due to squashing 10310259SAndrew.Bardsley@arm.comsystem.cpu.rename.serializingInsts 1296 # count of serializing insts renamed 10410259SAndrew.Bardsley@arm.comsystem.cpu.rename.tempSerializingInsts 1278 # count of temporary serializing insts renamed 10510259SAndrew.Bardsley@arm.comsystem.cpu.rename.skidInsts 351952477 # count of insts added to the skid buffer 10610259SAndrew.Bardsley@arm.comsystem.cpu.memDep0.insertedLoads 540247389 # Number of loads inserted to the mem dependence unit. 10710259SAndrew.Bardsley@arm.comsystem.cpu.memDep0.insertedStores 217453734 # Number of stores inserted to the mem dependence unit. 10810259SAndrew.Bardsley@arm.comsystem.cpu.memDep0.conflictingLoads 211358657 # Number of conflicting loads. 10910259SAndrew.Bardsley@arm.comsystem.cpu.memDep0.conflictingStores 61297047 # Number of conflicting stores. 11010259SAndrew.Bardsley@arm.comsystem.cpu.iq.iqInstsAdded 2143407595 # Number of instructions added to the IQ (excludes non-spec) 11110259SAndrew.Bardsley@arm.comsystem.cpu.iq.iqNonSpecInstsAdded 68408 # Number of non-speculative instructions added to the IQ 11210259SAndrew.Bardsley@arm.comsystem.cpu.iq.iqInstsIssued 1846659650 # Number of instructions issued 11310259SAndrew.Bardsley@arm.comsystem.cpu.iq.iqSquashedInstsIssued 1592160 # Number of squashed instructions issued 11410259SAndrew.Bardsley@arm.comsystem.cpu.iq.iqSquashedInstsExamined 612815347 # Number of squashed instructions iterated over during squash; mainly for profiling 11510259SAndrew.Bardsley@arm.comsystem.cpu.iq.iqSquashedOperandsExamined 1231279567 # Number of squashed operands that are examined and possibly removed from graph 11610259SAndrew.Bardsley@arm.comsystem.cpu.iq.iqSquashedNonSpecRemoved 67855 # Number of squashed non-spec instructions that were removed 11710259SAndrew.Bardsley@arm.comsystem.cpu.iq.issued_per_cycle::samples 907433762 # Number of insts issued each cycle 11810259SAndrew.Bardsley@arm.comsystem.cpu.iq.issued_per_cycle::mean 2.035035 # Number of insts issued each cycle 11910259SAndrew.Bardsley@arm.comsystem.cpu.iq.issued_per_cycle::stdev 1.801518 # Number of insts issued each cycle 12010259SAndrew.Bardsley@arm.comsystem.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 12113449Sgabeblack@google.comsystem.cpu.iq.issued_per_cycle::0 248935467 27.43% 27.43% # Number of insts issued each cycle 12213449Sgabeblack@google.comsystem.cpu.iq.issued_per_cycle::1 159182837 17.54% 44.97% # Number of insts issued each cycle 12313449Sgabeblack@google.comsystem.cpu.iq.issued_per_cycle::2 153661987 16.93% 61.91% # Number of insts issued each cycle 12413449Sgabeblack@google.comsystem.cpu.iq.issued_per_cycle::3 149232137 16.45% 78.35% # Number of insts issued each cycle 12513449Sgabeblack@google.comsystem.cpu.iq.issued_per_cycle::4 98738940 10.88% 89.24% # Number of insts issued each cycle 12610259SAndrew.Bardsley@arm.comsystem.cpu.iq.issued_per_cycle::5 59680898 6.58% 95.81% # Number of insts issued each cycle 12710259SAndrew.Bardsley@arm.comsystem.cpu.iq.issued_per_cycle::6 27969436 3.08% 98.89% # Number of insts issued each cycle 12810259SAndrew.Bardsley@arm.comsystem.cpu.iq.issued_per_cycle::7 8976918 0.99% 99.88% # Number of insts issued each cycle 12910259SAndrew.Bardsley@arm.comsystem.cpu.iq.issued_per_cycle::8 1055142 0.12% 100.00% # Number of insts issued each cycle 13010259SAndrew.Bardsley@arm.comsystem.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 13110259SAndrew.Bardsley@arm.comsystem.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 13210259SAndrew.Bardsley@arm.comsystem.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 13310259SAndrew.Bardsley@arm.comsystem.cpu.iq.issued_per_cycle::total 907433762 # Number of insts issued each cycle 13410259SAndrew.Bardsley@arm.comsystem.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 13510259SAndrew.Bardsley@arm.comsystem.cpu.iq.fu_full::IntAlu 2635361 18.49% 18.49% # attempts to use FU when none available 13610259SAndrew.Bardsley@arm.comsystem.cpu.iq.fu_full::IntMult 0 0.00% 18.49% # attempts to use FU when none available 13710259SAndrew.Bardsley@arm.comsystem.cpu.iq.fu_full::IntDiv 0 0.00% 18.49% # attempts to use FU when none available 13810259SAndrew.Bardsley@arm.comsystem.cpu.iq.fu_full::FloatAdd 0 0.00% 18.49% # attempts to use FU when none available 13910259SAndrew.Bardsley@arm.comsystem.cpu.iq.fu_full::FloatCmp 0 0.00% 18.49% # attempts to use FU when none available 14010259SAndrew.Bardsley@arm.comsystem.cpu.iq.fu_full::FloatCvt 0 0.00% 18.49% # attempts to use FU when none available 14110259SAndrew.Bardsley@arm.comsystem.cpu.iq.fu_full::FloatMult 0 0.00% 18.49% # attempts to use FU when none available 14210259SAndrew.Bardsley@arm.comsystem.cpu.iq.fu_full::FloatDiv 0 0.00% 18.49% # attempts to use FU when none available 14310259SAndrew.Bardsley@arm.comsystem.cpu.iq.fu_full::FloatSqrt 0 0.00% 18.49% # attempts to use FU when none available 14410259SAndrew.Bardsley@arm.comsystem.cpu.iq.fu_full::SimdAdd 0 0.00% 18.49% # attempts to use FU when none available 14510259SAndrew.Bardsley@arm.comsystem.cpu.iq.fu_full::SimdAddAcc 0 0.00% 18.49% # attempts to use FU when none available 14610259SAndrew.Bardsley@arm.comsystem.cpu.iq.fu_full::SimdAlu 0 0.00% 18.49% # attempts to use FU when none available 14710259SAndrew.Bardsley@arm.comsystem.cpu.iq.fu_full::SimdCmp 0 0.00% 18.49% # attempts to use FU when none available 14810259SAndrew.Bardsley@arm.comsystem.cpu.iq.fu_full::SimdCvt 0 0.00% 18.49% # attempts to use FU when none available 14910259SAndrew.Bardsley@arm.comsystem.cpu.iq.fu_full::SimdMisc 0 0.00% 18.49% # attempts to use FU when none available 15010259SAndrew.Bardsley@arm.comsystem.cpu.iq.fu_full::SimdMult 0 0.00% 18.49% # attempts to use FU when none available 15110259SAndrew.Bardsley@arm.comsystem.cpu.iq.fu_full::SimdMultAcc 0 0.00% 18.49% # attempts to use FU when none available 15210259SAndrew.Bardsley@arm.comsystem.cpu.iq.fu_full::SimdShift 0 0.00% 18.49% # attempts to use FU when none available 15310259SAndrew.Bardsley@arm.comsystem.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.49% # attempts to use FU when none available 15410259SAndrew.Bardsley@arm.comsystem.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.49% # attempts to use FU when none available 15510259SAndrew.Bardsley@arm.comsystem.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 18.49% # attempts to use FU when none available 15610259SAndrew.Bardsley@arm.comsystem.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.49% # attempts to use FU when none available 15710259SAndrew.Bardsley@arm.comsystem.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.49% # attempts to use FU when none available 15810259SAndrew.Bardsley@arm.comsystem.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 18.49% # attempts to use FU when none available 15910259SAndrew.Bardsley@arm.comsystem.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 18.49% # attempts to use FU when none available 16010259SAndrew.Bardsley@arm.comsystem.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 18.49% # attempts to use FU when none available 16110259SAndrew.Bardsley@arm.comsystem.cpu.iq.fu_full::SimdFloatMult 0 0.00% 18.49% # attempts to use FU when none available 16210259SAndrew.Bardsley@arm.comsystem.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.49% # attempts to use FU when none available 16310259SAndrew.Bardsley@arm.comsystem.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 18.49% # attempts to use FU when none available 16410259SAndrew.Bardsley@arm.comsystem.cpu.iq.fu_full::MemRead 8379879 58.81% 77.30% # attempts to use FU when none available 16510259SAndrew.Bardsley@arm.comsystem.cpu.iq.fu_full::MemWrite 3234007 22.70% 100.00% # attempts to use FU when none available 16610259SAndrew.Bardsley@arm.comsystem.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 16710259SAndrew.Bardsley@arm.comsystem.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 16810259SAndrew.Bardsley@arm.comsystem.cpu.iq.FU_type_0::No_OpClass 2716087 0.15% 0.15% # Type of FU issued 16910259SAndrew.Bardsley@arm.comsystem.cpu.iq.FU_type_0::IntAlu 1219498090 66.04% 66.19% # Type of FU issued 17010259SAndrew.Bardsley@arm.comsystem.cpu.iq.FU_type_0::IntMult 0 0.00% 66.19% # Type of FU issued 17110259SAndrew.Bardsley@arm.comsystem.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.19% # Type of FU issued 17210259SAndrew.Bardsley@arm.comsystem.cpu.iq.FU_type_0::FloatAdd 0 0.00% 66.19% # Type of FU issued 17310259SAndrew.Bardsley@arm.comsystem.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.19% # Type of FU issued 17410259SAndrew.Bardsley@arm.comsystem.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.19% # Type of FU issued 17510259SAndrew.Bardsley@arm.comsystem.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.19% # Type of FU issued 17610259SAndrew.Bardsley@arm.comsystem.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.19% # Type of FU issued 17710259SAndrew.Bardsley@arm.comsystem.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.19% # Type of FU issued 17810259SAndrew.Bardsley@arm.comsystem.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.19% # Type of FU issued 17910259SAndrew.Bardsley@arm.comsystem.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.19% # Type of FU issued 18010259SAndrew.Bardsley@arm.comsystem.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.19% # Type of FU issued 18110259SAndrew.Bardsley@arm.comsystem.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.19% # Type of FU issued 18210259SAndrew.Bardsley@arm.comsystem.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.19% # Type of FU issued 18310259SAndrew.Bardsley@arm.comsystem.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.19% # Type of FU issued 18410259SAndrew.Bardsley@arm.comsystem.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.19% # Type of FU issued 18510259SAndrew.Bardsley@arm.comsystem.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.19% # Type of FU issued 18610259SAndrew.Bardsley@arm.comsystem.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.19% # Type of FU issued 18710259SAndrew.Bardsley@arm.comsystem.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.19% # Type of FU issued 18810259SAndrew.Bardsley@arm.comsystem.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.19% # Type of FU issued 18910259SAndrew.Bardsley@arm.comsystem.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.19% # Type of FU issued 19010259SAndrew.Bardsley@arm.comsystem.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.19% # Type of FU issued 19110259SAndrew.Bardsley@arm.comsystem.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.19% # Type of FU issued 19210259SAndrew.Bardsley@arm.comsystem.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.19% # Type of FU issued 19310259SAndrew.Bardsley@arm.comsystem.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.19% # Type of FU issued 19410259SAndrew.Bardsley@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.19% # Type of FU issued 19510259SAndrew.Bardsley@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.19% # Type of FU issued 19610259SAndrew.Bardsley@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.19% # Type of FU issued 19710259SAndrew.Bardsley@arm.comsystem.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.19% # Type of FU issued 19810259SAndrew.Bardsley@arm.comsystem.cpu.iq.FU_type_0::MemRead 447052191 24.21% 90.39% # Type of FU issued 19910259SAndrew.Bardsley@arm.comsystem.cpu.iq.FU_type_0::MemWrite 177393282 9.61% 100.00% # Type of FU issued 20010259SAndrew.Bardsley@arm.comsystem.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 20110259SAndrew.Bardsley@arm.comsystem.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 20210259SAndrew.Bardsley@arm.comsystem.cpu.iq.FU_type_0::total 1846659650 # Type of FU issued 20310259SAndrew.Bardsley@arm.comsystem.cpu.iq.rate 2.005031 # Inst issue rate 20410259SAndrew.Bardsley@arm.comsystem.cpu.iq.fu_busy_cnt 14249247 # FU busy when requested 20510259SAndrew.Bardsley@arm.comsystem.cpu.iq.fu_busy_rate 0.007716 # FU busy rate (busy events/executed inst) 20610259SAndrew.Bardsley@arm.comsystem.cpu.iq.int_inst_queue_reads 4616586705 # Number of integer instruction queue reads 20710259SAndrew.Bardsley@arm.comsystem.cpu.iq.int_inst_queue_writes 2756248953 # Number of integer instruction queue writes 20810259SAndrew.Bardsley@arm.comsystem.cpu.iq.int_inst_queue_wakeup_accesses 1806266388 # Number of integer instruction queue wakeup accesses 20910259SAndrew.Bardsley@arm.comsystem.cpu.iq.fp_inst_queue_reads 7764 # Number of floating instruction queue reads 21010259SAndrew.Bardsley@arm.comsystem.cpu.iq.fp_inst_queue_writes 302326 # Number of floating instruction queue writes 21110259SAndrew.Bardsley@arm.comsystem.cpu.iq.fp_inst_queue_wakeup_accesses 267 # Number of floating instruction queue wakeup accesses 21210259SAndrew.Bardsley@arm.comsystem.cpu.iq.int_alu_accesses 1858190079 # Number of integer alu accesses 21310259SAndrew.Bardsley@arm.comsystem.cpu.iq.fp_alu_accesses 2731 # Number of floating point alu accesses 21410259SAndrew.Bardsley@arm.comsystem.cpu.iew.lsq.thread0.forwLoads 168174825 # Number of loads that had data forwarded from stores 21510259SAndrew.Bardsley@arm.comsystem.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 21610259SAndrew.Bardsley@arm.comsystem.cpu.iew.lsq.thread0.squashedLoads 156145229 # Number of loads squashed 21710259SAndrew.Bardsley@arm.comsystem.cpu.iew.lsq.thread0.ignoredResponses 432412 # Number of memory responses ignored because the instruction is squashed 21810259SAndrew.Bardsley@arm.comsystem.cpu.iew.lsq.thread0.memOrderViolation 271180 # Number of memory ordering violations 21910259SAndrew.Bardsley@arm.comsystem.cpu.iew.lsq.thread0.squashedStores 68293794 # Number of stores squashed 22010259SAndrew.Bardsley@arm.comsystem.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 22110259SAndrew.Bardsley@arm.comsystem.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 22210259SAndrew.Bardsley@arm.comsystem.cpu.iew.lsq.thread0.rescheduledLoads 7298 # Number of loads that were rescheduled 22310259SAndrew.Bardsley@arm.comsystem.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked 22410259SAndrew.Bardsley@arm.comsystem.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 22510259SAndrew.Bardsley@arm.comsystem.cpu.iew.iewSquashCycles 84026235 # Number of cycles IEW is squashing 22610259SAndrew.Bardsley@arm.comsystem.cpu.iew.iewBlockCycles 6572859 # Number of cycles IEW is blocking 22710259SAndrew.Bardsley@arm.comsystem.cpu.iew.iewUnblockCycles 1284585 # Number of cycles IEW is unblocking 22810259SAndrew.Bardsley@arm.comsystem.cpu.iew.iewDispatchedInsts 2143476003 # Number of instructions dispatched to IQ 22910259SAndrew.Bardsley@arm.comsystem.cpu.iew.iewDispSquashedInsts 2866964 # Number of squashed instructions skipped by dispatch 23010259SAndrew.Bardsley@arm.comsystem.cpu.iew.iewDispLoadInsts 540247389 # Number of dispatched load instructions 23110259SAndrew.Bardsley@arm.comsystem.cpu.iew.iewDispStoreInsts 217453979 # Number of dispatched store instructions 23210259SAndrew.Bardsley@arm.comsystem.cpu.iew.iewDispNonSpecInsts 5268 # Number of dispatched non-speculative instructions 23310259SAndrew.Bardsley@arm.comsystem.cpu.iew.iewIQFullEvents 966767 # Number of times the IQ has become full, causing a stall 23410259SAndrew.Bardsley@arm.comsystem.cpu.iew.iewLSQFullEvents 66701 # Number of times the LSQ has become full, causing a stall 23510259SAndrew.Bardsley@arm.comsystem.cpu.iew.memOrderViolationEvents 271180 # Number of memory order violations 23610259SAndrew.Bardsley@arm.comsystem.cpu.iew.predictedTakenIncorrect 10086388 # Number of branches that were predicted taken incorrectly 23710259SAndrew.Bardsley@arm.comsystem.cpu.iew.predictedNotTakenIncorrect 5256785 # Number of branches that were predicted not taken incorrectly 23810259SAndrew.Bardsley@arm.comsystem.cpu.iew.branchMispredicts 15343173 # Number of branch mispredicts detected at execute 23910259SAndrew.Bardsley@arm.comsystem.cpu.iew.iewExecutedInsts 1818783281 # Number of executed instructions 24010259SAndrew.Bardsley@arm.comsystem.cpu.iew.iewExecLoadInsts 438633483 # Number of load instructions executed 24110259SAndrew.Bardsley@arm.comsystem.cpu.iew.iewExecSquashedInsts 27876369 # Number of squashed instructions skipped in execute 24210259SAndrew.Bardsley@arm.comsystem.cpu.iew.exec_swp 0 # number of swp insts executed 24310259SAndrew.Bardsley@arm.comsystem.cpu.iew.exec_nop 0 # number of nop insts executed 24410259SAndrew.Bardsley@arm.comsystem.cpu.iew.exec_refs 610463331 # number of memory reference insts executed 24510259SAndrew.Bardsley@arm.comsystem.cpu.iew.exec_branches 170879553 # Number of branches executed 24610259SAndrew.Bardsley@arm.comsystem.cpu.iew.exec_stores 171829848 # Number of stores executed 24710259SAndrew.Bardsley@arm.comsystem.cpu.iew.exec_rate 1.974764 # Inst execution rate 24810259SAndrew.Bardsley@arm.comsystem.cpu.iew.wb_sent 1813538943 # cumulative count of insts sent to commit 24910259SAndrew.Bardsley@arm.comsystem.cpu.iew.wb_count 1806266655 # cumulative count of insts written-back 25010259SAndrew.Bardsley@arm.comsystem.cpu.iew.wb_producers 1378870906 # num instructions producing a value 25110259SAndrew.Bardsley@arm.comsystem.cpu.iew.wb_consumers 2933493121 # num instructions consuming a value 25210259SAndrew.Bardsley@arm.comsystem.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 25310259SAndrew.Bardsley@arm.comsystem.cpu.iew.wb_rate 1.961174 # insts written-back per cycle 25410259SAndrew.Bardsley@arm.comsystem.cpu.iew.wb_fanout 0.470044 # average fanout of values written-back 25510259SAndrew.Bardsley@arm.comsystem.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 25610259SAndrew.Bardsley@arm.comsystem.cpu.commit.commitCommittedInsts 826877144 # The number of committed instructions 25710259SAndrew.Bardsley@arm.comsystem.cpu.commit.commitCommittedOps 1528988756 # The number of committed instructions 25810259SAndrew.Bardsley@arm.comsystem.cpu.commit.commitSquashedInsts 614512471 # The number of squashed insts skipped by commit 25910259SAndrew.Bardsley@arm.comsystem.cpu.commit.commitNonSpecStalls 553 # The number of times commit has been forced to stall to communicate backwards 26010259SAndrew.Bardsley@arm.comsystem.cpu.commit.branchMispredicts 14337883 # The number of times a branch was mispredicted 26110259SAndrew.Bardsley@arm.comsystem.cpu.commit.committed_per_cycle::samples 823407527 # Number of insts commited each cycle 26210259SAndrew.Bardsley@arm.comsystem.cpu.commit.committed_per_cycle::mean 1.856904 # Number of insts commited each cycle 26310259SAndrew.Bardsley@arm.comsystem.cpu.commit.committed_per_cycle::stdev 2.319659 # Number of insts commited each cycle 26410259SAndrew.Bardsley@arm.comsystem.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 26510259SAndrew.Bardsley@arm.comsystem.cpu.commit.committed_per_cycle::0 305105182 37.05% 37.05% # Number of insts commited each cycle 26610259SAndrew.Bardsley@arm.comsystem.cpu.commit.committed_per_cycle::1 205650111 24.98% 62.03% # Number of insts commited each cycle 26710259SAndrew.Bardsley@arm.comsystem.cpu.commit.committed_per_cycle::2 74228668 9.01% 71.04% # Number of insts commited each cycle 26810259SAndrew.Bardsley@arm.comsystem.cpu.commit.committed_per_cycle::3 96597559 11.73% 82.78% # Number of insts commited each cycle 26910259SAndrew.Bardsley@arm.comsystem.cpu.commit.committed_per_cycle::4 29968597 3.64% 86.42% # Number of insts commited each cycle 27010259SAndrew.Bardsley@arm.comsystem.cpu.commit.committed_per_cycle::5 28751826 3.49% 89.91% # Number of insts commited each cycle 27110259SAndrew.Bardsley@arm.comsystem.cpu.commit.committed_per_cycle::6 15821579 1.92% 91.83% # Number of insts commited each cycle 27210259SAndrew.Bardsley@arm.comsystem.cpu.commit.committed_per_cycle::7 11746400 1.43% 93.26% # Number of insts commited each cycle 27310259SAndrew.Bardsley@arm.comsystem.cpu.commit.committed_per_cycle::8 55537605 6.74% 100.00% # Number of insts commited each cycle 27410259SAndrew.Bardsley@arm.comsystem.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 27510259SAndrew.Bardsley@arm.comsystem.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 27610259SAndrew.Bardsley@arm.comsystem.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 27710259SAndrew.Bardsley@arm.comsystem.cpu.commit.committed_per_cycle::total 823407527 # Number of insts commited each cycle 27810259SAndrew.Bardsley@arm.comsystem.cpu.commit.committedInsts 826877144 # Number of instructions committed 27910259SAndrew.Bardsley@arm.comsystem.cpu.commit.committedOps 1528988756 # Number of ops (including micro ops) committed 28010259SAndrew.Bardsley@arm.comsystem.cpu.commit.swp_count 0 # Number of s/w prefetches committed 28110259SAndrew.Bardsley@arm.comsystem.cpu.commit.refs 533262345 # Number of memory references committed 28210259SAndrew.Bardsley@arm.comsystem.cpu.commit.loads 384102160 # Number of loads committed 28310259SAndrew.Bardsley@arm.comsystem.cpu.commit.membars 0 # Number of memory barriers committed 28410259SAndrew.Bardsley@arm.comsystem.cpu.commit.branches 149758588 # Number of branches committed 28510259SAndrew.Bardsley@arm.comsystem.cpu.commit.fp_insts 0 # Number of committed floating point instructions. 28610259SAndrew.Bardsley@arm.comsystem.cpu.commit.int_insts 1528317614 # Number of committed integer instructions. 28710259SAndrew.Bardsley@arm.comsystem.cpu.commit.function_calls 0 # Number of function calls committed. 28810259SAndrew.Bardsley@arm.comsystem.cpu.commit.bw_lim_events 55537605 # number cycles where commit BW limit reached 28910259SAndrew.Bardsley@arm.comsystem.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 29010259SAndrew.Bardsley@arm.comsystem.cpu.rob.rob_reads 2911371149 # The number of ROB reads 29110259SAndrew.Bardsley@arm.comsystem.cpu.rob.rob_writes 4371143864 # The number of ROB writes 29210259SAndrew.Bardsley@arm.comsystem.cpu.timesIdled 309440 # Number of times that the entire CPU went into an idle state and unscheduled itself 29310259SAndrew.Bardsley@arm.comsystem.cpu.idleCycles 13579339 # Total number of cycles that the CPU has spent unscheduled due to idling 29410259SAndrew.Bardsley@arm.comsystem.cpu.committedInsts 826877144 # Number of Instructions Simulated 29510259SAndrew.Bardsley@arm.comsystem.cpu.committedOps 1528988756 # Number of Ops (including micro ops) Simulated 29610259SAndrew.Bardsley@arm.comsystem.cpu.committedInsts_total 826877144 # Number of Instructions Simulated 29710259SAndrew.Bardsley@arm.comsystem.cpu.cpi 1.113845 # CPI: Cycles Per Instruction 29810259SAndrew.Bardsley@arm.comsystem.cpu.cpi_total 1.113845 # CPI: Total CPI of All Threads 29910259SAndrew.Bardsley@arm.comsystem.cpu.ipc 0.897791 # IPC: Instructions Per Cycle 30010259SAndrew.Bardsley@arm.comsystem.cpu.ipc_total 0.897791 # IPC: Total IPC of All Threads 30110259SAndrew.Bardsley@arm.comsystem.cpu.int_regfile_reads 4004246874 # number of integer regfile reads 30210259SAndrew.Bardsley@arm.comsystem.cpu.int_regfile_writes 2286313998 # number of integer regfile writes 30310259SAndrew.Bardsley@arm.comsystem.cpu.fp_regfile_reads 266 # number of floating regfile reads 30410259SAndrew.Bardsley@arm.comsystem.cpu.fp_regfile_writes 1 # number of floating regfile writes 30510259SAndrew.Bardsley@arm.comsystem.cpu.misc_regfile_reads 1001920728 # number of misc regfile reads 30610259SAndrew.Bardsley@arm.comsystem.cpu.icache.replacements 5588 # number of replacements 30710259SAndrew.Bardsley@arm.comsystem.cpu.icache.tagsinuse 1044.044381 # Cycle average of tags in use 30810259SAndrew.Bardsley@arm.comsystem.cpu.icache.total_refs 183312403 # Total number of references to valid blocks. 30910259SAndrew.Bardsley@arm.comsystem.cpu.icache.sampled_refs 7204 # Sample count of references to valid blocks. 31010259SAndrew.Bardsley@arm.comsystem.cpu.icache.avg_refs 25445.919350 # Average number of references to valid blocks. 31110259SAndrew.Bardsley@arm.comsystem.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 31210259SAndrew.Bardsley@arm.comsystem.cpu.icache.occ_blocks::cpu.inst 1044.044381 # Average occupied blocks per requestor 31310259SAndrew.Bardsley@arm.comsystem.cpu.icache.occ_percent::cpu.inst 0.509787 # Average percentage of cache occupancy 31410259SAndrew.Bardsley@arm.comsystem.cpu.icache.occ_percent::total 0.509787 # Average percentage of cache occupancy 31510259SAndrew.Bardsley@arm.comsystem.cpu.icache.ReadReq_hits::cpu.inst 183329342 # number of ReadReq hits 31610259SAndrew.Bardsley@arm.comsystem.cpu.icache.ReadReq_hits::total 183329342 # number of ReadReq hits 31710259SAndrew.Bardsley@arm.comsystem.cpu.icache.demand_hits::cpu.inst 183329342 # number of demand (read+write) hits 31810259SAndrew.Bardsley@arm.comsystem.cpu.icache.demand_hits::total 183329342 # number of demand (read+write) hits 31910259SAndrew.Bardsley@arm.comsystem.cpu.icache.overall_hits::cpu.inst 183329342 # number of overall hits 32010259SAndrew.Bardsley@arm.comsystem.cpu.icache.overall_hits::total 183329342 # number of overall hits 32110259SAndrew.Bardsley@arm.comsystem.cpu.icache.ReadReq_misses::cpu.inst 222424 # number of ReadReq misses 32210259SAndrew.Bardsley@arm.comsystem.cpu.icache.ReadReq_misses::total 222424 # number of ReadReq misses 32310259SAndrew.Bardsley@arm.comsystem.cpu.icache.demand_misses::cpu.inst 222424 # number of demand (read+write) misses 32410259SAndrew.Bardsley@arm.comsystem.cpu.icache.demand_misses::total 222424 # number of demand (read+write) misses 32510259SAndrew.Bardsley@arm.comsystem.cpu.icache.overall_misses::cpu.inst 222424 # number of overall misses 32610259SAndrew.Bardsley@arm.comsystem.cpu.icache.overall_misses::total 222424 # number of overall misses 32710259SAndrew.Bardsley@arm.comsystem.cpu.icache.ReadReq_miss_latency::cpu.inst 1554709500 # number of ReadReq miss cycles 32810259SAndrew.Bardsley@arm.comsystem.cpu.icache.ReadReq_miss_latency::total 1554709500 # number of ReadReq miss cycles 32910259SAndrew.Bardsley@arm.comsystem.cpu.icache.demand_miss_latency::cpu.inst 1554709500 # number of demand (read+write) miss cycles 33010259SAndrew.Bardsley@arm.comsystem.cpu.icache.demand_miss_latency::total 1554709500 # number of demand (read+write) miss cycles 33110259SAndrew.Bardsley@arm.comsystem.cpu.icache.overall_miss_latency::cpu.inst 1554709500 # number of overall miss cycles 33210259SAndrew.Bardsley@arm.comsystem.cpu.icache.overall_miss_latency::total 1554709500 # number of overall miss cycles 33310259SAndrew.Bardsley@arm.comsystem.cpu.icache.ReadReq_accesses::cpu.inst 183551766 # number of ReadReq accesses(hits+misses) 33410259SAndrew.Bardsley@arm.comsystem.cpu.icache.ReadReq_accesses::total 183551766 # number of ReadReq accesses(hits+misses) 33510259SAndrew.Bardsley@arm.comsystem.cpu.icache.demand_accesses::cpu.inst 183551766 # number of demand (read+write) accesses 33610259SAndrew.Bardsley@arm.comsystem.cpu.icache.demand_accesses::total 183551766 # number of demand (read+write) accesses 33710259SAndrew.Bardsley@arm.comsystem.cpu.icache.overall_accesses::cpu.inst 183551766 # number of overall (read+write) accesses 33810259SAndrew.Bardsley@arm.comsystem.cpu.icache.overall_accesses::total 183551766 # number of overall (read+write) accesses 33910259SAndrew.Bardsley@arm.comsystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001212 # miss rate for ReadReq accesses 34010259SAndrew.Bardsley@arm.comsystem.cpu.icache.ReadReq_miss_rate::total 0.001212 # miss rate for ReadReq accesses 34110259SAndrew.Bardsley@arm.comsystem.cpu.icache.demand_miss_rate::cpu.inst 0.001212 # miss rate for demand accesses 34210259SAndrew.Bardsley@arm.comsystem.cpu.icache.demand_miss_rate::total 0.001212 # miss rate for demand accesses 34310259SAndrew.Bardsley@arm.comsystem.cpu.icache.overall_miss_rate::cpu.inst 0.001212 # miss rate for overall accesses 34410259SAndrew.Bardsley@arm.comsystem.cpu.icache.overall_miss_rate::total 0.001212 # miss rate for overall accesses 34510259SAndrew.Bardsley@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6989.845970 # average ReadReq miss latency 34610259SAndrew.Bardsley@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::total 6989.845970 # average ReadReq miss latency 34710259SAndrew.Bardsley@arm.comsystem.cpu.icache.demand_avg_miss_latency::cpu.inst 6989.845970 # average overall miss latency 34810259SAndrew.Bardsley@arm.comsystem.cpu.icache.demand_avg_miss_latency::total 6989.845970 # average overall miss latency 34910259SAndrew.Bardsley@arm.comsystem.cpu.icache.overall_avg_miss_latency::cpu.inst 6989.845970 # average overall miss latency 35010259SAndrew.Bardsley@arm.comsystem.cpu.icache.overall_avg_miss_latency::total 6989.845970 # average overall miss latency 35110259SAndrew.Bardsley@arm.comsystem.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 35210259SAndrew.Bardsley@arm.comsystem.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 35310259SAndrew.Bardsley@arm.comsystem.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 35410259SAndrew.Bardsley@arm.comsystem.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 35510259SAndrew.Bardsley@arm.comsystem.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 35610259SAndrew.Bardsley@arm.comsystem.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 35710259SAndrew.Bardsley@arm.comsystem.cpu.icache.fast_writes 0 # number of fast writes performed 35810259SAndrew.Bardsley@arm.comsystem.cpu.icache.cache_copies 0 # number of cache copies performed 35910259SAndrew.Bardsley@arm.comsystem.cpu.icache.ReadReq_mshr_hits::cpu.inst 1671 # number of ReadReq MSHR hits 36010259SAndrew.Bardsley@arm.comsystem.cpu.icache.ReadReq_mshr_hits::total 1671 # number of ReadReq MSHR hits 36110259SAndrew.Bardsley@arm.comsystem.cpu.icache.demand_mshr_hits::cpu.inst 1671 # number of demand (read+write) MSHR hits 36210259SAndrew.Bardsley@arm.comsystem.cpu.icache.demand_mshr_hits::total 1671 # number of demand (read+write) MSHR hits 36310259SAndrew.Bardsley@arm.comsystem.cpu.icache.overall_mshr_hits::cpu.inst 1671 # number of overall MSHR hits 36410259SAndrew.Bardsley@arm.comsystem.cpu.icache.overall_mshr_hits::total 1671 # number of overall MSHR hits 36510259SAndrew.Bardsley@arm.comsystem.cpu.icache.ReadReq_mshr_misses::cpu.inst 220753 # number of ReadReq MSHR misses 36610259SAndrew.Bardsley@arm.comsystem.cpu.icache.ReadReq_mshr_misses::total 220753 # number of ReadReq MSHR misses 36710259SAndrew.Bardsley@arm.comsystem.cpu.icache.demand_mshr_misses::cpu.inst 220753 # number of demand (read+write) MSHR misses 36810259SAndrew.Bardsley@arm.comsystem.cpu.icache.demand_mshr_misses::total 220753 # number of demand (read+write) MSHR misses 36910259SAndrew.Bardsley@arm.comsystem.cpu.icache.overall_mshr_misses::cpu.inst 220753 # number of overall MSHR misses 37010259SAndrew.Bardsley@arm.comsystem.cpu.icache.overall_mshr_misses::total 220753 # number of overall MSHR misses 37110259SAndrew.Bardsley@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 807012500 # number of ReadReq MSHR miss cycles 37210259SAndrew.Bardsley@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::total 807012500 # number of ReadReq MSHR miss cycles 37310259SAndrew.Bardsley@arm.comsystem.cpu.icache.demand_mshr_miss_latency::cpu.inst 807012500 # number of demand (read+write) MSHR miss cycles 37410259SAndrew.Bardsley@arm.comsystem.cpu.icache.demand_mshr_miss_latency::total 807012500 # number of demand (read+write) MSHR miss cycles 37510259SAndrew.Bardsley@arm.comsystem.cpu.icache.overall_mshr_miss_latency::cpu.inst 807012500 # number of overall MSHR miss cycles 37610259SAndrew.Bardsley@arm.comsystem.cpu.icache.overall_mshr_miss_latency::total 807012500 # number of overall MSHR miss cycles 37710259SAndrew.Bardsley@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001203 # mshr miss rate for ReadReq accesses 37810259SAndrew.Bardsley@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::total 0.001203 # mshr miss rate for ReadReq accesses 37910259SAndrew.Bardsley@arm.comsystem.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001203 # mshr miss rate for demand accesses 38010259SAndrew.Bardsley@arm.comsystem.cpu.icache.demand_mshr_miss_rate::total 0.001203 # mshr miss rate for demand accesses 38110259SAndrew.Bardsley@arm.comsystem.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001203 # mshr miss rate for overall accesses 38210259SAndrew.Bardsley@arm.comsystem.cpu.icache.overall_mshr_miss_rate::total 0.001203 # mshr miss rate for overall accesses 38310259SAndrew.Bardsley@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 3655.726083 # average ReadReq mshr miss latency 38413475Snikos.nikoleris@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::total 3655.726083 # average ReadReq mshr miss latency 38513475Snikos.nikoleris@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 3655.726083 # average overall mshr miss latency 38610259SAndrew.Bardsley@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::total 3655.726083 # average overall mshr miss latency 38710259SAndrew.Bardsley@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 3655.726083 # average overall mshr miss latency 38810259SAndrew.Bardsley@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::total 3655.726083 # average overall mshr miss latency 38910259SAndrew.Bardsley@arm.comsystem.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 39010259SAndrew.Bardsley@arm.comsystem.cpu.dcache.replacements 2526911 # number of replacements 39110259SAndrew.Bardsley@arm.comsystem.cpu.dcache.tagsinuse 4087.001481 # Cycle average of tags in use 39210259SAndrew.Bardsley@arm.comsystem.cpu.dcache.total_refs 415013959 # Total number of references to valid blocks. 39310259SAndrew.Bardsley@arm.comsystem.cpu.dcache.sampled_refs 2531007 # Sample count of references to valid blocks. 39410259SAndrew.Bardsley@arm.comsystem.cpu.dcache.avg_refs 163.971873 # Average number of references to valid blocks. 39510259SAndrew.Bardsley@arm.comsystem.cpu.dcache.warmup_cycle 2119650000 # Cycle when the warmup percentage was hit. 39610259SAndrew.Bardsley@arm.comsystem.cpu.dcache.occ_blocks::cpu.data 4087.001481 # Average occupied blocks per requestor 39710259SAndrew.Bardsley@arm.comsystem.cpu.dcache.occ_percent::cpu.data 0.997803 # Average percentage of cache occupancy 39810259SAndrew.Bardsley@arm.comsystem.cpu.dcache.occ_percent::total 0.997803 # Average percentage of cache occupancy 39910259SAndrew.Bardsley@arm.comsystem.cpu.dcache.ReadReq_hits::cpu.data 266164816 # number of ReadReq hits 40010259SAndrew.Bardsley@arm.comsystem.cpu.dcache.ReadReq_hits::total 266164816 # number of ReadReq hits 40110259SAndrew.Bardsley@arm.comsystem.cpu.dcache.WriteReq_hits::cpu.data 148172858 # number of WriteReq hits 40210259SAndrew.Bardsley@arm.comsystem.cpu.dcache.WriteReq_hits::total 148172858 # number of WriteReq hits 40310259SAndrew.Bardsley@arm.comsystem.cpu.dcache.demand_hits::cpu.data 414337674 # number of demand (read+write) hits 40410259SAndrew.Bardsley@arm.comsystem.cpu.dcache.demand_hits::total 414337674 # number of demand (read+write) hits 40510259SAndrew.Bardsley@arm.comsystem.cpu.dcache.overall_hits::cpu.data 414337674 # number of overall hits 40610259SAndrew.Bardsley@arm.comsystem.cpu.dcache.overall_hits::total 414337674 # number of overall hits 40710259SAndrew.Bardsley@arm.comsystem.cpu.dcache.ReadReq_misses::cpu.data 2652510 # number of ReadReq misses 40810259SAndrew.Bardsley@arm.comsystem.cpu.dcache.ReadReq_misses::total 2652510 # number of ReadReq misses 40910259SAndrew.Bardsley@arm.comsystem.cpu.dcache.WriteReq_misses::cpu.data 987343 # number of WriteReq misses 41010259SAndrew.Bardsley@arm.comsystem.cpu.dcache.WriteReq_misses::total 987343 # number of WriteReq misses 41110259SAndrew.Bardsley@arm.comsystem.cpu.dcache.demand_misses::cpu.data 3639853 # number of demand (read+write) misses 41210259SAndrew.Bardsley@arm.comsystem.cpu.dcache.demand_misses::total 3639853 # number of demand (read+write) misses 41310259SAndrew.Bardsley@arm.comsystem.cpu.dcache.overall_misses::cpu.data 3639853 # number of overall misses 41410259SAndrew.Bardsley@arm.comsystem.cpu.dcache.overall_misses::total 3639853 # number of overall misses 41510259SAndrew.Bardsley@arm.comsystem.cpu.dcache.ReadReq_miss_latency::cpu.data 36720929000 # number of ReadReq miss cycles 41610259SAndrew.Bardsley@arm.comsystem.cpu.dcache.ReadReq_miss_latency::total 36720929000 # number of ReadReq miss cycles 41710259SAndrew.Bardsley@arm.comsystem.cpu.dcache.WriteReq_miss_latency::cpu.data 18986429000 # number of WriteReq miss cycles 41810259SAndrew.Bardsley@arm.comsystem.cpu.dcache.WriteReq_miss_latency::total 18986429000 # number of WriteReq miss cycles 41910259SAndrew.Bardsley@arm.comsystem.cpu.dcache.demand_miss_latency::cpu.data 55707358000 # number of demand (read+write) miss cycles 42010259SAndrew.Bardsley@arm.comsystem.cpu.dcache.demand_miss_latency::total 55707358000 # number of demand (read+write) miss cycles 42110259SAndrew.Bardsley@arm.comsystem.cpu.dcache.overall_miss_latency::cpu.data 55707358000 # number of overall miss cycles 42210259SAndrew.Bardsley@arm.comsystem.cpu.dcache.overall_miss_latency::total 55707358000 # number of overall miss cycles 42310259SAndrew.Bardsley@arm.comsystem.cpu.dcache.ReadReq_accesses::cpu.data 268817326 # number of ReadReq accesses(hits+misses) 42410259SAndrew.Bardsley@arm.comsystem.cpu.dcache.ReadReq_accesses::total 268817326 # number of ReadReq accesses(hits+misses) 42510259SAndrew.Bardsley@arm.comsystem.cpu.dcache.WriteReq_accesses::cpu.data 149160201 # number of WriteReq accesses(hits+misses) 42610259SAndrew.Bardsley@arm.comsystem.cpu.dcache.WriteReq_accesses::total 149160201 # number of WriteReq accesses(hits+misses) 42710259SAndrew.Bardsley@arm.comsystem.cpu.dcache.demand_accesses::cpu.data 417977527 # number of demand (read+write) accesses 42810259SAndrew.Bardsley@arm.comsystem.cpu.dcache.demand_accesses::total 417977527 # number of demand (read+write) accesses 42910259SAndrew.Bardsley@arm.comsystem.cpu.dcache.overall_accesses::cpu.data 417977527 # number of overall (read+write) accesses 43010259SAndrew.Bardsley@arm.comsystem.cpu.dcache.overall_accesses::total 417977527 # number of overall (read+write) accesses 43110259SAndrew.Bardsley@arm.comsystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009867 # miss rate for ReadReq accesses 43210259SAndrew.Bardsley@arm.comsystem.cpu.dcache.ReadReq_miss_rate::total 0.009867 # miss rate for ReadReq accesses 43310259SAndrew.Bardsley@arm.comsystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006619 # miss rate for WriteReq accesses 43410259SAndrew.Bardsley@arm.comsystem.cpu.dcache.WriteReq_miss_rate::total 0.006619 # miss rate for WriteReq accesses 43510259SAndrew.Bardsley@arm.comsystem.cpu.dcache.demand_miss_rate::cpu.data 0.008708 # miss rate for demand accesses 43610259SAndrew.Bardsley@arm.comsystem.cpu.dcache.demand_miss_rate::total 0.008708 # miss rate for demand accesses 43710259SAndrew.Bardsley@arm.comsystem.cpu.dcache.overall_miss_rate::cpu.data 0.008708 # miss rate for overall accesses 43810259SAndrew.Bardsley@arm.comsystem.cpu.dcache.overall_miss_rate::total 0.008708 # miss rate for overall accesses 43910259SAndrew.Bardsley@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13843.841871 # average ReadReq miss latency 44010259SAndrew.Bardsley@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::total 13843.841871 # average ReadReq miss latency 44110259SAndrew.Bardsley@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 19229.820842 # average WriteReq miss latency 44210259SAndrew.Bardsley@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::total 19229.820842 # average WriteReq miss latency 44310259SAndrew.Bardsley@arm.comsystem.cpu.dcache.demand_avg_miss_latency::cpu.data 15304.837311 # average overall miss latency 44410259SAndrew.Bardsley@arm.comsystem.cpu.dcache.demand_avg_miss_latency::total 15304.837311 # average overall miss latency 44510259SAndrew.Bardsley@arm.comsystem.cpu.dcache.overall_avg_miss_latency::cpu.data 15304.837311 # average overall miss latency 44610259SAndrew.Bardsley@arm.comsystem.cpu.dcache.overall_avg_miss_latency::total 15304.837311 # average overall miss latency 44710259SAndrew.Bardsley@arm.comsystem.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 44810259SAndrew.Bardsley@arm.comsystem.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 44910259SAndrew.Bardsley@arm.comsystem.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 45010259SAndrew.Bardsley@arm.comsystem.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 45110259SAndrew.Bardsley@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 45210259SAndrew.Bardsley@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 45310259SAndrew.Bardsley@arm.comsystem.cpu.dcache.fast_writes 0 # number of fast writes performed 45410259SAndrew.Bardsley@arm.comsystem.cpu.dcache.cache_copies 0 # number of cache copies performed 45510259SAndrew.Bardsley@arm.comsystem.cpu.dcache.writebacks::writebacks 2302631 # number of writebacks 45610259SAndrew.Bardsley@arm.comsystem.cpu.dcache.writebacks::total 2302631 # number of writebacks 45710259SAndrew.Bardsley@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::cpu.data 892307 # number of ReadReq MSHR hits 45810259SAndrew.Bardsley@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::total 892307 # number of ReadReq MSHR hits 45910259SAndrew.Bardsley@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::cpu.data 3035 # number of WriteReq MSHR hits 46010259SAndrew.Bardsley@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::total 3035 # number of WriteReq MSHR hits 46110259SAndrew.Bardsley@arm.comsystem.cpu.dcache.demand_mshr_hits::cpu.data 895342 # number of demand (read+write) MSHR hits 46210259SAndrew.Bardsley@arm.comsystem.cpu.dcache.demand_mshr_hits::total 895342 # number of demand (read+write) MSHR hits 46310259SAndrew.Bardsley@arm.comsystem.cpu.dcache.overall_mshr_hits::cpu.data 895342 # number of overall MSHR hits 46410259SAndrew.Bardsley@arm.comsystem.cpu.dcache.overall_mshr_hits::total 895342 # number of overall MSHR hits 46510259SAndrew.Bardsley@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::cpu.data 1760203 # number of ReadReq MSHR misses 46610259SAndrew.Bardsley@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::total 1760203 # number of ReadReq MSHR misses 46710259SAndrew.Bardsley@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::cpu.data 984308 # number of WriteReq MSHR misses 46810259SAndrew.Bardsley@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::total 984308 # number of WriteReq MSHR misses 46910259SAndrew.Bardsley@arm.comsystem.cpu.dcache.demand_mshr_misses::cpu.data 2744511 # number of demand (read+write) MSHR misses 47010259SAndrew.Bardsley@arm.comsystem.cpu.dcache.demand_mshr_misses::total 2744511 # number of demand (read+write) MSHR misses 47110259SAndrew.Bardsley@arm.comsystem.cpu.dcache.overall_mshr_misses::cpu.data 2744511 # number of overall MSHR misses 47210259SAndrew.Bardsley@arm.comsystem.cpu.dcache.overall_mshr_misses::total 2744511 # number of overall MSHR misses 47310259SAndrew.Bardsley@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12496937149 # number of ReadReq MSHR miss cycles 47410259SAndrew.Bardsley@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::total 12496937149 # number of ReadReq MSHR miss cycles 47510259SAndrew.Bardsley@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 15830652502 # number of WriteReq MSHR miss cycles 47610259SAndrew.Bardsley@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::total 15830652502 # number of WriteReq MSHR miss cycles 47710259SAndrew.Bardsley@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::cpu.data 28327589651 # number of demand (read+write) MSHR miss cycles 47810259SAndrew.Bardsley@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::total 28327589651 # number of demand (read+write) MSHR miss cycles 47910259SAndrew.Bardsley@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::cpu.data 28327589651 # number of overall MSHR miss cycles 48010259SAndrew.Bardsley@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::total 28327589651 # number of overall MSHR miss cycles 48110259SAndrew.Bardsley@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006548 # mshr miss rate for ReadReq accesses 48210259SAndrew.Bardsley@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006548 # mshr miss rate for ReadReq accesses 48310259SAndrew.Bardsley@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006599 # mshr miss rate for WriteReq accesses 48410259SAndrew.Bardsley@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006599 # mshr miss rate for WriteReq accesses 48510259SAndrew.Bardsley@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006566 # mshr miss rate for demand accesses 48610259SAndrew.Bardsley@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::total 0.006566 # mshr miss rate for demand accesses 48710259SAndrew.Bardsley@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006566 # mshr miss rate for overall accesses 48810259SAndrew.Bardsley@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::total 0.006566 # mshr miss rate for overall accesses 48910259SAndrew.Bardsley@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7099.713584 # average ReadReq mshr miss latency 49010259SAndrew.Bardsley@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 7099.713584 # average ReadReq mshr miss latency 49110259SAndrew.Bardsley@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 16083.027367 # average WriteReq mshr miss latency 49210259SAndrew.Bardsley@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 16083.027367 # average WriteReq mshr miss latency 49310259SAndrew.Bardsley@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 10321.543492 # average overall mshr miss latency 49410259SAndrew.Bardsley@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::total 10321.543492 # average overall mshr miss latency 49510259SAndrew.Bardsley@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 10321.543492 # average overall mshr miss latency 49610259SAndrew.Bardsley@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::total 10321.543492 # average overall mshr miss latency 49710259SAndrew.Bardsley@arm.comsystem.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 49810259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.replacements 408577 # number of replacements 49910259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.tagsinuse 29310.101870 # Cycle average of tags in use 50010259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.total_refs 3608876 # Total number of references to valid blocks. 50110259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.sampled_refs 440919 # Sample count of references to valid blocks. 50210259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.avg_refs 8.184896 # Average number of references to valid blocks. 50310259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.warmup_cycle 220647003000 # Cycle when the warmup percentage was hit. 50410259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.occ_blocks::writebacks 21083.038182 # Average occupied blocks per requestor 50510259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.occ_blocks::cpu.inst 149.770059 # Average occupied blocks per requestor 50610259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.occ_blocks::cpu.data 8077.293628 # Average occupied blocks per requestor 50710259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.occ_percent::writebacks 0.643403 # Average percentage of cache occupancy 50810259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.occ_percent::cpu.inst 0.004571 # Average percentage of cache occupancy 50910259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.occ_percent::cpu.data 0.246499 # Average percentage of cache occupancy 51010259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.occ_percent::total 0.894473 # Average percentage of cache occupancy 51110259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadReq_hits::cpu.inst 3685 # number of ReadReq hits 51210259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadReq_hits::cpu.data 1537271 # number of ReadReq hits 51310259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadReq_hits::total 1540956 # number of ReadReq hits 51410259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.Writeback_hits::writebacks 2302631 # number of Writeback hits 51510259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.Writeback_hits::total 2302631 # number of Writeback hits 51610259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.UpgradeReq_hits::cpu.data 1259 # number of UpgradeReq hits 51710259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.UpgradeReq_hits::total 1259 # number of UpgradeReq hits 51810259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadExReq_hits::cpu.data 562411 # number of ReadExReq hits 51910259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadExReq_hits::total 562411 # number of ReadExReq hits 52010259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.demand_hits::cpu.inst 3685 # number of demand (read+write) hits 52110259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.demand_hits::cpu.data 2099682 # number of demand (read+write) hits 52210259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.demand_hits::total 2103367 # number of demand (read+write) hits 52310259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.overall_hits::cpu.inst 3685 # number of overall hits 52410259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.overall_hits::cpu.data 2099682 # number of overall hits 52510259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.overall_hits::total 2103367 # number of overall hits 52610259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadReq_misses::cpu.inst 3462 # number of ReadReq misses 52710259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadReq_misses::cpu.data 222130 # number of ReadReq misses 52810259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadReq_misses::total 225592 # number of ReadReq misses 52910259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.UpgradeReq_misses::cpu.data 212243 # number of UpgradeReq misses 53010259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.UpgradeReq_misses::total 212243 # number of UpgradeReq misses 53110259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadExReq_misses::cpu.data 209197 # number of ReadExReq misses 53210259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadExReq_misses::total 209197 # number of ReadExReq misses 53310259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.demand_misses::cpu.inst 3462 # number of demand (read+write) misses 53410259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.demand_misses::cpu.data 431327 # number of demand (read+write) misses 53510259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.demand_misses::total 434789 # number of demand (read+write) misses 53610259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.overall_misses::cpu.inst 3462 # number of overall misses 53710259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.overall_misses::cpu.data 431327 # number of overall misses 53810259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.overall_misses::total 434789 # number of overall misses 53910259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadReq_miss_latency::cpu.inst 121473500 # number of ReadReq miss cycles 54010259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadReq_miss_latency::cpu.data 7624503923 # number of ReadReq miss cycles 54110259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadReq_miss_latency::total 7745977423 # number of ReadReq miss cycles 54210259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 10569500 # number of UpgradeReq miss cycles 54310259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.UpgradeReq_miss_latency::total 10569500 # number of UpgradeReq miss cycles 54410259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7166790000 # number of ReadExReq miss cycles 54510259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::total 7166790000 # number of ReadExReq miss cycles 54610259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.inst 121473500 # number of demand (read+write) miss cycles 54710259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.data 14791293923 # number of demand (read+write) miss cycles 54810259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.demand_miss_latency::total 14912767423 # number of demand (read+write) miss cycles 54910259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.inst 121473500 # number of overall miss cycles 55010259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.data 14791293923 # number of overall miss cycles 55110259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.overall_miss_latency::total 14912767423 # number of overall miss cycles 55210259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadReq_accesses::cpu.inst 7147 # number of ReadReq accesses(hits+misses) 55310259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadReq_accesses::cpu.data 1759401 # number of ReadReq accesses(hits+misses) 55410259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadReq_accesses::total 1766548 # number of ReadReq accesses(hits+misses) 55510259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.Writeback_accesses::writebacks 2302631 # number of Writeback accesses(hits+misses) 55610259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.Writeback_accesses::total 2302631 # number of Writeback accesses(hits+misses) 55710259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.UpgradeReq_accesses::cpu.data 213502 # number of UpgradeReq accesses(hits+misses) 55810259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.UpgradeReq_accesses::total 213502 # number of UpgradeReq accesses(hits+misses) 55910259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadExReq_accesses::cpu.data 771608 # number of ReadExReq accesses(hits+misses) 56010259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadExReq_accesses::total 771608 # number of ReadExReq accesses(hits+misses) 56110259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.demand_accesses::cpu.inst 7147 # number of demand (read+write) accesses 56210259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.demand_accesses::cpu.data 2531009 # number of demand (read+write) accesses 56310259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.demand_accesses::total 2538156 # number of demand (read+write) accesses 56410259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.overall_accesses::cpu.inst 7147 # number of overall (read+write) accesses 56510259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.overall_accesses::cpu.data 2531009 # number of overall (read+write) accesses 56610259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.overall_accesses::total 2538156 # number of overall (read+write) accesses 56710259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.484399 # miss rate for ReadReq accesses 56810259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.126253 # miss rate for ReadReq accesses 56910259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::total 0.127702 # miss rate for ReadReq accesses 57010259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.994103 # miss rate for UpgradeReq accesses 57110259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.UpgradeReq_miss_rate::total 0.994103 # miss rate for UpgradeReq accesses 57210259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.271118 # miss rate for ReadExReq accesses 57310259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::total 0.271118 # miss rate for ReadExReq accesses 57410259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.484399 # miss rate for demand accesses 57510259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.data 0.170417 # miss rate for demand accesses 57610259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.demand_miss_rate::total 0.171301 # miss rate for demand accesses 57710259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.484399 # miss rate for overall accesses 57810259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.data 0.170417 # miss rate for overall accesses 57910259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.overall_miss_rate::total 0.171301 # miss rate for overall accesses 58010259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35087.666089 # average ReadReq miss latency 58110259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34324.512326 # average ReadReq miss latency 58210259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::total 34336.223904 # average ReadReq miss latency 58310259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 49.799051 # average UpgradeReq miss latency 58410259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.UpgradeReq_avg_miss_latency::total 49.799051 # average UpgradeReq miss latency 58510259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34258.569674 # average ReadExReq miss latency 58610259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::total 34258.569674 # average ReadExReq miss latency 58710259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35087.666089 # average overall miss latency 58810259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.data 34292.529619 # average overall miss latency 58910259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::total 34298.860880 # average overall miss latency 59010259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35087.666089 # average overall miss latency 59110259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.data 34292.529619 # average overall miss latency 59210259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::total 34298.860880 # average overall miss latency 59310259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 59410259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 59510259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 59610259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 59710259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 59810259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 59910259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.fast_writes 0 # number of fast writes performed 60010259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.cache_copies 0 # number of cache copies performed 60110259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.writebacks::writebacks 324862 # number of writebacks 60210259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.writebacks::total 324862 # number of writebacks 60310259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3462 # number of ReadReq MSHR misses 60410259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadReq_mshr_misses::cpu.data 222130 # number of ReadReq MSHR misses 60510259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadReq_mshr_misses::total 225592 # number of ReadReq MSHR misses 60610259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 212243 # number of UpgradeReq MSHR misses 60710259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_misses::total 212243 # number of UpgradeReq MSHR misses 60810259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 209197 # number of ReadExReq MSHR misses 60910259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadExReq_mshr_misses::total 209197 # number of ReadExReq MSHR misses 61010259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.inst 3462 # number of demand (read+write) MSHR misses 61110259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.data 431327 # number of demand (read+write) MSHR misses 61210259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.demand_mshr_misses::total 434789 # number of demand (read+write) MSHR misses 61310259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.inst 3462 # number of overall MSHR misses 61410259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.data 431327 # number of overall MSHR misses 61510259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.overall_mshr_misses::total 434789 # number of overall MSHR misses 61610259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 110501000 # number of ReadReq MSHR miss cycles 61710259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6934646999 # number of ReadReq MSHR miss cycles 61810259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::total 7045147999 # number of ReadReq MSHR miss cycles 61910259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 6580894500 # number of UpgradeReq MSHR miss cycles 62010259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 6580894500 # number of UpgradeReq MSHR miss cycles 62110259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6486675500 # number of ReadExReq MSHR miss cycles 62210259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6486675500 # number of ReadExReq MSHR miss cycles 62310259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 110501000 # number of demand (read+write) MSHR miss cycles 62410259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.data 13421322499 # number of demand (read+write) MSHR miss cycles 62510259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::total 13531823499 # number of demand (read+write) MSHR miss cycles 62610259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 110501000 # number of overall MSHR miss cycles 62710259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.data 13421322499 # number of overall MSHR miss cycles 62810259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::total 13531823499 # number of overall MSHR miss cycles 62910259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.484399 # mshr miss rate for ReadReq accesses 63010259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.126253 # mshr miss rate for ReadReq accesses 63110259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.127702 # mshr miss rate for ReadReq accesses 63210259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.994103 # mshr miss rate for UpgradeReq accesses 63310259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.994103 # mshr miss rate for UpgradeReq accesses 63410259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.271118 # mshr miss rate for ReadExReq accesses 63510259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.271118 # mshr miss rate for ReadExReq accesses 63610259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.484399 # mshr miss rate for demand accesses 63710259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.170417 # mshr miss rate for demand accesses 63810259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::total 0.171301 # mshr miss rate for demand accesses 63910259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.484399 # mshr miss rate for overall accesses 64010259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.170417 # mshr miss rate for overall accesses 64110259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::total 0.171301 # mshr miss rate for overall accesses 64210259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31918.255344 # average ReadReq mshr miss latency 64310259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31218.867325 # average ReadReq mshr miss latency 64410259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31229.600336 # average ReadReq mshr miss latency 64510259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31006.414817 # average UpgradeReq mshr miss latency 64610259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31006.414817 # average UpgradeReq mshr miss latency 64710259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31007.497717 # average ReadExReq mshr miss latency 64810259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31007.497717 # average ReadExReq mshr miss latency 64910259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31918.255344 # average overall mshr miss latency 65010259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31116.351397 # average overall mshr miss latency 65110259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::total 31122.736543 # average overall mshr miss latency 65210259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31918.255344 # average overall mshr miss latency 65310259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31116.351397 # average overall mshr miss latency 65410259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::total 31122.736543 # average overall mshr miss latency 65510259SAndrew.Bardsley@arm.comsystem.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 65610259SAndrew.Bardsley@arm.com 65710259SAndrew.Bardsley@arm.com---------- End Simulation Statistics ---------- 65810259SAndrew.Bardsley@arm.com