stats.txt revision 10999:e5744056cf76
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.417316 # Number of seconds simulated 4sim_ticks 417315805000 # Number of ticks simulated 5final_tick 417315805000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 92447 # Simulator instruction rate (inst/s) 8host_op_rate 170945 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 46657066 # Simulator tick rate (ticks/s) 10host_mem_usage 432180 # Number of bytes of host memory used 11host_seconds 8944.32 # Real time elapsed on the host 12sim_insts 826877109 # Number of instructions simulated 13sim_ops 1528988701 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 223744 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 24530944 # Number of bytes read from this memory 18system.physmem.bytes_read::total 24754688 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 223744 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 223744 # Number of instructions bytes read from this memory 21system.physmem.bytes_written::writebacks 18881856 # Number of bytes written to this memory 22system.physmem.bytes_written::total 18881856 # Number of bytes written to this memory 23system.physmem.num_reads::cpu.inst 3496 # Number of read requests responded to by this memory 24system.physmem.num_reads::cpu.data 383296 # Number of read requests responded to by this memory 25system.physmem.num_reads::total 386792 # Number of read requests responded to by this memory 26system.physmem.num_writes::writebacks 295029 # Number of write requests responded to by this memory 27system.physmem.num_writes::total 295029 # Number of write requests responded to by this memory 28system.physmem.bw_read::cpu.inst 536150 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::cpu.data 58782686 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::total 59318836 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_inst_read::cpu.inst 536150 # Instruction read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::total 536150 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_write::writebacks 45245964 # Write bandwidth from this memory (bytes/s) 34system.physmem.bw_write::total 45245964 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_total::writebacks 45245964 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::cpu.inst 536150 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.data 58782686 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::total 104564801 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.readReqs 386792 # Number of read requests accepted 40system.physmem.writeReqs 295029 # Number of write requests accepted 41system.physmem.readBursts 386792 # Number of DRAM read bursts, including those serviced by the write queue 42system.physmem.writeBursts 295029 # Number of DRAM write bursts, including those merged in the write queue 43system.physmem.bytesReadDRAM 24733440 # Total number of bytes read from DRAM 44system.physmem.bytesReadWrQ 21248 # Total number of bytes read from write queue 45system.physmem.bytesWritten 18880128 # Total number of bytes written to DRAM 46system.physmem.bytesReadSys 24754688 # Total read bytes from the system interface side 47system.physmem.bytesWrittenSys 18881856 # Total written bytes from the system interface side 48system.physmem.servicedByWrQ 332 # Number of DRAM read bursts serviced by the write queue 49system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 50system.physmem.neitherReadNorWriteReqs 179000 # Number of requests that are neither read nor write 51system.physmem.perBankRdBursts::0 24059 # Per bank write bursts 52system.physmem.perBankRdBursts::1 26401 # Per bank write bursts 53system.physmem.perBankRdBursts::2 24741 # Per bank write bursts 54system.physmem.perBankRdBursts::3 24611 # Per bank write bursts 55system.physmem.perBankRdBursts::4 23500 # Per bank write bursts 56system.physmem.perBankRdBursts::5 23770 # Per bank write bursts 57system.physmem.perBankRdBursts::6 24546 # Per bank write bursts 58system.physmem.perBankRdBursts::7 24382 # Per bank write bursts 59system.physmem.perBankRdBursts::8 23722 # Per bank write bursts 60system.physmem.perBankRdBursts::9 23975 # Per bank write bursts 61system.physmem.perBankRdBursts::10 24786 # Per bank write bursts 62system.physmem.perBankRdBursts::11 24066 # Per bank write bursts 63system.physmem.perBankRdBursts::12 23221 # Per bank write bursts 64system.physmem.perBankRdBursts::13 22949 # Per bank write bursts 65system.physmem.perBankRdBursts::14 23843 # Per bank write bursts 66system.physmem.perBankRdBursts::15 23888 # Per bank write bursts 67system.physmem.perBankWrBursts::0 18612 # Per bank write bursts 68system.physmem.perBankWrBursts::1 19924 # Per bank write bursts 69system.physmem.perBankWrBursts::2 18985 # Per bank write bursts 70system.physmem.perBankWrBursts::3 19009 # Per bank write bursts 71system.physmem.perBankWrBursts::4 18161 # Per bank write bursts 72system.physmem.perBankWrBursts::5 18506 # Per bank write bursts 73system.physmem.perBankWrBursts::6 19135 # Per bank write bursts 74system.physmem.perBankWrBursts::7 19090 # Per bank write bursts 75system.physmem.perBankWrBursts::8 18676 # Per bank write bursts 76system.physmem.perBankWrBursts::9 18214 # Per bank write bursts 77system.physmem.perBankWrBursts::10 18884 # Per bank write bursts 78system.physmem.perBankWrBursts::11 17768 # Per bank write bursts 79system.physmem.perBankWrBursts::12 17389 # Per bank write bursts 80system.physmem.perBankWrBursts::13 16996 # Per bank write bursts 81system.physmem.perBankWrBursts::14 17798 # Per bank write bursts 82system.physmem.perBankWrBursts::15 17855 # Per bank write bursts 83system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 84system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 85system.physmem.totGap 417315698500 # Total gap between requests 86system.physmem.readPktSize::0 0 # Read request sizes (log2) 87system.physmem.readPktSize::1 0 # Read request sizes (log2) 88system.physmem.readPktSize::2 0 # Read request sizes (log2) 89system.physmem.readPktSize::3 0 # Read request sizes (log2) 90system.physmem.readPktSize::4 0 # Read request sizes (log2) 91system.physmem.readPktSize::5 0 # Read request sizes (log2) 92system.physmem.readPktSize::6 386792 # Read request sizes (log2) 93system.physmem.writePktSize::0 0 # Write request sizes (log2) 94system.physmem.writePktSize::1 0 # Write request sizes (log2) 95system.physmem.writePktSize::2 0 # Write request sizes (log2) 96system.physmem.writePktSize::3 0 # Write request sizes (log2) 97system.physmem.writePktSize::4 0 # Write request sizes (log2) 98system.physmem.writePktSize::5 0 # Write request sizes (log2) 99system.physmem.writePktSize::6 295029 # Write request sizes (log2) 100system.physmem.rdQLenPdf::0 381444 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::1 4617 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::2 346 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::3 42 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::4 10 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 132system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 133system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 134system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::15 6179 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::16 6585 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::17 16949 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::18 17533 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::19 17607 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::20 17642 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::21 17652 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::22 17664 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::23 17717 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::24 17682 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::25 17732 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::26 17672 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::27 17725 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::28 17728 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::29 17715 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::30 17888 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::31 17610 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::32 17539 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::33 36 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::34 21 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::35 19 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::36 18 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::37 8 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::38 10 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::39 8 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::40 9 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::41 9 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::42 11 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::43 8 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::44 8 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::45 6 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::46 6 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::47 5 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::48 4 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::49 3 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::50 1 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::51 2 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::52 1 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::53 1 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::54 1 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 196system.physmem.bytesPerActivate::samples 147495 # Bytes accessed per row activation 197system.physmem.bytesPerActivate::mean 295.684816 # Bytes accessed per row activation 198system.physmem.bytesPerActivate::gmean 174.392327 # Bytes accessed per row activation 199system.physmem.bytesPerActivate::stdev 323.222401 # Bytes accessed per row activation 200system.physmem.bytesPerActivate::0-127 54844 37.18% 37.18% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::128-255 40100 27.19% 64.37% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::256-383 13710 9.30% 73.67% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::384-511 7409 5.02% 78.69% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::512-639 5412 3.67% 82.36% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::640-767 3888 2.64% 84.99% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::768-895 3038 2.06% 87.05% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::896-1023 2781 1.89% 88.94% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::1024-1151 16313 11.06% 100.00% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::total 147495 # Bytes accessed per row activation 210system.physmem.rdPerTurnAround::samples 17511 # Reads before turning the bus around for writes 211system.physmem.rdPerTurnAround::mean 22.068928 # Reads before turning the bus around for writes 212system.physmem.rdPerTurnAround::stdev 218.794243 # Reads before turning the bus around for writes 213system.physmem.rdPerTurnAround::0-1023 17500 99.94% 99.94% # Reads before turning the bus around for writes 214system.physmem.rdPerTurnAround::1024-2047 6 0.03% 99.97% # Reads before turning the bus around for writes 215system.physmem.rdPerTurnAround::2048-3071 1 0.01% 99.98% # Reads before turning the bus around for writes 216system.physmem.rdPerTurnAround::3072-4095 2 0.01% 99.99% # Reads before turning the bus around for writes 217system.physmem.rdPerTurnAround::8192-9215 1 0.01% 99.99% # Reads before turning the bus around for writes 218system.physmem.rdPerTurnAround::26624-27647 1 0.01% 100.00% # Reads before turning the bus around for writes 219system.physmem.rdPerTurnAround::total 17511 # Reads before turning the bus around for writes 220system.physmem.wrPerTurnAround::samples 17511 # Writes before turning the bus around for reads 221system.physmem.wrPerTurnAround::mean 16.846668 # Writes before turning the bus around for reads 222system.physmem.wrPerTurnAround::gmean 16.775279 # Writes before turning the bus around for reads 223system.physmem.wrPerTurnAround::stdev 2.561224 # Writes before turning the bus around for reads 224system.physmem.wrPerTurnAround::16-19 17315 98.88% 98.88% # Writes before turning the bus around for reads 225system.physmem.wrPerTurnAround::20-23 151 0.86% 99.74% # Writes before turning the bus around for reads 226system.physmem.wrPerTurnAround::24-27 21 0.12% 99.86% # Writes before turning the bus around for reads 227system.physmem.wrPerTurnAround::28-31 5 0.03% 99.89% # Writes before turning the bus around for reads 228system.physmem.wrPerTurnAround::32-35 3 0.02% 99.91% # Writes before turning the bus around for reads 229system.physmem.wrPerTurnAround::36-39 1 0.01% 99.91% # Writes before turning the bus around for reads 230system.physmem.wrPerTurnAround::40-43 1 0.01% 99.92% # Writes before turning the bus around for reads 231system.physmem.wrPerTurnAround::44-47 2 0.01% 99.93% # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::48-51 1 0.01% 99.94% # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::56-59 1 0.01% 99.94% # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::60-63 1 0.01% 99.95% # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::64-67 1 0.01% 99.95% # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::76-79 3 0.02% 99.97% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::88-91 1 0.01% 99.98% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::100-103 1 0.01% 99.98% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::104-107 1 0.01% 99.99% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::128-131 1 0.01% 99.99% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::212-215 1 0.01% 100.00% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::total 17511 # Writes before turning the bus around for reads 243system.physmem.totQLat 4302860250 # Total ticks spent queuing 244system.physmem.totMemAccLat 11548985250 # Total ticks spent from burst creation until serviced by the DRAM 245system.physmem.totBusLat 1932300000 # Total ticks spent in databus transfers 246system.physmem.avgQLat 11134.04 # Average queueing delay per DRAM burst 247system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 248system.physmem.avgMemAccLat 29884.04 # Average memory access latency per DRAM burst 249system.physmem.avgRdBW 59.27 # Average DRAM read bandwidth in MiByte/s 250system.physmem.avgWrBW 45.24 # Average achieved write bandwidth in MiByte/s 251system.physmem.avgRdBWSys 59.32 # Average system read bandwidth in MiByte/s 252system.physmem.avgWrBWSys 45.25 # Average system write bandwidth in MiByte/s 253system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 254system.physmem.busUtil 0.82 # Data bus utilization in percentage 255system.physmem.busUtilRead 0.46 # Data bus utilization in percentage for reads 256system.physmem.busUtilWrite 0.35 # Data bus utilization in percentage for writes 257system.physmem.avgRdQLen 1.06 # Average read queue length when enqueuing 258system.physmem.avgWrQLen 22.40 # Average write queue length when enqueuing 259system.physmem.readRowHits 318003 # Number of row buffer hits during reads 260system.physmem.writeRowHits 215951 # Number of row buffer hits during writes 261system.physmem.readRowHitRate 82.29 # Row buffer hit rate for reads 262system.physmem.writeRowHitRate 73.20 # Row buffer hit rate for writes 263system.physmem.avgGap 612060.49 # Average gap between requests 264system.physmem.pageHitRate 78.35 # Row buffer hit rate, read and write combined 265system.physmem_0.actEnergy 569562840 # Energy for activate commands per rank (pJ) 266system.physmem_0.preEnergy 310773375 # Energy for precharge commands per rank (pJ) 267system.physmem_0.readEnergy 1528737600 # Energy for read commands per rank (pJ) 268system.physmem_0.writeEnergy 980981280 # Energy for write commands per rank (pJ) 269system.physmem_0.refreshEnergy 27256781760 # Energy for refresh commands per rank (pJ) 270system.physmem_0.actBackEnergy 63486572355 # Energy for active background per rank (pJ) 271system.physmem_0.preBackEnergy 194697293250 # Energy for precharge background per rank (pJ) 272system.physmem_0.totalEnergy 288830702460 # Total energy per rank (pJ) 273system.physmem_0.averagePower 692.121537 # Core power per rank (mW) 274system.physmem_0.memoryStateTime::IDLE 323337240250 # Time in different power states 275system.physmem_0.memoryStateTime::REF 13934960000 # Time in different power states 276system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 277system.physmem_0.memoryStateTime::ACT 80039955000 # Time in different power states 278system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 279system.physmem_1.actEnergy 545136480 # Energy for activate commands per rank (pJ) 280system.physmem_1.preEnergy 297445500 # Energy for precharge commands per rank (pJ) 281system.physmem_1.readEnergy 1485127800 # Energy for read commands per rank (pJ) 282system.physmem_1.writeEnergy 930216960 # Energy for write commands per rank (pJ) 283system.physmem_1.refreshEnergy 27256781760 # Energy for refresh commands per rank (pJ) 284system.physmem_1.actBackEnergy 61714779795 # Energy for active background per rank (pJ) 285system.physmem_1.preBackEnergy 196251513750 # Energy for precharge background per rank (pJ) 286system.physmem_1.totalEnergy 288481002045 # Total energy per rank (pJ) 287system.physmem_1.averagePower 691.283509 # Core power per rank (mW) 288system.physmem_1.memoryStateTime::IDLE 325936894250 # Time in different power states 289system.physmem_1.memoryStateTime::REF 13934960000 # Time in different power states 290system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 291system.physmem_1.memoryStateTime::ACT 77440301000 # Time in different power states 292system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 293system.cpu.branchPred.lookups 230117471 # Number of BP lookups 294system.cpu.branchPred.condPredicted 230117471 # Number of conditional branches predicted 295system.cpu.branchPred.condIncorrect 9743461 # Number of conditional branches incorrect 296system.cpu.branchPred.BTBLookups 131565165 # Number of BTB lookups 297system.cpu.branchPred.BTBHits 128785895 # Number of BTB hits 298system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 299system.cpu.branchPred.BTBHitPct 97.887534 # BTB Hit Percentage 300system.cpu.branchPred.usedRAS 27740805 # Number of times the RAS was used to get a target. 301system.cpu.branchPred.RASInCorrect 1463511 # Number of incorrect RAS predictions. 302system.cpu_clk_domain.clock 500 # Clock period in ticks 303system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks 304system.cpu.workload.num_syscalls 551 # Number of system calls 305system.cpu.numCycles 834631611 # number of cpu cycles simulated 306system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 307system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 308system.cpu.fetch.icacheStallCycles 185091560 # Number of cycles fetch is stalled on an Icache miss 309system.cpu.fetch.Insts 1269611575 # Number of instructions fetch has processed 310system.cpu.fetch.Branches 230117471 # Number of branches that fetch encountered 311system.cpu.fetch.predictedBranches 156526700 # Number of branches that fetch has predicted taken 312system.cpu.fetch.Cycles 638324625 # Number of cycles fetch has run and was not squashing or blocked 313system.cpu.fetch.SquashCycles 20217139 # Number of cycles fetch has spent squashing 314system.cpu.fetch.TlbCycles 543 # Number of cycles fetch has spent waiting for tlb 315system.cpu.fetch.MiscStallCycles 96744 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 316system.cpu.fetch.PendingTrapStallCycles 810626 # Number of stall cycles due to pending traps 317system.cpu.fetch.PendingQuiesceStallCycles 1773 # Number of stall cycles due to pending quiesce instructions 318system.cpu.fetch.IcacheWaitRetryStallCycles 110 # Number of stall cycles due to full MSHR 319system.cpu.fetch.CacheLines 179459083 # Number of cache lines fetched 320system.cpu.fetch.IcacheSquashes 2721482 # Number of outstanding Icache misses that were squashed 321system.cpu.fetch.ItlbSquashes 2 # Number of outstanding ITLB misses that were squashed 322system.cpu.fetch.rateDist::samples 834434550 # Number of instructions fetched each cycle (Total) 323system.cpu.fetch.rateDist::mean 2.830059 # Number of instructions fetched each cycle (Total) 324system.cpu.fetch.rateDist::stdev 3.382636 # Number of instructions fetched each cycle (Total) 325system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 326system.cpu.fetch.rateDist::0 426827210 51.15% 51.15% # Number of instructions fetched each cycle (Total) 327system.cpu.fetch.rateDist::1 33688698 4.04% 55.19% # Number of instructions fetched each cycle (Total) 328system.cpu.fetch.rateDist::2 32854559 3.94% 59.13% # Number of instructions fetched each cycle (Total) 329system.cpu.fetch.rateDist::3 33384869 4.00% 63.13% # Number of instructions fetched each cycle (Total) 330system.cpu.fetch.rateDist::4 27147041 3.25% 66.38% # Number of instructions fetched each cycle (Total) 331system.cpu.fetch.rateDist::5 27739461 3.32% 69.70% # Number of instructions fetched each cycle (Total) 332system.cpu.fetch.rateDist::6 37019184 4.44% 74.14% # Number of instructions fetched each cycle (Total) 333system.cpu.fetch.rateDist::7 33642570 4.03% 78.17% # Number of instructions fetched each cycle (Total) 334system.cpu.fetch.rateDist::8 182130958 21.83% 100.00% # Number of instructions fetched each cycle (Total) 335system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 336system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 337system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 338system.cpu.fetch.rateDist::total 834434550 # Number of instructions fetched each cycle (Total) 339system.cpu.fetch.branchRate 0.275711 # Number of branch fetches per cycle 340system.cpu.fetch.rate 1.521164 # Number of inst fetches per cycle 341system.cpu.decode.IdleCycles 127499737 # Number of cycles decode is idle 342system.cpu.decode.BlockedCycles 374953474 # Number of cycles decode is blocked 343system.cpu.decode.RunCycles 240627559 # Number of cycles decode is running 344system.cpu.decode.UnblockCycles 81245211 # Number of cycles decode is unblocking 345system.cpu.decode.SquashCycles 10108569 # Number of cycles decode is squashing 346system.cpu.decode.DecodedInsts 2225588633 # Number of instructions handled by decode 347system.cpu.rename.SquashCycles 10108569 # Number of cycles rename is squashing 348system.cpu.rename.IdleCycles 159647168 # Number of cycles rename is idle 349system.cpu.rename.BlockCycles 159927889 # Number of cycles rename is blocking 350system.cpu.rename.serializeStallCycles 39744 # count of cycles rename stalled for serializing inst 351system.cpu.rename.RunCycles 285634401 # Number of cycles rename is running 352system.cpu.rename.UnblockCycles 219076779 # Number of cycles rename is unblocking 353system.cpu.rename.RenamedInsts 2175363345 # Number of instructions processed by rename 354system.cpu.rename.ROBFullEvents 166678 # Number of times rename has blocked due to ROB full 355system.cpu.rename.IQFullEvents 136608012 # Number of times rename has blocked due to IQ full 356system.cpu.rename.LQFullEvents 24443504 # Number of times rename has blocked due to LQ full 357system.cpu.rename.SQFullEvents 48002145 # Number of times rename has blocked due to SQ full 358system.cpu.rename.RenamedOperands 2279615876 # Number of destination operands rename has renamed 359system.cpu.rename.RenameLookups 5501425511 # Number of register rename lookups that rename has made 360system.cpu.rename.int_rename_lookups 3499355021 # Number of integer rename lookups 361system.cpu.rename.fp_rename_lookups 55759 # Number of floating rename lookups 362system.cpu.rename.CommittedMaps 1614040854 # Number of HB maps that are committed 363system.cpu.rename.UndoneMaps 665575022 # Number of HB maps that are undone due to squashing 364system.cpu.rename.serializingInsts 3123 # count of serializing insts renamed 365system.cpu.rename.tempSerializingInsts 2916 # count of temporary serializing insts renamed 366system.cpu.rename.skidInsts 415832299 # count of insts added to the skid buffer 367system.cpu.memDep0.insertedLoads 528432376 # Number of loads inserted to the mem dependence unit. 368system.cpu.memDep0.insertedStores 209864891 # Number of stores inserted to the mem dependence unit. 369system.cpu.memDep0.conflictingLoads 239237917 # Number of conflicting loads. 370system.cpu.memDep0.conflictingStores 72205880 # Number of conflicting stores. 371system.cpu.iq.iqInstsAdded 2101284212 # Number of instructions added to the IQ (excludes non-spec) 372system.cpu.iq.iqNonSpecInstsAdded 24336 # Number of non-speculative instructions added to the IQ 373system.cpu.iq.iqInstsIssued 1827034633 # Number of instructions issued 374system.cpu.iq.iqSquashedInstsIssued 401491 # Number of squashed instructions issued 375system.cpu.iq.iqSquashedInstsExamined 572319847 # Number of squashed instructions iterated over during squash; mainly for profiling 376system.cpu.iq.iqSquashedOperandsExamined 974276898 # Number of squashed operands that are examined and possibly removed from graph 377system.cpu.iq.iqSquashedNonSpecRemoved 23784 # Number of squashed non-spec instructions that were removed 378system.cpu.iq.issued_per_cycle::samples 834434550 # Number of insts issued each cycle 379system.cpu.iq.issued_per_cycle::mean 2.189548 # Number of insts issued each cycle 380system.cpu.iq.issued_per_cycle::stdev 2.072515 # Number of insts issued each cycle 381system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 382system.cpu.iq.issued_per_cycle::0 254639697 30.52% 30.52% # Number of insts issued each cycle 383system.cpu.iq.issued_per_cycle::1 125724347 15.07% 45.58% # Number of insts issued each cycle 384system.cpu.iq.issued_per_cycle::2 119353828 14.30% 59.89% # Number of insts issued each cycle 385system.cpu.iq.issued_per_cycle::3 111074898 13.31% 73.20% # Number of insts issued each cycle 386system.cpu.iq.issued_per_cycle::4 92504387 11.09% 84.28% # Number of insts issued each cycle 387system.cpu.iq.issued_per_cycle::5 61470741 7.37% 91.65% # Number of insts issued each cycle 388system.cpu.iq.issued_per_cycle::6 43061930 5.16% 96.81% # Number of insts issued each cycle 389system.cpu.iq.issued_per_cycle::7 19202673 2.30% 99.11% # Number of insts issued each cycle 390system.cpu.iq.issued_per_cycle::8 7402049 0.89% 100.00% # Number of insts issued each cycle 391system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 392system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 393system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 394system.cpu.iq.issued_per_cycle::total 834434550 # Number of insts issued each cycle 395system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 396system.cpu.iq.fu_full::IntAlu 11320186 42.67% 42.67% # attempts to use FU when none available 397system.cpu.iq.fu_full::IntMult 0 0.00% 42.67% # attempts to use FU when none available 398system.cpu.iq.fu_full::IntDiv 0 0.00% 42.67% # attempts to use FU when none available 399system.cpu.iq.fu_full::FloatAdd 0 0.00% 42.67% # attempts to use FU when none available 400system.cpu.iq.fu_full::FloatCmp 0 0.00% 42.67% # attempts to use FU when none available 401system.cpu.iq.fu_full::FloatCvt 0 0.00% 42.67% # attempts to use FU when none available 402system.cpu.iq.fu_full::FloatMult 0 0.00% 42.67% # attempts to use FU when none available 403system.cpu.iq.fu_full::FloatDiv 0 0.00% 42.67% # attempts to use FU when none available 404system.cpu.iq.fu_full::FloatSqrt 0 0.00% 42.67% # attempts to use FU when none available 405system.cpu.iq.fu_full::SimdAdd 0 0.00% 42.67% # attempts to use FU when none available 406system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 42.67% # attempts to use FU when none available 407system.cpu.iq.fu_full::SimdAlu 0 0.00% 42.67% # attempts to use FU when none available 408system.cpu.iq.fu_full::SimdCmp 0 0.00% 42.67% # attempts to use FU when none available 409system.cpu.iq.fu_full::SimdCvt 0 0.00% 42.67% # attempts to use FU when none available 410system.cpu.iq.fu_full::SimdMisc 0 0.00% 42.67% # attempts to use FU when none available 411system.cpu.iq.fu_full::SimdMult 0 0.00% 42.67% # attempts to use FU when none available 412system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 42.67% # attempts to use FU when none available 413system.cpu.iq.fu_full::SimdShift 0 0.00% 42.67% # attempts to use FU when none available 414system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 42.67% # attempts to use FU when none available 415system.cpu.iq.fu_full::SimdSqrt 0 0.00% 42.67% # attempts to use FU when none available 416system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 42.67% # attempts to use FU when none available 417system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 42.67% # attempts to use FU when none available 418system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 42.67% # attempts to use FU when none available 419system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 42.67% # attempts to use FU when none available 420system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 42.67% # attempts to use FU when none available 421system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 42.67% # attempts to use FU when none available 422system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 42.67% # attempts to use FU when none available 423system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 42.67% # attempts to use FU when none available 424system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 42.67% # attempts to use FU when none available 425system.cpu.iq.fu_full::MemRead 12172571 45.88% 88.55% # attempts to use FU when none available 426system.cpu.iq.fu_full::MemWrite 3037482 11.45% 100.00% # attempts to use FU when none available 427system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 428system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 429system.cpu.iq.FU_type_0::No_OpClass 2711288 0.15% 0.15% # Type of FU issued 430system.cpu.iq.FU_type_0::IntAlu 1211298887 66.30% 66.45% # Type of FU issued 431system.cpu.iq.FU_type_0::IntMult 388808 0.02% 66.47% # Type of FU issued 432system.cpu.iq.FU_type_0::IntDiv 3881058 0.21% 66.68% # Type of FU issued 433system.cpu.iq.FU_type_0::FloatAdd 134 0.00% 66.68% # Type of FU issued 434system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.68% # Type of FU issued 435system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.68% # Type of FU issued 436system.cpu.iq.FU_type_0::FloatMult 33 0.00% 66.68% # Type of FU issued 437system.cpu.iq.FU_type_0::FloatDiv 403 0.00% 66.68% # Type of FU issued 438system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.68% # Type of FU issued 439system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.68% # Type of FU issued 440system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.68% # Type of FU issued 441system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.68% # Type of FU issued 442system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.68% # Type of FU issued 443system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.68% # Type of FU issued 444system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.68% # Type of FU issued 445system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.68% # Type of FU issued 446system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.68% # Type of FU issued 447system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.68% # Type of FU issued 448system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.68% # Type of FU issued 449system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.68% # Type of FU issued 450system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.68% # Type of FU issued 451system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.68% # Type of FU issued 452system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.68% # Type of FU issued 453system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.68% # Type of FU issued 454system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.68% # Type of FU issued 455system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.68% # Type of FU issued 456system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.68% # Type of FU issued 457system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.68% # Type of FU issued 458system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.68% # Type of FU issued 459system.cpu.iq.FU_type_0::MemRead 435055867 23.81% 90.49% # Type of FU issued 460system.cpu.iq.FU_type_0::MemWrite 173698155 9.51% 100.00% # Type of FU issued 461system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 462system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 463system.cpu.iq.FU_type_0::total 1827034633 # Type of FU issued 464system.cpu.iq.rate 2.189031 # Inst issue rate 465system.cpu.iq.fu_busy_cnt 26530239 # FU busy when requested 466system.cpu.iq.fu_busy_rate 0.014521 # FU busy rate (busy events/executed inst) 467system.cpu.iq.int_inst_queue_reads 4515402541 # Number of integer instruction queue reads 468system.cpu.iq.int_inst_queue_writes 2673889112 # Number of integer instruction queue writes 469system.cpu.iq.int_inst_queue_wakeup_accesses 1796964967 # Number of integer instruction queue wakeup accesses 470system.cpu.iq.fp_inst_queue_reads 33005 # Number of floating instruction queue reads 471system.cpu.iq.fp_inst_queue_writes 70700 # Number of floating instruction queue writes 472system.cpu.iq.fp_inst_queue_wakeup_accesses 7229 # Number of floating instruction queue wakeup accesses 473system.cpu.iq.int_alu_accesses 1850838268 # Number of integer alu accesses 474system.cpu.iq.fp_alu_accesses 15316 # Number of floating point alu accesses 475system.cpu.iew.lsq.thread0.forwLoads 185431148 # Number of loads that had data forwarded from stores 476system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 477system.cpu.iew.lsq.thread0.squashedLoads 144332039 # Number of loads squashed 478system.cpu.iew.lsq.thread0.ignoredResponses 211913 # Number of memory responses ignored because the instruction is squashed 479system.cpu.iew.lsq.thread0.memOrderViolation 385225 # Number of memory ordering violations 480system.cpu.iew.lsq.thread0.squashedStores 60704705 # Number of stores squashed 481system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 482system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 483system.cpu.iew.lsq.thread0.rescheduledLoads 19195 # Number of loads that were rescheduled 484system.cpu.iew.lsq.thread0.cacheBlocked 1040 # Number of times an access to memory failed due to the cache being blocked 485system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 486system.cpu.iew.iewSquashCycles 10108569 # Number of cycles IEW is squashing 487system.cpu.iew.iewBlockCycles 107095351 # Number of cycles IEW is blocking 488system.cpu.iew.iewUnblockCycles 6179627 # Number of cycles IEW is unblocking 489system.cpu.iew.iewDispatchedInsts 2101308548 # Number of instructions dispatched to IQ 490system.cpu.iew.iewDispSquashedInsts 404076 # Number of squashed instructions skipped by dispatch 491system.cpu.iew.iewDispLoadInsts 528434196 # Number of dispatched load instructions 492system.cpu.iew.iewDispStoreInsts 209864891 # Number of dispatched store instructions 493system.cpu.iew.iewDispNonSpecInsts 6959 # Number of dispatched non-speculative instructions 494system.cpu.iew.iewIQFullEvents 1875437 # Number of times the IQ has become full, causing a stall 495system.cpu.iew.iewLSQFullEvents 3414890 # Number of times the LSQ has become full, causing a stall 496system.cpu.iew.memOrderViolationEvents 385225 # Number of memory order violations 497system.cpu.iew.predictedTakenIncorrect 5746544 # Number of branches that were predicted taken incorrectly 498system.cpu.iew.predictedNotTakenIncorrect 4564008 # Number of branches that were predicted not taken incorrectly 499system.cpu.iew.branchMispredicts 10310552 # Number of branch mispredicts detected at execute 500system.cpu.iew.iewExecutedInsts 1805625643 # Number of executed instructions 501system.cpu.iew.iewExecLoadInsts 428837620 # Number of load instructions executed 502system.cpu.iew.iewExecSquashedInsts 21408990 # Number of squashed instructions skipped in execute 503system.cpu.iew.exec_swp 0 # number of swp insts executed 504system.cpu.iew.exec_nop 0 # number of nop insts executed 505system.cpu.iew.exec_refs 599025712 # number of memory reference insts executed 506system.cpu.iew.exec_branches 171773578 # Number of branches executed 507system.cpu.iew.exec_stores 170188092 # Number of stores executed 508system.cpu.iew.exec_rate 2.163380 # Inst execution rate 509system.cpu.iew.wb_sent 1802216227 # cumulative count of insts sent to commit 510system.cpu.iew.wb_count 1796972196 # cumulative count of insts written-back 511system.cpu.iew.wb_producers 1368071729 # num instructions producing a value 512system.cpu.iew.wb_consumers 2090120765 # num instructions consuming a value 513system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 514system.cpu.iew.wb_rate 2.153012 # insts written-back per cycle 515system.cpu.iew.wb_fanout 0.654542 # average fanout of values written-back 516system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 517system.cpu.commit.commitSquashedInsts 572398548 # The number of squashed insts skipped by commit 518system.cpu.commit.commitNonSpecStalls 552 # The number of times commit has been forced to stall to communicate backwards 519system.cpu.commit.branchMispredicts 9828987 # The number of times a branch was mispredicted 520system.cpu.commit.committed_per_cycle::samples 756729949 # Number of insts commited each cycle 521system.cpu.commit.committed_per_cycle::mean 2.020521 # Number of insts commited each cycle 522system.cpu.commit.committed_per_cycle::stdev 2.547401 # Number of insts commited each cycle 523system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 524system.cpu.commit.committed_per_cycle::0 287871292 38.04% 38.04% # Number of insts commited each cycle 525system.cpu.commit.committed_per_cycle::1 175370720 23.17% 61.22% # Number of insts commited each cycle 526system.cpu.commit.committed_per_cycle::2 57379665 7.58% 68.80% # Number of insts commited each cycle 527system.cpu.commit.committed_per_cycle::3 86292739 11.40% 80.20% # Number of insts commited each cycle 528system.cpu.commit.committed_per_cycle::4 27182541 3.59% 83.79% # Number of insts commited each cycle 529system.cpu.commit.committed_per_cycle::5 27109377 3.58% 87.38% # Number of insts commited each cycle 530system.cpu.commit.committed_per_cycle::6 9779675 1.29% 88.67% # Number of insts commited each cycle 531system.cpu.commit.committed_per_cycle::7 8926185 1.18% 89.85% # Number of insts commited each cycle 532system.cpu.commit.committed_per_cycle::8 76817755 10.15% 100.00% # Number of insts commited each cycle 533system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 534system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 535system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 536system.cpu.commit.committed_per_cycle::total 756729949 # Number of insts commited each cycle 537system.cpu.commit.committedInsts 826877109 # Number of instructions committed 538system.cpu.commit.committedOps 1528988701 # Number of ops (including micro ops) committed 539system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 540system.cpu.commit.refs 533262343 # Number of memory references committed 541system.cpu.commit.loads 384102157 # Number of loads committed 542system.cpu.commit.membars 0 # Number of memory barriers committed 543system.cpu.commit.branches 149758583 # Number of branches committed 544system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. 545system.cpu.commit.int_insts 1526605509 # Number of committed integer instructions. 546system.cpu.commit.function_calls 17673145 # Number of function calls committed. 547system.cpu.commit.op_class_0::No_OpClass 1819099 0.12% 0.12% # Class of committed instruction 548system.cpu.commit.op_class_0::IntAlu 989721889 64.73% 64.85% # Class of committed instruction 549system.cpu.commit.op_class_0::IntMult 306834 0.02% 64.87% # Class of committed instruction 550system.cpu.commit.op_class_0::IntDiv 3878536 0.25% 65.12% # Class of committed instruction 551system.cpu.commit.op_class_0::FloatAdd 0 0.00% 65.12% # Class of committed instruction 552system.cpu.commit.op_class_0::FloatCmp 0 0.00% 65.12% # Class of committed instruction 553system.cpu.commit.op_class_0::FloatCvt 0 0.00% 65.12% # Class of committed instruction 554system.cpu.commit.op_class_0::FloatMult 0 0.00% 65.12% # Class of committed instruction 555system.cpu.commit.op_class_0::FloatDiv 0 0.00% 65.12% # Class of committed instruction 556system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 65.12% # Class of committed instruction 557system.cpu.commit.op_class_0::SimdAdd 0 0.00% 65.12% # Class of committed instruction 558system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 65.12% # Class of committed instruction 559system.cpu.commit.op_class_0::SimdAlu 0 0.00% 65.12% # Class of committed instruction 560system.cpu.commit.op_class_0::SimdCmp 0 0.00% 65.12% # Class of committed instruction 561system.cpu.commit.op_class_0::SimdCvt 0 0.00% 65.12% # Class of committed instruction 562system.cpu.commit.op_class_0::SimdMisc 0 0.00% 65.12% # Class of committed instruction 563system.cpu.commit.op_class_0::SimdMult 0 0.00% 65.12% # Class of committed instruction 564system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 65.12% # Class of committed instruction 565system.cpu.commit.op_class_0::SimdShift 0 0.00% 65.12% # Class of committed instruction 566system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 65.12% # Class of committed instruction 567system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 65.12% # Class of committed instruction 568system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 65.12% # Class of committed instruction 569system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 65.12% # Class of committed instruction 570system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 65.12% # Class of committed instruction 571system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 65.12% # Class of committed instruction 572system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 65.12% # Class of committed instruction 573system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 65.12% # Class of committed instruction 574system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 65.12% # Class of committed instruction 575system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.12% # Class of committed instruction 576system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.12% # Class of committed instruction 577system.cpu.commit.op_class_0::MemRead 384102157 25.12% 90.24% # Class of committed instruction 578system.cpu.commit.op_class_0::MemWrite 149160186 9.76% 100.00% # Class of committed instruction 579system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 580system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 581system.cpu.commit.op_class_0::total 1528988701 # Class of committed instruction 582system.cpu.commit.bw_lim_events 76817755 # number cycles where commit BW limit reached 583system.cpu.rob.rob_reads 2781299443 # The number of ROB reads 584system.cpu.rob.rob_writes 4280666670 # The number of ROB writes 585system.cpu.timesIdled 2296 # Number of times that the entire CPU went into an idle state and unscheduled itself 586system.cpu.idleCycles 197061 # Total number of cycles that the CPU has spent unscheduled due to idling 587system.cpu.committedInsts 826877109 # Number of Instructions Simulated 588system.cpu.committedOps 1528988701 # Number of Ops (including micro ops) Simulated 589system.cpu.cpi 1.009378 # CPI: Cycles Per Instruction 590system.cpu.cpi_total 1.009378 # CPI: Total CPI of All Threads 591system.cpu.ipc 0.990709 # IPC: Instructions Per Cycle 592system.cpu.ipc_total 0.990709 # IPC: Total IPC of All Threads 593system.cpu.int_regfile_reads 2762055581 # number of integer regfile reads 594system.cpu.int_regfile_writes 1465119637 # number of integer regfile writes 595system.cpu.fp_regfile_reads 7518 # number of floating regfile reads 596system.cpu.fp_regfile_writes 448 # number of floating regfile writes 597system.cpu.cc_regfile_reads 600894138 # number of cc regfile reads 598system.cpu.cc_regfile_writes 409652534 # number of cc regfile writes 599system.cpu.misc_regfile_reads 990211728 # number of misc regfile reads 600system.cpu.misc_regfile_writes 1 # number of misc regfile writes 601system.cpu.dcache.tags.replacements 2534268 # number of replacements 602system.cpu.dcache.tags.tagsinuse 4088.022618 # Cycle average of tags in use 603system.cpu.dcache.tags.total_refs 387933013 # Total number of references to valid blocks. 604system.cpu.dcache.tags.sampled_refs 2538364 # Sample count of references to valid blocks. 605system.cpu.dcache.tags.avg_refs 152.827968 # Average number of references to valid blocks. 606system.cpu.dcache.tags.warmup_cycle 1679458500 # Cycle when the warmup percentage was hit. 607system.cpu.dcache.tags.occ_blocks::cpu.data 4088.022618 # Average occupied blocks per requestor 608system.cpu.dcache.tags.occ_percent::cpu.data 0.998052 # Average percentage of cache occupancy 609system.cpu.dcache.tags.occ_percent::total 0.998052 # Average percentage of cache occupancy 610system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 611system.cpu.dcache.tags.age_task_id_blocks_1024::0 26 # Occupied blocks per task id 612system.cpu.dcache.tags.age_task_id_blocks_1024::1 24 # Occupied blocks per task id 613system.cpu.dcache.tags.age_task_id_blocks_1024::2 875 # Occupied blocks per task id 614system.cpu.dcache.tags.age_task_id_blocks_1024::3 3171 # Occupied blocks per task id 615system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 616system.cpu.dcache.tags.tag_accesses 784997698 # Number of tag accesses 617system.cpu.dcache.tags.data_accesses 784997698 # Number of data accesses 618system.cpu.dcache.ReadReq_hits::cpu.data 239283827 # number of ReadReq hits 619system.cpu.dcache.ReadReq_hits::total 239283827 # number of ReadReq hits 620system.cpu.dcache.WriteReq_hits::cpu.data 148189705 # number of WriteReq hits 621system.cpu.dcache.WriteReq_hits::total 148189705 # number of WriteReq hits 622system.cpu.dcache.demand_hits::cpu.data 387473532 # number of demand (read+write) hits 623system.cpu.dcache.demand_hits::total 387473532 # number of demand (read+write) hits 624system.cpu.dcache.overall_hits::cpu.data 387473532 # number of overall hits 625system.cpu.dcache.overall_hits::total 387473532 # number of overall hits 626system.cpu.dcache.ReadReq_misses::cpu.data 2785638 # number of ReadReq misses 627system.cpu.dcache.ReadReq_misses::total 2785638 # number of ReadReq misses 628system.cpu.dcache.WriteReq_misses::cpu.data 970497 # number of WriteReq misses 629system.cpu.dcache.WriteReq_misses::total 970497 # number of WriteReq misses 630system.cpu.dcache.demand_misses::cpu.data 3756135 # number of demand (read+write) misses 631system.cpu.dcache.demand_misses::total 3756135 # number of demand (read+write) misses 632system.cpu.dcache.overall_misses::cpu.data 3756135 # number of overall misses 633system.cpu.dcache.overall_misses::total 3756135 # number of overall misses 634system.cpu.dcache.ReadReq_miss_latency::cpu.data 59461217500 # number of ReadReq miss cycles 635system.cpu.dcache.ReadReq_miss_latency::total 59461217500 # number of ReadReq miss cycles 636system.cpu.dcache.WriteReq_miss_latency::cpu.data 30522057998 # number of WriteReq miss cycles 637system.cpu.dcache.WriteReq_miss_latency::total 30522057998 # number of WriteReq miss cycles 638system.cpu.dcache.demand_miss_latency::cpu.data 89983275498 # number of demand (read+write) miss cycles 639system.cpu.dcache.demand_miss_latency::total 89983275498 # number of demand (read+write) miss cycles 640system.cpu.dcache.overall_miss_latency::cpu.data 89983275498 # number of overall miss cycles 641system.cpu.dcache.overall_miss_latency::total 89983275498 # number of overall miss cycles 642system.cpu.dcache.ReadReq_accesses::cpu.data 242069465 # number of ReadReq accesses(hits+misses) 643system.cpu.dcache.ReadReq_accesses::total 242069465 # number of ReadReq accesses(hits+misses) 644system.cpu.dcache.WriteReq_accesses::cpu.data 149160202 # number of WriteReq accesses(hits+misses) 645system.cpu.dcache.WriteReq_accesses::total 149160202 # number of WriteReq accesses(hits+misses) 646system.cpu.dcache.demand_accesses::cpu.data 391229667 # number of demand (read+write) accesses 647system.cpu.dcache.demand_accesses::total 391229667 # number of demand (read+write) accesses 648system.cpu.dcache.overall_accesses::cpu.data 391229667 # number of overall (read+write) accesses 649system.cpu.dcache.overall_accesses::total 391229667 # number of overall (read+write) accesses 650system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011508 # miss rate for ReadReq accesses 651system.cpu.dcache.ReadReq_miss_rate::total 0.011508 # miss rate for ReadReq accesses 652system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006506 # miss rate for WriteReq accesses 653system.cpu.dcache.WriteReq_miss_rate::total 0.006506 # miss rate for WriteReq accesses 654system.cpu.dcache.demand_miss_rate::cpu.data 0.009601 # miss rate for demand accesses 655system.cpu.dcache.demand_miss_rate::total 0.009601 # miss rate for demand accesses 656system.cpu.dcache.overall_miss_rate::cpu.data 0.009601 # miss rate for overall accesses 657system.cpu.dcache.overall_miss_rate::total 0.009601 # miss rate for overall accesses 658system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21345.636978 # average ReadReq miss latency 659system.cpu.dcache.ReadReq_avg_miss_latency::total 21345.636978 # average ReadReq miss latency 660system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31449.925139 # average WriteReq miss latency 661system.cpu.dcache.WriteReq_avg_miss_latency::total 31449.925139 # average WriteReq miss latency 662system.cpu.dcache.demand_avg_miss_latency::cpu.data 23956.347548 # average overall miss latency 663system.cpu.dcache.demand_avg_miss_latency::total 23956.347548 # average overall miss latency 664system.cpu.dcache.overall_avg_miss_latency::cpu.data 23956.347548 # average overall miss latency 665system.cpu.dcache.overall_avg_miss_latency::total 23956.347548 # average overall miss latency 666system.cpu.dcache.blocked_cycles::no_mshrs 11065 # number of cycles access was blocked 667system.cpu.dcache.blocked_cycles::no_targets 19 # number of cycles access was blocked 668system.cpu.dcache.blocked::no_mshrs 1184 # number of cycles access was blocked 669system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked 670system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.345439 # average number of cycles each access was blocked 671system.cpu.dcache.avg_blocked_cycles::no_targets 9.500000 # average number of cycles each access was blocked 672system.cpu.dcache.fast_writes 0 # number of fast writes performed 673system.cpu.dcache.cache_copies 0 # number of cache copies performed 674system.cpu.dcache.writebacks::writebacks 2332624 # number of writebacks 675system.cpu.dcache.writebacks::total 2332624 # number of writebacks 676system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1017670 # number of ReadReq MSHR hits 677system.cpu.dcache.ReadReq_mshr_hits::total 1017670 # number of ReadReq MSHR hits 678system.cpu.dcache.WriteReq_mshr_hits::cpu.data 19246 # number of WriteReq MSHR hits 679system.cpu.dcache.WriteReq_mshr_hits::total 19246 # number of WriteReq MSHR hits 680system.cpu.dcache.demand_mshr_hits::cpu.data 1036916 # number of demand (read+write) MSHR hits 681system.cpu.dcache.demand_mshr_hits::total 1036916 # number of demand (read+write) MSHR hits 682system.cpu.dcache.overall_mshr_hits::cpu.data 1036916 # number of overall MSHR hits 683system.cpu.dcache.overall_mshr_hits::total 1036916 # number of overall MSHR hits 684system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1767968 # number of ReadReq MSHR misses 685system.cpu.dcache.ReadReq_mshr_misses::total 1767968 # number of ReadReq MSHR misses 686system.cpu.dcache.WriteReq_mshr_misses::cpu.data 951251 # number of WriteReq MSHR misses 687system.cpu.dcache.WriteReq_mshr_misses::total 951251 # number of WriteReq MSHR misses 688system.cpu.dcache.demand_mshr_misses::cpu.data 2719219 # number of demand (read+write) MSHR misses 689system.cpu.dcache.demand_mshr_misses::total 2719219 # number of demand (read+write) MSHR misses 690system.cpu.dcache.overall_mshr_misses::cpu.data 2719219 # number of overall MSHR misses 691system.cpu.dcache.overall_mshr_misses::total 2719219 # number of overall MSHR misses 692system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33611924000 # number of ReadReq MSHR miss cycles 693system.cpu.dcache.ReadReq_mshr_miss_latency::total 33611924000 # number of ReadReq MSHR miss cycles 694system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 29320675500 # number of WriteReq MSHR miss cycles 695system.cpu.dcache.WriteReq_mshr_miss_latency::total 29320675500 # number of WriteReq MSHR miss cycles 696system.cpu.dcache.demand_mshr_miss_latency::cpu.data 62932599500 # number of demand (read+write) MSHR miss cycles 697system.cpu.dcache.demand_mshr_miss_latency::total 62932599500 # number of demand (read+write) MSHR miss cycles 698system.cpu.dcache.overall_mshr_miss_latency::cpu.data 62932599500 # number of overall MSHR miss cycles 699system.cpu.dcache.overall_mshr_miss_latency::total 62932599500 # number of overall MSHR miss cycles 700system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007304 # mshr miss rate for ReadReq accesses 701system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007304 # mshr miss rate for ReadReq accesses 702system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006377 # mshr miss rate for WriteReq accesses 703system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006377 # mshr miss rate for WriteReq accesses 704system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006950 # mshr miss rate for demand accesses 705system.cpu.dcache.demand_mshr_miss_rate::total 0.006950 # mshr miss rate for demand accesses 706system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006950 # mshr miss rate for overall accesses 707system.cpu.dcache.overall_mshr_miss_rate::total 0.006950 # mshr miss rate for overall accesses 708system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19011.613332 # average ReadReq mshr miss latency 709system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19011.613332 # average ReadReq mshr miss latency 710system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30823.279555 # average WriteReq mshr miss latency 711system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30823.279555 # average WriteReq mshr miss latency 712system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23143.630395 # average overall mshr miss latency 713system.cpu.dcache.demand_avg_mshr_miss_latency::total 23143.630395 # average overall mshr miss latency 714system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23143.630395 # average overall mshr miss latency 715system.cpu.dcache.overall_avg_mshr_miss_latency::total 23143.630395 # average overall mshr miss latency 716system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 717system.cpu.icache.tags.replacements 6980 # number of replacements 718system.cpu.icache.tags.tagsinuse 1050.498551 # Cycle average of tags in use 719system.cpu.icache.tags.total_refs 179263698 # Total number of references to valid blocks. 720system.cpu.icache.tags.sampled_refs 8570 # Sample count of references to valid blocks. 721system.cpu.icache.tags.avg_refs 20917.584364 # Average number of references to valid blocks. 722system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 723system.cpu.icache.tags.occ_blocks::cpu.inst 1050.498551 # Average occupied blocks per requestor 724system.cpu.icache.tags.occ_percent::cpu.inst 0.512939 # Average percentage of cache occupancy 725system.cpu.icache.tags.occ_percent::total 0.512939 # Average percentage of cache occupancy 726system.cpu.icache.tags.occ_task_id_blocks::1024 1590 # Occupied blocks per task id 727system.cpu.icache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id 728system.cpu.icache.tags.age_task_id_blocks_1024::1 18 # Occupied blocks per task id 729system.cpu.icache.tags.age_task_id_blocks_1024::2 43 # Occupied blocks per task id 730system.cpu.icache.tags.age_task_id_blocks_1024::3 300 # Occupied blocks per task id 731system.cpu.icache.tags.age_task_id_blocks_1024::4 1165 # Occupied blocks per task id 732system.cpu.icache.tags.occ_task_id_percent::1024 0.776367 # Percentage of cache occupancy per task id 733system.cpu.icache.tags.tag_accesses 359107751 # Number of tag accesses 734system.cpu.icache.tags.data_accesses 359107751 # Number of data accesses 735system.cpu.icache.ReadReq_hits::cpu.inst 179266886 # number of ReadReq hits 736system.cpu.icache.ReadReq_hits::total 179266886 # number of ReadReq hits 737system.cpu.icache.demand_hits::cpu.inst 179266886 # number of demand (read+write) hits 738system.cpu.icache.demand_hits::total 179266886 # number of demand (read+write) hits 739system.cpu.icache.overall_hits::cpu.inst 179266886 # number of overall hits 740system.cpu.icache.overall_hits::total 179266886 # number of overall hits 741system.cpu.icache.ReadReq_misses::cpu.inst 192197 # number of ReadReq misses 742system.cpu.icache.ReadReq_misses::total 192197 # number of ReadReq misses 743system.cpu.icache.demand_misses::cpu.inst 192197 # number of demand (read+write) misses 744system.cpu.icache.demand_misses::total 192197 # number of demand (read+write) misses 745system.cpu.icache.overall_misses::cpu.inst 192197 # number of overall misses 746system.cpu.icache.overall_misses::total 192197 # number of overall misses 747system.cpu.icache.ReadReq_miss_latency::cpu.inst 1252320498 # number of ReadReq miss cycles 748system.cpu.icache.ReadReq_miss_latency::total 1252320498 # number of ReadReq miss cycles 749system.cpu.icache.demand_miss_latency::cpu.inst 1252320498 # number of demand (read+write) miss cycles 750system.cpu.icache.demand_miss_latency::total 1252320498 # number of demand (read+write) miss cycles 751system.cpu.icache.overall_miss_latency::cpu.inst 1252320498 # number of overall miss cycles 752system.cpu.icache.overall_miss_latency::total 1252320498 # number of overall miss cycles 753system.cpu.icache.ReadReq_accesses::cpu.inst 179459083 # number of ReadReq accesses(hits+misses) 754system.cpu.icache.ReadReq_accesses::total 179459083 # number of ReadReq accesses(hits+misses) 755system.cpu.icache.demand_accesses::cpu.inst 179459083 # number of demand (read+write) accesses 756system.cpu.icache.demand_accesses::total 179459083 # number of demand (read+write) accesses 757system.cpu.icache.overall_accesses::cpu.inst 179459083 # number of overall (read+write) accesses 758system.cpu.icache.overall_accesses::total 179459083 # number of overall (read+write) accesses 759system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001071 # miss rate for ReadReq accesses 760system.cpu.icache.ReadReq_miss_rate::total 0.001071 # miss rate for ReadReq accesses 761system.cpu.icache.demand_miss_rate::cpu.inst 0.001071 # miss rate for demand accesses 762system.cpu.icache.demand_miss_rate::total 0.001071 # miss rate for demand accesses 763system.cpu.icache.overall_miss_rate::cpu.inst 0.001071 # miss rate for overall accesses 764system.cpu.icache.overall_miss_rate::total 0.001071 # miss rate for overall accesses 765system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6515.817094 # average ReadReq miss latency 766system.cpu.icache.ReadReq_avg_miss_latency::total 6515.817094 # average ReadReq miss latency 767system.cpu.icache.demand_avg_miss_latency::cpu.inst 6515.817094 # average overall miss latency 768system.cpu.icache.demand_avg_miss_latency::total 6515.817094 # average overall miss latency 769system.cpu.icache.overall_avg_miss_latency::cpu.inst 6515.817094 # average overall miss latency 770system.cpu.icache.overall_avg_miss_latency::total 6515.817094 # average overall miss latency 771system.cpu.icache.blocked_cycles::no_mshrs 1416 # number of cycles access was blocked 772system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 773system.cpu.icache.blocked::no_mshrs 21 # number of cycles access was blocked 774system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 775system.cpu.icache.avg_blocked_cycles::no_mshrs 67.428571 # average number of cycles each access was blocked 776system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 777system.cpu.icache.fast_writes 0 # number of fast writes performed 778system.cpu.icache.cache_copies 0 # number of cache copies performed 779system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2611 # number of ReadReq MSHR hits 780system.cpu.icache.ReadReq_mshr_hits::total 2611 # number of ReadReq MSHR hits 781system.cpu.icache.demand_mshr_hits::cpu.inst 2611 # number of demand (read+write) MSHR hits 782system.cpu.icache.demand_mshr_hits::total 2611 # number of demand (read+write) MSHR hits 783system.cpu.icache.overall_mshr_hits::cpu.inst 2611 # number of overall MSHR hits 784system.cpu.icache.overall_mshr_hits::total 2611 # number of overall MSHR hits 785system.cpu.icache.ReadReq_mshr_misses::cpu.inst 189586 # number of ReadReq MSHR misses 786system.cpu.icache.ReadReq_mshr_misses::total 189586 # number of ReadReq MSHR misses 787system.cpu.icache.demand_mshr_misses::cpu.inst 189586 # number of demand (read+write) MSHR misses 788system.cpu.icache.demand_mshr_misses::total 189586 # number of demand (read+write) MSHR misses 789system.cpu.icache.overall_mshr_misses::cpu.inst 189586 # number of overall MSHR misses 790system.cpu.icache.overall_mshr_misses::total 189586 # number of overall MSHR misses 791system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 945150498 # number of ReadReq MSHR miss cycles 792system.cpu.icache.ReadReq_mshr_miss_latency::total 945150498 # number of ReadReq MSHR miss cycles 793system.cpu.icache.demand_mshr_miss_latency::cpu.inst 945150498 # number of demand (read+write) MSHR miss cycles 794system.cpu.icache.demand_mshr_miss_latency::total 945150498 # number of demand (read+write) MSHR miss cycles 795system.cpu.icache.overall_mshr_miss_latency::cpu.inst 945150498 # number of overall MSHR miss cycles 796system.cpu.icache.overall_mshr_miss_latency::total 945150498 # number of overall MSHR miss cycles 797system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001056 # mshr miss rate for ReadReq accesses 798system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001056 # mshr miss rate for ReadReq accesses 799system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001056 # mshr miss rate for demand accesses 800system.cpu.icache.demand_mshr_miss_rate::total 0.001056 # mshr miss rate for demand accesses 801system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001056 # mshr miss rate for overall accesses 802system.cpu.icache.overall_mshr_miss_rate::total 0.001056 # mshr miss rate for overall accesses 803system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 4985.339097 # average ReadReq mshr miss latency 804system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 4985.339097 # average ReadReq mshr miss latency 805system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 4985.339097 # average overall mshr miss latency 806system.cpu.icache.demand_avg_mshr_miss_latency::total 4985.339097 # average overall mshr miss latency 807system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 4985.339097 # average overall mshr miss latency 808system.cpu.icache.overall_avg_mshr_miss_latency::total 4985.339097 # average overall mshr miss latency 809system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 810system.cpu.l2cache.tags.replacements 354113 # number of replacements 811system.cpu.l2cache.tags.tagsinuse 29616.739115 # Cycle average of tags in use 812system.cpu.l2cache.tags.total_refs 3899842 # Total number of references to valid blocks. 813system.cpu.l2cache.tags.sampled_refs 386474 # Sample count of references to valid blocks. 814system.cpu.l2cache.tags.avg_refs 10.090826 # Average number of references to valid blocks. 815system.cpu.l2cache.tags.warmup_cycle 197713230000 # Cycle when the warmup percentage was hit. 816system.cpu.l2cache.tags.occ_blocks::writebacks 20951.203852 # Average occupied blocks per requestor 817system.cpu.l2cache.tags.occ_blocks::cpu.inst 251.356614 # Average occupied blocks per requestor 818system.cpu.l2cache.tags.occ_blocks::cpu.data 8414.178648 # Average occupied blocks per requestor 819system.cpu.l2cache.tags.occ_percent::writebacks 0.639380 # Average percentage of cache occupancy 820system.cpu.l2cache.tags.occ_percent::cpu.inst 0.007671 # Average percentage of cache occupancy 821system.cpu.l2cache.tags.occ_percent::cpu.data 0.256780 # Average percentage of cache occupancy 822system.cpu.l2cache.tags.occ_percent::total 0.903831 # Average percentage of cache occupancy 823system.cpu.l2cache.tags.occ_task_id_blocks::1024 32361 # Occupied blocks per task id 824system.cpu.l2cache.tags.age_task_id_blocks_1024::0 82 # Occupied blocks per task id 825system.cpu.l2cache.tags.age_task_id_blocks_1024::1 3 # Occupied blocks per task id 826system.cpu.l2cache.tags.age_task_id_blocks_1024::2 244 # Occupied blocks per task id 827system.cpu.l2cache.tags.age_task_id_blocks_1024::3 13363 # Occupied blocks per task id 828system.cpu.l2cache.tags.age_task_id_blocks_1024::4 18669 # Occupied blocks per task id 829system.cpu.l2cache.tags.occ_task_id_percent::1024 0.987579 # Percentage of cache occupancy per task id 830system.cpu.l2cache.tags.tag_accesses 43221136 # Number of tag accesses 831system.cpu.l2cache.tags.data_accesses 43221136 # Number of data accesses 832system.cpu.l2cache.Writeback_hits::writebacks 2332624 # number of Writeback hits 833system.cpu.l2cache.Writeback_hits::total 2332624 # number of Writeback hits 834system.cpu.l2cache.UpgradeReq_hits::cpu.data 1893 # number of UpgradeReq hits 835system.cpu.l2cache.UpgradeReq_hits::total 1893 # number of UpgradeReq hits 836system.cpu.l2cache.ReadExReq_hits::cpu.data 564122 # number of ReadExReq hits 837system.cpu.l2cache.ReadExReq_hits::total 564122 # number of ReadExReq hits 838system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 5120 # number of ReadCleanReq hits 839system.cpu.l2cache.ReadCleanReq_hits::total 5120 # number of ReadCleanReq hits 840system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1590908 # number of ReadSharedReq hits 841system.cpu.l2cache.ReadSharedReq_hits::total 1590908 # number of ReadSharedReq hits 842system.cpu.l2cache.demand_hits::cpu.inst 5120 # number of demand (read+write) hits 843system.cpu.l2cache.demand_hits::cpu.data 2155030 # number of demand (read+write) hits 844system.cpu.l2cache.demand_hits::total 2160150 # number of demand (read+write) hits 845system.cpu.l2cache.overall_hits::cpu.inst 5120 # number of overall hits 846system.cpu.l2cache.overall_hits::cpu.data 2155030 # number of overall hits 847system.cpu.l2cache.overall_hits::total 2160150 # number of overall hits 848system.cpu.l2cache.UpgradeReq_misses::cpu.data 178962 # number of UpgradeReq misses 849system.cpu.l2cache.UpgradeReq_misses::total 178962 # number of UpgradeReq misses 850system.cpu.l2cache.ReadExReq_misses::cpu.data 206662 # number of ReadExReq misses 851system.cpu.l2cache.ReadExReq_misses::total 206662 # number of ReadExReq misses 852system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3498 # number of ReadCleanReq misses 853system.cpu.l2cache.ReadCleanReq_misses::total 3498 # number of ReadCleanReq misses 854system.cpu.l2cache.ReadSharedReq_misses::cpu.data 176672 # number of ReadSharedReq misses 855system.cpu.l2cache.ReadSharedReq_misses::total 176672 # number of ReadSharedReq misses 856system.cpu.l2cache.demand_misses::cpu.inst 3498 # number of demand (read+write) misses 857system.cpu.l2cache.demand_misses::cpu.data 383334 # number of demand (read+write) misses 858system.cpu.l2cache.demand_misses::total 386832 # number of demand (read+write) misses 859system.cpu.l2cache.overall_misses::cpu.inst 3498 # number of overall misses 860system.cpu.l2cache.overall_misses::cpu.data 383334 # number of overall misses 861system.cpu.l2cache.overall_misses::total 386832 # number of overall misses 862system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 13321000 # number of UpgradeReq miss cycles 863system.cpu.l2cache.UpgradeReq_miss_latency::total 13321000 # number of UpgradeReq miss cycles 864system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 16381444000 # number of ReadExReq miss cycles 865system.cpu.l2cache.ReadExReq_miss_latency::total 16381444000 # number of ReadExReq miss cycles 866system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 284753500 # number of ReadCleanReq miss cycles 867system.cpu.l2cache.ReadCleanReq_miss_latency::total 284753500 # number of ReadCleanReq miss cycles 868system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 14216734500 # number of ReadSharedReq miss cycles 869system.cpu.l2cache.ReadSharedReq_miss_latency::total 14216734500 # number of ReadSharedReq miss cycles 870system.cpu.l2cache.demand_miss_latency::cpu.inst 284753500 # number of demand (read+write) miss cycles 871system.cpu.l2cache.demand_miss_latency::cpu.data 30598178500 # number of demand (read+write) miss cycles 872system.cpu.l2cache.demand_miss_latency::total 30882932000 # number of demand (read+write) miss cycles 873system.cpu.l2cache.overall_miss_latency::cpu.inst 284753500 # number of overall miss cycles 874system.cpu.l2cache.overall_miss_latency::cpu.data 30598178500 # number of overall miss cycles 875system.cpu.l2cache.overall_miss_latency::total 30882932000 # number of overall miss cycles 876system.cpu.l2cache.Writeback_accesses::writebacks 2332624 # number of Writeback accesses(hits+misses) 877system.cpu.l2cache.Writeback_accesses::total 2332624 # number of Writeback accesses(hits+misses) 878system.cpu.l2cache.UpgradeReq_accesses::cpu.data 180855 # number of UpgradeReq accesses(hits+misses) 879system.cpu.l2cache.UpgradeReq_accesses::total 180855 # number of UpgradeReq accesses(hits+misses) 880system.cpu.l2cache.ReadExReq_accesses::cpu.data 770784 # number of ReadExReq accesses(hits+misses) 881system.cpu.l2cache.ReadExReq_accesses::total 770784 # number of ReadExReq accesses(hits+misses) 882system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 8618 # number of ReadCleanReq accesses(hits+misses) 883system.cpu.l2cache.ReadCleanReq_accesses::total 8618 # number of ReadCleanReq accesses(hits+misses) 884system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1767580 # number of ReadSharedReq accesses(hits+misses) 885system.cpu.l2cache.ReadSharedReq_accesses::total 1767580 # number of ReadSharedReq accesses(hits+misses) 886system.cpu.l2cache.demand_accesses::cpu.inst 8618 # number of demand (read+write) accesses 887system.cpu.l2cache.demand_accesses::cpu.data 2538364 # number of demand (read+write) accesses 888system.cpu.l2cache.demand_accesses::total 2546982 # number of demand (read+write) accesses 889system.cpu.l2cache.overall_accesses::cpu.inst 8618 # number of overall (read+write) accesses 890system.cpu.l2cache.overall_accesses::cpu.data 2538364 # number of overall (read+write) accesses 891system.cpu.l2cache.overall_accesses::total 2546982 # number of overall (read+write) accesses 892system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.989533 # miss rate for UpgradeReq accesses 893system.cpu.l2cache.UpgradeReq_miss_rate::total 0.989533 # miss rate for UpgradeReq accesses 894system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.268119 # miss rate for ReadExReq accesses 895system.cpu.l2cache.ReadExReq_miss_rate::total 0.268119 # miss rate for ReadExReq accesses 896system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.405895 # miss rate for ReadCleanReq accesses 897system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.405895 # miss rate for ReadCleanReq accesses 898system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.099951 # miss rate for ReadSharedReq accesses 899system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.099951 # miss rate for ReadSharedReq accesses 900system.cpu.l2cache.demand_miss_rate::cpu.inst 0.405895 # miss rate for demand accesses 901system.cpu.l2cache.demand_miss_rate::cpu.data 0.151016 # miss rate for demand accesses 902system.cpu.l2cache.demand_miss_rate::total 0.151879 # miss rate for demand accesses 903system.cpu.l2cache.overall_miss_rate::cpu.inst 0.405895 # miss rate for overall accesses 904system.cpu.l2cache.overall_miss_rate::cpu.data 0.151016 # miss rate for overall accesses 905system.cpu.l2cache.overall_miss_rate::total 0.151879 # miss rate for overall accesses 906system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 74.434796 # average UpgradeReq miss latency 907system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 74.434796 # average UpgradeReq miss latency 908system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79266.841509 # average ReadExReq miss latency 909system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79266.841509 # average ReadExReq miss latency 910system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 81404.659806 # average ReadCleanReq miss latency 911system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 81404.659806 # average ReadCleanReq miss latency 912system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80469.652803 # average ReadSharedReq miss latency 913system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80469.652803 # average ReadSharedReq miss latency 914system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 81404.659806 # average overall miss latency 915system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79821.196398 # average overall miss latency 916system.cpu.l2cache.demand_avg_miss_latency::total 79835.515159 # average overall miss latency 917system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 81404.659806 # average overall miss latency 918system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79821.196398 # average overall miss latency 919system.cpu.l2cache.overall_avg_miss_latency::total 79835.515159 # average overall miss latency 920system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 921system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 922system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 923system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 924system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 925system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 926system.cpu.l2cache.fast_writes 0 # number of fast writes performed 927system.cpu.l2cache.cache_copies 0 # number of cache copies performed 928system.cpu.l2cache.writebacks::writebacks 295029 # number of writebacks 929system.cpu.l2cache.writebacks::total 295029 # number of writebacks 930system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits 931system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits 932system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits 933system.cpu.l2cache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits 934system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits 935system.cpu.l2cache.overall_mshr_hits::total 1 # number of overall MSHR hits 936system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 2030 # number of CleanEvict MSHR misses 937system.cpu.l2cache.CleanEvict_mshr_misses::total 2030 # number of CleanEvict MSHR misses 938system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 178962 # number of UpgradeReq MSHR misses 939system.cpu.l2cache.UpgradeReq_mshr_misses::total 178962 # number of UpgradeReq MSHR misses 940system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206662 # number of ReadExReq MSHR misses 941system.cpu.l2cache.ReadExReq_mshr_misses::total 206662 # number of ReadExReq MSHR misses 942system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3497 # number of ReadCleanReq MSHR misses 943system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3497 # number of ReadCleanReq MSHR misses 944system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 176672 # number of ReadSharedReq MSHR misses 945system.cpu.l2cache.ReadSharedReq_mshr_misses::total 176672 # number of ReadSharedReq MSHR misses 946system.cpu.l2cache.demand_mshr_misses::cpu.inst 3497 # number of demand (read+write) MSHR misses 947system.cpu.l2cache.demand_mshr_misses::cpu.data 383334 # number of demand (read+write) MSHR misses 948system.cpu.l2cache.demand_mshr_misses::total 386831 # number of demand (read+write) MSHR misses 949system.cpu.l2cache.overall_mshr_misses::cpu.inst 3497 # number of overall MSHR misses 950system.cpu.l2cache.overall_mshr_misses::cpu.data 383334 # number of overall MSHR misses 951system.cpu.l2cache.overall_mshr_misses::total 386831 # number of overall MSHR misses 952system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 3764941068 # number of UpgradeReq MSHR miss cycles 953system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 3764941068 # number of UpgradeReq MSHR miss cycles 954system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 14314824000 # number of ReadExReq MSHR miss cycles 955system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 14314824000 # number of ReadExReq MSHR miss cycles 956system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 249717000 # number of ReadCleanReq MSHR miss cycles 957system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 249717000 # number of ReadCleanReq MSHR miss cycles 958system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 12450014500 # number of ReadSharedReq MSHR miss cycles 959system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 12450014500 # number of ReadSharedReq MSHR miss cycles 960system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 249717000 # number of demand (read+write) MSHR miss cycles 961system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 26764838500 # number of demand (read+write) MSHR miss cycles 962system.cpu.l2cache.demand_mshr_miss_latency::total 27014555500 # number of demand (read+write) MSHR miss cycles 963system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 249717000 # number of overall MSHR miss cycles 964system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 26764838500 # number of overall MSHR miss cycles 965system.cpu.l2cache.overall_mshr_miss_latency::total 27014555500 # number of overall MSHR miss cycles 966system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 967system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 968system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.989533 # mshr miss rate for UpgradeReq accesses 969system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.989533 # mshr miss rate for UpgradeReq accesses 970system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.268119 # mshr miss rate for ReadExReq accesses 971system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.268119 # mshr miss rate for ReadExReq accesses 972system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.405779 # mshr miss rate for ReadCleanReq accesses 973system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.405779 # mshr miss rate for ReadCleanReq accesses 974system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.099951 # mshr miss rate for ReadSharedReq accesses 975system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.099951 # mshr miss rate for ReadSharedReq accesses 976system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.405779 # mshr miss rate for demand accesses 977system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.151016 # mshr miss rate for demand accesses 978system.cpu.l2cache.demand_mshr_miss_rate::total 0.151878 # mshr miss rate for demand accesses 979system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.405779 # mshr miss rate for overall accesses 980system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.151016 # mshr miss rate for overall accesses 981system.cpu.l2cache.overall_mshr_miss_rate::total 0.151878 # mshr miss rate for overall accesses 982system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 21037.656419 # average UpgradeReq mshr miss latency 983system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 21037.656419 # average UpgradeReq mshr miss latency 984system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69266.841509 # average ReadExReq mshr miss latency 985system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69266.841509 # average ReadExReq mshr miss latency 986system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 71408.921933 # average ReadCleanReq mshr miss latency 987system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 71408.921933 # average ReadCleanReq mshr miss latency 988system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70469.652803 # average ReadSharedReq mshr miss latency 989system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70469.652803 # average ReadSharedReq mshr miss latency 990system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71408.921933 # average overall mshr miss latency 991system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69821.196398 # average overall mshr miss latency 992system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69835.549633 # average overall mshr miss latency 993system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71408.921933 # average overall mshr miss latency 994system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69821.196398 # average overall mshr miss latency 995system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69835.549633 # average overall mshr miss latency 996system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 997system.cpu.toL2Bus.trans_dist::ReadResp 1957165 # Transaction distribution 998system.cpu.toL2Bus.trans_dist::Writeback 2627653 # Transaction distribution 999system.cpu.toL2Bus.trans_dist::CleanEvict 256317 # Transaction distribution 1000system.cpu.toL2Bus.trans_dist::UpgradeReq 180855 # Transaction distribution 1001system.cpu.toL2Bus.trans_dist::UpgradeResp 180855 # Transaction distribution 1002system.cpu.toL2Bus.trans_dist::ReadExReq 770784 # Transaction distribution 1003system.cpu.toL2Bus.trans_dist::ReadExResp 770784 # Transaction distribution 1004system.cpu.toL2Bus.trans_dist::ReadCleanReq 189586 # Transaction distribution 1005system.cpu.toL2Bus.trans_dist::ReadSharedReq 1767580 # Transaction distribution 1006system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 204722 # Packet count per connected master and slave (bytes) 1007system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7961776 # Packet count per connected master and slave (bytes) 1008system.cpu.toL2Bus.pkt_count::total 8166498 # Packet count per connected master and slave (bytes) 1009system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 551488 # Cumulative packet size per connected master and slave (bytes) 1010system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 311743232 # Cumulative packet size per connected master and slave (bytes) 1011system.cpu.toL2Bus.pkt_size::total 312294720 # Cumulative packet size per connected master and slave (bytes) 1012system.cpu.toL2Bus.snoops 535081 # Total snoops (count) 1013system.cpu.toL2Bus.snoop_fanout::samples 5804166 # Request fanout histogram 1014system.cpu.toL2Bus.snoop_fanout::mean 1.061010 # Request fanout histogram 1015system.cpu.toL2Bus.snoop_fanout::stdev 0.239349 # Request fanout histogram 1016system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1017system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1018system.cpu.toL2Bus.snoop_fanout::1 5450053 93.90% 93.90% # Request fanout histogram 1019system.cpu.toL2Bus.snoop_fanout::2 354113 6.10% 100.00% # Request fanout histogram 1020system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1021system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 1022system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 1023system.cpu.toL2Bus.snoop_fanout::total 5804166 # Request fanout histogram 1024system.cpu.toL2Bus.reqLayer0.occupancy 5083850495 # Layer occupancy (ticks) 1025system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) 1026system.cpu.toL2Bus.respLayer0.occupancy 284382490 # Layer occupancy (ticks) 1027system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 1028system.cpu.toL2Bus.respLayer1.occupancy 3897973573 # Layer occupancy (ticks) 1029system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) 1030system.membus.trans_dist::ReadResp 180168 # Transaction distribution 1031system.membus.trans_dist::Writeback 295029 # Transaction distribution 1032system.membus.trans_dist::CleanEvict 57519 # Transaction distribution 1033system.membus.trans_dist::UpgradeReq 179000 # Transaction distribution 1034system.membus.trans_dist::UpgradeResp 179000 # Transaction distribution 1035system.membus.trans_dist::ReadExReq 206624 # Transaction distribution 1036system.membus.trans_dist::ReadExResp 206624 # Transaction distribution 1037system.membus.trans_dist::ReadSharedReq 180168 # Transaction distribution 1038system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1484132 # Packet count per connected master and slave (bytes) 1039system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1484132 # Packet count per connected master and slave (bytes) 1040system.membus.pkt_count::total 1484132 # Packet count per connected master and slave (bytes) 1041system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43636544 # Cumulative packet size per connected master and slave (bytes) 1042system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43636544 # Cumulative packet size per connected master and slave (bytes) 1043system.membus.pkt_size::total 43636544 # Cumulative packet size per connected master and slave (bytes) 1044system.membus.snoops 0 # Total snoops (count) 1045system.membus.snoop_fanout::samples 918340 # Request fanout histogram 1046system.membus.snoop_fanout::mean 0 # Request fanout histogram 1047system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1048system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1049system.membus.snoop_fanout::0 918340 100.00% 100.00% # Request fanout histogram 1050system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 1051system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1052system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1053system.membus.snoop_fanout::max_value 0 # Request fanout histogram 1054system.membus.snoop_fanout::total 918340 # Request fanout histogram 1055system.membus.reqLayer0.occupancy 2219848930 # Layer occupancy (ticks) 1056system.membus.reqLayer0.utilization 0.5 # Layer utilization (%) 1057system.membus.respLayer1.occupancy 2404009566 # Layer occupancy (ticks) 1058system.membus.respLayer1.utilization 0.6 # Layer utilization (%) 1059 1060---------- End Simulation Statistics ---------- 1061