xref: /gem5/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.451764                       # Number of seconds simulated
sim_ticks                                451764406000                       # Number of ticks simulated
final_tick                               451764406000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 112231                       # Simulator instruction rate (inst/s)
host_op_rate                                   207527                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                               61317335                       # Simulator tick rate (ticks/s)
host_mem_usage                                 367016                       # Number of bytes of host memory used
host_seconds                                  7367.65                       # Real time elapsed on the host
sim_insts                                   826877109                       # Number of instructions simulated
sim_ops                                    1528988701                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu.inst            224064                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data          24540544                       # Number of bytes read from this memory
system.physmem.bytes_read::total             24764608                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst       224064                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          224064                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks     18820736                       # Number of bytes written to this memory
system.physmem.bytes_written::total          18820736                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst               3501                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             383446                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                386947                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          294074                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               294074                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst               495975                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data             54321553                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                54817528                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          495975                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             495975                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks          41660511                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total               41660511                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks          41660511                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst              495975                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data            54321553                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               96478039                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        386948                       # Number of read requests accepted
system.physmem.writeReqs                       294074                       # Number of write requests accepted
system.physmem.readBursts                      386948                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     294074                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 24743168                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                     21504                       # Total number of bytes read from write queue
system.physmem.bytesWritten                  18819072                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  24764672                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys               18820736                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      336                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs         179060                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               24122                       # Per bank write bursts
system.physmem.perBankRdBursts::1               26505                       # Per bank write bursts
system.physmem.perBankRdBursts::2               24681                       # Per bank write bursts
system.physmem.perBankRdBursts::3               24611                       # Per bank write bursts
system.physmem.perBankRdBursts::4               23302                       # Per bank write bursts
system.physmem.perBankRdBursts::5               23732                       # Per bank write bursts
system.physmem.perBankRdBursts::6               24448                       # Per bank write bursts
system.physmem.perBankRdBursts::7               24311                       # Per bank write bursts
system.physmem.perBankRdBursts::8               23620                       # Per bank write bursts
system.physmem.perBankRdBursts::9               23937                       # Per bank write bursts
system.physmem.perBankRdBursts::10              24812                       # Per bank write bursts
system.physmem.perBankRdBursts::11              24076                       # Per bank write bursts
system.physmem.perBankRdBursts::12              23393                       # Per bank write bursts
system.physmem.perBankRdBursts::13              22985                       # Per bank write bursts
system.physmem.perBankRdBursts::14              24096                       # Per bank write bursts
system.physmem.perBankRdBursts::15              23981                       # Per bank write bursts
system.physmem.perBankWrBursts::0               18558                       # Per bank write bursts
system.physmem.perBankWrBursts::1               19850                       # Per bank write bursts
system.physmem.perBankWrBursts::2               18948                       # Per bank write bursts
system.physmem.perBankWrBursts::3               18946                       # Per bank write bursts
system.physmem.perBankWrBursts::4               18040                       # Per bank write bursts
system.physmem.perBankWrBursts::5               18437                       # Per bank write bursts
system.physmem.perBankWrBursts::6               18993                       # Per bank write bursts
system.physmem.perBankWrBursts::7               18991                       # Per bank write bursts
system.physmem.perBankWrBursts::8               18543                       # Per bank write bursts
system.physmem.perBankWrBursts::9               18160                       # Per bank write bursts
system.physmem.perBankWrBursts::10              18841                       # Per bank write bursts
system.physmem.perBankWrBursts::11              17736                       # Per bank write bursts
system.physmem.perBankWrBursts::12              17380                       # Per bank write bursts
system.physmem.perBankWrBursts::13              16967                       # Per bank write bursts
system.physmem.perBankWrBursts::14              17832                       # Per bank write bursts
system.physmem.perBankWrBursts::15              17826                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                    451764392500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  386948                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                 294074                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    381637                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                      4588                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                       337                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                        38                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                        10                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         2                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     6121                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     6527                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                    16919                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                    17478                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                    17566                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                    17579                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                    17557                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                    17583                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                    17609                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                    17628                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                    17613                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                    17619                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                    17776                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                    17688                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                    17635                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                    17848                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                    17586                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                    17479                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                       44                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                       21                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                       19                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                       14                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                       15                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                       18                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                       26                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                       26                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                       21                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                       14                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                        6                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                        3                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                        3                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                        5                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                        5                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                        4                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                        3                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples       147402                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      295.521852                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     174.115334                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     323.715133                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          54829     37.20%     37.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        40372     27.39%     64.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383        13383      9.08%     73.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         7515      5.10%     78.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         5234      3.55%     82.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         3732      2.53%     84.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         3157      2.14%     86.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         2805      1.90%     88.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151        16375     11.11%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total         147402                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples         17447                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        22.158537                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      209.201153                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-1023          17434     99.93%     99.93% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1024-2047            9      0.05%     99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2048-3071            2      0.01%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::3072-4095            1      0.01%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::26624-27647            1      0.01%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total           17447                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples         17447                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        16.853786                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       16.774474                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev        2.995315                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19           17244     98.84%     98.84% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23             149      0.85%     99.69% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27              24      0.14%     99.83% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31               7      0.04%     99.87% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35               4      0.02%     99.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39               4      0.02%     99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43               2      0.01%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47               2      0.01%     99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51               1      0.01%     99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59               2      0.01%     99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67               1      0.01%     99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75               1      0.01%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83               1      0.01%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-99               1      0.01%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-107             1      0.01%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-147             1      0.01%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::200-203             1      0.01%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::236-239             1      0.01%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total           17447                       # Writes before turning the bus around for reads
system.physmem.totQLat                     4338654000                       # Total ticks spent queuing
system.physmem.totMemAccLat               11587629000                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                   1933060000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       11222.24                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  29972.24                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                          54.77                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                          41.66                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                       54.82                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                       41.66                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.75                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.43                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.33                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.02                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        21.93                       # Average write queue length when enqueuing
system.physmem.readRowHits                     317693                       # Number of row buffer hits during reads
system.physmem.writeRowHits                    215552                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   82.17                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  73.30                       # Row buffer hit rate for writes
system.physmem.avgGap                       663362.41                       # Average gap between requests
system.physmem.pageHitRate                      78.34                       # Row buffer hit rate, read and write combined
system.physmem.memoryStateTime::IDLE     312439483250                       # Time in different power states
system.physmem.memoryStateTime::REF       15085200000                       # Time in different power states
system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
system.physmem.memoryStateTime::ACT      124235187750                       # Time in different power states
system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
system.physmem.actEnergy::0                 567642600                       # Energy for activate commands per rank (pJ)
system.physmem.actEnergy::1                 546300720                       # Energy for activate commands per rank (pJ)
system.physmem.preEnergy::0                 309725625                       # Energy for precharge commands per rank (pJ)
system.physmem.preEnergy::1                 298080750                       # Energy for precharge commands per rank (pJ)
system.physmem.readEnergy::0               1526397600                       # Energy for read commands per rank (pJ)
system.physmem.readEnergy::1               1488559800                       # Energy for read commands per rank (pJ)
system.physmem.writeEnergy::0               976736880                       # Energy for write commands per rank (pJ)
system.physmem.writeEnergy::1               928272960                       # Energy for write commands per rank (pJ)
system.physmem.refreshEnergy::0           29506651200                       # Energy for refresh commands per rank (pJ)
system.physmem.refreshEnergy::1           29506651200                       # Energy for refresh commands per rank (pJ)
system.physmem.actBackEnergy::0           64826566830                       # Energy for active background per rank (pJ)
system.physmem.actBackEnergy::1           62404533090                       # Energy for active background per rank (pJ)
system.physmem.preBackEnergy::0          214189673250                       # Energy for precharge background per rank (pJ)
system.physmem.preBackEnergy::1          216314264250                       # Energy for precharge background per rank (pJ)
system.physmem.totalEnergy::0            311903393985                       # Total energy per rank (pJ)
system.physmem.totalEnergy::1            311486662770                       # Total energy per rank (pJ)
system.physmem.averagePower::0             690.420687                       # Core power per rank (mW)
system.physmem.averagePower::1             689.498222                       # Core power per rank (mW)
system.membus.trans_dist::ReadReq              179971                       # Transaction distribution
system.membus.trans_dist::ReadResp             179970                       # Transaction distribution
system.membus.trans_dist::Writeback            294074                       # Transaction distribution
system.membus.trans_dist::UpgradeReq           179060                       # Transaction distribution
system.membus.trans_dist::UpgradeResp          179060                       # Transaction distribution
system.membus.trans_dist::ReadExReq            206977                       # Transaction distribution
system.membus.trans_dist::ReadExResp           206977                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1426089                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total      1426089                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                1426089                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     43585344                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::total     43585344                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                43585344                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                                0                       # Total snoops (count)
system.membus.snoop_fanout::samples            860082                       # Request fanout histogram
system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                  860082    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
system.membus.snoop_fanout::total              860082                       # Request fanout histogram
system.membus.reqLayer0.occupancy          3467694500                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.8                       # Layer utilization (%)
system.membus.respLayer1.occupancy         3995364517                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              0.9                       # Layer utilization (%)
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.branchPred.lookups               231811700                       # Number of BP lookups
system.cpu.branchPred.condPredicted         231811700                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect           9749774                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups            132043202                       # Number of BTB lookups
system.cpu.branchPred.BTBHits               129334985                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             97.948992                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                28034260                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect            1466603                       # Number of incorrect RAS predictions.
system.cpu.apic_clk_domain.clock                 8000                       # Clock period in ticks
system.cpu.workload.num_syscalls                  551                       # Number of system calls
system.cpu.numCycles                        903528833                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles          186193866                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                     1278658073                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                   231811700                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches          157369245                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                     706106364                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                20239877                       # Number of cycles fetch has spent squashing
system.cpu.fetch.TlbCycles                       1021                       # Number of cycles fetch has spent waiting for tlb
system.cpu.fetch.MiscStallCycles                98431                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles        825605                       # Number of stall cycles due to pending traps
system.cpu.fetch.PendingQuiesceStallCycles         1885                       # Number of stall cycles due to pending quiesce instructions
system.cpu.fetch.IcacheWaitRetryStallCycles           18                       # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines                 180561661                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes               2733230                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.ItlbSquashes                       2                       # Number of outstanding ITLB misses that were squashed
system.cpu.fetch.rateDist::samples          903347128                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              2.632355                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             3.341099                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                492680103     54.54%     54.54% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                 34123521      3.78%     58.32% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                 33275891      3.68%     62.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                 33627770      3.72%     65.72% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4                 27182272      3.01%     68.73% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5                 27855831      3.08%     71.82% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6                 37310737      4.13%     75.95% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7                 33828820      3.74%     79.69% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8                183462183     20.31%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total            903347128                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.256563                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        1.415182                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                127724228                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles             442644539                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                 240143304                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles              82715119                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles               10119938                       # Number of cycles decode is squashing
system.cpu.decode.DecodedInsts             2233772257                       # Number of instructions handled by decode
system.cpu.rename.SquashCycles               10119938                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                159908050                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles               227395701                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles          31553                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                 285948747                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles             219943139                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts             2183809979                       # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents                169165                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents              140088736                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents               23988102                       # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents               45039827                       # Number of times rename has blocked due to SQ full
system.cpu.rename.RenamedOperands          2289176453                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups            5526365527                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups       3514194402                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups             52054                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps            1614040854                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                675135599                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts               2312                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts           2290                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                 426537147                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads            530783294                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores           210410050                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads         240827707                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores         72173678                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                 2112785390                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded               25204                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                1829110925                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued            437516                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined       579120624                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined   1007560279                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved          24652                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples     903347128                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         2.024815                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        2.069613                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0           319005991     35.31%     35.31% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1           130297139     14.42%     49.74% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2           120325805     13.32%     63.06% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3           111338872     12.33%     75.38% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4            91295017     10.11%     85.49% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5            61401299      6.80%     92.29% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6            43188488      4.78%     97.07% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7            19128067      2.12%     99.18% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8             7366450      0.82%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total       903347128                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                11298417     42.44%     42.44% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                      0      0.00%     42.44% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%     42.44% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%     42.44% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%     42.44% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%     42.44% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%     42.44% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%     42.44% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     42.44% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%     42.44% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     42.44% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%     42.44% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%     42.44% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%     42.44% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%     42.44% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%     42.44% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     42.44% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%     42.44% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     42.44% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     42.44% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     42.44% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     42.44% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     42.44% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     42.44% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     42.44% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     42.44% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     42.44% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     42.44% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     42.44% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead               12271176     46.10%     88.54% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite               3050228     11.46%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass           2719541      0.15%      0.15% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu            1212963557     66.31%     66.46% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult               389902      0.02%     66.48% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv               3881002      0.21%     66.70% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd                 122      0.00%     66.70% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     66.70% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     66.70% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     66.70% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     66.70% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     66.70% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     66.70% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     66.70% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     66.70% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     66.70% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     66.70% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     66.70% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     66.70% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     66.70% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     66.70% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     66.70% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     66.70% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     66.70% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     66.70% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     66.70% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     66.70% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     66.70% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     66.70% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     66.70% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     66.70% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     66.70% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead            435438564     23.81%     90.50% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite           173718237      9.50%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total             1829110925                       # Type of FU issued
system.cpu.iq.rate                           2.024408                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                    26619821                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.014553                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads         4588595925                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes        2692200263                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses   1799476115                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads               30390                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes              66120                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses         6655                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses             1852997149                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                   14056                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads        185108157                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads    146685050                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses       212835                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation       388917                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores     61249864                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads        18586                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked           815                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles               10119938                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles               166724787                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles              10164048                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts          2112810594                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts            401170                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts             530787207                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts            210410050                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts               7737                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                4462758                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents               3568650                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents         388917                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect        5751622                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect      4609702                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts             10361324                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts            1807989007                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts             429368726                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts          21121918                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                             0                       # number of nop insts executed
system.cpu.iew.exec_refs                    599512830                       # number of memory reference insts executed
system.cpu.iew.exec_branches                171944433                       # Number of branches executed
system.cpu.iew.exec_stores                  170144104                       # Number of stores executed
system.cpu.iew.exec_rate                     2.001031                       # Inst execution rate
system.cpu.iew.wb_sent                     1804759601                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                    1799482770                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                1369602342                       # num instructions producing a value
system.cpu.iew.wb_consumers                2093301343                       # num instructions consuming a value
system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate                       1.991616                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.654279                       # average fanout of values written-back
system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts       584047933                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls             552                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts           9837228                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples    824173638                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     1.855178                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     2.504108                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0    355774644     43.17%     43.17% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1    174944190     21.23%     64.39% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2     57267566      6.95%     71.34% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3     86311577     10.47%     81.82% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4     27168668      3.30%     85.11% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5     27065091      3.28%     88.40% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6      9878369      1.20%     89.59% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7      8803957      1.07%     90.66% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8     76959576      9.34%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total    824173638                       # Number of insts commited each cycle
system.cpu.commit.committedInsts            826877109                       # Number of instructions committed
system.cpu.commit.committedOps             1528988701                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                      533262343                       # Number of memory references committed
system.cpu.commit.loads                     384102157                       # Number of loads committed
system.cpu.commit.membars                           0                       # Number of memory barriers committed
system.cpu.commit.branches                  149758583                       # Number of branches committed
system.cpu.commit.fp_insts                          0                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                1526605509                       # Number of committed integer instructions.
system.cpu.commit.function_calls             17673145                       # Number of function calls committed.
system.cpu.commit.op_class_0::No_OpClass      1819099      0.12%      0.12% # Class of committed instruction
system.cpu.commit.op_class_0::IntAlu        989721889     64.73%     64.85% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult          306834      0.02%     64.87% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv          3878536      0.25%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd              0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp              0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt              0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult             0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv              0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd               0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu               0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp               0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt               0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc              0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult              0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift             0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd            0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp            0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt            0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc            0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead       384102157     25.12%     90.24% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite      149160186      9.76%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total        1528988701                       # Class of committed instruction
system.cpu.commit.bw_lim_events              76959576                       # number cycles where commit BW limit reached
system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
system.cpu.rob.rob_reads                   2860250696                       # The number of ROB reads
system.cpu.rob.rob_writes                  4305432556                       # The number of ROB writes
system.cpu.timesIdled                            2603                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                          181705                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts                   826877109                       # Number of Instructions Simulated
system.cpu.committedOps                    1528988701                       # Number of Ops (including micro ops) Simulated
system.cpu.cpi                               1.092700                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         1.092700                       # CPI: Total CPI of All Threads
system.cpu.ipc                               0.915164                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         0.915164                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads               2763452214                       # number of integer regfile reads
system.cpu.int_regfile_writes              1467518123                       # number of integer regfile writes
system.cpu.fp_regfile_reads                      6756                       # number of floating regfile reads
system.cpu.fp_regfile_writes                      202                       # number of floating regfile writes
system.cpu.cc_regfile_reads                 600952146                       # number of cc regfile reads
system.cpu.cc_regfile_writes                409697644                       # number of cc regfile writes
system.cpu.misc_regfile_reads               991728878                       # number of misc regfile reads
system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
system.cpu.toL2Bus.trans_dist::ReadReq        1956687                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp       1956686                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback      2333034                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq       180860                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp       180860                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq       771518                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp       771518                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       198212                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      7771975                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total           7970187                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       551552                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    311785216                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total          312336768                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops                      180976                       # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples      5242099                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean               3                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::3            5242099    100.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::4                  0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value            3                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value            3                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total        5242099                       # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy     4970549506                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          1.1                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy     284884490                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy    3981162622                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          0.9                       # Layer utilization (%)
system.cpu.icache.tags.replacements              7001                       # number of replacements
system.cpu.icache.tags.tagsinuse          1081.953602                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs           180366705                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs              8614                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs          20938.786278                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst  1081.953602                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.528298                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.528298                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024         1613                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0           65                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1           10                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2           55                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3          311                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4         1172                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024     0.787598                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses         361312916                       # Number of tag accesses
system.cpu.icache.tags.data_accesses        361312916                       # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst    180369624                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total       180369624                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst     180369624                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total        180369624                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst    180369624                       # number of overall hits
system.cpu.icache.overall_hits::total       180369624                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst       192037                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total        192037                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst       192037                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total         192037                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst       192037                       # number of overall misses
system.cpu.icache.overall_misses::total        192037                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst   1182728989                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total   1182728989                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst   1182728989                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total   1182728989                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst   1182728989                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total   1182728989                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst    180561661                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total    180561661                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst    180561661                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total    180561661                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst    180561661                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total    180561661                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.001064                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.001064                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.001064                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.001064                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.001064                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.001064                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst  6158.859954                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total  6158.859954                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst  6158.859954                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total  6158.859954                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst  6158.859954                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total  6158.859954                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs          857                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                15                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs    57.133333                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst         2443                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total         2443                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst         2443                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total         2443                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst         2443                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total         2443                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst       189594                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total       189594                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst       189594                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total       189594                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst       189594                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total       189594                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    702034010                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total    702034010                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst    702034010                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total    702034010                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst    702034010                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total    702034010                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.001050                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.001050                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.001050                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.001050                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.001050                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.001050                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst  3702.828201                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total  3702.828201                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst  3702.828201                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total  3702.828201                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst  3702.828201                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total  3702.828201                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements           354269                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        29686.230679                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs            3704231                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs           386628                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs             9.580866                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle     196903741500                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 21108.649111                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst   250.939279                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data  8326.642289                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.644185                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.007658                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.254109                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.905952                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024        32359                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0           81                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1            1                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2          247                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3        11757                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4        20273                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.987518                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses         41649377                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses        41649377                       # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.inst         5116                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data      1590623                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total        1595739                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks      2333034                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total      2333034                       # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data         1835                       # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total         1835                       # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data       564506                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total       564506                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst         5116                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data      2155129                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total         2160245                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst         5116                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data      2155129                       # number of overall hits
system.cpu.l2cache.overall_hits::total        2160245                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst         3502                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data       176470                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total       179972                       # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data       179025                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total       179025                       # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data       207012                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       207012                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst         3502                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       383482                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        386984                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst         3502                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       383482                       # number of overall misses
system.cpu.l2cache.overall_misses::total       386984                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    259185750                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data  12941216954                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total  13200402704                       # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data      9580588                       # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total      9580588                       # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  14943351215                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total  14943351215                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst    259185750                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data  27884568169                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total  28143753919                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst    259185750                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data  27884568169                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total  28143753919                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst         8618                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data      1767093                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total      1775711                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks      2333034                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total      2333034                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data       180860                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total       180860                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data       771518                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       771518                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst         8618                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data      2538611                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      2547229                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst         8618                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data      2538611                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      2547229                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.406359                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.099865                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.101352                       # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.989854                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total     0.989854                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.268318                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.268318                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.406359                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.151060                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.151924                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.406359                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.151060                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.151924                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74010.779555                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 73333.807185                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 73346.980108                       # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data    53.515364                       # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total    53.515364                       # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72185.917797                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72185.917797                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74010.779555                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72714.151300                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 72725.885099                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74010.779555                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72714.151300                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 72725.885099                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks       294074                       # number of writebacks
system.cpu.l2cache.writebacks::total           294074                       # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst            1                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total            1                       # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst            1                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total            1                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst            1                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total            1                       # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         3501                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data       176470                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total       179971                       # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data       179025                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total       179025                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       207012                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       207012                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst         3501                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       383482                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       386983                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst         3501                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       383482                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       386983                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    215395750                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data  10692730954                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total  10908126704                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data   1807258037                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total   1807258037                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  12309448785                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  12309448785                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    215395750                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  23002179739                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total  23217575489                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    215395750                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  23002179739                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total  23217575489                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.406243                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.099865                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.101352                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.989854                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.989854                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.268318                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.268318                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.406243                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.151060                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.151923                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.406243                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.151060                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.151923                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61524.064553                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60592.344047                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60610.468931                       # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10095.003698                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10095.003698                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59462.489059                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59462.489059                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61524.064553                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59982.423527                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59996.370613                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61524.064553                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59982.423527                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59996.370613                       # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.dcache.tags.replacements           2534514                       # number of replacements
system.cpu.dcache.tags.tagsinuse          4088.721227                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs           388791403                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs           2538610                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs            153.151293                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle        1658510250                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data  4088.721227                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.998223                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.998223                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0           28                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1           20                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2          861                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3         3187                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses         786699916                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses        786699916                       # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data    240205034                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total       240205034                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data    148189734                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total      148189734                       # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data     388394768                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total        388394768                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data    388394768                       # number of overall hits
system.cpu.dcache.overall_hits::total       388394768                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data      2715417                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total       2715417                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data       970468                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total       970468                       # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data      3685885                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        3685885                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      3685885                       # number of overall misses
system.cpu.dcache.overall_misses::total       3685885                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data  55284847940                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total  55284847940                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data  27786671624                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total  27786671624                       # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data  83071519564                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total  83071519564                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data  83071519564                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total  83071519564                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data    242920451                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total    242920451                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data    149160202                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total    149160202                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data    392080653                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total    392080653                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data    392080653                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total    392080653                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.011178                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.011178                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.006506                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.006506                       # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.009401                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.009401                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.009401                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.009401                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20359.616199                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 20359.616199                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28632.238903                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 28632.238903                       # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 22537.740479                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 22537.740479                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 22537.740479                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 22537.740479                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs         8578                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets           67                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs               914                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               5                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs     9.385120                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets    13.400000                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks      2333034                       # number of writebacks
system.cpu.dcache.writebacks::total           2333034                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data       948123                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total       948123                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data        18291                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total        18291                       # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data       966414                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total       966414                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data       966414                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total       966414                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1767294                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total      1767294                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       952177                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       952177                       # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data      2719471                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total      2719471                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data      2719471                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total      2719471                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  30652377753                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total  30652377753                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  25560484625                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total  25560484625                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  56212862378                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  56212862378                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  56212862378                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  56212862378                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.007275                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.007275                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.006384                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.006384                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.006936                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.006936                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.006936                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.006936                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17344.243659                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17344.243659                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 26844.257554                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 26844.257554                       # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20670.513632                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 20670.513632                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20670.513632                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 20670.513632                       # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate

---------- End Simulation Statistics   ----------