stats.txt revision 10352:5f1f92bf76ee
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.451995 # Number of seconds simulated 4sim_ticks 451994820000 # Number of ticks simulated 5final_tick 451994820000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 140398 # Simulator instruction rate (inst/s) 8host_op_rate 259611 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 76745378 # Simulator tick rate (ticks/s) 10host_mem_usage 366028 # Number of bytes of host memory used 11host_seconds 5889.54 # Real time elapsed on the host 12sim_insts 826877109 # Number of instructions simulated 13sim_ops 1528988701 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 225600 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 24537408 # Number of bytes read from this memory 18system.physmem.bytes_read::total 24763008 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 225600 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 225600 # Number of instructions bytes read from this memory 21system.physmem.bytes_written::writebacks 18819200 # Number of bytes written to this memory 22system.physmem.bytes_written::total 18819200 # Number of bytes written to this memory 23system.physmem.num_reads::cpu.inst 3525 # Number of read requests responded to by this memory 24system.physmem.num_reads::cpu.data 383397 # Number of read requests responded to by this memory 25system.physmem.num_reads::total 386922 # Number of read requests responded to by this memory 26system.physmem.num_writes::writebacks 294050 # Number of write requests responded to by this memory 27system.physmem.num_writes::total 294050 # Number of write requests responded to by this memory 28system.physmem.bw_read::cpu.inst 499121 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::cpu.data 54286923 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::total 54786044 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_inst_read::cpu.inst 499121 # Instruction read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::total 499121 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_write::writebacks 41635875 # Write bandwidth from this memory (bytes/s) 34system.physmem.bw_write::total 41635875 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_total::writebacks 41635875 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::cpu.inst 499121 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.data 54286923 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::total 96421919 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.readReqs 386922 # Number of read requests accepted 40system.physmem.writeReqs 294050 # Number of write requests accepted 41system.physmem.readBursts 386922 # Number of DRAM read bursts, including those serviced by the write queue 42system.physmem.writeBursts 294050 # Number of DRAM write bursts, including those merged in the write queue 43system.physmem.bytesReadDRAM 24741248 # Total number of bytes read from DRAM 44system.physmem.bytesReadWrQ 21760 # Total number of bytes read from write queue 45system.physmem.bytesWritten 18817856 # Total number of bytes written to DRAM 46system.physmem.bytesReadSys 24763008 # Total read bytes from the system interface side 47system.physmem.bytesWrittenSys 18819200 # Total written bytes from the system interface side 48system.physmem.servicedByWrQ 340 # Number of DRAM read bursts serviced by the write queue 49system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 50system.physmem.neitherReadNorWriteReqs 187441 # Number of requests that are neither read nor write 51system.physmem.perBankRdBursts::0 24125 # Per bank write bursts 52system.physmem.perBankRdBursts::1 26507 # Per bank write bursts 53system.physmem.perBankRdBursts::2 24686 # Per bank write bursts 54system.physmem.perBankRdBursts::3 24623 # Per bank write bursts 55system.physmem.perBankRdBursts::4 23302 # Per bank write bursts 56system.physmem.perBankRdBursts::5 23746 # Per bank write bursts 57system.physmem.perBankRdBursts::6 24462 # Per bank write bursts 58system.physmem.perBankRdBursts::7 24273 # Per bank write bursts 59system.physmem.perBankRdBursts::8 23635 # Per bank write bursts 60system.physmem.perBankRdBursts::9 23973 # Per bank write bursts 61system.physmem.perBankRdBursts::10 24803 # Per bank write bursts 62system.physmem.perBankRdBursts::11 24077 # Per bank write bursts 63system.physmem.perBankRdBursts::12 23354 # Per bank write bursts 64system.physmem.perBankRdBursts::13 22972 # Per bank write bursts 65system.physmem.perBankRdBursts::14 24056 # Per bank write bursts 66system.physmem.perBankRdBursts::15 23988 # Per bank write bursts 67system.physmem.perBankWrBursts::0 18554 # Per bank write bursts 68system.physmem.perBankWrBursts::1 19852 # Per bank write bursts 69system.physmem.perBankWrBursts::2 18949 # Per bank write bursts 70system.physmem.perBankWrBursts::3 18947 # Per bank write bursts 71system.physmem.perBankWrBursts::4 18033 # Per bank write bursts 72system.physmem.perBankWrBursts::5 18442 # Per bank write bursts 73system.physmem.perBankWrBursts::6 18997 # Per bank write bursts 74system.physmem.perBankWrBursts::7 18979 # Per bank write bursts 75system.physmem.perBankWrBursts::8 18544 # Per bank write bursts 76system.physmem.perBankWrBursts::9 18172 # Per bank write bursts 77system.physmem.perBankWrBursts::10 18845 # Per bank write bursts 78system.physmem.perBankWrBursts::11 17739 # Per bank write bursts 79system.physmem.perBankWrBursts::12 17374 # Per bank write bursts 80system.physmem.perBankWrBursts::13 16976 # Per bank write bursts 81system.physmem.perBankWrBursts::14 17812 # Per bank write bursts 82system.physmem.perBankWrBursts::15 17814 # Per bank write bursts 83system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 84system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 85system.physmem.totGap 451994795000 # Total gap between requests 86system.physmem.readPktSize::0 0 # Read request sizes (log2) 87system.physmem.readPktSize::1 0 # Read request sizes (log2) 88system.physmem.readPktSize::2 0 # Read request sizes (log2) 89system.physmem.readPktSize::3 0 # Read request sizes (log2) 90system.physmem.readPktSize::4 0 # Read request sizes (log2) 91system.physmem.readPktSize::5 0 # Read request sizes (log2) 92system.physmem.readPktSize::6 386922 # Read request sizes (log2) 93system.physmem.writePktSize::0 0 # Write request sizes (log2) 94system.physmem.writePktSize::1 0 # Write request sizes (log2) 95system.physmem.writePktSize::2 0 # Write request sizes (log2) 96system.physmem.writePktSize::3 0 # Write request sizes (log2) 97system.physmem.writePktSize::4 0 # Write request sizes (log2) 98system.physmem.writePktSize::5 0 # Write request sizes (log2) 99system.physmem.writePktSize::6 294050 # Write request sizes (log2) 100system.physmem.rdQLenPdf::0 381621 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::1 4565 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::2 350 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::3 36 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 132system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 133system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 134system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::15 6304 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::16 6696 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::17 16856 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::18 17449 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::19 17548 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::20 17578 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::21 17578 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::22 17585 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::23 17629 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::24 17625 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::25 17630 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::26 17600 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::27 17764 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::28 17623 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::29 17600 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::30 17825 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::31 17512 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::32 17461 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::33 42 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::34 30 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::35 22 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::36 15 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::37 6 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::38 8 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::39 6 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::40 6 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::41 5 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::42 6 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::43 4 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::44 4 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::45 6 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::46 4 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::47 4 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::48 1 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::49 1 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::50 1 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::51 1 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 196system.physmem.bytesPerActivate::samples 147161 # Bytes accessed per row activation 197system.physmem.bytesPerActivate::mean 295.990160 # Bytes accessed per row activation 198system.physmem.bytesPerActivate::gmean 174.516116 # Bytes accessed per row activation 199system.physmem.bytesPerActivate::stdev 323.823787 # Bytes accessed per row activation 200system.physmem.bytesPerActivate::0-127 54586 37.09% 37.09% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::128-255 40330 27.41% 64.50% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::256-383 13573 9.22% 73.72% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::384-511 7350 4.99% 78.72% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::512-639 5242 3.56% 82.28% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::640-767 3782 2.57% 84.85% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::768-895 3105 2.11% 86.96% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::896-1023 2774 1.89% 88.84% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::1024-1151 16419 11.16% 100.00% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::total 147161 # Bytes accessed per row activation 210system.physmem.rdPerTurnAround::samples 17431 # Reads before turning the bus around for writes 211system.physmem.rdPerTurnAround::mean 22.177500 # Reads before turning the bus around for writes 212system.physmem.rdPerTurnAround::stdev 209.580978 # Reads before turning the bus around for writes 213system.physmem.rdPerTurnAround::0-1023 17417 99.92% 99.92% # Reads before turning the bus around for writes 214system.physmem.rdPerTurnAround::1024-2047 9 0.05% 99.97% # Reads before turning the bus around for writes 215system.physmem.rdPerTurnAround::2048-3071 3 0.02% 99.99% # Reads before turning the bus around for writes 216system.physmem.rdPerTurnAround::3072-4095 1 0.01% 99.99% # Reads before turning the bus around for writes 217system.physmem.rdPerTurnAround::26624-27647 1 0.01% 100.00% # Reads before turning the bus around for writes 218system.physmem.rdPerTurnAround::total 17431 # Reads before turning the bus around for writes 219system.physmem.wrPerTurnAround::samples 17431 # Writes before turning the bus around for reads 220system.physmem.wrPerTurnAround::mean 16.868166 # Writes before turning the bus around for reads 221system.physmem.wrPerTurnAround::gmean 16.795967 # Writes before turning the bus around for reads 222system.physmem.wrPerTurnAround::stdev 2.664820 # Writes before turning the bus around for reads 223system.physmem.wrPerTurnAround::16-19 17240 98.90% 98.90% # Writes before turning the bus around for reads 224system.physmem.wrPerTurnAround::20-23 139 0.80% 99.70% # Writes before turning the bus around for reads 225system.physmem.wrPerTurnAround::24-27 22 0.13% 99.83% # Writes before turning the bus around for reads 226system.physmem.wrPerTurnAround::28-31 7 0.04% 99.87% # Writes before turning the bus around for reads 227system.physmem.wrPerTurnAround::32-35 7 0.04% 99.91% # Writes before turning the bus around for reads 228system.physmem.wrPerTurnAround::36-39 1 0.01% 99.91% # Writes before turning the bus around for reads 229system.physmem.wrPerTurnAround::40-43 2 0.01% 99.93% # Writes before turning the bus around for reads 230system.physmem.wrPerTurnAround::44-47 2 0.01% 99.94% # Writes before turning the bus around for reads 231system.physmem.wrPerTurnAround::52-55 1 0.01% 99.94% # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::60-63 1 0.01% 99.95% # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::64-67 1 0.01% 99.95% # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::68-71 1 0.01% 99.96% # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::72-75 2 0.01% 99.97% # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::76-79 1 0.01% 99.98% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::80-83 1 0.01% 99.98% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::104-107 1 0.01% 99.99% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::124-127 1 0.01% 99.99% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::248-251 1 0.01% 100.00% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::total 17431 # Writes before turning the bus around for reads 242system.physmem.totQLat 4215540250 # Total ticks spent queuing 243system.physmem.totMemAccLat 11463952750 # Total ticks spent from burst creation until serviced by the DRAM 244system.physmem.totBusLat 1932910000 # Total ticks spent in databus transfers 245system.physmem.avgQLat 10904.65 # Average queueing delay per DRAM burst 246system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 247system.physmem.avgMemAccLat 29654.65 # Average memory access latency per DRAM burst 248system.physmem.avgRdBW 54.74 # Average DRAM read bandwidth in MiByte/s 249system.physmem.avgWrBW 41.63 # Average achieved write bandwidth in MiByte/s 250system.physmem.avgRdBWSys 54.79 # Average system read bandwidth in MiByte/s 251system.physmem.avgWrBWSys 41.64 # Average system write bandwidth in MiByte/s 252system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 253system.physmem.busUtil 0.75 # Data bus utilization in percentage 254system.physmem.busUtilRead 0.43 # Data bus utilization in percentage for reads 255system.physmem.busUtilWrite 0.33 # Data bus utilization in percentage for writes 256system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing 257system.physmem.avgWrQLen 21.68 # Average write queue length when enqueuing 258system.physmem.readRowHits 317951 # Number of row buffer hits during reads 259system.physmem.writeRowHits 215487 # Number of row buffer hits during writes 260system.physmem.readRowHitRate 82.25 # Row buffer hit rate for reads 261system.physmem.writeRowHitRate 73.28 # Row buffer hit rate for writes 262system.physmem.avgGap 663749.46 # Average gap between requests 263system.physmem.pageHitRate 78.37 # Row buffer hit rate, read and write combined 264system.physmem.memoryStateTime::IDLE 313004335000 # Time in different power states 265system.physmem.memoryStateTime::REF 15093000000 # Time in different power states 266system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states 267system.physmem.memoryStateTime::ACT 123894751250 # Time in different power states 268system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states 269system.membus.throughput 96421919 # Throughput (bytes/s) 270system.membus.trans_dist::ReadReq 179924 # Transaction distribution 271system.membus.trans_dist::ReadResp 179924 # Transaction distribution 272system.membus.trans_dist::Writeback 294050 # Transaction distribution 273system.membus.trans_dist::UpgradeReq 187441 # Transaction distribution 274system.membus.trans_dist::UpgradeResp 187441 # Transaction distribution 275system.membus.trans_dist::ReadExReq 206998 # Transaction distribution 276system.membus.trans_dist::ReadExResp 206998 # Transaction distribution 277system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1442776 # Packet count per connected master and slave (bytes) 278system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1442776 # Packet count per connected master and slave (bytes) 279system.membus.pkt_count::total 1442776 # Packet count per connected master and slave (bytes) 280system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43582208 # Cumulative packet size per connected master and slave (bytes) 281system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 43582208 # Cumulative packet size per connected master and slave (bytes) 282system.membus.tot_pkt_size::total 43582208 # Cumulative packet size per connected master and slave (bytes) 283system.membus.data_through_bus 43582208 # Total data (bytes) 284system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 285system.membus.reqLayer0.occupancy 3478883000 # Layer occupancy (ticks) 286system.membus.reqLayer0.utilization 0.8 # Layer utilization (%) 287system.membus.respLayer1.occupancy 4009907869 # Layer occupancy (ticks) 288system.membus.respLayer1.utilization 0.9 # Layer utilization (%) 289system.cpu_clk_domain.clock 500 # Clock period in ticks 290system.cpu.branchPred.lookups 231904597 # Number of BP lookups 291system.cpu.branchPred.condPredicted 231904597 # Number of conditional branches predicted 292system.cpu.branchPred.condIncorrect 9750550 # Number of conditional branches incorrect 293system.cpu.branchPred.BTBLookups 132080719 # Number of BTB lookups 294system.cpu.branchPred.BTBHits 129337939 # Number of BTB hits 295system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 296system.cpu.branchPred.BTBHitPct 97.923406 # BTB Hit Percentage 297system.cpu.branchPred.usedRAS 28018771 # Number of times the RAS was used to get a target. 298system.cpu.branchPred.RASInCorrect 1471173 # Number of incorrect RAS predictions. 299system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks 300system.cpu.workload.num_syscalls 551 # Number of system calls 301system.cpu.numCycles 903989670 # number of cpu cycles simulated 302system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 303system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 304system.cpu.fetch.icacheStallCycles 186228043 # Number of cycles fetch is stalled on an Icache miss 305system.cpu.fetch.Insts 1278728730 # Number of instructions fetch has processed 306system.cpu.fetch.Branches 231904597 # Number of branches that fetch encountered 307system.cpu.fetch.predictedBranches 157356710 # Number of branches that fetch has predicted taken 308system.cpu.fetch.Cycles 706545798 # Number of cycles fetch has run and was not squashing or blocked 309system.cpu.fetch.SquashCycles 20232368 # Number of cycles fetch has spent squashing 310system.cpu.fetch.TlbCycles 1261 # Number of cycles fetch has spent waiting for tlb 311system.cpu.fetch.MiscStallCycles 97161 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 312system.cpu.fetch.PendingTrapStallCycles 819145 # Number of stall cycles due to pending traps 313system.cpu.fetch.PendingQuiesceStallCycles 1413 # Number of stall cycles due to pending quiesce instructions 314system.cpu.fetch.IcacheWaitRetryStallCycles 33 # Number of stall cycles due to full MSHR 315system.cpu.fetch.CacheLines 180562981 # Number of cache lines fetched 316system.cpu.fetch.IcacheSquashes 2742944 # Number of outstanding Icache misses that were squashed 317system.cpu.fetch.ItlbSquashes 6 # Number of outstanding ITLB misses that were squashed 318system.cpu.fetch.rateDist::samples 903809038 # Number of instructions fetched each cycle (Total) 319system.cpu.fetch.rateDist::mean 2.631393 # Number of instructions fetched each cycle (Total) 320system.cpu.fetch.rateDist::stdev 3.340645 # Number of instructions fetched each cycle (Total) 321system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 322system.cpu.fetch.rateDist::0 493137827 54.56% 54.56% # Number of instructions fetched each cycle (Total) 323system.cpu.fetch.rateDist::1 34022388 3.76% 58.33% # Number of instructions fetched each cycle (Total) 324system.cpu.fetch.rateDist::2 33226150 3.68% 62.00% # Number of instructions fetched each cycle (Total) 325system.cpu.fetch.rateDist::3 33639943 3.72% 65.72% # Number of instructions fetched each cycle (Total) 326system.cpu.fetch.rateDist::4 27288864 3.02% 68.74% # Number of instructions fetched each cycle (Total) 327system.cpu.fetch.rateDist::5 27888530 3.09% 71.83% # Number of instructions fetched each cycle (Total) 328system.cpu.fetch.rateDist::6 37359921 4.13% 75.96% # Number of instructions fetched each cycle (Total) 329system.cpu.fetch.rateDist::7 33838464 3.74% 79.71% # Number of instructions fetched each cycle (Total) 330system.cpu.fetch.rateDist::8 183406951 20.29% 100.00% # Number of instructions fetched each cycle (Total) 331system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 332system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 333system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 334system.cpu.fetch.rateDist::total 903809038 # Number of instructions fetched each cycle (Total) 335system.cpu.fetch.branchRate 0.256535 # Number of branch fetches per cycle 336system.cpu.fetch.rate 1.414539 # Number of inst fetches per cycle 337system.cpu.decode.IdleCycles 127644706 # Number of cycles decode is idle 338system.cpu.decode.BlockedCycles 443195641 # Number of cycles decode is blocked 339system.cpu.decode.RunCycles 240140806 # Number of cycles decode is running 340system.cpu.decode.UnblockCycles 82711701 # Number of cycles decode is unblocking 341system.cpu.decode.SquashCycles 10116184 # Number of cycles decode is squashing 342system.cpu.decode.DecodedInsts 2234020290 # Number of instructions handled by decode 343system.cpu.rename.SquashCycles 10116184 # Number of cycles rename is squashing 344system.cpu.rename.IdleCycles 159943307 # Number of cycles rename is idle 345system.cpu.rename.BlockCycles 227345077 # Number of cycles rename is blocking 346system.cpu.rename.serializeStallCycles 31762 # count of cycles rename stalled for serializing inst 347system.cpu.rename.RunCycles 285830207 # Number of cycles rename is running 348system.cpu.rename.UnblockCycles 220542501 # Number of cycles rename is unblocking 349system.cpu.rename.RenamedInsts 2184066361 # Number of instructions processed by rename 350system.cpu.rename.ROBFullEvents 187446 # Number of times rename has blocked due to ROB full 351system.cpu.rename.IQFullEvents 141210134 # Number of times rename has blocked due to IQ full 352system.cpu.rename.LQFullEvents 24116907 # Number of times rename has blocked due to LQ full 353system.cpu.rename.SQFullEvents 44409056 # Number of times rename has blocked due to SQ full 354system.cpu.rename.RenamedOperands 2289283449 # Number of destination operands rename has renamed 355system.cpu.rename.RenameLookups 5527269614 # Number of register rename lookups that rename has made 356system.cpu.rename.int_rename_lookups 3515022878 # Number of integer rename lookups 357system.cpu.rename.fp_rename_lookups 52095 # Number of floating rename lookups 358system.cpu.rename.CommittedMaps 1614040854 # Number of HB maps that are committed 359system.cpu.rename.UndoneMaps 675242595 # Number of HB maps that are undone due to squashing 360system.cpu.rename.serializingInsts 2439 # count of serializing insts renamed 361system.cpu.rename.tempSerializingInsts 2426 # count of temporary serializing insts renamed 362system.cpu.rename.skidInsts 427926698 # count of insts added to the skid buffer 363system.cpu.memDep0.insertedLoads 530815140 # Number of loads inserted to the mem dependence unit. 364system.cpu.memDep0.insertedStores 210460978 # Number of stores inserted to the mem dependence unit. 365system.cpu.memDep0.conflictingLoads 240742093 # Number of conflicting loads. 366system.cpu.memDep0.conflictingStores 72507120 # Number of conflicting stores. 367system.cpu.iq.iqInstsAdded 2112837832 # Number of instructions added to the IQ (excludes non-spec) 368system.cpu.iq.iqNonSpecInstsAdded 25371 # Number of non-speculative instructions added to the IQ 369system.cpu.iq.iqInstsIssued 1829122546 # Number of instructions issued 370system.cpu.iq.iqSquashedInstsIssued 418643 # Number of squashed instructions issued 371system.cpu.iq.iqSquashedInstsExamined 579202583 # Number of squashed instructions iterated over during squash; mainly for profiling 372system.cpu.iq.iqSquashedOperandsExamined 1008004721 # Number of squashed operands that are examined and possibly removed from graph 373system.cpu.iq.iqSquashedNonSpecRemoved 24819 # Number of squashed non-spec instructions that were removed 374system.cpu.iq.issued_per_cycle::samples 903809038 # Number of insts issued each cycle 375system.cpu.iq.issued_per_cycle::mean 2.023793 # Number of insts issued each cycle 376system.cpu.iq.issued_per_cycle::stdev 2.068035 # Number of insts issued each cycle 377system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 378system.cpu.iq.issued_per_cycle::0 318787682 35.27% 35.27% # Number of insts issued each cycle 379system.cpu.iq.issued_per_cycle::1 130796714 14.47% 49.74% # Number of insts issued each cycle 380system.cpu.iq.issued_per_cycle::2 120566882 13.34% 63.08% # Number of insts issued each cycle 381system.cpu.iq.issued_per_cycle::3 111745228 12.36% 75.45% # Number of insts issued each cycle 382system.cpu.iq.issued_per_cycle::4 90951236 10.06% 85.51% # Number of insts issued each cycle 383system.cpu.iq.issued_per_cycle::5 61425555 6.80% 92.31% # Number of insts issued each cycle 384system.cpu.iq.issued_per_cycle::6 43081513 4.77% 97.07% # Number of insts issued each cycle 385system.cpu.iq.issued_per_cycle::7 19099237 2.11% 99.19% # Number of insts issued each cycle 386system.cpu.iq.issued_per_cycle::8 7354991 0.81% 100.00% # Number of insts issued each cycle 387system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 388system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 389system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 390system.cpu.iq.issued_per_cycle::total 903809038 # Number of insts issued each cycle 391system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 392system.cpu.iq.fu_full::IntAlu 11301614 42.50% 42.50% # attempts to use FU when none available 393system.cpu.iq.fu_full::IntMult 0 0.00% 42.50% # attempts to use FU when none available 394system.cpu.iq.fu_full::IntDiv 0 0.00% 42.50% # attempts to use FU when none available 395system.cpu.iq.fu_full::FloatAdd 0 0.00% 42.50% # attempts to use FU when none available 396system.cpu.iq.fu_full::FloatCmp 0 0.00% 42.50% # attempts to use FU when none available 397system.cpu.iq.fu_full::FloatCvt 0 0.00% 42.50% # attempts to use FU when none available 398system.cpu.iq.fu_full::FloatMult 0 0.00% 42.50% # attempts to use FU when none available 399system.cpu.iq.fu_full::FloatDiv 0 0.00% 42.50% # attempts to use FU when none available 400system.cpu.iq.fu_full::FloatSqrt 0 0.00% 42.50% # attempts to use FU when none available 401system.cpu.iq.fu_full::SimdAdd 0 0.00% 42.50% # attempts to use FU when none available 402system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 42.50% # attempts to use FU when none available 403system.cpu.iq.fu_full::SimdAlu 0 0.00% 42.50% # attempts to use FU when none available 404system.cpu.iq.fu_full::SimdCmp 0 0.00% 42.50% # attempts to use FU when none available 405system.cpu.iq.fu_full::SimdCvt 0 0.00% 42.50% # attempts to use FU when none available 406system.cpu.iq.fu_full::SimdMisc 0 0.00% 42.50% # attempts to use FU when none available 407system.cpu.iq.fu_full::SimdMult 0 0.00% 42.50% # attempts to use FU when none available 408system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 42.50% # attempts to use FU when none available 409system.cpu.iq.fu_full::SimdShift 0 0.00% 42.50% # attempts to use FU when none available 410system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 42.50% # attempts to use FU when none available 411system.cpu.iq.fu_full::SimdSqrt 0 0.00% 42.50% # attempts to use FU when none available 412system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 42.50% # attempts to use FU when none available 413system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 42.50% # attempts to use FU when none available 414system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 42.50% # attempts to use FU when none available 415system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 42.50% # attempts to use FU when none available 416system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 42.50% # attempts to use FU when none available 417system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 42.50% # attempts to use FU when none available 418system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 42.50% # attempts to use FU when none available 419system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 42.50% # attempts to use FU when none available 420system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 42.50% # attempts to use FU when none available 421system.cpu.iq.fu_full::MemRead 12240522 46.03% 88.53% # attempts to use FU when none available 422system.cpu.iq.fu_full::MemWrite 3051129 11.47% 100.00% # attempts to use FU when none available 423system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 424system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 425system.cpu.iq.FU_type_0::No_OpClass 2716130 0.15% 0.15% # Type of FU issued 426system.cpu.iq.FU_type_0::IntAlu 1212914034 66.31% 66.46% # Type of FU issued 427system.cpu.iq.FU_type_0::IntMult 390088 0.02% 66.48% # Type of FU issued 428system.cpu.iq.FU_type_0::IntDiv 3880828 0.21% 66.69% # Type of FU issued 429system.cpu.iq.FU_type_0::FloatAdd 131 0.00% 66.69% # Type of FU issued 430system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.69% # Type of FU issued 431system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.69% # Type of FU issued 432system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.69% # Type of FU issued 433system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.69% # Type of FU issued 434system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.69% # Type of FU issued 435system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.69% # Type of FU issued 436system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.69% # Type of FU issued 437system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.69% # Type of FU issued 438system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.69% # Type of FU issued 439system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.69% # Type of FU issued 440system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.69% # Type of FU issued 441system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.69% # Type of FU issued 442system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.69% # Type of FU issued 443system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.69% # Type of FU issued 444system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.69% # Type of FU issued 445system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.69% # Type of FU issued 446system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.69% # Type of FU issued 447system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.69% # Type of FU issued 448system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.69% # Type of FU issued 449system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.69% # Type of FU issued 450system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.69% # Type of FU issued 451system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.69% # Type of FU issued 452system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.69% # Type of FU issued 453system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.69% # Type of FU issued 454system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.69% # Type of FU issued 455system.cpu.iq.FU_type_0::MemRead 435498208 23.81% 90.50% # Type of FU issued 456system.cpu.iq.FU_type_0::MemWrite 173723127 9.50% 100.00% # Type of FU issued 457system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 458system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 459system.cpu.iq.FU_type_0::total 1829122546 # Type of FU issued 460system.cpu.iq.rate 2.023389 # Inst issue rate 461system.cpu.iq.fu_busy_cnt 26593265 # FU busy when requested 462system.cpu.iq.fu_busy_rate 0.014539 # FU busy rate (busy events/executed inst) 463system.cpu.iq.int_inst_queue_reads 4589034997 # Number of integer instruction queue reads 464system.cpu.iq.int_inst_queue_writes 2692332475 # Number of integer instruction queue writes 465system.cpu.iq.int_inst_queue_wakeup_accesses 1799432823 # Number of integer instruction queue wakeup accesses 466system.cpu.iq.fp_inst_queue_reads 31041 # Number of floating instruction queue reads 467system.cpu.iq.fp_inst_queue_writes 65517 # Number of floating instruction queue writes 468system.cpu.iq.fp_inst_queue_wakeup_accesses 6732 # Number of floating instruction queue wakeup accesses 469system.cpu.iq.int_alu_accesses 1852985406 # Number of integer alu accesses 470system.cpu.iq.fp_alu_accesses 14275 # Number of floating point alu accesses 471system.cpu.iew.lsq.thread0.forwLoads 184951720 # Number of loads that had data forwarded from stores 472system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 473system.cpu.iew.lsq.thread0.squashedLoads 146715422 # Number of loads squashed 474system.cpu.iew.lsq.thread0.ignoredResponses 214760 # Number of memory responses ignored because the instruction is squashed 475system.cpu.iew.lsq.thread0.memOrderViolation 386957 # Number of memory ordering violations 476system.cpu.iew.lsq.thread0.squashedStores 61300792 # Number of stores squashed 477system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 478system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 479system.cpu.iew.lsq.thread0.rescheduledLoads 19364 # Number of loads that were rescheduled 480system.cpu.iew.lsq.thread0.cacheBlocked 985 # Number of times an access to memory failed due to the cache being blocked 481system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 482system.cpu.iew.iewSquashCycles 10116184 # Number of cycles IEW is squashing 483system.cpu.iew.iewBlockCycles 166422776 # Number of cycles IEW is blocking 484system.cpu.iew.iewUnblockCycles 10091675 # Number of cycles IEW is unblocking 485system.cpu.iew.iewDispatchedInsts 2112863203 # Number of instructions dispatched to IQ 486system.cpu.iew.iewDispSquashedInsts 400666 # Number of squashed instructions skipped by dispatch 487system.cpu.iew.iewDispLoadInsts 530817579 # Number of dispatched load instructions 488system.cpu.iew.iewDispStoreInsts 210460978 # Number of dispatched store instructions 489system.cpu.iew.iewDispNonSpecInsts 7795 # Number of dispatched non-speculative instructions 490system.cpu.iew.iewIQFullEvents 4446284 # Number of times the IQ has become full, causing a stall 491system.cpu.iew.iewLSQFullEvents 3513204 # Number of times the LSQ has become full, causing a stall 492system.cpu.iew.memOrderViolationEvents 386957 # Number of memory order violations 493system.cpu.iew.predictedTakenIncorrect 5751076 # Number of branches that were predicted taken incorrectly 494system.cpu.iew.predictedNotTakenIncorrect 4630882 # Number of branches that were predicted not taken incorrectly 495system.cpu.iew.branchMispredicts 10381958 # Number of branch mispredicts detected at execute 496system.cpu.iew.iewExecutedInsts 1808023539 # Number of executed instructions 497system.cpu.iew.iewExecLoadInsts 429432372 # Number of load instructions executed 498system.cpu.iew.iewExecSquashedInsts 21099007 # Number of squashed instructions skipped in execute 499system.cpu.iew.exec_swp 0 # number of swp insts executed 500system.cpu.iew.exec_nop 0 # number of nop insts executed 501system.cpu.iew.exec_refs 599547125 # number of memory reference insts executed 502system.cpu.iew.exec_branches 171962867 # Number of branches executed 503system.cpu.iew.exec_stores 170114753 # Number of stores executed 504system.cpu.iew.exec_rate 2.000049 # Inst execution rate 505system.cpu.iew.wb_sent 1804768043 # cumulative count of insts sent to commit 506system.cpu.iew.wb_count 1799439555 # cumulative count of insts written-back 507system.cpu.iew.wb_producers 1369592486 # num instructions producing a value 508system.cpu.iew.wb_consumers 2093220611 # num instructions consuming a value 509system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 510system.cpu.iew.wb_rate 1.990553 # insts written-back per cycle 511system.cpu.iew.wb_fanout 0.654299 # average fanout of values written-back 512system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 513system.cpu.commit.commitSquashedInsts 584100413 # The number of squashed insts skipped by commit 514system.cpu.commit.commitNonSpecStalls 552 # The number of times commit has been forced to stall to communicate backwards 515system.cpu.commit.branchMispredicts 9836004 # The number of times a branch was mispredicted 516system.cpu.commit.committed_per_cycle::samples 824637269 # Number of insts commited each cycle 517system.cpu.commit.committed_per_cycle::mean 1.854135 # Number of insts commited each cycle 518system.cpu.commit.committed_per_cycle::stdev 2.503267 # Number of insts commited each cycle 519system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 520system.cpu.commit.committed_per_cycle::0 355822450 43.15% 43.15% # Number of insts commited each cycle 521system.cpu.commit.committed_per_cycle::1 175430054 21.27% 64.42% # Number of insts commited each cycle 522system.cpu.commit.committed_per_cycle::2 57247046 6.94% 71.36% # Number of insts commited each cycle 523system.cpu.commit.committed_per_cycle::3 86422444 10.48% 81.84% # Number of insts commited each cycle 524system.cpu.commit.committed_per_cycle::4 27139119 3.29% 85.14% # Number of insts commited each cycle 525system.cpu.commit.committed_per_cycle::5 27033560 3.28% 88.41% # Number of insts commited each cycle 526system.cpu.commit.committed_per_cycle::6 9709039 1.18% 89.59% # Number of insts commited each cycle 527system.cpu.commit.committed_per_cycle::7 8849743 1.07% 90.66% # Number of insts commited each cycle 528system.cpu.commit.committed_per_cycle::8 76983814 9.34% 100.00% # Number of insts commited each cycle 529system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 530system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 531system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 532system.cpu.commit.committed_per_cycle::total 824637269 # Number of insts commited each cycle 533system.cpu.commit.committedInsts 826877109 # Number of instructions committed 534system.cpu.commit.committedOps 1528988701 # Number of ops (including micro ops) committed 535system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 536system.cpu.commit.refs 533262343 # Number of memory references committed 537system.cpu.commit.loads 384102157 # Number of loads committed 538system.cpu.commit.membars 0 # Number of memory barriers committed 539system.cpu.commit.branches 149758583 # Number of branches committed 540system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. 541system.cpu.commit.int_insts 1526605509 # Number of committed integer instructions. 542system.cpu.commit.function_calls 17673145 # Number of function calls committed. 543system.cpu.commit.op_class_0::No_OpClass 1819099 0.12% 0.12% # Class of committed instruction 544system.cpu.commit.op_class_0::IntAlu 989721889 64.73% 64.85% # Class of committed instruction 545system.cpu.commit.op_class_0::IntMult 306834 0.02% 64.87% # Class of committed instruction 546system.cpu.commit.op_class_0::IntDiv 3878536 0.25% 65.12% # Class of committed instruction 547system.cpu.commit.op_class_0::FloatAdd 0 0.00% 65.12% # Class of committed instruction 548system.cpu.commit.op_class_0::FloatCmp 0 0.00% 65.12% # Class of committed instruction 549system.cpu.commit.op_class_0::FloatCvt 0 0.00% 65.12% # Class of committed instruction 550system.cpu.commit.op_class_0::FloatMult 0 0.00% 65.12% # Class of committed instruction 551system.cpu.commit.op_class_0::FloatDiv 0 0.00% 65.12% # Class of committed instruction 552system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 65.12% # Class of committed instruction 553system.cpu.commit.op_class_0::SimdAdd 0 0.00% 65.12% # Class of committed instruction 554system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 65.12% # Class of committed instruction 555system.cpu.commit.op_class_0::SimdAlu 0 0.00% 65.12% # Class of committed instruction 556system.cpu.commit.op_class_0::SimdCmp 0 0.00% 65.12% # Class of committed instruction 557system.cpu.commit.op_class_0::SimdCvt 0 0.00% 65.12% # Class of committed instruction 558system.cpu.commit.op_class_0::SimdMisc 0 0.00% 65.12% # Class of committed instruction 559system.cpu.commit.op_class_0::SimdMult 0 0.00% 65.12% # Class of committed instruction 560system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 65.12% # Class of committed instruction 561system.cpu.commit.op_class_0::SimdShift 0 0.00% 65.12% # Class of committed instruction 562system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 65.12% # Class of committed instruction 563system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 65.12% # Class of committed instruction 564system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 65.12% # Class of committed instruction 565system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 65.12% # Class of committed instruction 566system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 65.12% # Class of committed instruction 567system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 65.12% # Class of committed instruction 568system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 65.12% # Class of committed instruction 569system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 65.12% # Class of committed instruction 570system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 65.12% # Class of committed instruction 571system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.12% # Class of committed instruction 572system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.12% # Class of committed instruction 573system.cpu.commit.op_class_0::MemRead 384102157 25.12% 90.24% # Class of committed instruction 574system.cpu.commit.op_class_0::MemWrite 149160186 9.76% 100.00% # Class of committed instruction 575system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 576system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 577system.cpu.commit.op_class_0::total 1528988701 # Class of committed instruction 578system.cpu.commit.bw_lim_events 76983814 # number cycles where commit BW limit reached 579system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 580system.cpu.rob.rob_reads 2860742569 # The number of ROB reads 581system.cpu.rob.rob_writes 4305535749 # The number of ROB writes 582system.cpu.timesIdled 2688 # Number of times that the entire CPU went into an idle state and unscheduled itself 583system.cpu.idleCycles 180632 # Total number of cycles that the CPU has spent unscheduled due to idling 584system.cpu.committedInsts 826877109 # Number of Instructions Simulated 585system.cpu.committedOps 1528988701 # Number of Ops (including micro ops) Simulated 586system.cpu.cpi 1.093258 # CPI: Cycles Per Instruction 587system.cpu.cpi_total 1.093258 # CPI: Total CPI of All Threads 588system.cpu.ipc 0.914698 # IPC: Instructions Per Cycle 589system.cpu.ipc_total 0.914698 # IPC: Total IPC of All Threads 590system.cpu.int_regfile_reads 2763635866 # number of integer regfile reads 591system.cpu.int_regfile_writes 1467536960 # number of integer regfile writes 592system.cpu.fp_regfile_reads 6799 # number of floating regfile reads 593system.cpu.fp_regfile_writes 207 # number of floating regfile writes 594system.cpu.cc_regfile_reads 600939716 # number of cc regfile reads 595system.cpu.cc_regfile_writes 409698109 # number of cc regfile writes 596system.cpu.misc_regfile_reads 991748256 # number of misc regfile reads 597system.cpu.misc_regfile_writes 1 # number of misc regfile writes 598system.cpu.toL2Bus.throughput 717782102 # Throughput (bytes/s) 599system.cpu.toL2Bus.trans_dist::ReadReq 1964869 # Transaction distribution 600system.cpu.toL2Bus.trans_dist::ReadResp 1964868 # Transaction distribution 601system.cpu.toL2Bus.trans_dist::Writeback 2332907 # Transaction distribution 602system.cpu.toL2Bus.trans_dist::UpgradeReq 189308 # Transaction distribution 603system.cpu.toL2Bus.trans_dist::UpgradeResp 189308 # Transaction distribution 604system.cpu.toL2Bus.trans_dist::ReadExReq 771503 # Transaction distribution 605system.cpu.toL2Bus.trans_dist::ReadExResp 771503 # Transaction distribution 606system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 206675 # Packet count per connected master and slave (bytes) 607system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7788165 # Packet count per connected master and slave (bytes) 608system.cpu.toL2Bus.pkt_count::total 7994840 # Packet count per connected master and slave (bytes) 609system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 551936 # Cumulative packet size per connected master and slave (bytes) 610system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 311758592 # Cumulative packet size per connected master and slave (bytes) 611system.cpu.toL2Bus.tot_pkt_size::total 312310528 # Cumulative packet size per connected master and slave (bytes) 612system.cpu.toL2Bus.data_through_bus 312310528 # Total data (bytes) 613system.cpu.toL2Bus.snoop_data_through_bus 12123264 # Total snoop data (bytes) 614system.cpu.toL2Bus.reqLayer0.occupancy 4978085168 # Layer occupancy (ticks) 615system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) 616system.cpu.toL2Bus.respLayer0.occupancy 297561992 # Layer occupancy (ticks) 617system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 618system.cpu.toL2Bus.respLayer1.occupancy 3985022632 # Layer occupancy (ticks) 619system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) 620system.cpu.icache.tags.replacements 6996 # number of replacements 621system.cpu.icache.tags.tagsinuse 1078.278361 # Cycle average of tags in use 622system.cpu.icache.tags.total_refs 180359326 # Total number of references to valid blocks. 623system.cpu.icache.tags.sampled_refs 8602 # Sample count of references to valid blocks. 624system.cpu.icache.tags.avg_refs 20967.138572 # Average number of references to valid blocks. 625system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 626system.cpu.icache.tags.occ_blocks::cpu.inst 1078.278361 # Average occupied blocks per requestor 627system.cpu.icache.tags.occ_percent::cpu.inst 0.526503 # Average percentage of cache occupancy 628system.cpu.icache.tags.occ_percent::total 0.526503 # Average percentage of cache occupancy 629system.cpu.icache.tags.occ_task_id_blocks::1024 1606 # Occupied blocks per task id 630system.cpu.icache.tags.age_task_id_blocks_1024::0 68 # Occupied blocks per task id 631system.cpu.icache.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id 632system.cpu.icache.tags.age_task_id_blocks_1024::2 56 # Occupied blocks per task id 633system.cpu.icache.tags.age_task_id_blocks_1024::3 301 # Occupied blocks per task id 634system.cpu.icache.tags.age_task_id_blocks_1024::4 1173 # Occupied blocks per task id 635system.cpu.icache.tags.occ_task_id_percent::1024 0.784180 # Percentage of cache occupancy per task id 636system.cpu.icache.tags.tag_accesses 361324012 # Number of tag accesses 637system.cpu.icache.tags.data_accesses 361324012 # Number of data accesses 638system.cpu.icache.ReadReq_hits::cpu.inst 180362453 # number of ReadReq hits 639system.cpu.icache.ReadReq_hits::total 180362453 # number of ReadReq hits 640system.cpu.icache.demand_hits::cpu.inst 180362453 # number of demand (read+write) hits 641system.cpu.icache.demand_hits::total 180362453 # number of demand (read+write) hits 642system.cpu.icache.overall_hits::cpu.inst 180362453 # number of overall hits 643system.cpu.icache.overall_hits::total 180362453 # number of overall hits 644system.cpu.icache.ReadReq_misses::cpu.inst 200528 # number of ReadReq misses 645system.cpu.icache.ReadReq_misses::total 200528 # number of ReadReq misses 646system.cpu.icache.demand_misses::cpu.inst 200528 # number of demand (read+write) misses 647system.cpu.icache.demand_misses::total 200528 # number of demand (read+write) misses 648system.cpu.icache.overall_misses::cpu.inst 200528 # number of overall misses 649system.cpu.icache.overall_misses::total 200528 # number of overall misses 650system.cpu.icache.ReadReq_miss_latency::cpu.inst 1221704738 # number of ReadReq miss cycles 651system.cpu.icache.ReadReq_miss_latency::total 1221704738 # number of ReadReq miss cycles 652system.cpu.icache.demand_miss_latency::cpu.inst 1221704738 # number of demand (read+write) miss cycles 653system.cpu.icache.demand_miss_latency::total 1221704738 # number of demand (read+write) miss cycles 654system.cpu.icache.overall_miss_latency::cpu.inst 1221704738 # number of overall miss cycles 655system.cpu.icache.overall_miss_latency::total 1221704738 # number of overall miss cycles 656system.cpu.icache.ReadReq_accesses::cpu.inst 180562981 # number of ReadReq accesses(hits+misses) 657system.cpu.icache.ReadReq_accesses::total 180562981 # number of ReadReq accesses(hits+misses) 658system.cpu.icache.demand_accesses::cpu.inst 180562981 # number of demand (read+write) accesses 659system.cpu.icache.demand_accesses::total 180562981 # number of demand (read+write) accesses 660system.cpu.icache.overall_accesses::cpu.inst 180562981 # number of overall (read+write) accesses 661system.cpu.icache.overall_accesses::total 180562981 # number of overall (read+write) accesses 662system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001111 # miss rate for ReadReq accesses 663system.cpu.icache.ReadReq_miss_rate::total 0.001111 # miss rate for ReadReq accesses 664system.cpu.icache.demand_miss_rate::cpu.inst 0.001111 # miss rate for demand accesses 665system.cpu.icache.demand_miss_rate::total 0.001111 # miss rate for demand accesses 666system.cpu.icache.overall_miss_rate::cpu.inst 0.001111 # miss rate for overall accesses 667system.cpu.icache.overall_miss_rate::total 0.001111 # miss rate for overall accesses 668system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6092.439649 # average ReadReq miss latency 669system.cpu.icache.ReadReq_avg_miss_latency::total 6092.439649 # average ReadReq miss latency 670system.cpu.icache.demand_avg_miss_latency::cpu.inst 6092.439649 # average overall miss latency 671system.cpu.icache.demand_avg_miss_latency::total 6092.439649 # average overall miss latency 672system.cpu.icache.overall_avg_miss_latency::cpu.inst 6092.439649 # average overall miss latency 673system.cpu.icache.overall_avg_miss_latency::total 6092.439649 # average overall miss latency 674system.cpu.icache.blocked_cycles::no_mshrs 899 # number of cycles access was blocked 675system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 676system.cpu.icache.blocked::no_mshrs 14 # number of cycles access was blocked 677system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 678system.cpu.icache.avg_blocked_cycles::no_mshrs 64.214286 # average number of cycles each access was blocked 679system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 680system.cpu.icache.fast_writes 0 # number of fast writes performed 681system.cpu.icache.cache_copies 0 # number of cache copies performed 682system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2477 # number of ReadReq MSHR hits 683system.cpu.icache.ReadReq_mshr_hits::total 2477 # number of ReadReq MSHR hits 684system.cpu.icache.demand_mshr_hits::cpu.inst 2477 # number of demand (read+write) MSHR hits 685system.cpu.icache.demand_mshr_hits::total 2477 # number of demand (read+write) MSHR hits 686system.cpu.icache.overall_mshr_hits::cpu.inst 2477 # number of overall MSHR hits 687system.cpu.icache.overall_mshr_hits::total 2477 # number of overall MSHR hits 688system.cpu.icache.ReadReq_mshr_misses::cpu.inst 198051 # number of ReadReq MSHR misses 689system.cpu.icache.ReadReq_mshr_misses::total 198051 # number of ReadReq MSHR misses 690system.cpu.icache.demand_mshr_misses::cpu.inst 198051 # number of demand (read+write) MSHR misses 691system.cpu.icache.demand_mshr_misses::total 198051 # number of demand (read+write) MSHR misses 692system.cpu.icache.overall_mshr_misses::cpu.inst 198051 # number of overall MSHR misses 693system.cpu.icache.overall_mshr_misses::total 198051 # number of overall MSHR misses 694system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 720791257 # number of ReadReq MSHR miss cycles 695system.cpu.icache.ReadReq_mshr_miss_latency::total 720791257 # number of ReadReq MSHR miss cycles 696system.cpu.icache.demand_mshr_miss_latency::cpu.inst 720791257 # number of demand (read+write) MSHR miss cycles 697system.cpu.icache.demand_mshr_miss_latency::total 720791257 # number of demand (read+write) MSHR miss cycles 698system.cpu.icache.overall_mshr_miss_latency::cpu.inst 720791257 # number of overall MSHR miss cycles 699system.cpu.icache.overall_mshr_miss_latency::total 720791257 # number of overall MSHR miss cycles 700system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001097 # mshr miss rate for ReadReq accesses 701system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001097 # mshr miss rate for ReadReq accesses 702system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001097 # mshr miss rate for demand accesses 703system.cpu.icache.demand_mshr_miss_rate::total 0.001097 # mshr miss rate for demand accesses 704system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001097 # mshr miss rate for overall accesses 705system.cpu.icache.overall_mshr_miss_rate::total 0.001097 # mshr miss rate for overall accesses 706system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 3639.422457 # average ReadReq mshr miss latency 707system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 3639.422457 # average ReadReq mshr miss latency 708system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 3639.422457 # average overall mshr miss latency 709system.cpu.icache.demand_avg_mshr_miss_latency::total 3639.422457 # average overall mshr miss latency 710system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 3639.422457 # average overall mshr miss latency 711system.cpu.icache.overall_avg_mshr_miss_latency::total 3639.422457 # average overall mshr miss latency 712system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 713system.cpu.l2cache.tags.replacements 354243 # number of replacements 714system.cpu.l2cache.tags.tagsinuse 29686.826365 # Cycle average of tags in use 715system.cpu.l2cache.tags.total_refs 3703753 # Total number of references to valid blocks. 716system.cpu.l2cache.tags.sampled_refs 386599 # Sample count of references to valid blocks. 717system.cpu.l2cache.tags.avg_refs 9.580348 # Average number of references to valid blocks. 718system.cpu.l2cache.tags.warmup_cycle 196870877000 # Cycle when the warmup percentage was hit. 719system.cpu.l2cache.tags.occ_blocks::writebacks 21114.566965 # Average occupied blocks per requestor 720system.cpu.l2cache.tags.occ_blocks::cpu.inst 251.784741 # Average occupied blocks per requestor 721system.cpu.l2cache.tags.occ_blocks::cpu.data 8320.474659 # Average occupied blocks per requestor 722system.cpu.l2cache.tags.occ_percent::writebacks 0.644365 # Average percentage of cache occupancy 723system.cpu.l2cache.tags.occ_percent::cpu.inst 0.007684 # Average percentage of cache occupancy 724system.cpu.l2cache.tags.occ_percent::cpu.data 0.253921 # Average percentage of cache occupancy 725system.cpu.l2cache.tags.occ_percent::total 0.905970 # Average percentage of cache occupancy 726system.cpu.l2cache.tags.occ_task_id_blocks::1024 32356 # Occupied blocks per task id 727system.cpu.l2cache.tags.age_task_id_blocks_1024::0 86 # Occupied blocks per task id 728system.cpu.l2cache.tags.age_task_id_blocks_1024::2 245 # Occupied blocks per task id 729system.cpu.l2cache.tags.age_task_id_blocks_1024::3 11756 # Occupied blocks per task id 730system.cpu.l2cache.tags.age_task_id_blocks_1024::4 20269 # Occupied blocks per task id 731system.cpu.l2cache.tags.occ_task_id_percent::1024 0.987427 # Percentage of cache occupancy per task id 732system.cpu.l2cache.tags.tag_accesses 41713697 # Number of tag accesses 733system.cpu.l2cache.tags.data_accesses 41713697 # Number of data accesses 734system.cpu.l2cache.ReadReq_hits::cpu.inst 5098 # number of ReadReq hits 735system.cpu.l2cache.ReadReq_hits::cpu.data 1590419 # number of ReadReq hits 736system.cpu.l2cache.ReadReq_hits::total 1595517 # number of ReadReq hits 737system.cpu.l2cache.Writeback_hits::writebacks 2332907 # number of Writeback hits 738system.cpu.l2cache.Writeback_hits::total 2332907 # number of Writeback hits 739system.cpu.l2cache.UpgradeReq_hits::cpu.data 1899 # number of UpgradeReq hits 740system.cpu.l2cache.UpgradeReq_hits::total 1899 # number of UpgradeReq hits 741system.cpu.l2cache.ReadExReq_hits::cpu.data 564473 # number of ReadExReq hits 742system.cpu.l2cache.ReadExReq_hits::total 564473 # number of ReadExReq hits 743system.cpu.l2cache.demand_hits::cpu.inst 5098 # number of demand (read+write) hits 744system.cpu.l2cache.demand_hits::cpu.data 2154892 # number of demand (read+write) hits 745system.cpu.l2cache.demand_hits::total 2159990 # number of demand (read+write) hits 746system.cpu.l2cache.overall_hits::cpu.inst 5098 # number of overall hits 747system.cpu.l2cache.overall_hits::cpu.data 2154892 # number of overall hits 748system.cpu.l2cache.overall_hits::total 2159990 # number of overall hits 749system.cpu.l2cache.ReadReq_misses::cpu.inst 3527 # number of ReadReq misses 750system.cpu.l2cache.ReadReq_misses::cpu.data 176399 # number of ReadReq misses 751system.cpu.l2cache.ReadReq_misses::total 179926 # number of ReadReq misses 752system.cpu.l2cache.UpgradeReq_misses::cpu.data 187409 # number of UpgradeReq misses 753system.cpu.l2cache.UpgradeReq_misses::total 187409 # number of UpgradeReq misses 754system.cpu.l2cache.ReadExReq_misses::cpu.data 207030 # number of ReadExReq misses 755system.cpu.l2cache.ReadExReq_misses::total 207030 # number of ReadExReq misses 756system.cpu.l2cache.demand_misses::cpu.inst 3527 # number of demand (read+write) misses 757system.cpu.l2cache.demand_misses::cpu.data 383429 # number of demand (read+write) misses 758system.cpu.l2cache.demand_misses::total 386956 # number of demand (read+write) misses 759system.cpu.l2cache.overall_misses::cpu.inst 3527 # number of overall misses 760system.cpu.l2cache.overall_misses::cpu.data 383429 # number of overall misses 761system.cpu.l2cache.overall_misses::total 386956 # number of overall misses 762system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 260064000 # number of ReadReq miss cycles 763system.cpu.l2cache.ReadReq_miss_latency::cpu.data 12901251712 # number of ReadReq miss cycles 764system.cpu.l2cache.ReadReq_miss_latency::total 13161315712 # number of ReadReq miss cycles 765system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 9489092 # number of UpgradeReq miss cycles 766system.cpu.l2cache.UpgradeReq_miss_latency::total 9489092 # number of UpgradeReq miss cycles 767system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 14857910968 # number of ReadExReq miss cycles 768system.cpu.l2cache.ReadExReq_miss_latency::total 14857910968 # number of ReadExReq miss cycles 769system.cpu.l2cache.demand_miss_latency::cpu.inst 260064000 # number of demand (read+write) miss cycles 770system.cpu.l2cache.demand_miss_latency::cpu.data 27759162680 # number of demand (read+write) miss cycles 771system.cpu.l2cache.demand_miss_latency::total 28019226680 # number of demand (read+write) miss cycles 772system.cpu.l2cache.overall_miss_latency::cpu.inst 260064000 # number of overall miss cycles 773system.cpu.l2cache.overall_miss_latency::cpu.data 27759162680 # number of overall miss cycles 774system.cpu.l2cache.overall_miss_latency::total 28019226680 # number of overall miss cycles 775system.cpu.l2cache.ReadReq_accesses::cpu.inst 8625 # number of ReadReq accesses(hits+misses) 776system.cpu.l2cache.ReadReq_accesses::cpu.data 1766818 # number of ReadReq accesses(hits+misses) 777system.cpu.l2cache.ReadReq_accesses::total 1775443 # number of ReadReq accesses(hits+misses) 778system.cpu.l2cache.Writeback_accesses::writebacks 2332907 # number of Writeback accesses(hits+misses) 779system.cpu.l2cache.Writeback_accesses::total 2332907 # number of Writeback accesses(hits+misses) 780system.cpu.l2cache.UpgradeReq_accesses::cpu.data 189308 # number of UpgradeReq accesses(hits+misses) 781system.cpu.l2cache.UpgradeReq_accesses::total 189308 # number of UpgradeReq accesses(hits+misses) 782system.cpu.l2cache.ReadExReq_accesses::cpu.data 771503 # number of ReadExReq accesses(hits+misses) 783system.cpu.l2cache.ReadExReq_accesses::total 771503 # number of ReadExReq accesses(hits+misses) 784system.cpu.l2cache.demand_accesses::cpu.inst 8625 # number of demand (read+write) accesses 785system.cpu.l2cache.demand_accesses::cpu.data 2538321 # number of demand (read+write) accesses 786system.cpu.l2cache.demand_accesses::total 2546946 # number of demand (read+write) accesses 787system.cpu.l2cache.overall_accesses::cpu.inst 8625 # number of overall (read+write) accesses 788system.cpu.l2cache.overall_accesses::cpu.data 2538321 # number of overall (read+write) accesses 789system.cpu.l2cache.overall_accesses::total 2546946 # number of overall (read+write) accesses 790system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.408928 # miss rate for ReadReq accesses 791system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.099840 # miss rate for ReadReq accesses 792system.cpu.l2cache.ReadReq_miss_rate::total 0.101341 # miss rate for ReadReq accesses 793system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.989969 # miss rate for UpgradeReq accesses 794system.cpu.l2cache.UpgradeReq_miss_rate::total 0.989969 # miss rate for UpgradeReq accesses 795system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.268346 # miss rate for ReadExReq accesses 796system.cpu.l2cache.ReadExReq_miss_rate::total 0.268346 # miss rate for ReadExReq accesses 797system.cpu.l2cache.demand_miss_rate::cpu.inst 0.408928 # miss rate for demand accesses 798system.cpu.l2cache.demand_miss_rate::cpu.data 0.151056 # miss rate for demand accesses 799system.cpu.l2cache.demand_miss_rate::total 0.151929 # miss rate for demand accesses 800system.cpu.l2cache.overall_miss_rate::cpu.inst 0.408928 # miss rate for overall accesses 801system.cpu.l2cache.overall_miss_rate::cpu.data 0.151056 # miss rate for overall accesses 802system.cpu.l2cache.overall_miss_rate::total 0.151929 # miss rate for overall accesses 803system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73735.185710 # average ReadReq miss latency 804system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 73136.762181 # average ReadReq miss latency 805system.cpu.l2cache.ReadReq_avg_miss_latency::total 73148.492780 # average ReadReq miss latency 806system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 50.633065 # average UpgradeReq miss latency 807system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 50.633065 # average UpgradeReq miss latency 808system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71766.946665 # average ReadExReq miss latency 809system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71766.946665 # average ReadExReq miss latency 810system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73735.185710 # average overall miss latency 811system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72397.139184 # average overall miss latency 812system.cpu.l2cache.demand_avg_miss_latency::total 72409.335118 # average overall miss latency 813system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73735.185710 # average overall miss latency 814system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72397.139184 # average overall miss latency 815system.cpu.l2cache.overall_avg_miss_latency::total 72409.335118 # average overall miss latency 816system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 817system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 818system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 819system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 820system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 821system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 822system.cpu.l2cache.fast_writes 0 # number of fast writes performed 823system.cpu.l2cache.cache_copies 0 # number of cache copies performed 824system.cpu.l2cache.writebacks::writebacks 294050 # number of writebacks 825system.cpu.l2cache.writebacks::total 294050 # number of writebacks 826system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits 827system.cpu.l2cache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits 828system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits 829system.cpu.l2cache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits 830system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits 831system.cpu.l2cache.overall_mshr_hits::total 1 # number of overall MSHR hits 832system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3526 # number of ReadReq MSHR misses 833system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 176399 # number of ReadReq MSHR misses 834system.cpu.l2cache.ReadReq_mshr_misses::total 179925 # number of ReadReq MSHR misses 835system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 187409 # number of UpgradeReq MSHR misses 836system.cpu.l2cache.UpgradeReq_mshr_misses::total 187409 # number of UpgradeReq MSHR misses 837system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 207030 # number of ReadExReq MSHR misses 838system.cpu.l2cache.ReadExReq_mshr_misses::total 207030 # number of ReadExReq MSHR misses 839system.cpu.l2cache.demand_mshr_misses::cpu.inst 3526 # number of demand (read+write) MSHR misses 840system.cpu.l2cache.demand_mshr_misses::cpu.data 383429 # number of demand (read+write) MSHR misses 841system.cpu.l2cache.demand_mshr_misses::total 386955 # number of demand (read+write) MSHR misses 842system.cpu.l2cache.overall_mshr_misses::cpu.inst 3526 # number of overall MSHR misses 843system.cpu.l2cache.overall_mshr_misses::cpu.data 383429 # number of overall MSHR misses 844system.cpu.l2cache.overall_mshr_misses::total 386955 # number of overall MSHR misses 845system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 215844500 # number of ReadReq MSHR miss cycles 846system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 10653560712 # number of ReadReq MSHR miss cycles 847system.cpu.l2cache.ReadReq_mshr_miss_latency::total 10869405212 # number of ReadReq MSHR miss cycles 848system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1890449014 # number of UpgradeReq MSHR miss cycles 849system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1890449014 # number of UpgradeReq MSHR miss cycles 850system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 12223591032 # number of ReadExReq MSHR miss cycles 851system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 12223591032 # number of ReadExReq MSHR miss cycles 852system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 215844500 # number of demand (read+write) MSHR miss cycles 853system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 22877151744 # number of demand (read+write) MSHR miss cycles 854system.cpu.l2cache.demand_mshr_miss_latency::total 23092996244 # number of demand (read+write) MSHR miss cycles 855system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 215844500 # number of overall MSHR miss cycles 856system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 22877151744 # number of overall MSHR miss cycles 857system.cpu.l2cache.overall_mshr_miss_latency::total 23092996244 # number of overall MSHR miss cycles 858system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.408812 # mshr miss rate for ReadReq accesses 859system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.099840 # mshr miss rate for ReadReq accesses 860system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.101341 # mshr miss rate for ReadReq accesses 861system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.989969 # mshr miss rate for UpgradeReq accesses 862system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.989969 # mshr miss rate for UpgradeReq accesses 863system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.268346 # mshr miss rate for ReadExReq accesses 864system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.268346 # mshr miss rate for ReadExReq accesses 865system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.408812 # mshr miss rate for demand accesses 866system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.151056 # mshr miss rate for demand accesses 867system.cpu.l2cache.demand_mshr_miss_rate::total 0.151929 # mshr miss rate for demand accesses 868system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.408812 # mshr miss rate for overall accesses 869system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.151056 # mshr miss rate for overall accesses 870system.cpu.l2cache.overall_mshr_miss_rate::total 0.151929 # mshr miss rate for overall accesses 871system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61215.116279 # average ReadReq mshr miss latency 872system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60394.677475 # average ReadReq mshr miss latency 873system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60410.755659 # average ReadReq mshr miss latency 874system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10087.290440 # average UpgradeReq mshr miss latency 875system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10087.290440 # average UpgradeReq mshr miss latency 876system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59042.607506 # average ReadExReq mshr miss latency 877system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59042.607506 # average ReadExReq mshr miss latency 878system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61215.116279 # average overall mshr miss latency 879system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59664.636071 # average overall mshr miss latency 880system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59678.764311 # average overall mshr miss latency 881system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61215.116279 # average overall mshr miss latency 882system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59664.636071 # average overall mshr miss latency 883system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59678.764311 # average overall mshr miss latency 884system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 885system.cpu.dcache.tags.replacements 2534225 # number of replacements 886system.cpu.dcache.tags.tagsinuse 4088.724937 # Cycle average of tags in use 887system.cpu.dcache.tags.total_refs 389006458 # Total number of references to valid blocks. 888system.cpu.dcache.tags.sampled_refs 2538321 # Sample count of references to valid blocks. 889system.cpu.dcache.tags.avg_refs 153.253453 # Average number of references to valid blocks. 890system.cpu.dcache.tags.warmup_cycle 1658510250 # Cycle when the warmup percentage was hit. 891system.cpu.dcache.tags.occ_blocks::cpu.data 4088.724937 # Average occupied blocks per requestor 892system.cpu.dcache.tags.occ_percent::cpu.data 0.998224 # Average percentage of cache occupancy 893system.cpu.dcache.tags.occ_percent::total 0.998224 # Average percentage of cache occupancy 894system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 895system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id 896system.cpu.dcache.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id 897system.cpu.dcache.tags.age_task_id_blocks_1024::2 803 # Occupied blocks per task id 898system.cpu.dcache.tags.age_task_id_blocks_1024::3 3247 # Occupied blocks per task id 899system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 900system.cpu.dcache.tags.tag_accesses 787132235 # Number of tag accesses 901system.cpu.dcache.tags.data_accesses 787132235 # Number of data accesses 902system.cpu.dcache.ReadReq_hits::cpu.data 240408250 # number of ReadReq hits 903system.cpu.dcache.ReadReq_hits::total 240408250 # number of ReadReq hits 904system.cpu.dcache.WriteReq_hits::cpu.data 148181290 # number of WriteReq hits 905system.cpu.dcache.WriteReq_hits::total 148181290 # number of WriteReq hits 906system.cpu.dcache.demand_hits::cpu.data 388589540 # number of demand (read+write) hits 907system.cpu.dcache.demand_hits::total 388589540 # number of demand (read+write) hits 908system.cpu.dcache.overall_hits::cpu.data 388589540 # number of overall hits 909system.cpu.dcache.overall_hits::total 388589540 # number of overall hits 910system.cpu.dcache.ReadReq_misses::cpu.data 2728505 # number of ReadReq misses 911system.cpu.dcache.ReadReq_misses::total 2728505 # number of ReadReq misses 912system.cpu.dcache.WriteReq_misses::cpu.data 978912 # number of WriteReq misses 913system.cpu.dcache.WriteReq_misses::total 978912 # number of WriteReq misses 914system.cpu.dcache.demand_misses::cpu.data 3707417 # number of demand (read+write) misses 915system.cpu.dcache.demand_misses::total 3707417 # number of demand (read+write) misses 916system.cpu.dcache.overall_misses::cpu.data 3707417 # number of overall misses 917system.cpu.dcache.overall_misses::total 3707417 # number of overall misses 918system.cpu.dcache.ReadReq_miss_latency::cpu.data 55514293617 # number of ReadReq miss cycles 919system.cpu.dcache.ReadReq_miss_latency::total 55514293617 # number of ReadReq miss cycles 920system.cpu.dcache.WriteReq_miss_latency::cpu.data 27913016377 # number of WriteReq miss cycles 921system.cpu.dcache.WriteReq_miss_latency::total 27913016377 # number of WriteReq miss cycles 922system.cpu.dcache.demand_miss_latency::cpu.data 83427309994 # number of demand (read+write) miss cycles 923system.cpu.dcache.demand_miss_latency::total 83427309994 # number of demand (read+write) miss cycles 924system.cpu.dcache.overall_miss_latency::cpu.data 83427309994 # number of overall miss cycles 925system.cpu.dcache.overall_miss_latency::total 83427309994 # number of overall miss cycles 926system.cpu.dcache.ReadReq_accesses::cpu.data 243136755 # number of ReadReq accesses(hits+misses) 927system.cpu.dcache.ReadReq_accesses::total 243136755 # number of ReadReq accesses(hits+misses) 928system.cpu.dcache.WriteReq_accesses::cpu.data 149160202 # number of WriteReq accesses(hits+misses) 929system.cpu.dcache.WriteReq_accesses::total 149160202 # number of WriteReq accesses(hits+misses) 930system.cpu.dcache.demand_accesses::cpu.data 392296957 # number of demand (read+write) accesses 931system.cpu.dcache.demand_accesses::total 392296957 # number of demand (read+write) accesses 932system.cpu.dcache.overall_accesses::cpu.data 392296957 # number of overall (read+write) accesses 933system.cpu.dcache.overall_accesses::total 392296957 # number of overall (read+write) accesses 934system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011222 # miss rate for ReadReq accesses 935system.cpu.dcache.ReadReq_miss_rate::total 0.011222 # miss rate for ReadReq accesses 936system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006563 # miss rate for WriteReq accesses 937system.cpu.dcache.WriteReq_miss_rate::total 0.006563 # miss rate for WriteReq accesses 938system.cpu.dcache.demand_miss_rate::cpu.data 0.009451 # miss rate for demand accesses 939system.cpu.dcache.demand_miss_rate::total 0.009451 # miss rate for demand accesses 940system.cpu.dcache.overall_miss_rate::cpu.data 0.009451 # miss rate for overall accesses 941system.cpu.dcache.overall_miss_rate::total 0.009451 # miss rate for overall accesses 942system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20346.047970 # average ReadReq miss latency 943system.cpu.dcache.ReadReq_avg_miss_latency::total 20346.047970 # average ReadReq miss latency 944system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28514.326494 # average WriteReq miss latency 945system.cpu.dcache.WriteReq_avg_miss_latency::total 28514.326494 # average WriteReq miss latency 946system.cpu.dcache.demand_avg_miss_latency::cpu.data 22502.812603 # average overall miss latency 947system.cpu.dcache.demand_avg_miss_latency::total 22502.812603 # average overall miss latency 948system.cpu.dcache.overall_avg_miss_latency::cpu.data 22502.812603 # average overall miss latency 949system.cpu.dcache.overall_avg_miss_latency::total 22502.812603 # average overall miss latency 950system.cpu.dcache.blocked_cycles::no_mshrs 9167 # number of cycles access was blocked 951system.cpu.dcache.blocked_cycles::no_targets 150 # number of cycles access was blocked 952system.cpu.dcache.blocked::no_mshrs 1009 # number of cycles access was blocked 953system.cpu.dcache.blocked::no_targets 4 # number of cycles access was blocked 954system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.085233 # average number of cycles each access was blocked 955system.cpu.dcache.avg_blocked_cycles::no_targets 37.500000 # average number of cycles each access was blocked 956system.cpu.dcache.fast_writes 0 # number of fast writes performed 957system.cpu.dcache.cache_copies 0 # number of cache copies performed 958system.cpu.dcache.writebacks::writebacks 2332907 # number of writebacks 959system.cpu.dcache.writebacks::total 2332907 # number of writebacks 960system.cpu.dcache.ReadReq_mshr_hits::cpu.data 961470 # number of ReadReq MSHR hits 961system.cpu.dcache.ReadReq_mshr_hits::total 961470 # number of ReadReq MSHR hits 962system.cpu.dcache.WriteReq_mshr_hits::cpu.data 18318 # number of WriteReq MSHR hits 963system.cpu.dcache.WriteReq_mshr_hits::total 18318 # number of WriteReq MSHR hits 964system.cpu.dcache.demand_mshr_hits::cpu.data 979788 # number of demand (read+write) MSHR hits 965system.cpu.dcache.demand_mshr_hits::total 979788 # number of demand (read+write) MSHR hits 966system.cpu.dcache.overall_mshr_hits::cpu.data 979788 # number of overall MSHR hits 967system.cpu.dcache.overall_mshr_hits::total 979788 # number of overall MSHR hits 968system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1767035 # number of ReadReq MSHR misses 969system.cpu.dcache.ReadReq_mshr_misses::total 1767035 # number of ReadReq MSHR misses 970system.cpu.dcache.WriteReq_mshr_misses::cpu.data 960594 # number of WriteReq MSHR misses 971system.cpu.dcache.WriteReq_mshr_misses::total 960594 # number of WriteReq MSHR misses 972system.cpu.dcache.demand_mshr_misses::cpu.data 2727629 # number of demand (read+write) MSHR misses 973system.cpu.dcache.demand_mshr_misses::total 2727629 # number of demand (read+write) MSHR misses 974system.cpu.dcache.overall_mshr_misses::cpu.data 2727629 # number of overall MSHR misses 975system.cpu.dcache.overall_mshr_misses::total 2727629 # number of overall MSHR misses 976system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 30608716000 # number of ReadReq MSHR miss cycles 977system.cpu.dcache.ReadReq_mshr_miss_latency::total 30608716000 # number of ReadReq MSHR miss cycles 978system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 25669918867 # number of WriteReq MSHR miss cycles 979system.cpu.dcache.WriteReq_mshr_miss_latency::total 25669918867 # number of WriteReq MSHR miss cycles 980system.cpu.dcache.demand_mshr_miss_latency::cpu.data 56278634867 # number of demand (read+write) MSHR miss cycles 981system.cpu.dcache.demand_mshr_miss_latency::total 56278634867 # number of demand (read+write) MSHR miss cycles 982system.cpu.dcache.overall_mshr_miss_latency::cpu.data 56278634867 # number of overall MSHR miss cycles 983system.cpu.dcache.overall_mshr_miss_latency::total 56278634867 # number of overall MSHR miss cycles 984system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007268 # mshr miss rate for ReadReq accesses 985system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007268 # mshr miss rate for ReadReq accesses 986system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006440 # mshr miss rate for WriteReq accesses 987system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006440 # mshr miss rate for WriteReq accesses 988system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006953 # mshr miss rate for demand accesses 989system.cpu.dcache.demand_mshr_miss_rate::total 0.006953 # mshr miss rate for demand accesses 990system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006953 # mshr miss rate for overall accesses 991system.cpu.dcache.overall_mshr_miss_rate::total 0.006953 # mshr miss rate for overall accesses 992system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17322.076812 # average ReadReq mshr miss latency 993system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17322.076812 # average ReadReq mshr miss latency 994system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 26722.963986 # average WriteReq mshr miss latency 995system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 26722.963986 # average WriteReq mshr miss latency 996system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20632.804119 # average overall mshr miss latency 997system.cpu.dcache.demand_avg_mshr_miss_latency::total 20632.804119 # average overall mshr miss latency 998system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20632.804119 # average overall mshr miss latency 999system.cpu.dcache.overall_avg_mshr_miss_latency::total 20632.804119 # average overall mshr miss latency 1000system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1001 1002---------- End Simulation Statistics ---------- 1003