config.ini revision 9213
1[root] 2type=Root 3children=system 4full_system=false 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 9[system] 10type=System 11children=cpu membus physmem 12boot_osflags=a 13clock=1 14init_param=0 15kernel= 16load_addr_mask=1099511627775 17mem_mode=atomic 18memories=system.physmem 19num_work_ids=16 20readfile= 21symbolfile= 22work_begin_ckpt_count=0 23work_begin_cpu_id_exit=-1 24work_begin_exit_count=0 25work_cpus_ckpt_count=0 26work_end_ckpt_count=0 27work_end_exit_count=0 28work_item_id=-1 29system_port=system.membus.slave[0] 30 31[system.cpu] 32type=DerivO3CPU 33children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload 34BTBEntries=4096 35BTBTagSize=16 36LFSTSize=1024 37LQEntries=32 38LSQCheckLoads=true 39LSQDepCheckShift=4 40RASSize=16 41SQEntries=32 42SSITSize=1024 43activity=0 44backComSize=5 45cachePorts=200 46checker=Null 47choiceCtrBits=2 48choicePredictorSize=8192 49clock=500 50commitToDecodeDelay=1 51commitToFetchDelay=1 52commitToIEWDelay=1 53commitToRenameDelay=1 54commitWidth=8 55cpu_id=0 56decodeToFetchDelay=1 57decodeToRenameDelay=1 58decodeWidth=8 59defer_registration=false 60dispatchWidth=8 61do_checkpoint_insts=true 62do_quiesce=true 63do_statistics_insts=true 64dtb=system.cpu.dtb 65fetchToDecodeDelay=1 66fetchTrapLatency=1 67fetchWidth=8 68forwardComSize=5 69fuPool=system.cpu.fuPool 70function_trace=false 71function_trace_start=0 72globalCtrBits=2 73globalHistoryBits=13 74globalPredictorSize=8192 75iewToCommitDelay=1 76iewToDecodeDelay=1 77iewToFetchDelay=1 78iewToRenameDelay=1 79instShiftAmt=2 80interrupts=system.cpu.interrupts 81issueToExecuteDelay=1 82issueWidth=8 83itb=system.cpu.itb 84localCtrBits=2 85localHistoryBits=11 86localHistoryTableSize=2048 87localPredictorSize=2048 88max_insts_all_threads=0 89max_insts_any_thread=0 90max_loads_all_threads=0 91max_loads_any_thread=0 92needsTSO=true 93numIQEntries=64 94numPhysFloatRegs=256 95numPhysIntRegs=256 96numROBEntries=192 97numRobs=1 98numThreads=1 99predType=tournament 100profile=0 101progress_interval=0 102renameToDecodeDelay=1 103renameToFetchDelay=1 104renameToIEWDelay=2 105renameToROBDelay=1 106renameWidth=8 107smtCommitPolicy=RoundRobin 108smtFetchPolicy=SingleThread 109smtIQPolicy=Partitioned 110smtIQThreshold=100 111smtLSQPolicy=Partitioned 112smtLSQThreshold=100 113smtNumFetchingThreads=1 114smtROBPolicy=Partitioned 115smtROBThreshold=100 116squashWidth=8 117store_set_clear_period=250000 118system=system 119tracer=system.cpu.tracer 120trapLatency=13 121wbDepth=1 122wbWidth=8 123workload=system.cpu.workload 124dcache_port=system.cpu.dcache.cpu_side 125icache_port=system.cpu.icache.cpu_side 126 127[system.cpu.dcache] 128type=BaseCache 129addr_ranges=0:18446744073709551615 130assoc=2 131block_size=64 132clock=1 133forward_snoops=true 134hash_delay=1 135is_top_level=true 136latency=1000 137max_miss_count=0 138mshrs=10 139prefetch_on_access=false 140prefetcher=Null 141prioritizeRequests=false 142repl=Null 143size=262144 144subblock_size=0 145system=system 146tgts_per_mshr=20 147trace_addr=0 148two_queue=false 149write_buffers=8 150cpu_side=system.cpu.dcache_port 151mem_side=system.cpu.toL2Bus.slave[1] 152 153[system.cpu.dtb] 154type=X86TLB 155children=walker 156size=64 157walker=system.cpu.dtb.walker 158 159[system.cpu.dtb.walker] 160type=X86PagetableWalker 161clock=1 162system=system 163port=system.cpu.toL2Bus.slave[3] 164 165[system.cpu.fuPool] 166type=FUPool 167children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 168FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 169 170[system.cpu.fuPool.FUList0] 171type=FUDesc 172children=opList 173count=6 174opList=system.cpu.fuPool.FUList0.opList 175 176[system.cpu.fuPool.FUList0.opList] 177type=OpDesc 178issueLat=1 179opClass=IntAlu 180opLat=1 181 182[system.cpu.fuPool.FUList1] 183type=FUDesc 184children=opList0 opList1 185count=2 186opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 187 188[system.cpu.fuPool.FUList1.opList0] 189type=OpDesc 190issueLat=1 191opClass=IntMult 192opLat=3 193 194[system.cpu.fuPool.FUList1.opList1] 195type=OpDesc 196issueLat=19 197opClass=IntDiv 198opLat=20 199 200[system.cpu.fuPool.FUList2] 201type=FUDesc 202children=opList0 opList1 opList2 203count=4 204opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 205 206[system.cpu.fuPool.FUList2.opList0] 207type=OpDesc 208issueLat=1 209opClass=FloatAdd 210opLat=2 211 212[system.cpu.fuPool.FUList2.opList1] 213type=OpDesc 214issueLat=1 215opClass=FloatCmp 216opLat=2 217 218[system.cpu.fuPool.FUList2.opList2] 219type=OpDesc 220issueLat=1 221opClass=FloatCvt 222opLat=2 223 224[system.cpu.fuPool.FUList3] 225type=FUDesc 226children=opList0 opList1 opList2 227count=2 228opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 229 230[system.cpu.fuPool.FUList3.opList0] 231type=OpDesc 232issueLat=1 233opClass=FloatMult 234opLat=4 235 236[system.cpu.fuPool.FUList3.opList1] 237type=OpDesc 238issueLat=12 239opClass=FloatDiv 240opLat=12 241 242[system.cpu.fuPool.FUList3.opList2] 243type=OpDesc 244issueLat=24 245opClass=FloatSqrt 246opLat=24 247 248[system.cpu.fuPool.FUList4] 249type=FUDesc 250children=opList 251count=0 252opList=system.cpu.fuPool.FUList4.opList 253 254[system.cpu.fuPool.FUList4.opList] 255type=OpDesc 256issueLat=1 257opClass=MemRead 258opLat=1 259 260[system.cpu.fuPool.FUList5] 261type=FUDesc 262children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 263count=4 264opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 265 266[system.cpu.fuPool.FUList5.opList00] 267type=OpDesc 268issueLat=1 269opClass=SimdAdd 270opLat=1 271 272[system.cpu.fuPool.FUList5.opList01] 273type=OpDesc 274issueLat=1 275opClass=SimdAddAcc 276opLat=1 277 278[system.cpu.fuPool.FUList5.opList02] 279type=OpDesc 280issueLat=1 281opClass=SimdAlu 282opLat=1 283 284[system.cpu.fuPool.FUList5.opList03] 285type=OpDesc 286issueLat=1 287opClass=SimdCmp 288opLat=1 289 290[system.cpu.fuPool.FUList5.opList04] 291type=OpDesc 292issueLat=1 293opClass=SimdCvt 294opLat=1 295 296[system.cpu.fuPool.FUList5.opList05] 297type=OpDesc 298issueLat=1 299opClass=SimdMisc 300opLat=1 301 302[system.cpu.fuPool.FUList5.opList06] 303type=OpDesc 304issueLat=1 305opClass=SimdMult 306opLat=1 307 308[system.cpu.fuPool.FUList5.opList07] 309type=OpDesc 310issueLat=1 311opClass=SimdMultAcc 312opLat=1 313 314[system.cpu.fuPool.FUList5.opList08] 315type=OpDesc 316issueLat=1 317opClass=SimdShift 318opLat=1 319 320[system.cpu.fuPool.FUList5.opList09] 321type=OpDesc 322issueLat=1 323opClass=SimdShiftAcc 324opLat=1 325 326[system.cpu.fuPool.FUList5.opList10] 327type=OpDesc 328issueLat=1 329opClass=SimdSqrt 330opLat=1 331 332[system.cpu.fuPool.FUList5.opList11] 333type=OpDesc 334issueLat=1 335opClass=SimdFloatAdd 336opLat=1 337 338[system.cpu.fuPool.FUList5.opList12] 339type=OpDesc 340issueLat=1 341opClass=SimdFloatAlu 342opLat=1 343 344[system.cpu.fuPool.FUList5.opList13] 345type=OpDesc 346issueLat=1 347opClass=SimdFloatCmp 348opLat=1 349 350[system.cpu.fuPool.FUList5.opList14] 351type=OpDesc 352issueLat=1 353opClass=SimdFloatCvt 354opLat=1 355 356[system.cpu.fuPool.FUList5.opList15] 357type=OpDesc 358issueLat=1 359opClass=SimdFloatDiv 360opLat=1 361 362[system.cpu.fuPool.FUList5.opList16] 363type=OpDesc 364issueLat=1 365opClass=SimdFloatMisc 366opLat=1 367 368[system.cpu.fuPool.FUList5.opList17] 369type=OpDesc 370issueLat=1 371opClass=SimdFloatMult 372opLat=1 373 374[system.cpu.fuPool.FUList5.opList18] 375type=OpDesc 376issueLat=1 377opClass=SimdFloatMultAcc 378opLat=1 379 380[system.cpu.fuPool.FUList5.opList19] 381type=OpDesc 382issueLat=1 383opClass=SimdFloatSqrt 384opLat=1 385 386[system.cpu.fuPool.FUList6] 387type=FUDesc 388children=opList 389count=0 390opList=system.cpu.fuPool.FUList6.opList 391 392[system.cpu.fuPool.FUList6.opList] 393type=OpDesc 394issueLat=1 395opClass=MemWrite 396opLat=1 397 398[system.cpu.fuPool.FUList7] 399type=FUDesc 400children=opList0 opList1 401count=4 402opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 403 404[system.cpu.fuPool.FUList7.opList0] 405type=OpDesc 406issueLat=1 407opClass=MemRead 408opLat=1 409 410[system.cpu.fuPool.FUList7.opList1] 411type=OpDesc 412issueLat=1 413opClass=MemWrite 414opLat=1 415 416[system.cpu.fuPool.FUList8] 417type=FUDesc 418children=opList 419count=1 420opList=system.cpu.fuPool.FUList8.opList 421 422[system.cpu.fuPool.FUList8.opList] 423type=OpDesc 424issueLat=3 425opClass=IprAccess 426opLat=3 427 428[system.cpu.icache] 429type=BaseCache 430addr_ranges=0:18446744073709551615 431assoc=2 432block_size=64 433clock=1 434forward_snoops=true 435hash_delay=1 436is_top_level=true 437latency=1000 438max_miss_count=0 439mshrs=10 440prefetch_on_access=false 441prefetcher=Null 442prioritizeRequests=false 443repl=Null 444size=131072 445subblock_size=0 446system=system 447tgts_per_mshr=20 448trace_addr=0 449two_queue=false 450write_buffers=8 451cpu_side=system.cpu.icache_port 452mem_side=system.cpu.toL2Bus.slave[0] 453 454[system.cpu.interrupts] 455type=X86LocalApic 456clock=1 457int_latency=1000 458pio_addr=2305843009213693952 459pio_latency=100000 460system=system 461int_master=system.membus.slave[2] 462int_slave=system.membus.master[2] 463pio=system.membus.master[1] 464 465[system.cpu.itb] 466type=X86TLB 467children=walker 468size=64 469walker=system.cpu.itb.walker 470 471[system.cpu.itb.walker] 472type=X86PagetableWalker 473clock=1 474system=system 475port=system.cpu.toL2Bus.slave[2] 476 477[system.cpu.l2cache] 478type=BaseCache 479addr_ranges=0:18446744073709551615 480assoc=2 481block_size=64 482clock=1 483forward_snoops=true 484hash_delay=1 485is_top_level=false 486latency=1000 487max_miss_count=0 488mshrs=10 489prefetch_on_access=false 490prefetcher=Null 491prioritizeRequests=false 492repl=Null 493size=2097152 494subblock_size=0 495system=system 496tgts_per_mshr=5 497trace_addr=0 498two_queue=false 499write_buffers=8 500cpu_side=system.cpu.toL2Bus.master[0] 501mem_side=system.membus.slave[1] 502 503[system.cpu.toL2Bus] 504type=CoherentBus 505block_size=64 506clock=1000 507header_cycles=1 508use_default_range=false 509width=8 510master=system.cpu.l2cache.cpu_side 511slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port 512 513[system.cpu.tracer] 514type=ExeTracer 515 516[system.cpu.workload] 517type=LiveProcess 518cmd=parser 2.1.dict -batch 519cwd=build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing 520egid=100 521env= 522errout=cerr 523euid=100 524executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/parser 525gid=100 526input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in 527max_stack_size=67108864 528output=cout 529pid=100 530ppid=99 531simpoint=114600000000 532system=system 533uid=100 534 535[system.membus] 536type=CoherentBus 537block_size=64 538clock=1000 539header_cycles=1 540use_default_range=false 541width=8 542master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave 543slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master 544 545[system.physmem] 546type=SimpleMemory 547clock=1 548conf_table_reported=false 549file= 550in_addr_map=true 551latency=30000 552latency_var=0 553null=false 554range=0:134217727 555zero=false 556port=system.membus.master[0] 557 558