config.ini revision 9079
1[root] 2type=Root 3children=system 4full_system=false 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 9[system] 10type=System 11children=cpu membus physmem 12boot_osflags=a 13init_param=0 14kernel= 15load_addr_mask=1099511627775 16mem_mode=atomic 17memories=system.physmem 18num_work_ids=16 19readfile= 20symbolfile= 21work_begin_ckpt_count=0 22work_begin_cpu_id_exit=-1 23work_begin_exit_count=0 24work_cpus_ckpt_count=0 25work_end_ckpt_count=0 26work_end_exit_count=0 27work_item_id=-1 28system_port=system.membus.slave[0] 29 30[system.cpu] 31type=DerivO3CPU 32children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload 33BTBEntries=4096 34BTBTagSize=16 35LFSTSize=1024 36LQEntries=32 37LSQCheckLoads=true 38LSQDepCheckShift=4 39RASSize=16 40SQEntries=32 41SSITSize=1024 42activity=0 43backComSize=5 44cachePorts=200 45checker=Null 46choiceCtrBits=2 47choicePredictorSize=8192 48clock=500 49commitToDecodeDelay=1 50commitToFetchDelay=1 51commitToIEWDelay=1 52commitToRenameDelay=1 53commitWidth=8 54cpu_id=0 55decodeToFetchDelay=1 56decodeToRenameDelay=1 57decodeWidth=8 58defer_registration=false 59dispatchWidth=8 60do_checkpoint_insts=true 61do_quiesce=true 62do_statistics_insts=true 63dtb=system.cpu.dtb 64fetchToDecodeDelay=1 65fetchTrapLatency=1 66fetchWidth=8 67forwardComSize=5 68fuPool=system.cpu.fuPool 69function_trace=false 70function_trace_start=0 71globalCtrBits=2 72globalHistoryBits=13 73globalPredictorSize=8192 74iewToCommitDelay=1 75iewToDecodeDelay=1 76iewToFetchDelay=1 77iewToRenameDelay=1 78instShiftAmt=2 79interrupts=system.cpu.interrupts 80issueToExecuteDelay=1 81issueWidth=8 82itb=system.cpu.itb 83localCtrBits=2 84localHistoryBits=11 85localHistoryTableSize=2048 86localPredictorSize=2048 87max_insts_all_threads=0 88max_insts_any_thread=0 89max_loads_all_threads=0 90max_loads_any_thread=0 91needsTSO=true 92numIQEntries=64 93numPhysFloatRegs=256 94numPhysIntRegs=256 95numROBEntries=192 96numRobs=1 97numThreads=1 98phase=0 99predType=tournament 100profile=0 101progress_interval=0 102renameToDecodeDelay=1 103renameToFetchDelay=1 104renameToIEWDelay=2 105renameToROBDelay=1 106renameWidth=8 107smtCommitPolicy=RoundRobin 108smtFetchPolicy=SingleThread 109smtIQPolicy=Partitioned 110smtIQThreshold=100 111smtLSQPolicy=Partitioned 112smtLSQThreshold=100 113smtNumFetchingThreads=1 114smtROBPolicy=Partitioned 115smtROBThreshold=100 116squashWidth=8 117store_set_clear_period=250000 118system=system 119tracer=system.cpu.tracer 120trapLatency=13 121wbDepth=1 122wbWidth=8 123workload=system.cpu.workload 124dcache_port=system.cpu.dcache.cpu_side 125icache_port=system.cpu.icache.cpu_side 126 127[system.cpu.dcache] 128type=BaseCache 129addr_ranges=0:18446744073709551615 130assoc=2 131block_size=64 132forward_snoops=true 133hash_delay=1 134is_top_level=true 135latency=1000 136max_miss_count=0 137mshrs=10 138prefetch_on_access=false 139prefetcher=Null 140prioritizeRequests=false 141repl=Null 142size=262144 143subblock_size=0 144system=system 145tgts_per_mshr=20 146trace_addr=0 147two_queue=false 148write_buffers=8 149cpu_side=system.cpu.dcache_port 150mem_side=system.cpu.toL2Bus.slave[1] 151 152[system.cpu.dtb] 153type=X86TLB 154children=walker 155size=64 156walker=system.cpu.dtb.walker 157 158[system.cpu.dtb.walker] 159type=X86PagetableWalker 160system=system 161port=system.cpu.toL2Bus.slave[3] 162 163[system.cpu.fuPool] 164type=FUPool 165children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 166FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 167 168[system.cpu.fuPool.FUList0] 169type=FUDesc 170children=opList 171count=6 172opList=system.cpu.fuPool.FUList0.opList 173 174[system.cpu.fuPool.FUList0.opList] 175type=OpDesc 176issueLat=1 177opClass=IntAlu 178opLat=1 179 180[system.cpu.fuPool.FUList1] 181type=FUDesc 182children=opList0 opList1 183count=2 184opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 185 186[system.cpu.fuPool.FUList1.opList0] 187type=OpDesc 188issueLat=1 189opClass=IntMult 190opLat=3 191 192[system.cpu.fuPool.FUList1.opList1] 193type=OpDesc 194issueLat=19 195opClass=IntDiv 196opLat=20 197 198[system.cpu.fuPool.FUList2] 199type=FUDesc 200children=opList0 opList1 opList2 201count=4 202opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 203 204[system.cpu.fuPool.FUList2.opList0] 205type=OpDesc 206issueLat=1 207opClass=FloatAdd 208opLat=2 209 210[system.cpu.fuPool.FUList2.opList1] 211type=OpDesc 212issueLat=1 213opClass=FloatCmp 214opLat=2 215 216[system.cpu.fuPool.FUList2.opList2] 217type=OpDesc 218issueLat=1 219opClass=FloatCvt 220opLat=2 221 222[system.cpu.fuPool.FUList3] 223type=FUDesc 224children=opList0 opList1 opList2 225count=2 226opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 227 228[system.cpu.fuPool.FUList3.opList0] 229type=OpDesc 230issueLat=1 231opClass=FloatMult 232opLat=4 233 234[system.cpu.fuPool.FUList3.opList1] 235type=OpDesc 236issueLat=12 237opClass=FloatDiv 238opLat=12 239 240[system.cpu.fuPool.FUList3.opList2] 241type=OpDesc 242issueLat=24 243opClass=FloatSqrt 244opLat=24 245 246[system.cpu.fuPool.FUList4] 247type=FUDesc 248children=opList 249count=0 250opList=system.cpu.fuPool.FUList4.opList 251 252[system.cpu.fuPool.FUList4.opList] 253type=OpDesc 254issueLat=1 255opClass=MemRead 256opLat=1 257 258[system.cpu.fuPool.FUList5] 259type=FUDesc 260children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 261count=4 262opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 263 264[system.cpu.fuPool.FUList5.opList00] 265type=OpDesc 266issueLat=1 267opClass=SimdAdd 268opLat=1 269 270[system.cpu.fuPool.FUList5.opList01] 271type=OpDesc 272issueLat=1 273opClass=SimdAddAcc 274opLat=1 275 276[system.cpu.fuPool.FUList5.opList02] 277type=OpDesc 278issueLat=1 279opClass=SimdAlu 280opLat=1 281 282[system.cpu.fuPool.FUList5.opList03] 283type=OpDesc 284issueLat=1 285opClass=SimdCmp 286opLat=1 287 288[system.cpu.fuPool.FUList5.opList04] 289type=OpDesc 290issueLat=1 291opClass=SimdCvt 292opLat=1 293 294[system.cpu.fuPool.FUList5.opList05] 295type=OpDesc 296issueLat=1 297opClass=SimdMisc 298opLat=1 299 300[system.cpu.fuPool.FUList5.opList06] 301type=OpDesc 302issueLat=1 303opClass=SimdMult 304opLat=1 305 306[system.cpu.fuPool.FUList5.opList07] 307type=OpDesc 308issueLat=1 309opClass=SimdMultAcc 310opLat=1 311 312[system.cpu.fuPool.FUList5.opList08] 313type=OpDesc 314issueLat=1 315opClass=SimdShift 316opLat=1 317 318[system.cpu.fuPool.FUList5.opList09] 319type=OpDesc 320issueLat=1 321opClass=SimdShiftAcc 322opLat=1 323 324[system.cpu.fuPool.FUList5.opList10] 325type=OpDesc 326issueLat=1 327opClass=SimdSqrt 328opLat=1 329 330[system.cpu.fuPool.FUList5.opList11] 331type=OpDesc 332issueLat=1 333opClass=SimdFloatAdd 334opLat=1 335 336[system.cpu.fuPool.FUList5.opList12] 337type=OpDesc 338issueLat=1 339opClass=SimdFloatAlu 340opLat=1 341 342[system.cpu.fuPool.FUList5.opList13] 343type=OpDesc 344issueLat=1 345opClass=SimdFloatCmp 346opLat=1 347 348[system.cpu.fuPool.FUList5.opList14] 349type=OpDesc 350issueLat=1 351opClass=SimdFloatCvt 352opLat=1 353 354[system.cpu.fuPool.FUList5.opList15] 355type=OpDesc 356issueLat=1 357opClass=SimdFloatDiv 358opLat=1 359 360[system.cpu.fuPool.FUList5.opList16] 361type=OpDesc 362issueLat=1 363opClass=SimdFloatMisc 364opLat=1 365 366[system.cpu.fuPool.FUList5.opList17] 367type=OpDesc 368issueLat=1 369opClass=SimdFloatMult 370opLat=1 371 372[system.cpu.fuPool.FUList5.opList18] 373type=OpDesc 374issueLat=1 375opClass=SimdFloatMultAcc 376opLat=1 377 378[system.cpu.fuPool.FUList5.opList19] 379type=OpDesc 380issueLat=1 381opClass=SimdFloatSqrt 382opLat=1 383 384[system.cpu.fuPool.FUList6] 385type=FUDesc 386children=opList 387count=0 388opList=system.cpu.fuPool.FUList6.opList 389 390[system.cpu.fuPool.FUList6.opList] 391type=OpDesc 392issueLat=1 393opClass=MemWrite 394opLat=1 395 396[system.cpu.fuPool.FUList7] 397type=FUDesc 398children=opList0 opList1 399count=4 400opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 401 402[system.cpu.fuPool.FUList7.opList0] 403type=OpDesc 404issueLat=1 405opClass=MemRead 406opLat=1 407 408[system.cpu.fuPool.FUList7.opList1] 409type=OpDesc 410issueLat=1 411opClass=MemWrite 412opLat=1 413 414[system.cpu.fuPool.FUList8] 415type=FUDesc 416children=opList 417count=1 418opList=system.cpu.fuPool.FUList8.opList 419 420[system.cpu.fuPool.FUList8.opList] 421type=OpDesc 422issueLat=3 423opClass=IprAccess 424opLat=3 425 426[system.cpu.icache] 427type=BaseCache 428addr_ranges=0:18446744073709551615 429assoc=2 430block_size=64 431forward_snoops=true 432hash_delay=1 433is_top_level=true 434latency=1000 435max_miss_count=0 436mshrs=10 437prefetch_on_access=false 438prefetcher=Null 439prioritizeRequests=false 440repl=Null 441size=131072 442subblock_size=0 443system=system 444tgts_per_mshr=20 445trace_addr=0 446two_queue=false 447write_buffers=8 448cpu_side=system.cpu.icache_port 449mem_side=system.cpu.toL2Bus.slave[0] 450 451[system.cpu.interrupts] 452type=X86LocalApic 453int_latency=1000 454pio_addr=2305843009213693952 455pio_latency=1000 456system=system 457int_master=system.membus.slave[2] 458int_slave=system.membus.master[2] 459pio=system.membus.master[1] 460 461[system.cpu.itb] 462type=X86TLB 463children=walker 464size=64 465walker=system.cpu.itb.walker 466 467[system.cpu.itb.walker] 468type=X86PagetableWalker 469system=system 470port=system.cpu.toL2Bus.slave[2] 471 472[system.cpu.l2cache] 473type=BaseCache 474addr_ranges=0:18446744073709551615 475assoc=2 476block_size=64 477forward_snoops=true 478hash_delay=1 479is_top_level=false 480latency=1000 481max_miss_count=0 482mshrs=10 483prefetch_on_access=false 484prefetcher=Null 485prioritizeRequests=false 486repl=Null 487size=2097152 488subblock_size=0 489system=system 490tgts_per_mshr=5 491trace_addr=0 492two_queue=false 493write_buffers=8 494cpu_side=system.cpu.toL2Bus.master[0] 495mem_side=system.membus.slave[1] 496 497[system.cpu.toL2Bus] 498type=CoherentBus 499block_size=64 500clock=1000 501header_cycles=1 502use_default_range=false 503width=64 504master=system.cpu.l2cache.cpu_side 505slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port 506 507[system.cpu.tracer] 508type=ExeTracer 509 510[system.cpu.workload] 511type=LiveProcess 512cmd=parser 2.1.dict -batch 513cwd=build/X86/tests/fast/long/se/20.parser/x86/linux/o3-timing 514egid=100 515env= 516errout=cerr 517euid=100 518executable=/dist/m5/cpu2000/binaries/x86/linux/parser 519gid=100 520input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in 521max_stack_size=67108864 522output=cout 523pid=100 524ppid=99 525simpoint=114600000000 526system=system 527uid=100 528 529[system.membus] 530type=CoherentBus 531block_size=64 532clock=1000 533header_cycles=1 534use_default_range=false 535width=64 536master=system.physmem.port[0] system.cpu.interrupts.pio system.cpu.interrupts.int_slave 537slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master 538 539[system.physmem] 540type=SimpleMemory 541conf_table_reported=false 542file= 543in_addr_map=true 544latency=30000 545latency_var=0 546null=false 547range=0:134217727 548zero=false 549port=system.membus.master[0] 550 551