config.ini revision 11570
1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=System 13children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain 17default_p_state=UNDEFINED 18eventq_index=0 19exit_on_work_items=false 20init_param=0 21kernel= 22kernel_addr_check=true 23load_addr_mask=1099511627775 24load_offset=0 25mem_mode=timing 26mem_ranges= 27memories=system.physmem 28mmap_using_noreserve=false 29multi_thread=false 30num_work_ids=16 31p_state_clk_gate_bins=20 32p_state_clk_gate_max=1000000000000 33p_state_clk_gate_min=1000 34power_model=Null 35readfile= 36symbolfile= 37thermal_components= 38thermal_model=Null 39work_begin_ckpt_count=0 40work_begin_cpu_id_exit=-1 41work_begin_exit_count=0 42work_cpus_ckpt_count=0 43work_end_ckpt_count=0 44work_end_exit_count=0 45work_item_id=-1 46system_port=system.membus.slave[0] 47 48[system.clk_domain] 49type=SrcClockDomain 50clock=1000 51domain_id=-1 52eventq_index=0 53init_perf_level=0 54voltage_domain=system.voltage_domain 55 56[system.cpu] 57type=DerivO3CPU 58children=apic_clk_domain branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload 59LFSTSize=1024 60LQEntries=32 61LSQCheckLoads=true 62LSQDepCheckShift=4 63SQEntries=32 64SSITSize=1024 65activity=0 66backComSize=5 67branchPred=system.cpu.branchPred 68cachePorts=200 69checker=Null 70clk_domain=system.cpu_clk_domain 71commitToDecodeDelay=1 72commitToFetchDelay=1 73commitToIEWDelay=1 74commitToRenameDelay=1 75commitWidth=8 76cpu_id=0 77decodeToFetchDelay=1 78decodeToRenameDelay=1 79decodeWidth=8 80default_p_state=UNDEFINED 81dispatchWidth=8 82do_checkpoint_insts=true 83do_quiesce=true 84do_statistics_insts=true 85dtb=system.cpu.dtb 86eventq_index=0 87fetchBufferSize=64 88fetchQueueSize=32 89fetchToDecodeDelay=1 90fetchTrapLatency=1 91fetchWidth=8 92forwardComSize=5 93fuPool=system.cpu.fuPool 94function_trace=false 95function_trace_start=0 96iewToCommitDelay=1 97iewToDecodeDelay=1 98iewToFetchDelay=1 99iewToRenameDelay=1 100interrupts=system.cpu.interrupts 101isa=system.cpu.isa 102issueToExecuteDelay=1 103issueWidth=8 104itb=system.cpu.itb 105max_insts_all_threads=0 106max_insts_any_thread=0 107max_loads_all_threads=0 108max_loads_any_thread=0 109needsTSO=true 110numIQEntries=64 111numPhysCCRegs=1280 112numPhysFloatRegs=256 113numPhysIntRegs=256 114numROBEntries=192 115numRobs=1 116numThreads=1 117p_state_clk_gate_bins=20 118p_state_clk_gate_max=1000000000000 119p_state_clk_gate_min=1000 120power_model=Null 121profile=0 122progress_interval=0 123renameToDecodeDelay=1 124renameToFetchDelay=1 125renameToIEWDelay=2 126renameToROBDelay=1 127renameWidth=8 128simpoint_start_insts= 129smtCommitPolicy=RoundRobin 130smtFetchPolicy=SingleThread 131smtIQPolicy=Partitioned 132smtIQThreshold=100 133smtLSQPolicy=Partitioned 134smtLSQThreshold=100 135smtNumFetchingThreads=1 136smtROBPolicy=Partitioned 137smtROBThreshold=100 138socket_id=0 139squashWidth=8 140store_set_clear_period=250000 141switched_out=false 142system=system 143tracer=system.cpu.tracer 144trapLatency=13 145wbWidth=8 146workload=system.cpu.workload 147dcache_port=system.cpu.dcache.cpu_side 148icache_port=system.cpu.icache.cpu_side 149 150[system.cpu.apic_clk_domain] 151type=DerivedClockDomain 152clk_divider=16 153clk_domain=system.cpu_clk_domain 154eventq_index=0 155 156[system.cpu.branchPred] 157type=TournamentBP 158BTBEntries=4096 159BTBTagSize=16 160RASSize=16 161choiceCtrBits=2 162choicePredictorSize=8192 163eventq_index=0 164globalCtrBits=2 165globalPredictorSize=8192 166indirectHashGHR=true 167indirectHashTargets=true 168indirectPathLength=3 169indirectSets=256 170indirectTagSize=16 171indirectWays=2 172instShiftAmt=2 173localCtrBits=2 174localHistoryTableSize=2048 175localPredictorSize=2048 176numThreads=1 177useIndirect=true 178 179[system.cpu.dcache] 180type=Cache 181children=tags 182addr_ranges=0:18446744073709551615 183assoc=2 184clk_domain=system.cpu_clk_domain 185clusivity=mostly_incl 186default_p_state=UNDEFINED 187demand_mshr_reserve=1 188eventq_index=0 189hit_latency=2 190is_read_only=false 191max_miss_count=0 192mshrs=4 193p_state_clk_gate_bins=20 194p_state_clk_gate_max=1000000000000 195p_state_clk_gate_min=1000 196power_model=Null 197prefetch_on_access=false 198prefetcher=Null 199response_latency=2 200sequential_access=false 201size=262144 202system=system 203tags=system.cpu.dcache.tags 204tgts_per_mshr=20 205write_buffers=8 206writeback_clean=false 207cpu_side=system.cpu.dcache_port 208mem_side=system.cpu.toL2Bus.slave[1] 209 210[system.cpu.dcache.tags] 211type=LRU 212assoc=2 213block_size=64 214clk_domain=system.cpu_clk_domain 215default_p_state=UNDEFINED 216eventq_index=0 217hit_latency=2 218p_state_clk_gate_bins=20 219p_state_clk_gate_max=1000000000000 220p_state_clk_gate_min=1000 221power_model=Null 222sequential_access=false 223size=262144 224 225[system.cpu.dtb] 226type=X86TLB 227children=walker 228eventq_index=0 229size=64 230walker=system.cpu.dtb.walker 231 232[system.cpu.dtb.walker] 233type=X86PagetableWalker 234clk_domain=system.cpu_clk_domain 235default_p_state=UNDEFINED 236eventq_index=0 237num_squash_per_cycle=4 238p_state_clk_gate_bins=20 239p_state_clk_gate_max=1000000000000 240p_state_clk_gate_min=1000 241power_model=Null 242system=system 243port=system.cpu.toL2Bus.slave[3] 244 245[system.cpu.fuPool] 246type=FUPool 247children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 248FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 249eventq_index=0 250 251[system.cpu.fuPool.FUList0] 252type=FUDesc 253children=opList 254count=6 255eventq_index=0 256opList=system.cpu.fuPool.FUList0.opList 257 258[system.cpu.fuPool.FUList0.opList] 259type=OpDesc 260eventq_index=0 261opClass=IntAlu 262opLat=1 263pipelined=true 264 265[system.cpu.fuPool.FUList1] 266type=FUDesc 267children=opList0 opList1 268count=2 269eventq_index=0 270opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 271 272[system.cpu.fuPool.FUList1.opList0] 273type=OpDesc 274eventq_index=0 275opClass=IntMult 276opLat=3 277pipelined=true 278 279[system.cpu.fuPool.FUList1.opList1] 280type=OpDesc 281eventq_index=0 282opClass=IntDiv 283opLat=1 284pipelined=false 285 286[system.cpu.fuPool.FUList2] 287type=FUDesc 288children=opList0 opList1 opList2 289count=4 290eventq_index=0 291opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 292 293[system.cpu.fuPool.FUList2.opList0] 294type=OpDesc 295eventq_index=0 296opClass=FloatAdd 297opLat=2 298pipelined=true 299 300[system.cpu.fuPool.FUList2.opList1] 301type=OpDesc 302eventq_index=0 303opClass=FloatCmp 304opLat=2 305pipelined=true 306 307[system.cpu.fuPool.FUList2.opList2] 308type=OpDesc 309eventq_index=0 310opClass=FloatCvt 311opLat=2 312pipelined=true 313 314[system.cpu.fuPool.FUList3] 315type=FUDesc 316children=opList0 opList1 opList2 317count=2 318eventq_index=0 319opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 320 321[system.cpu.fuPool.FUList3.opList0] 322type=OpDesc 323eventq_index=0 324opClass=FloatMult 325opLat=4 326pipelined=true 327 328[system.cpu.fuPool.FUList3.opList1] 329type=OpDesc 330eventq_index=0 331opClass=FloatDiv 332opLat=12 333pipelined=false 334 335[system.cpu.fuPool.FUList3.opList2] 336type=OpDesc 337eventq_index=0 338opClass=FloatSqrt 339opLat=24 340pipelined=false 341 342[system.cpu.fuPool.FUList4] 343type=FUDesc 344children=opList 345count=0 346eventq_index=0 347opList=system.cpu.fuPool.FUList4.opList 348 349[system.cpu.fuPool.FUList4.opList] 350type=OpDesc 351eventq_index=0 352opClass=MemRead 353opLat=1 354pipelined=true 355 356[system.cpu.fuPool.FUList5] 357type=FUDesc 358children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 359count=4 360eventq_index=0 361opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 362 363[system.cpu.fuPool.FUList5.opList00] 364type=OpDesc 365eventq_index=0 366opClass=SimdAdd 367opLat=1 368pipelined=true 369 370[system.cpu.fuPool.FUList5.opList01] 371type=OpDesc 372eventq_index=0 373opClass=SimdAddAcc 374opLat=1 375pipelined=true 376 377[system.cpu.fuPool.FUList5.opList02] 378type=OpDesc 379eventq_index=0 380opClass=SimdAlu 381opLat=1 382pipelined=true 383 384[system.cpu.fuPool.FUList5.opList03] 385type=OpDesc 386eventq_index=0 387opClass=SimdCmp 388opLat=1 389pipelined=true 390 391[system.cpu.fuPool.FUList5.opList04] 392type=OpDesc 393eventq_index=0 394opClass=SimdCvt 395opLat=1 396pipelined=true 397 398[system.cpu.fuPool.FUList5.opList05] 399type=OpDesc 400eventq_index=0 401opClass=SimdMisc 402opLat=1 403pipelined=true 404 405[system.cpu.fuPool.FUList5.opList06] 406type=OpDesc 407eventq_index=0 408opClass=SimdMult 409opLat=1 410pipelined=true 411 412[system.cpu.fuPool.FUList5.opList07] 413type=OpDesc 414eventq_index=0 415opClass=SimdMultAcc 416opLat=1 417pipelined=true 418 419[system.cpu.fuPool.FUList5.opList08] 420type=OpDesc 421eventq_index=0 422opClass=SimdShift 423opLat=1 424pipelined=true 425 426[system.cpu.fuPool.FUList5.opList09] 427type=OpDesc 428eventq_index=0 429opClass=SimdShiftAcc 430opLat=1 431pipelined=true 432 433[system.cpu.fuPool.FUList5.opList10] 434type=OpDesc 435eventq_index=0 436opClass=SimdSqrt 437opLat=1 438pipelined=true 439 440[system.cpu.fuPool.FUList5.opList11] 441type=OpDesc 442eventq_index=0 443opClass=SimdFloatAdd 444opLat=1 445pipelined=true 446 447[system.cpu.fuPool.FUList5.opList12] 448type=OpDesc 449eventq_index=0 450opClass=SimdFloatAlu 451opLat=1 452pipelined=true 453 454[system.cpu.fuPool.FUList5.opList13] 455type=OpDesc 456eventq_index=0 457opClass=SimdFloatCmp 458opLat=1 459pipelined=true 460 461[system.cpu.fuPool.FUList5.opList14] 462type=OpDesc 463eventq_index=0 464opClass=SimdFloatCvt 465opLat=1 466pipelined=true 467 468[system.cpu.fuPool.FUList5.opList15] 469type=OpDesc 470eventq_index=0 471opClass=SimdFloatDiv 472opLat=1 473pipelined=true 474 475[system.cpu.fuPool.FUList5.opList16] 476type=OpDesc 477eventq_index=0 478opClass=SimdFloatMisc 479opLat=1 480pipelined=true 481 482[system.cpu.fuPool.FUList5.opList17] 483type=OpDesc 484eventq_index=0 485opClass=SimdFloatMult 486opLat=1 487pipelined=true 488 489[system.cpu.fuPool.FUList5.opList18] 490type=OpDesc 491eventq_index=0 492opClass=SimdFloatMultAcc 493opLat=1 494pipelined=true 495 496[system.cpu.fuPool.FUList5.opList19] 497type=OpDesc 498eventq_index=0 499opClass=SimdFloatSqrt 500opLat=1 501pipelined=true 502 503[system.cpu.fuPool.FUList6] 504type=FUDesc 505children=opList 506count=0 507eventq_index=0 508opList=system.cpu.fuPool.FUList6.opList 509 510[system.cpu.fuPool.FUList6.opList] 511type=OpDesc 512eventq_index=0 513opClass=MemWrite 514opLat=1 515pipelined=true 516 517[system.cpu.fuPool.FUList7] 518type=FUDesc 519children=opList0 opList1 520count=4 521eventq_index=0 522opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 523 524[system.cpu.fuPool.FUList7.opList0] 525type=OpDesc 526eventq_index=0 527opClass=MemRead 528opLat=1 529pipelined=true 530 531[system.cpu.fuPool.FUList7.opList1] 532type=OpDesc 533eventq_index=0 534opClass=MemWrite 535opLat=1 536pipelined=true 537 538[system.cpu.fuPool.FUList8] 539type=FUDesc 540children=opList 541count=1 542eventq_index=0 543opList=system.cpu.fuPool.FUList8.opList 544 545[system.cpu.fuPool.FUList8.opList] 546type=OpDesc 547eventq_index=0 548opClass=IprAccess 549opLat=3 550pipelined=false 551 552[system.cpu.icache] 553type=Cache 554children=tags 555addr_ranges=0:18446744073709551615 556assoc=2 557clk_domain=system.cpu_clk_domain 558clusivity=mostly_incl 559default_p_state=UNDEFINED 560demand_mshr_reserve=1 561eventq_index=0 562hit_latency=2 563is_read_only=true 564max_miss_count=0 565mshrs=4 566p_state_clk_gate_bins=20 567p_state_clk_gate_max=1000000000000 568p_state_clk_gate_min=1000 569power_model=Null 570prefetch_on_access=false 571prefetcher=Null 572response_latency=2 573sequential_access=false 574size=131072 575system=system 576tags=system.cpu.icache.tags 577tgts_per_mshr=20 578write_buffers=8 579writeback_clean=true 580cpu_side=system.cpu.icache_port 581mem_side=system.cpu.toL2Bus.slave[0] 582 583[system.cpu.icache.tags] 584type=LRU 585assoc=2 586block_size=64 587clk_domain=system.cpu_clk_domain 588default_p_state=UNDEFINED 589eventq_index=0 590hit_latency=2 591p_state_clk_gate_bins=20 592p_state_clk_gate_max=1000000000000 593p_state_clk_gate_min=1000 594power_model=Null 595sequential_access=false 596size=131072 597 598[system.cpu.interrupts] 599type=X86LocalApic 600clk_domain=system.cpu.apic_clk_domain 601default_p_state=UNDEFINED 602eventq_index=0 603int_latency=1000 604p_state_clk_gate_bins=20 605p_state_clk_gate_max=1000000000000 606p_state_clk_gate_min=1000 607pio_addr=2305843009213693952 608pio_latency=100000 609power_model=Null 610system=system 611int_master=system.membus.slave[2] 612int_slave=system.membus.master[2] 613pio=system.membus.master[1] 614 615[system.cpu.isa] 616type=X86ISA 617eventq_index=0 618 619[system.cpu.itb] 620type=X86TLB 621children=walker 622eventq_index=0 623size=64 624walker=system.cpu.itb.walker 625 626[system.cpu.itb.walker] 627type=X86PagetableWalker 628clk_domain=system.cpu_clk_domain 629default_p_state=UNDEFINED 630eventq_index=0 631num_squash_per_cycle=4 632p_state_clk_gate_bins=20 633p_state_clk_gate_max=1000000000000 634p_state_clk_gate_min=1000 635power_model=Null 636system=system 637port=system.cpu.toL2Bus.slave[2] 638 639[system.cpu.l2cache] 640type=Cache 641children=tags 642addr_ranges=0:18446744073709551615 643assoc=8 644clk_domain=system.cpu_clk_domain 645clusivity=mostly_incl 646default_p_state=UNDEFINED 647demand_mshr_reserve=1 648eventq_index=0 649hit_latency=20 650is_read_only=false 651max_miss_count=0 652mshrs=20 653p_state_clk_gate_bins=20 654p_state_clk_gate_max=1000000000000 655p_state_clk_gate_min=1000 656power_model=Null 657prefetch_on_access=false 658prefetcher=Null 659response_latency=20 660sequential_access=false 661size=2097152 662system=system 663tags=system.cpu.l2cache.tags 664tgts_per_mshr=12 665write_buffers=8 666writeback_clean=false 667cpu_side=system.cpu.toL2Bus.master[0] 668mem_side=system.membus.slave[1] 669 670[system.cpu.l2cache.tags] 671type=LRU 672assoc=8 673block_size=64 674clk_domain=system.cpu_clk_domain 675default_p_state=UNDEFINED 676eventq_index=0 677hit_latency=20 678p_state_clk_gate_bins=20 679p_state_clk_gate_max=1000000000000 680p_state_clk_gate_min=1000 681power_model=Null 682sequential_access=false 683size=2097152 684 685[system.cpu.toL2Bus] 686type=CoherentXBar 687children=snoop_filter 688clk_domain=system.cpu_clk_domain 689default_p_state=UNDEFINED 690eventq_index=0 691forward_latency=0 692frontend_latency=1 693p_state_clk_gate_bins=20 694p_state_clk_gate_max=1000000000000 695p_state_clk_gate_min=1000 696point_of_coherency=false 697power_model=Null 698response_latency=1 699snoop_filter=system.cpu.toL2Bus.snoop_filter 700snoop_response_latency=1 701system=system 702use_default_range=false 703width=32 704master=system.cpu.l2cache.cpu_side 705slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port 706 707[system.cpu.toL2Bus.snoop_filter] 708type=SnoopFilter 709eventq_index=0 710lookup_latency=0 711max_capacity=8388608 712system=system 713 714[system.cpu.tracer] 715type=ExeTracer 716eventq_index=0 717 718[system.cpu.workload] 719type=LiveProcess 720cmd=parser 2.1.dict -batch 721cwd=build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing 722drivers= 723egid=100 724env= 725errout=cerr 726euid=100 727eventq_index=0 728executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/x86/linux/parser 729gid=100 730input=/arm/projectscratch/randd/systems/dist/cpu2000/data/parser/mdred/input/parser.in 731kvmInSE=false 732max_stack_size=67108864 733output=cout 734pid=100 735ppid=99 736simpoint=114600000000 737system=system 738uid=100 739useArchPT=false 740 741[system.cpu_clk_domain] 742type=SrcClockDomain 743clock=500 744domain_id=-1 745eventq_index=0 746init_perf_level=0 747voltage_domain=system.voltage_domain 748 749[system.dvfs_handler] 750type=DVFSHandler 751domains= 752enable=false 753eventq_index=0 754sys_clk_domain=system.clk_domain 755transition_latency=100000000 756 757[system.membus] 758type=CoherentXBar 759clk_domain=system.clk_domain 760default_p_state=UNDEFINED 761eventq_index=0 762forward_latency=4 763frontend_latency=3 764p_state_clk_gate_bins=20 765p_state_clk_gate_max=1000000000000 766p_state_clk_gate_min=1000 767point_of_coherency=true 768power_model=Null 769response_latency=2 770snoop_filter=Null 771snoop_response_latency=4 772system=system 773use_default_range=false 774width=16 775master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave 776slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master 777 778[system.physmem] 779type=DRAMCtrl 780IDD0=0.075000 781IDD02=0.000000 782IDD2N=0.050000 783IDD2N2=0.000000 784IDD2P0=0.000000 785IDD2P02=0.000000 786IDD2P1=0.000000 787IDD2P12=0.000000 788IDD3N=0.057000 789IDD3N2=0.000000 790IDD3P0=0.000000 791IDD3P02=0.000000 792IDD3P1=0.000000 793IDD3P12=0.000000 794IDD4R=0.187000 795IDD4R2=0.000000 796IDD4W=0.165000 797IDD4W2=0.000000 798IDD5=0.220000 799IDD52=0.000000 800IDD6=0.000000 801IDD62=0.000000 802VDD=1.500000 803VDD2=0.000000 804activation_limit=4 805addr_mapping=RoRaBaCoCh 806bank_groups_per_rank=0 807banks_per_rank=8 808burst_length=8 809channels=1 810clk_domain=system.clk_domain 811conf_table_reported=true 812default_p_state=UNDEFINED 813device_bus_width=8 814device_rowbuffer_size=1024 815device_size=536870912 816devices_per_rank=8 817dll=true 818eventq_index=0 819in_addr_map=true 820max_accesses_per_row=16 821mem_sched_policy=frfcfs 822min_writes_per_switch=16 823null=false 824p_state_clk_gate_bins=20 825p_state_clk_gate_max=1000000000000 826p_state_clk_gate_min=1000 827page_policy=open_adaptive 828power_model=Null 829range=0:134217727 830ranks_per_channel=2 831read_buffer_size=32 832static_backend_latency=10000 833static_frontend_latency=10000 834tBURST=5000 835tCCD_L=0 836tCK=1250 837tCL=13750 838tCS=2500 839tRAS=35000 840tRCD=13750 841tREFI=7800000 842tRFC=260000 843tRP=13750 844tRRD=6000 845tRRD_L=0 846tRTP=7500 847tRTW=2500 848tWR=15000 849tWTR=7500 850tXAW=30000 851tXP=0 852tXPDLL=0 853tXS=0 854tXSDLL=0 855write_buffer_size=64 856write_high_thresh_perc=85 857write_low_thresh_perc=50 858port=system.membus.master[0] 859 860[system.voltage_domain] 861type=VoltageDomain 862eventq_index=0 863voltage=1.000000 864 865