config.ini revision 10901
1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=System 13children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain 17eventq_index=0 18init_param=0 19kernel= 20kernel_addr_check=true 21load_addr_mask=1099511627775 22load_offset=0 23mem_mode=timing 24mem_ranges= 25memories=system.physmem 26mmap_using_noreserve=false 27num_work_ids=16 28readfile= 29symbolfile= 30work_begin_ckpt_count=0 31work_begin_cpu_id_exit=-1 32work_begin_exit_count=0 33work_cpus_ckpt_count=0 34work_end_ckpt_count=0 35work_end_exit_count=0 36work_item_id=-1 37system_port=system.membus.slave[0] 38 39[system.clk_domain] 40type=SrcClockDomain 41clock=1000 42domain_id=-1 43eventq_index=0 44init_perf_level=0 45voltage_domain=system.voltage_domain 46 47[system.cpu] 48type=DerivO3CPU 49children=apic_clk_domain branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload 50LFSTSize=1024 51LQEntries=32 52LSQCheckLoads=true 53LSQDepCheckShift=4 54SQEntries=32 55SSITSize=1024 56activity=0 57backComSize=5 58branchPred=system.cpu.branchPred 59cachePorts=200 60checker=Null 61clk_domain=system.cpu_clk_domain 62commitToDecodeDelay=1 63commitToFetchDelay=1 64commitToIEWDelay=1 65commitToRenameDelay=1 66commitWidth=8 67cpu_id=0 68decodeToFetchDelay=1 69decodeToRenameDelay=1 70decodeWidth=8 71dispatchWidth=8 72do_checkpoint_insts=true 73do_quiesce=true 74do_statistics_insts=true 75dtb=system.cpu.dtb 76eventq_index=0 77fetchBufferSize=64 78fetchQueueSize=32 79fetchToDecodeDelay=1 80fetchTrapLatency=1 81fetchWidth=8 82forwardComSize=5 83fuPool=system.cpu.fuPool 84function_trace=false 85function_trace_start=0 86iewToCommitDelay=1 87iewToDecodeDelay=1 88iewToFetchDelay=1 89iewToRenameDelay=1 90interrupts=system.cpu.interrupts 91isa=system.cpu.isa 92issueToExecuteDelay=1 93issueWidth=8 94itb=system.cpu.itb 95max_insts_all_threads=0 96max_insts_any_thread=0 97max_loads_all_threads=0 98max_loads_any_thread=0 99needsTSO=true 100numIQEntries=64 101numPhysCCRegs=1280 102numPhysFloatRegs=256 103numPhysIntRegs=256 104numROBEntries=192 105numRobs=1 106numThreads=1 107profile=0 108progress_interval=0 109renameToDecodeDelay=1 110renameToFetchDelay=1 111renameToIEWDelay=2 112renameToROBDelay=1 113renameWidth=8 114simpoint_start_insts= 115smtCommitPolicy=RoundRobin 116smtFetchPolicy=SingleThread 117smtIQPolicy=Partitioned 118smtIQThreshold=100 119smtLSQPolicy=Partitioned 120smtLSQThreshold=100 121smtNumFetchingThreads=1 122smtROBPolicy=Partitioned 123smtROBThreshold=100 124socket_id=0 125squashWidth=8 126store_set_clear_period=250000 127switched_out=false 128system=system 129tracer=system.cpu.tracer 130trapLatency=13 131wbWidth=8 132workload=system.cpu.workload 133dcache_port=system.cpu.dcache.cpu_side 134icache_port=system.cpu.icache.cpu_side 135 136[system.cpu.apic_clk_domain] 137type=DerivedClockDomain 138clk_divider=16 139clk_domain=system.cpu_clk_domain 140eventq_index=0 141 142[system.cpu.branchPred] 143type=TournamentBP 144BTBEntries=4096 145BTBTagSize=16 146RASSize=16 147choiceCtrBits=2 148choicePredictorSize=8192 149eventq_index=0 150globalCtrBits=2 151globalPredictorSize=8192 152instShiftAmt=2 153localCtrBits=2 154localHistoryTableSize=2048 155localPredictorSize=2048 156numThreads=1 157 158[system.cpu.dcache] 159type=BaseCache 160children=tags 161addr_ranges=0:18446744073709551615 162assoc=2 163clk_domain=system.cpu_clk_domain 164demand_mshr_reserve=1 165eventq_index=0 166forward_snoops=true 167hit_latency=2 168is_read_only=false 169max_miss_count=0 170mshrs=4 171prefetch_on_access=false 172prefetcher=Null 173response_latency=2 174sequential_access=false 175size=262144 176system=system 177tags=system.cpu.dcache.tags 178tgts_per_mshr=20 179write_buffers=8 180cpu_side=system.cpu.dcache_port 181mem_side=system.cpu.toL2Bus.slave[1] 182 183[system.cpu.dcache.tags] 184type=LRU 185assoc=2 186block_size=64 187clk_domain=system.cpu_clk_domain 188eventq_index=0 189hit_latency=2 190sequential_access=false 191size=262144 192 193[system.cpu.dtb] 194type=X86TLB 195children=walker 196eventq_index=0 197size=64 198walker=system.cpu.dtb.walker 199 200[system.cpu.dtb.walker] 201type=X86PagetableWalker 202clk_domain=system.cpu_clk_domain 203eventq_index=0 204num_squash_per_cycle=4 205system=system 206port=system.cpu.toL2Bus.slave[3] 207 208[system.cpu.fuPool] 209type=FUPool 210children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 211FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 212eventq_index=0 213 214[system.cpu.fuPool.FUList0] 215type=FUDesc 216children=opList 217count=6 218eventq_index=0 219opList=system.cpu.fuPool.FUList0.opList 220 221[system.cpu.fuPool.FUList0.opList] 222type=OpDesc 223eventq_index=0 224opClass=IntAlu 225opLat=1 226pipelined=true 227 228[system.cpu.fuPool.FUList1] 229type=FUDesc 230children=opList0 opList1 231count=2 232eventq_index=0 233opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 234 235[system.cpu.fuPool.FUList1.opList0] 236type=OpDesc 237eventq_index=0 238opClass=IntMult 239opLat=3 240pipelined=true 241 242[system.cpu.fuPool.FUList1.opList1] 243type=OpDesc 244eventq_index=0 245opClass=IntDiv 246opLat=1 247pipelined=false 248 249[system.cpu.fuPool.FUList2] 250type=FUDesc 251children=opList0 opList1 opList2 252count=4 253eventq_index=0 254opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 255 256[system.cpu.fuPool.FUList2.opList0] 257type=OpDesc 258eventq_index=0 259opClass=FloatAdd 260opLat=2 261pipelined=true 262 263[system.cpu.fuPool.FUList2.opList1] 264type=OpDesc 265eventq_index=0 266opClass=FloatCmp 267opLat=2 268pipelined=true 269 270[system.cpu.fuPool.FUList2.opList2] 271type=OpDesc 272eventq_index=0 273opClass=FloatCvt 274opLat=2 275pipelined=true 276 277[system.cpu.fuPool.FUList3] 278type=FUDesc 279children=opList0 opList1 opList2 280count=2 281eventq_index=0 282opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 283 284[system.cpu.fuPool.FUList3.opList0] 285type=OpDesc 286eventq_index=0 287opClass=FloatMult 288opLat=4 289pipelined=true 290 291[system.cpu.fuPool.FUList3.opList1] 292type=OpDesc 293eventq_index=0 294opClass=FloatDiv 295opLat=12 296pipelined=false 297 298[system.cpu.fuPool.FUList3.opList2] 299type=OpDesc 300eventq_index=0 301opClass=FloatSqrt 302opLat=24 303pipelined=false 304 305[system.cpu.fuPool.FUList4] 306type=FUDesc 307children=opList 308count=0 309eventq_index=0 310opList=system.cpu.fuPool.FUList4.opList 311 312[system.cpu.fuPool.FUList4.opList] 313type=OpDesc 314eventq_index=0 315opClass=MemRead 316opLat=1 317pipelined=true 318 319[system.cpu.fuPool.FUList5] 320type=FUDesc 321children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 322count=4 323eventq_index=0 324opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 325 326[system.cpu.fuPool.FUList5.opList00] 327type=OpDesc 328eventq_index=0 329opClass=SimdAdd 330opLat=1 331pipelined=true 332 333[system.cpu.fuPool.FUList5.opList01] 334type=OpDesc 335eventq_index=0 336opClass=SimdAddAcc 337opLat=1 338pipelined=true 339 340[system.cpu.fuPool.FUList5.opList02] 341type=OpDesc 342eventq_index=0 343opClass=SimdAlu 344opLat=1 345pipelined=true 346 347[system.cpu.fuPool.FUList5.opList03] 348type=OpDesc 349eventq_index=0 350opClass=SimdCmp 351opLat=1 352pipelined=true 353 354[system.cpu.fuPool.FUList5.opList04] 355type=OpDesc 356eventq_index=0 357opClass=SimdCvt 358opLat=1 359pipelined=true 360 361[system.cpu.fuPool.FUList5.opList05] 362type=OpDesc 363eventq_index=0 364opClass=SimdMisc 365opLat=1 366pipelined=true 367 368[system.cpu.fuPool.FUList5.opList06] 369type=OpDesc 370eventq_index=0 371opClass=SimdMult 372opLat=1 373pipelined=true 374 375[system.cpu.fuPool.FUList5.opList07] 376type=OpDesc 377eventq_index=0 378opClass=SimdMultAcc 379opLat=1 380pipelined=true 381 382[system.cpu.fuPool.FUList5.opList08] 383type=OpDesc 384eventq_index=0 385opClass=SimdShift 386opLat=1 387pipelined=true 388 389[system.cpu.fuPool.FUList5.opList09] 390type=OpDesc 391eventq_index=0 392opClass=SimdShiftAcc 393opLat=1 394pipelined=true 395 396[system.cpu.fuPool.FUList5.opList10] 397type=OpDesc 398eventq_index=0 399opClass=SimdSqrt 400opLat=1 401pipelined=true 402 403[system.cpu.fuPool.FUList5.opList11] 404type=OpDesc 405eventq_index=0 406opClass=SimdFloatAdd 407opLat=1 408pipelined=true 409 410[system.cpu.fuPool.FUList5.opList12] 411type=OpDesc 412eventq_index=0 413opClass=SimdFloatAlu 414opLat=1 415pipelined=true 416 417[system.cpu.fuPool.FUList5.opList13] 418type=OpDesc 419eventq_index=0 420opClass=SimdFloatCmp 421opLat=1 422pipelined=true 423 424[system.cpu.fuPool.FUList5.opList14] 425type=OpDesc 426eventq_index=0 427opClass=SimdFloatCvt 428opLat=1 429pipelined=true 430 431[system.cpu.fuPool.FUList5.opList15] 432type=OpDesc 433eventq_index=0 434opClass=SimdFloatDiv 435opLat=1 436pipelined=true 437 438[system.cpu.fuPool.FUList5.opList16] 439type=OpDesc 440eventq_index=0 441opClass=SimdFloatMisc 442opLat=1 443pipelined=true 444 445[system.cpu.fuPool.FUList5.opList17] 446type=OpDesc 447eventq_index=0 448opClass=SimdFloatMult 449opLat=1 450pipelined=true 451 452[system.cpu.fuPool.FUList5.opList18] 453type=OpDesc 454eventq_index=0 455opClass=SimdFloatMultAcc 456opLat=1 457pipelined=true 458 459[system.cpu.fuPool.FUList5.opList19] 460type=OpDesc 461eventq_index=0 462opClass=SimdFloatSqrt 463opLat=1 464pipelined=true 465 466[system.cpu.fuPool.FUList6] 467type=FUDesc 468children=opList 469count=0 470eventq_index=0 471opList=system.cpu.fuPool.FUList6.opList 472 473[system.cpu.fuPool.FUList6.opList] 474type=OpDesc 475eventq_index=0 476opClass=MemWrite 477opLat=1 478pipelined=true 479 480[system.cpu.fuPool.FUList7] 481type=FUDesc 482children=opList0 opList1 483count=4 484eventq_index=0 485opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 486 487[system.cpu.fuPool.FUList7.opList0] 488type=OpDesc 489eventq_index=0 490opClass=MemRead 491opLat=1 492pipelined=true 493 494[system.cpu.fuPool.FUList7.opList1] 495type=OpDesc 496eventq_index=0 497opClass=MemWrite 498opLat=1 499pipelined=true 500 501[system.cpu.fuPool.FUList8] 502type=FUDesc 503children=opList 504count=1 505eventq_index=0 506opList=system.cpu.fuPool.FUList8.opList 507 508[system.cpu.fuPool.FUList8.opList] 509type=OpDesc 510eventq_index=0 511opClass=IprAccess 512opLat=3 513pipelined=false 514 515[system.cpu.icache] 516type=BaseCache 517children=tags 518addr_ranges=0:18446744073709551615 519assoc=2 520clk_domain=system.cpu_clk_domain 521demand_mshr_reserve=1 522eventq_index=0 523forward_snoops=true 524hit_latency=2 525is_read_only=true 526max_miss_count=0 527mshrs=4 528prefetch_on_access=false 529prefetcher=Null 530response_latency=2 531sequential_access=false 532size=131072 533system=system 534tags=system.cpu.icache.tags 535tgts_per_mshr=20 536write_buffers=8 537cpu_side=system.cpu.icache_port 538mem_side=system.cpu.toL2Bus.slave[0] 539 540[system.cpu.icache.tags] 541type=LRU 542assoc=2 543block_size=64 544clk_domain=system.cpu_clk_domain 545eventq_index=0 546hit_latency=2 547sequential_access=false 548size=131072 549 550[system.cpu.interrupts] 551type=X86LocalApic 552clk_domain=system.cpu.apic_clk_domain 553eventq_index=0 554int_latency=1000 555pio_addr=2305843009213693952 556pio_latency=100000 557system=system 558int_master=system.membus.slave[2] 559int_slave=system.membus.master[2] 560pio=system.membus.master[1] 561 562[system.cpu.isa] 563type=X86ISA 564eventq_index=0 565 566[system.cpu.itb] 567type=X86TLB 568children=walker 569eventq_index=0 570size=64 571walker=system.cpu.itb.walker 572 573[system.cpu.itb.walker] 574type=X86PagetableWalker 575clk_domain=system.cpu_clk_domain 576eventq_index=0 577num_squash_per_cycle=4 578system=system 579port=system.cpu.toL2Bus.slave[2] 580 581[system.cpu.l2cache] 582type=BaseCache 583children=tags 584addr_ranges=0:18446744073709551615 585assoc=8 586clk_domain=system.cpu_clk_domain 587demand_mshr_reserve=1 588eventq_index=0 589forward_snoops=true 590hit_latency=20 591is_read_only=false 592max_miss_count=0 593mshrs=20 594prefetch_on_access=false 595prefetcher=Null 596response_latency=20 597sequential_access=false 598size=2097152 599system=system 600tags=system.cpu.l2cache.tags 601tgts_per_mshr=12 602write_buffers=8 603cpu_side=system.cpu.toL2Bus.master[0] 604mem_side=system.membus.slave[1] 605 606[system.cpu.l2cache.tags] 607type=LRU 608assoc=8 609block_size=64 610clk_domain=system.cpu_clk_domain 611eventq_index=0 612hit_latency=20 613sequential_access=false 614size=2097152 615 616[system.cpu.toL2Bus] 617type=CoherentXBar 618clk_domain=system.cpu_clk_domain 619eventq_index=0 620forward_latency=0 621frontend_latency=1 622response_latency=1 623snoop_filter=Null 624snoop_response_latency=1 625system=system 626use_default_range=false 627width=32 628master=system.cpu.l2cache.cpu_side 629slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port 630 631[system.cpu.tracer] 632type=ExeTracer 633eventq_index=0 634 635[system.cpu.workload] 636type=LiveProcess 637cmd=parser 2.1.dict -batch 638cwd=build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing 639drivers= 640egid=100 641env= 642errout=cerr 643euid=100 644eventq_index=0 645executable=/home/stever/m5/dist/cpu2000/binaries/x86/linux/parser 646gid=100 647input=/home/stever/m5/dist/cpu2000/data/parser/mdred/input/parser.in 648kvmInSE=false 649max_stack_size=67108864 650output=cout 651pid=100 652ppid=99 653simpoint=114600000000 654system=system 655uid=100 656useArchPT=false 657 658[system.cpu_clk_domain] 659type=SrcClockDomain 660clock=500 661domain_id=-1 662eventq_index=0 663init_perf_level=0 664voltage_domain=system.voltage_domain 665 666[system.dvfs_handler] 667type=DVFSHandler 668domains= 669enable=false 670eventq_index=0 671sys_clk_domain=system.clk_domain 672transition_latency=100000000 673 674[system.membus] 675type=CoherentXBar 676clk_domain=system.clk_domain 677eventq_index=0 678forward_latency=4 679frontend_latency=3 680response_latency=2 681snoop_filter=Null 682snoop_response_latency=4 683system=system 684use_default_range=false 685width=16 686master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave 687slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master 688 689[system.physmem] 690type=DRAMCtrl 691IDD0=0.075000 692IDD02=0.000000 693IDD2N=0.050000 694IDD2N2=0.000000 695IDD2P0=0.000000 696IDD2P02=0.000000 697IDD2P1=0.000000 698IDD2P12=0.000000 699IDD3N=0.057000 700IDD3N2=0.000000 701IDD3P0=0.000000 702IDD3P02=0.000000 703IDD3P1=0.000000 704IDD3P12=0.000000 705IDD4R=0.187000 706IDD4R2=0.000000 707IDD4W=0.165000 708IDD4W2=0.000000 709IDD5=0.220000 710IDD52=0.000000 711IDD6=0.000000 712IDD62=0.000000 713VDD=1.500000 714VDD2=0.000000 715activation_limit=4 716addr_mapping=RoRaBaCoCh 717bank_groups_per_rank=0 718banks_per_rank=8 719burst_length=8 720channels=1 721clk_domain=system.clk_domain 722conf_table_reported=true 723device_bus_width=8 724device_rowbuffer_size=1024 725device_size=536870912 726devices_per_rank=8 727dll=true 728eventq_index=0 729in_addr_map=true 730max_accesses_per_row=16 731mem_sched_policy=frfcfs 732min_writes_per_switch=16 733null=false 734page_policy=open_adaptive 735range=0:134217727 736ranks_per_channel=2 737read_buffer_size=32 738static_backend_latency=10000 739static_frontend_latency=10000 740tBURST=5000 741tCCD_L=0 742tCK=1250 743tCL=13750 744tCS=2500 745tRAS=35000 746tRCD=13750 747tREFI=7800000 748tRFC=260000 749tRP=13750 750tRRD=6000 751tRRD_L=0 752tRTP=7500 753tRTW=2500 754tWR=15000 755tWTR=7500 756tXAW=30000 757tXP=0 758tXPDLL=0 759tXS=0 760tXSDLL=0 761write_buffer_size=64 762write_high_thresh_perc=85 763write_low_thresh_perc=50 764port=system.membus.master[0] 765 766[system.voltage_domain] 767type=VoltageDomain 768eventq_index=0 769voltage=1.000000 770 771