config.ini revision 10036
1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=System 13children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain 17eventq_index=0 18init_param=0 19kernel= 20load_addr_mask=1099511627775 21mem_mode=timing 22mem_ranges= 23memories=system.physmem 24num_work_ids=16 25readfile= 26symbolfile= 27work_begin_ckpt_count=0 28work_begin_cpu_id_exit=-1 29work_begin_exit_count=0 30work_cpus_ckpt_count=0 31work_end_ckpt_count=0 32work_end_exit_count=0 33work_item_id=-1 34system_port=system.membus.slave[0] 35 36[system.clk_domain] 37type=SrcClockDomain 38clock=1000 39eventq_index=0 40voltage_domain=system.voltage_domain 41 42[system.cpu] 43type=DerivO3CPU 44children=apic_clk_domain branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload 45LFSTSize=1024 46LQEntries=32 47LSQCheckLoads=true 48LSQDepCheckShift=4 49SQEntries=32 50SSITSize=1024 51activity=0 52backComSize=5 53branchPred=system.cpu.branchPred 54cachePorts=200 55checker=Null 56clk_domain=system.cpu_clk_domain 57commitToDecodeDelay=1 58commitToFetchDelay=1 59commitToIEWDelay=1 60commitToRenameDelay=1 61commitWidth=8 62cpu_id=0 63decodeToFetchDelay=1 64decodeToRenameDelay=1 65decodeWidth=8 66dispatchWidth=8 67do_checkpoint_insts=true 68do_quiesce=true 69do_statistics_insts=true 70dtb=system.cpu.dtb 71eventq_index=0 72fetchBufferSize=64 73fetchToDecodeDelay=1 74fetchTrapLatency=1 75fetchWidth=8 76forwardComSize=5 77fuPool=system.cpu.fuPool 78function_trace=false 79function_trace_start=0 80iewToCommitDelay=1 81iewToDecodeDelay=1 82iewToFetchDelay=1 83iewToRenameDelay=1 84interrupts=system.cpu.interrupts 85isa=system.cpu.isa 86issueToExecuteDelay=1 87issueWidth=8 88itb=system.cpu.itb 89max_insts_all_threads=0 90max_insts_any_thread=0 91max_loads_all_threads=0 92max_loads_any_thread=0 93needsTSO=true 94numIQEntries=64 95numPhysCCRegs=1280 96numPhysFloatRegs=256 97numPhysIntRegs=256 98numROBEntries=192 99numRobs=1 100numThreads=1 101profile=0 102progress_interval=0 103renameToDecodeDelay=1 104renameToFetchDelay=1 105renameToIEWDelay=2 106renameToROBDelay=1 107renameWidth=8 108simpoint_start_insts= 109smtCommitPolicy=RoundRobin 110smtFetchPolicy=SingleThread 111smtIQPolicy=Partitioned 112smtIQThreshold=100 113smtLSQPolicy=Partitioned 114smtLSQThreshold=100 115smtNumFetchingThreads=1 116smtROBPolicy=Partitioned 117smtROBThreshold=100 118squashWidth=8 119store_set_clear_period=250000 120switched_out=false 121system=system 122tracer=system.cpu.tracer 123trapLatency=13 124wbDepth=1 125wbWidth=8 126workload=system.cpu.workload 127dcache_port=system.cpu.dcache.cpu_side 128icache_port=system.cpu.icache.cpu_side 129 130[system.cpu.apic_clk_domain] 131type=DerivedClockDomain 132clk_divider=16 133clk_domain=system.cpu_clk_domain 134eventq_index=0 135 136[system.cpu.branchPred] 137type=BranchPredictor 138BTBEntries=4096 139BTBTagSize=16 140RASSize=16 141choiceCtrBits=2 142choicePredictorSize=8192 143eventq_index=0 144globalCtrBits=2 145globalPredictorSize=8192 146instShiftAmt=2 147localCtrBits=2 148localHistoryTableSize=2048 149localPredictorSize=2048 150numThreads=1 151predType=tournament 152 153[system.cpu.dcache] 154type=BaseCache 155children=tags 156addr_ranges=0:18446744073709551615 157assoc=2 158clk_domain=system.cpu_clk_domain 159eventq_index=0 160forward_snoops=true 161hit_latency=2 162is_top_level=true 163max_miss_count=0 164mshrs=4 165prefetch_on_access=false 166prefetcher=Null 167response_latency=2 168sequential_access=false 169size=262144 170system=system 171tags=system.cpu.dcache.tags 172tgts_per_mshr=20 173two_queue=false 174write_buffers=8 175cpu_side=system.cpu.dcache_port 176mem_side=system.cpu.toL2Bus.slave[1] 177 178[system.cpu.dcache.tags] 179type=LRU 180assoc=2 181block_size=64 182clk_domain=system.cpu_clk_domain 183eventq_index=0 184hit_latency=2 185sequential_access=false 186size=262144 187 188[system.cpu.dtb] 189type=X86TLB 190children=walker 191eventq_index=0 192size=64 193walker=system.cpu.dtb.walker 194 195[system.cpu.dtb.walker] 196type=X86PagetableWalker 197clk_domain=system.cpu_clk_domain 198eventq_index=0 199num_squash_per_cycle=4 200system=system 201port=system.cpu.toL2Bus.slave[3] 202 203[system.cpu.fuPool] 204type=FUPool 205children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 206FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 207eventq_index=0 208 209[system.cpu.fuPool.FUList0] 210type=FUDesc 211children=opList 212count=6 213eventq_index=0 214opList=system.cpu.fuPool.FUList0.opList 215 216[system.cpu.fuPool.FUList0.opList] 217type=OpDesc 218eventq_index=0 219issueLat=1 220opClass=IntAlu 221opLat=1 222 223[system.cpu.fuPool.FUList1] 224type=FUDesc 225children=opList0 opList1 226count=2 227eventq_index=0 228opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 229 230[system.cpu.fuPool.FUList1.opList0] 231type=OpDesc 232eventq_index=0 233issueLat=1 234opClass=IntMult 235opLat=3 236 237[system.cpu.fuPool.FUList1.opList1] 238type=OpDesc 239eventq_index=0 240issueLat=19 241opClass=IntDiv 242opLat=20 243 244[system.cpu.fuPool.FUList2] 245type=FUDesc 246children=opList0 opList1 opList2 247count=4 248eventq_index=0 249opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 250 251[system.cpu.fuPool.FUList2.opList0] 252type=OpDesc 253eventq_index=0 254issueLat=1 255opClass=FloatAdd 256opLat=2 257 258[system.cpu.fuPool.FUList2.opList1] 259type=OpDesc 260eventq_index=0 261issueLat=1 262opClass=FloatCmp 263opLat=2 264 265[system.cpu.fuPool.FUList2.opList2] 266type=OpDesc 267eventq_index=0 268issueLat=1 269opClass=FloatCvt 270opLat=2 271 272[system.cpu.fuPool.FUList3] 273type=FUDesc 274children=opList0 opList1 opList2 275count=2 276eventq_index=0 277opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 278 279[system.cpu.fuPool.FUList3.opList0] 280type=OpDesc 281eventq_index=0 282issueLat=1 283opClass=FloatMult 284opLat=4 285 286[system.cpu.fuPool.FUList3.opList1] 287type=OpDesc 288eventq_index=0 289issueLat=12 290opClass=FloatDiv 291opLat=12 292 293[system.cpu.fuPool.FUList3.opList2] 294type=OpDesc 295eventq_index=0 296issueLat=24 297opClass=FloatSqrt 298opLat=24 299 300[system.cpu.fuPool.FUList4] 301type=FUDesc 302children=opList 303count=0 304eventq_index=0 305opList=system.cpu.fuPool.FUList4.opList 306 307[system.cpu.fuPool.FUList4.opList] 308type=OpDesc 309eventq_index=0 310issueLat=1 311opClass=MemRead 312opLat=1 313 314[system.cpu.fuPool.FUList5] 315type=FUDesc 316children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 317count=4 318eventq_index=0 319opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 320 321[system.cpu.fuPool.FUList5.opList00] 322type=OpDesc 323eventq_index=0 324issueLat=1 325opClass=SimdAdd 326opLat=1 327 328[system.cpu.fuPool.FUList5.opList01] 329type=OpDesc 330eventq_index=0 331issueLat=1 332opClass=SimdAddAcc 333opLat=1 334 335[system.cpu.fuPool.FUList5.opList02] 336type=OpDesc 337eventq_index=0 338issueLat=1 339opClass=SimdAlu 340opLat=1 341 342[system.cpu.fuPool.FUList5.opList03] 343type=OpDesc 344eventq_index=0 345issueLat=1 346opClass=SimdCmp 347opLat=1 348 349[system.cpu.fuPool.FUList5.opList04] 350type=OpDesc 351eventq_index=0 352issueLat=1 353opClass=SimdCvt 354opLat=1 355 356[system.cpu.fuPool.FUList5.opList05] 357type=OpDesc 358eventq_index=0 359issueLat=1 360opClass=SimdMisc 361opLat=1 362 363[system.cpu.fuPool.FUList5.opList06] 364type=OpDesc 365eventq_index=0 366issueLat=1 367opClass=SimdMult 368opLat=1 369 370[system.cpu.fuPool.FUList5.opList07] 371type=OpDesc 372eventq_index=0 373issueLat=1 374opClass=SimdMultAcc 375opLat=1 376 377[system.cpu.fuPool.FUList5.opList08] 378type=OpDesc 379eventq_index=0 380issueLat=1 381opClass=SimdShift 382opLat=1 383 384[system.cpu.fuPool.FUList5.opList09] 385type=OpDesc 386eventq_index=0 387issueLat=1 388opClass=SimdShiftAcc 389opLat=1 390 391[system.cpu.fuPool.FUList5.opList10] 392type=OpDesc 393eventq_index=0 394issueLat=1 395opClass=SimdSqrt 396opLat=1 397 398[system.cpu.fuPool.FUList5.opList11] 399type=OpDesc 400eventq_index=0 401issueLat=1 402opClass=SimdFloatAdd 403opLat=1 404 405[system.cpu.fuPool.FUList5.opList12] 406type=OpDesc 407eventq_index=0 408issueLat=1 409opClass=SimdFloatAlu 410opLat=1 411 412[system.cpu.fuPool.FUList5.opList13] 413type=OpDesc 414eventq_index=0 415issueLat=1 416opClass=SimdFloatCmp 417opLat=1 418 419[system.cpu.fuPool.FUList5.opList14] 420type=OpDesc 421eventq_index=0 422issueLat=1 423opClass=SimdFloatCvt 424opLat=1 425 426[system.cpu.fuPool.FUList5.opList15] 427type=OpDesc 428eventq_index=0 429issueLat=1 430opClass=SimdFloatDiv 431opLat=1 432 433[system.cpu.fuPool.FUList5.opList16] 434type=OpDesc 435eventq_index=0 436issueLat=1 437opClass=SimdFloatMisc 438opLat=1 439 440[system.cpu.fuPool.FUList5.opList17] 441type=OpDesc 442eventq_index=0 443issueLat=1 444opClass=SimdFloatMult 445opLat=1 446 447[system.cpu.fuPool.FUList5.opList18] 448type=OpDesc 449eventq_index=0 450issueLat=1 451opClass=SimdFloatMultAcc 452opLat=1 453 454[system.cpu.fuPool.FUList5.opList19] 455type=OpDesc 456eventq_index=0 457issueLat=1 458opClass=SimdFloatSqrt 459opLat=1 460 461[system.cpu.fuPool.FUList6] 462type=FUDesc 463children=opList 464count=0 465eventq_index=0 466opList=system.cpu.fuPool.FUList6.opList 467 468[system.cpu.fuPool.FUList6.opList] 469type=OpDesc 470eventq_index=0 471issueLat=1 472opClass=MemWrite 473opLat=1 474 475[system.cpu.fuPool.FUList7] 476type=FUDesc 477children=opList0 opList1 478count=4 479eventq_index=0 480opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 481 482[system.cpu.fuPool.FUList7.opList0] 483type=OpDesc 484eventq_index=0 485issueLat=1 486opClass=MemRead 487opLat=1 488 489[system.cpu.fuPool.FUList7.opList1] 490type=OpDesc 491eventq_index=0 492issueLat=1 493opClass=MemWrite 494opLat=1 495 496[system.cpu.fuPool.FUList8] 497type=FUDesc 498children=opList 499count=1 500eventq_index=0 501opList=system.cpu.fuPool.FUList8.opList 502 503[system.cpu.fuPool.FUList8.opList] 504type=OpDesc 505eventq_index=0 506issueLat=3 507opClass=IprAccess 508opLat=3 509 510[system.cpu.icache] 511type=BaseCache 512children=tags 513addr_ranges=0:18446744073709551615 514assoc=2 515clk_domain=system.cpu_clk_domain 516eventq_index=0 517forward_snoops=true 518hit_latency=2 519is_top_level=true 520max_miss_count=0 521mshrs=4 522prefetch_on_access=false 523prefetcher=Null 524response_latency=2 525sequential_access=false 526size=131072 527system=system 528tags=system.cpu.icache.tags 529tgts_per_mshr=20 530two_queue=false 531write_buffers=8 532cpu_side=system.cpu.icache_port 533mem_side=system.cpu.toL2Bus.slave[0] 534 535[system.cpu.icache.tags] 536type=LRU 537assoc=2 538block_size=64 539clk_domain=system.cpu_clk_domain 540eventq_index=0 541hit_latency=2 542sequential_access=false 543size=131072 544 545[system.cpu.interrupts] 546type=X86LocalApic 547clk_domain=system.cpu.apic_clk_domain 548eventq_index=0 549int_latency=1000 550pio_addr=2305843009213693952 551pio_latency=100000 552system=system 553int_master=system.membus.slave[2] 554int_slave=system.membus.master[2] 555pio=system.membus.master[1] 556 557[system.cpu.isa] 558type=X86ISA 559eventq_index=0 560 561[system.cpu.itb] 562type=X86TLB 563children=walker 564eventq_index=0 565size=64 566walker=system.cpu.itb.walker 567 568[system.cpu.itb.walker] 569type=X86PagetableWalker 570clk_domain=system.cpu_clk_domain 571eventq_index=0 572num_squash_per_cycle=4 573system=system 574port=system.cpu.toL2Bus.slave[2] 575 576[system.cpu.l2cache] 577type=BaseCache 578children=tags 579addr_ranges=0:18446744073709551615 580assoc=8 581clk_domain=system.cpu_clk_domain 582eventq_index=0 583forward_snoops=true 584hit_latency=20 585is_top_level=false 586max_miss_count=0 587mshrs=20 588prefetch_on_access=false 589prefetcher=Null 590response_latency=20 591sequential_access=false 592size=2097152 593system=system 594tags=system.cpu.l2cache.tags 595tgts_per_mshr=12 596two_queue=false 597write_buffers=8 598cpu_side=system.cpu.toL2Bus.master[0] 599mem_side=system.membus.slave[1] 600 601[system.cpu.l2cache.tags] 602type=LRU 603assoc=8 604block_size=64 605clk_domain=system.cpu_clk_domain 606eventq_index=0 607hit_latency=20 608sequential_access=false 609size=2097152 610 611[system.cpu.toL2Bus] 612type=CoherentBus 613clk_domain=system.cpu_clk_domain 614eventq_index=0 615header_cycles=1 616system=system 617use_default_range=false 618width=32 619master=system.cpu.l2cache.cpu_side 620slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port 621 622[system.cpu.tracer] 623type=ExeTracer 624eventq_index=0 625 626[system.cpu.workload] 627type=LiveProcess 628cmd=parser 2.1.dict -batch 629cwd=build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing 630egid=100 631env= 632errout=cerr 633euid=100 634eventq_index=0 635executable=/dist/cpu2000/binaries/x86/linux/parser 636gid=100 637input=/dist/cpu2000/data/parser/mdred/input/parser.in 638max_stack_size=67108864 639output=cout 640pid=100 641ppid=99 642simpoint=114600000000 643system=system 644uid=100 645 646[system.cpu_clk_domain] 647type=SrcClockDomain 648clock=500 649eventq_index=0 650voltage_domain=system.voltage_domain 651 652[system.membus] 653type=CoherentBus 654clk_domain=system.clk_domain 655eventq_index=0 656header_cycles=1 657system=system 658use_default_range=false 659width=8 660master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave 661slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master 662 663[system.physmem] 664type=SimpleDRAM 665activation_limit=4 666addr_mapping=RaBaChCo 667banks_per_rank=8 668burst_length=8 669channels=1 670clk_domain=system.clk_domain 671conf_table_reported=true 672device_bus_width=8 673device_rowbuffer_size=1024 674devices_per_rank=8 675eventq_index=0 676in_addr_map=true 677mem_sched_policy=frfcfs 678null=false 679page_policy=open 680range=0:134217727 681ranks_per_channel=2 682read_buffer_size=32 683static_backend_latency=10000 684static_frontend_latency=10000 685tBURST=5000 686tCL=13750 687tRAS=35000 688tRCD=13750 689tREFI=7800000 690tRFC=300000 691tRP=13750 692tRRD=6250 693tWTR=7500 694tXAW=40000 695write_buffer_size=32 696write_high_thresh_perc=70 697write_low_thresh_perc=0 698port=system.membus.master[0] 699 700[system.voltage_domain] 701type=VoltageDomain 702eventq_index=0 703voltage=1.000000 704 705