config.ini revision 9265
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4708825Snilay@cs.wisc.edu 4718825Snilay@cs.wisc.edu[system.cpu.itb.walker] 4728825Snilay@cs.wisc.edutype=X86PagetableWalker 4739213Snilay@cs.wisc.educlock=1 4748825Snilay@cs.wisc.edusystem=system 4758983Snate@binkert.orgport=system.cpu.toL2Bus.slave[2] 4767893SN/A 4777893SN/A[system.cpu.l2cache] 4787893SN/Atype=BaseCache 4798983Snate@binkert.orgaddr_ranges=0:18446744073709551615 4807893SN/Aassoc=2 4817893SN/Ablock_size=64 4829213Snilay@cs.wisc.educlock=1 4837893SN/Aforward_snoops=true 4847893SN/Ahash_delay=1 4858200SN/Ais_top_level=false 4867893SN/Alatency=1000 4877893SN/Amax_miss_count=0 4887893SN/Amshrs=10 4897893SN/Aprefetch_on_access=false 4908835SAli.Saidi@ARM.comprefetcher=Null 4917893SN/AprioritizeRequests=false 4927893SN/Arepl=Null 4937893SN/Asize=2097152 4947893SN/Asubblock_size=0 4958835SAli.Saidi@ARM.comsystem=system 4967893SN/Atgts_per_mshr=5 4977893SN/Atrace_addr=0 4987893SN/Atwo_queue=false 4997893SN/Awrite_buffers=8 5008983Snate@binkert.orgcpu_side=system.cpu.toL2Bus.master[0] 5018983Snate@binkert.orgmem_side=system.membus.slave[1] 5027893SN/A 5037893SN/A[system.cpu.toL2Bus] 5049039Sgblack@eecs.umich.edutype=CoherentBus 5057893SN/Ablock_size=64 5067893SN/Aclock=1000 5077893SN/Aheader_cycles=1 5087893SN/Ause_default_range=false 5099096Sandreas.hansson@arm.comwidth=8 5108983Snate@binkert.orgmaster=system.cpu.l2cache.cpu_side 5118983Snate@binkert.orgslave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port 5127893SN/A 5137893SN/A[system.cpu.tracer] 5147893SN/Atype=ExeTracer 5157893SN/A 5167893SN/A[system.cpu.workload] 5177893SN/Atype=LiveProcess 5187893SN/Acmd=parser 2.1.dict -batch 5199134Ssaidi@eecs.umich.educwd=build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing 5207893SN/Aegid=100 5217893SN/Aenv= 5227893SN/Aerrout=cerr 5237893SN/Aeuid=100 5249213Snilay@cs.wisc.eduexecutable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/parser 5257893SN/Agid=100 5269213Snilay@cs.wisc.eduinput=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in 5277893SN/Amax_stack_size=67108864 5287893SN/Aoutput=cout 5297893SN/Apid=100 5307893SN/Appid=99 5317893SN/Asimpoint=114600000000 5327893SN/Asystem=system 5337893SN/Auid=100 5347893SN/A 5357893SN/A[system.membus] 5369039Sgblack@eecs.umich.edutype=CoherentBus 5377893SN/Ablock_size=64 5387893SN/Aclock=1000 5397893SN/Aheader_cycles=1 5407893SN/Ause_default_range=false 5419096Sandreas.hansson@arm.comwidth=8 5429134Ssaidi@eecs.umich.edumaster=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave 5438983Snate@binkert.orgslave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master 5447893SN/A 5457893SN/A[system.physmem] 5468983Snate@binkert.orgtype=SimpleMemory 5479213Snilay@cs.wisc.educlock=1 5488983Snate@binkert.orgconf_table_reported=false 5497893SN/Afile= 5508983Snate@binkert.orgin_addr_map=true 5517893SN/Alatency=30000 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