config.ini revision 8521
1[root] 2type=Root 3children=system 4time_sync_enable=false 5time_sync_period=100000000000 6time_sync_spin_threshold=100000000 7 8[system] 9type=System 10children=cpu membus physmem 11mem_mode=atomic 12memories=system.physmem 13physmem=system.physmem 14work_begin_ckpt_count=0 15work_begin_cpu_id_exit=-1 16work_begin_exit_count=0 17work_cpus_ckpt_count=0 18work_end_ckpt_count=0 19work_end_exit_count=0 20work_item_id=-1 21 22[system.cpu] 23type=DerivO3CPU 24children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload 25BTBEntries=4096 26BTBTagSize=16 27LFSTSize=1024 28LQEntries=32 29LSQCheckLoads=true 30LSQDepCheckShift=4 31RASSize=16 32SQEntries=32 33SSITSize=1024 34activity=0 35backComSize=5 36cachePorts=200 37checker=Null 38choiceCtrBits=2 39choicePredictorSize=8192 40clock=500 41commitToDecodeDelay=1 42commitToFetchDelay=1 43commitToIEWDelay=1 44commitToRenameDelay=1 45commitWidth=8 46cpu_id=0 47decodeToFetchDelay=1 48decodeToRenameDelay=1 49decodeWidth=8 50defer_registration=false 51dispatchWidth=8 52do_checkpoint_insts=true 53do_statistics_insts=true 54dtb=system.cpu.dtb 55fetchToDecodeDelay=1 56fetchTrapLatency=1 57fetchWidth=8 58forwardComSize=5 59fuPool=system.cpu.fuPool 60function_trace=false 61function_trace_start=0 62globalCtrBits=2 63globalHistoryBits=13 64globalPredictorSize=8192 65iewToCommitDelay=1 66iewToDecodeDelay=1 67iewToFetchDelay=1 68iewToRenameDelay=1 69instShiftAmt=2 70issueToExecuteDelay=1 71issueWidth=8 72itb=system.cpu.itb 73localCtrBits=2 74localHistoryBits=11 75localHistoryTableSize=2048 76localPredictorSize=2048 77max_insts_all_threads=0 78max_insts_any_thread=0 79max_loads_all_threads=0 80max_loads_any_thread=0 81numIQEntries=64 82numPhysFloatRegs=256 83numPhysIntRegs=256 84numROBEntries=192 85numRobs=1 86numThreads=1 87phase=0 88predType=tournament 89progress_interval=0 90renameToDecodeDelay=1 91renameToFetchDelay=1 92renameToIEWDelay=2 93renameToROBDelay=1 94renameWidth=8 95smtCommitPolicy=RoundRobin 96smtFetchPolicy=SingleThread 97smtIQPolicy=Partitioned 98smtIQThreshold=100 99smtLSQPolicy=Partitioned 100smtLSQThreshold=100 101smtNumFetchingThreads=1 102smtROBPolicy=Partitioned 103smtROBThreshold=100 104squashWidth=8 105store_set_clear_period=250000 106system=system 107tracer=system.cpu.tracer 108trapLatency=13 109wbDepth=1 110wbWidth=8 111workload=system.cpu.workload 112dcache_port=system.cpu.dcache.cpu_side 113icache_port=system.cpu.icache.cpu_side 114 115[system.cpu.dcache] 116type=BaseCache 117addr_range=0:18446744073709551615 118assoc=2 119block_size=64 120forward_snoops=true 121hash_delay=1 122is_top_level=true 123latency=1000 124max_miss_count=0 125mshrs=10 126num_cpus=1 127prefetch_data_accesses_only=false 128prefetch_degree=1 129prefetch_latency=10000 130prefetch_on_access=false 131prefetch_past_page=false 132prefetch_policy=none 133prefetch_serial_squash=false 134prefetch_use_cpu_id=true 135prefetcher_size=100 136prioritizeRequests=false 137repl=Null 138size=262144 139subblock_size=0 140tgts_per_mshr=20 141trace_addr=0 142two_queue=false 143write_buffers=8 144cpu_side=system.cpu.dcache_port 145mem_side=system.cpu.toL2Bus.port[1] 146 147[system.cpu.dtb] 148type=X86TLB 149size=64 150 151[system.cpu.fuPool] 152type=FUPool 153children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 154FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 155 156[system.cpu.fuPool.FUList0] 157type=FUDesc 158children=opList 159count=6 160opList=system.cpu.fuPool.FUList0.opList 161 162[system.cpu.fuPool.FUList0.opList] 163type=OpDesc 164issueLat=1 165opClass=IntAlu 166opLat=1 167 168[system.cpu.fuPool.FUList1] 169type=FUDesc 170children=opList0 opList1 171count=2 172opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 173 174[system.cpu.fuPool.FUList1.opList0] 175type=OpDesc 176issueLat=1 177opClass=IntMult 178opLat=3 179 180[system.cpu.fuPool.FUList1.opList1] 181type=OpDesc 182issueLat=19 183opClass=IntDiv 184opLat=20 185 186[system.cpu.fuPool.FUList2] 187type=FUDesc 188children=opList0 opList1 opList2 189count=4 190opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 191 192[system.cpu.fuPool.FUList2.opList0] 193type=OpDesc 194issueLat=1 195opClass=FloatAdd 196opLat=2 197 198[system.cpu.fuPool.FUList2.opList1] 199type=OpDesc 200issueLat=1 201opClass=FloatCmp 202opLat=2 203 204[system.cpu.fuPool.FUList2.opList2] 205type=OpDesc 206issueLat=1 207opClass=FloatCvt 208opLat=2 209 210[system.cpu.fuPool.FUList3] 211type=FUDesc 212children=opList0 opList1 opList2 213count=2 214opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 215 216[system.cpu.fuPool.FUList3.opList0] 217type=OpDesc 218issueLat=1 219opClass=FloatMult 220opLat=4 221 222[system.cpu.fuPool.FUList3.opList1] 223type=OpDesc 224issueLat=12 225opClass=FloatDiv 226opLat=12 227 228[system.cpu.fuPool.FUList3.opList2] 229type=OpDesc 230issueLat=24 231opClass=FloatSqrt 232opLat=24 233 234[system.cpu.fuPool.FUList4] 235type=FUDesc 236children=opList 237count=0 238opList=system.cpu.fuPool.FUList4.opList 239 240[system.cpu.fuPool.FUList4.opList] 241type=OpDesc 242issueLat=1 243opClass=MemRead 244opLat=1 245 246[system.cpu.fuPool.FUList5] 247type=FUDesc 248children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 249count=4 250opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 251 252[system.cpu.fuPool.FUList5.opList00] 253type=OpDesc 254issueLat=1 255opClass=SimdAdd 256opLat=1 257 258[system.cpu.fuPool.FUList5.opList01] 259type=OpDesc 260issueLat=1 261opClass=SimdAddAcc 262opLat=1 263 264[system.cpu.fuPool.FUList5.opList02] 265type=OpDesc 266issueLat=1 267opClass=SimdAlu 268opLat=1 269 270[system.cpu.fuPool.FUList5.opList03] 271type=OpDesc 272issueLat=1 273opClass=SimdCmp 274opLat=1 275 276[system.cpu.fuPool.FUList5.opList04] 277type=OpDesc 278issueLat=1 279opClass=SimdCvt 280opLat=1 281 282[system.cpu.fuPool.FUList5.opList05] 283type=OpDesc 284issueLat=1 285opClass=SimdMisc 286opLat=1 287 288[system.cpu.fuPool.FUList5.opList06] 289type=OpDesc 290issueLat=1 291opClass=SimdMult 292opLat=1 293 294[system.cpu.fuPool.FUList5.opList07] 295type=OpDesc 296issueLat=1 297opClass=SimdMultAcc 298opLat=1 299 300[system.cpu.fuPool.FUList5.opList08] 301type=OpDesc 302issueLat=1 303opClass=SimdShift 304opLat=1 305 306[system.cpu.fuPool.FUList5.opList09] 307type=OpDesc 308issueLat=1 309opClass=SimdShiftAcc 310opLat=1 311 312[system.cpu.fuPool.FUList5.opList10] 313type=OpDesc 314issueLat=1 315opClass=SimdSqrt 316opLat=1 317 318[system.cpu.fuPool.FUList5.opList11] 319type=OpDesc 320issueLat=1 321opClass=SimdFloatAdd 322opLat=1 323 324[system.cpu.fuPool.FUList5.opList12] 325type=OpDesc 326issueLat=1 327opClass=SimdFloatAlu 328opLat=1 329 330[system.cpu.fuPool.FUList5.opList13] 331type=OpDesc 332issueLat=1 333opClass=SimdFloatCmp 334opLat=1 335 336[system.cpu.fuPool.FUList5.opList14] 337type=OpDesc 338issueLat=1 339opClass=SimdFloatCvt 340opLat=1 341 342[system.cpu.fuPool.FUList5.opList15] 343type=OpDesc 344issueLat=1 345opClass=SimdFloatDiv 346opLat=1 347 348[system.cpu.fuPool.FUList5.opList16] 349type=OpDesc 350issueLat=1 351opClass=SimdFloatMisc 352opLat=1 353 354[system.cpu.fuPool.FUList5.opList17] 355type=OpDesc 356issueLat=1 357opClass=SimdFloatMult 358opLat=1 359 360[system.cpu.fuPool.FUList5.opList18] 361type=OpDesc 362issueLat=1 363opClass=SimdFloatMultAcc 364opLat=1 365 366[system.cpu.fuPool.FUList5.opList19] 367type=OpDesc 368issueLat=1 369opClass=SimdFloatSqrt 370opLat=1 371 372[system.cpu.fuPool.FUList6] 373type=FUDesc 374children=opList 375count=0 376opList=system.cpu.fuPool.FUList6.opList 377 378[system.cpu.fuPool.FUList6.opList] 379type=OpDesc 380issueLat=1 381opClass=MemWrite 382opLat=1 383 384[system.cpu.fuPool.FUList7] 385type=FUDesc 386children=opList0 opList1 387count=4 388opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 389 390[system.cpu.fuPool.FUList7.opList0] 391type=OpDesc 392issueLat=1 393opClass=MemRead 394opLat=1 395 396[system.cpu.fuPool.FUList7.opList1] 397type=OpDesc 398issueLat=1 399opClass=MemWrite 400opLat=1 401 402[system.cpu.fuPool.FUList8] 403type=FUDesc 404children=opList 405count=1 406opList=system.cpu.fuPool.FUList8.opList 407 408[system.cpu.fuPool.FUList8.opList] 409type=OpDesc 410issueLat=3 411opClass=IprAccess 412opLat=3 413 414[system.cpu.icache] 415type=BaseCache 416addr_range=0:18446744073709551615 417assoc=2 418block_size=64 419forward_snoops=true 420hash_delay=1 421is_top_level=true 422latency=1000 423max_miss_count=0 424mshrs=10 425num_cpus=1 426prefetch_data_accesses_only=false 427prefetch_degree=1 428prefetch_latency=10000 429prefetch_on_access=false 430prefetch_past_page=false 431prefetch_policy=none 432prefetch_serial_squash=false 433prefetch_use_cpu_id=true 434prefetcher_size=100 435prioritizeRequests=false 436repl=Null 437size=131072 438subblock_size=0 439tgts_per_mshr=20 440trace_addr=0 441two_queue=false 442write_buffers=8 443cpu_side=system.cpu.icache_port 444mem_side=system.cpu.toL2Bus.port[0] 445 446[system.cpu.itb] 447type=X86TLB 448size=64 449 450[system.cpu.l2cache] 451type=BaseCache 452addr_range=0:18446744073709551615 453assoc=2 454block_size=64 455forward_snoops=true 456hash_delay=1 457is_top_level=false 458latency=1000 459max_miss_count=0 460mshrs=10 461num_cpus=1 462prefetch_data_accesses_only=false 463prefetch_degree=1 464prefetch_latency=10000 465prefetch_on_access=false 466prefetch_past_page=false 467prefetch_policy=none 468prefetch_serial_squash=false 469prefetch_use_cpu_id=true 470prefetcher_size=100 471prioritizeRequests=false 472repl=Null 473size=2097152 474subblock_size=0 475tgts_per_mshr=5 476trace_addr=0 477two_queue=false 478write_buffers=8 479cpu_side=system.cpu.toL2Bus.port[2] 480mem_side=system.membus.port[1] 481 482[system.cpu.toL2Bus] 483type=Bus 484block_size=64 485bus_id=0 486clock=1000 487header_cycles=1 488use_default_range=false 489width=64 490port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side 491 492[system.cpu.tracer] 493type=ExeTracer 494 495[system.cpu.workload] 496type=LiveProcess 497cmd=parser 2.1.dict -batch 498cwd=build/X86_SE/tests/opt/long/20.parser/x86/linux/o3-timing 499egid=100 500env= 501errout=cerr 502euid=100 503executable=/arm/scratch/sysexplr/dist/cpu2000/binaries/x86/linux/parser 504gid=100 505input=/arm/scratch/sysexplr/dist/cpu2000/data/parser/mdred/input/parser.in 506max_stack_size=67108864 507output=cout 508pid=100 509ppid=99 510simpoint=114600000000 511system=system 512uid=100 513 514[system.membus] 515type=Bus 516block_size=64 517bus_id=0 518clock=1000 519header_cycles=1 520use_default_range=false 521width=64 522port=system.physmem.port[0] system.cpu.l2cache.mem_side 523 524[system.physmem] 525type=PhysicalMemory 526file= 527latency=30000 528latency_var=0 529null=false 530range=0:134217727 531zero=false 532port=system.membus.port[0] 533 534