config.ini revision 7935
1[root] 2type=Root 3children=system 4time_sync_enable=false 5time_sync_period=100000000000 6time_sync_spin_threshold=100000000 7 8[system] 9type=System 10children=cpu membus physmem 11mem_mode=atomic 12physmem=system.physmem 13work_begin_ckpt_count=0 14work_begin_cpu_id_exit=-1 15work_begin_exit_count=0 16work_cpus_ckpt_count=0 17work_end_ckpt_count=0 18work_end_exit_count=0 19work_item_id=-1 20 21[system.cpu] 22type=DerivO3CPU 23children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload 24BTBEntries=4096 25BTBTagSize=16 26LFSTSize=1024 27LQEntries=32 28RASSize=16 29SQEntries=32 30SSITSize=1024 31activity=0 32backComSize=5 33cachePorts=200 34checker=Null 35choiceCtrBits=2 36choicePredictorSize=8192 37clock=500 38commitToDecodeDelay=1 39commitToFetchDelay=1 40commitToIEWDelay=1 41commitToRenameDelay=1 42commitWidth=8 43cpu_id=0 44decodeToFetchDelay=1 45decodeToRenameDelay=1 46decodeWidth=8 47defer_registration=false 48dispatchWidth=8 49do_checkpoint_insts=true 50do_statistics_insts=true 51dtb=system.cpu.dtb 52fetchToDecodeDelay=1 53fetchTrapLatency=1 54fetchWidth=8 55forwardComSize=5 56fuPool=system.cpu.fuPool 57function_trace=false 58function_trace_start=0 59globalCtrBits=2 60globalHistoryBits=13 61globalPredictorSize=8192 62iewToCommitDelay=1 63iewToDecodeDelay=1 64iewToFetchDelay=1 65iewToRenameDelay=1 66instShiftAmt=2 67issueToExecuteDelay=1 68issueWidth=8 69itb=system.cpu.itb 70localCtrBits=2 71localHistoryBits=11 72localHistoryTableSize=2048 73localPredictorSize=2048 74max_insts_all_threads=0 75max_insts_any_thread=0 76max_loads_all_threads=0 77max_loads_any_thread=0 78numIQEntries=64 79numPhysFloatRegs=256 80numPhysIntRegs=256 81numROBEntries=192 82numRobs=1 83numThreads=1 84phase=0 85predType=tournament 86progress_interval=0 87renameToDecodeDelay=1 88renameToFetchDelay=1 89renameToIEWDelay=2 90renameToROBDelay=1 91renameWidth=8 92smtCommitPolicy=RoundRobin 93smtFetchPolicy=SingleThread 94smtIQPolicy=Partitioned 95smtIQThreshold=100 96smtLSQPolicy=Partitioned 97smtLSQThreshold=100 98smtNumFetchingThreads=1 99smtROBPolicy=Partitioned 100smtROBThreshold=100 101squashWidth=8 102system=system 103tracer=system.cpu.tracer 104trapLatency=13 105wbDepth=1 106wbWidth=8 107workload=system.cpu.workload 108dcache_port=system.cpu.dcache.cpu_side 109icache_port=system.cpu.icache.cpu_side 110 111[system.cpu.dcache] 112type=BaseCache 113addr_range=0:18446744073709551615 114assoc=2 115block_size=64 116forward_snoops=true 117hash_delay=1 118latency=1000 119max_miss_count=0 120mshrs=10 121num_cpus=1 122prefetch_data_accesses_only=false 123prefetch_degree=1 124prefetch_latency=10000 125prefetch_on_access=false 126prefetch_past_page=false 127prefetch_policy=none 128prefetch_serial_squash=false 129prefetch_use_cpu_id=true 130prefetcher_size=100 131prioritizeRequests=false 132repl=Null 133size=262144 134subblock_size=0 135tgts_per_mshr=20 136trace_addr=0 137two_queue=false 138write_buffers=8 139cpu_side=system.cpu.dcache_port 140mem_side=system.cpu.toL2Bus.port[1] 141 142[system.cpu.dtb] 143type=X86TLB 144size=64 145 146[system.cpu.fuPool] 147type=FUPool 148children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 149FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 150 151[system.cpu.fuPool.FUList0] 152type=FUDesc 153children=opList 154count=6 155opList=system.cpu.fuPool.FUList0.opList 156 157[system.cpu.fuPool.FUList0.opList] 158type=OpDesc 159issueLat=1 160opClass=IntAlu 161opLat=1 162 163[system.cpu.fuPool.FUList1] 164type=FUDesc 165children=opList0 opList1 166count=2 167opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 168 169[system.cpu.fuPool.FUList1.opList0] 170type=OpDesc 171issueLat=1 172opClass=IntMult 173opLat=3 174 175[system.cpu.fuPool.FUList1.opList1] 176type=OpDesc 177issueLat=19 178opClass=IntDiv 179opLat=20 180 181[system.cpu.fuPool.FUList2] 182type=FUDesc 183children=opList0 opList1 opList2 184count=4 185opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 186 187[system.cpu.fuPool.FUList2.opList0] 188type=OpDesc 189issueLat=1 190opClass=FloatAdd 191opLat=2 192 193[system.cpu.fuPool.FUList2.opList1] 194type=OpDesc 195issueLat=1 196opClass=FloatCmp 197opLat=2 198 199[system.cpu.fuPool.FUList2.opList2] 200type=OpDesc 201issueLat=1 202opClass=FloatCvt 203opLat=2 204 205[system.cpu.fuPool.FUList3] 206type=FUDesc 207children=opList0 opList1 opList2 208count=2 209opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 210 211[system.cpu.fuPool.FUList3.opList0] 212type=OpDesc 213issueLat=1 214opClass=FloatMult 215opLat=4 216 217[system.cpu.fuPool.FUList3.opList1] 218type=OpDesc 219issueLat=12 220opClass=FloatDiv 221opLat=12 222 223[system.cpu.fuPool.FUList3.opList2] 224type=OpDesc 225issueLat=24 226opClass=FloatSqrt 227opLat=24 228 229[system.cpu.fuPool.FUList4] 230type=FUDesc 231children=opList 232count=0 233opList=system.cpu.fuPool.FUList4.opList 234 235[system.cpu.fuPool.FUList4.opList] 236type=OpDesc 237issueLat=1 238opClass=MemRead 239opLat=1 240 241[system.cpu.fuPool.FUList5] 242type=FUDesc 243children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 244count=4 245opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 246 247[system.cpu.fuPool.FUList5.opList00] 248type=OpDesc 249issueLat=1 250opClass=SimdAdd 251opLat=1 252 253[system.cpu.fuPool.FUList5.opList01] 254type=OpDesc 255issueLat=1 256opClass=SimdAddAcc 257opLat=1 258 259[system.cpu.fuPool.FUList5.opList02] 260type=OpDesc 261issueLat=1 262opClass=SimdAlu 263opLat=1 264 265[system.cpu.fuPool.FUList5.opList03] 266type=OpDesc 267issueLat=1 268opClass=SimdCmp 269opLat=1 270 271[system.cpu.fuPool.FUList5.opList04] 272type=OpDesc 273issueLat=1 274opClass=SimdCvt 275opLat=1 276 277[system.cpu.fuPool.FUList5.opList05] 278type=OpDesc 279issueLat=1 280opClass=SimdMisc 281opLat=1 282 283[system.cpu.fuPool.FUList5.opList06] 284type=OpDesc 285issueLat=1 286opClass=SimdMult 287opLat=1 288 289[system.cpu.fuPool.FUList5.opList07] 290type=OpDesc 291issueLat=1 292opClass=SimdMultAcc 293opLat=1 294 295[system.cpu.fuPool.FUList5.opList08] 296type=OpDesc 297issueLat=1 298opClass=SimdShift 299opLat=1 300 301[system.cpu.fuPool.FUList5.opList09] 302type=OpDesc 303issueLat=1 304opClass=SimdShiftAcc 305opLat=1 306 307[system.cpu.fuPool.FUList5.opList10] 308type=OpDesc 309issueLat=1 310opClass=SimdSqrt 311opLat=1 312 313[system.cpu.fuPool.FUList5.opList11] 314type=OpDesc 315issueLat=1 316opClass=SimdFloatAdd 317opLat=1 318 319[system.cpu.fuPool.FUList5.opList12] 320type=OpDesc 321issueLat=1 322opClass=SimdFloatAlu 323opLat=1 324 325[system.cpu.fuPool.FUList5.opList13] 326type=OpDesc 327issueLat=1 328opClass=SimdFloatCmp 329opLat=1 330 331[system.cpu.fuPool.FUList5.opList14] 332type=OpDesc 333issueLat=1 334opClass=SimdFloatCvt 335opLat=1 336 337[system.cpu.fuPool.FUList5.opList15] 338type=OpDesc 339issueLat=1 340opClass=SimdFloatDiv 341opLat=1 342 343[system.cpu.fuPool.FUList5.opList16] 344type=OpDesc 345issueLat=1 346opClass=SimdFloatMisc 347opLat=1 348 349[system.cpu.fuPool.FUList5.opList17] 350type=OpDesc 351issueLat=1 352opClass=SimdFloatMult 353opLat=1 354 355[system.cpu.fuPool.FUList5.opList18] 356type=OpDesc 357issueLat=1 358opClass=SimdFloatMultAcc 359opLat=1 360 361[system.cpu.fuPool.FUList5.opList19] 362type=OpDesc 363issueLat=1 364opClass=SimdFloatSqrt 365opLat=1 366 367[system.cpu.fuPool.FUList6] 368type=FUDesc 369children=opList 370count=0 371opList=system.cpu.fuPool.FUList6.opList 372 373[system.cpu.fuPool.FUList6.opList] 374type=OpDesc 375issueLat=1 376opClass=MemWrite 377opLat=1 378 379[system.cpu.fuPool.FUList7] 380type=FUDesc 381children=opList0 opList1 382count=4 383opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 384 385[system.cpu.fuPool.FUList7.opList0] 386type=OpDesc 387issueLat=1 388opClass=MemRead 389opLat=1 390 391[system.cpu.fuPool.FUList7.opList1] 392type=OpDesc 393issueLat=1 394opClass=MemWrite 395opLat=1 396 397[system.cpu.fuPool.FUList8] 398type=FUDesc 399children=opList 400count=1 401opList=system.cpu.fuPool.FUList8.opList 402 403[system.cpu.fuPool.FUList8.opList] 404type=OpDesc 405issueLat=3 406opClass=IprAccess 407opLat=3 408 409[system.cpu.icache] 410type=BaseCache 411addr_range=0:18446744073709551615 412assoc=2 413block_size=64 414forward_snoops=true 415hash_delay=1 416latency=1000 417max_miss_count=0 418mshrs=10 419num_cpus=1 420prefetch_data_accesses_only=false 421prefetch_degree=1 422prefetch_latency=10000 423prefetch_on_access=false 424prefetch_past_page=false 425prefetch_policy=none 426prefetch_serial_squash=false 427prefetch_use_cpu_id=true 428prefetcher_size=100 429prioritizeRequests=false 430repl=Null 431size=131072 432subblock_size=0 433tgts_per_mshr=20 434trace_addr=0 435two_queue=false 436write_buffers=8 437cpu_side=system.cpu.icache_port 438mem_side=system.cpu.toL2Bus.port[0] 439 440[system.cpu.itb] 441type=X86TLB 442size=64 443 444[system.cpu.l2cache] 445type=BaseCache 446addr_range=0:18446744073709551615 447assoc=2 448block_size=64 449forward_snoops=true 450hash_delay=1 451latency=1000 452max_miss_count=0 453mshrs=10 454num_cpus=1 455prefetch_data_accesses_only=false 456prefetch_degree=1 457prefetch_latency=10000 458prefetch_on_access=false 459prefetch_past_page=false 460prefetch_policy=none 461prefetch_serial_squash=false 462prefetch_use_cpu_id=true 463prefetcher_size=100 464prioritizeRequests=false 465repl=Null 466size=2097152 467subblock_size=0 468tgts_per_mshr=5 469trace_addr=0 470two_queue=false 471write_buffers=8 472cpu_side=system.cpu.toL2Bus.port[2] 473mem_side=system.membus.port[1] 474 475[system.cpu.toL2Bus] 476type=Bus 477block_size=64 478bus_id=0 479clock=1000 480header_cycles=1 481use_default_range=false 482width=64 483port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side 484 485[system.cpu.tracer] 486type=ExeTracer 487 488[system.cpu.workload] 489type=LiveProcess 490cmd=parser 2.1.dict -batch 491cwd=build/X86_SE/tests/fast/long/20.parser/x86/linux/o3-timing 492egid=100 493env= 494errout=cerr 495euid=100 496executable=/dist/m5/cpu2000/binaries/x86/linux/parser 497gid=100 498input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in 499max_stack_size=67108864 500output=cout 501pid=100 502ppid=99 503simpoint=114600000000 504system=system 505uid=100 506 507[system.membus] 508type=Bus 509block_size=64 510bus_id=0 511clock=1000 512header_cycles=1 513use_default_range=false 514width=64 515port=system.physmem.port[0] system.cpu.l2cache.mem_side 516 517[system.physmem] 518type=PhysicalMemory 519file= 520latency=30000 521latency_var=0 522null=false 523range=0:134217727 524zero=false 525port=system.membus.port[0] 526 527