config.ini revision 7893
1[root] 2type=Root 3children=system 4time_sync_enable=false 5time_sync_period=100000000000 6time_sync_spin_threshold=100000000 7 8[system] 9type=System 10children=cpu membus physmem 11mem_mode=atomic 12physmem=system.physmem 13 14[system.cpu] 15type=DerivO3CPU 16children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload 17BTBEntries=4096 18BTBTagSize=16 19LFSTSize=1024 20LQEntries=32 21RASSize=16 22SQEntries=32 23SSITSize=1024 24activity=0 25backComSize=5 26cachePorts=200 27checker=Null 28choiceCtrBits=2 29choicePredictorSize=8192 30clock=500 31commitToDecodeDelay=1 32commitToFetchDelay=1 33commitToIEWDelay=1 34commitToRenameDelay=1 35commitWidth=8 36cpu_id=0 37decodeToFetchDelay=1 38decodeToRenameDelay=1 39decodeWidth=8 40defer_registration=false 41dispatchWidth=8 42do_checkpoint_insts=true 43do_statistics_insts=true 44dtb=system.cpu.dtb 45fetchToDecodeDelay=1 46fetchTrapLatency=1 47fetchWidth=8 48forwardComSize=5 49fuPool=system.cpu.fuPool 50function_trace=false 51function_trace_start=0 52globalCtrBits=2 53globalHistoryBits=13 54globalPredictorSize=8192 55iewToCommitDelay=1 56iewToDecodeDelay=1 57iewToFetchDelay=1 58iewToRenameDelay=1 59instShiftAmt=2 60issueToExecuteDelay=1 61issueWidth=8 62itb=system.cpu.itb 63localCtrBits=2 64localHistoryBits=11 65localHistoryTableSize=2048 66localPredictorSize=2048 67max_insts_all_threads=0 68max_insts_any_thread=0 69max_loads_all_threads=0 70max_loads_any_thread=0 71numIQEntries=64 72numPhysFloatRegs=256 73numPhysIntRegs=256 74numROBEntries=192 75numRobs=1 76numThreads=1 77phase=0 78predType=tournament 79progress_interval=0 80renameToDecodeDelay=1 81renameToFetchDelay=1 82renameToIEWDelay=2 83renameToROBDelay=1 84renameWidth=8 85smtCommitPolicy=RoundRobin 86smtFetchPolicy=SingleThread 87smtIQPolicy=Partitioned 88smtIQThreshold=100 89smtLSQPolicy=Partitioned 90smtLSQThreshold=100 91smtNumFetchingThreads=1 92smtROBPolicy=Partitioned 93smtROBThreshold=100 94squashWidth=8 95system=system 96tracer=system.cpu.tracer 97trapLatency=13 98wbDepth=1 99wbWidth=8 100workload=system.cpu.workload 101dcache_port=system.cpu.dcache.cpu_side 102icache_port=system.cpu.icache.cpu_side 103 104[system.cpu.dcache] 105type=BaseCache 106addr_range=0:18446744073709551615 107assoc=2 108block_size=64 109forward_snoops=true 110hash_delay=1 111latency=1000 112max_miss_count=0 113mshrs=10 114num_cpus=1 115prefetch_data_accesses_only=false 116prefetch_degree=1 117prefetch_latency=10000 118prefetch_on_access=false 119prefetch_past_page=false 120prefetch_policy=none 121prefetch_serial_squash=false 122prefetch_use_cpu_id=true 123prefetcher_size=100 124prioritizeRequests=false 125repl=Null 126size=262144 127subblock_size=0 128tgts_per_mshr=20 129trace_addr=0 130two_queue=false 131write_buffers=8 132cpu_side=system.cpu.dcache_port 133mem_side=system.cpu.toL2Bus.port[1] 134 135[system.cpu.dtb] 136type=X86TLB 137size=64 138 139[system.cpu.fuPool] 140type=FUPool 141children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 142FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 143 144[system.cpu.fuPool.FUList0] 145type=FUDesc 146children=opList 147count=6 148opList=system.cpu.fuPool.FUList0.opList 149 150[system.cpu.fuPool.FUList0.opList] 151type=OpDesc 152issueLat=1 153opClass=IntAlu 154opLat=1 155 156[system.cpu.fuPool.FUList1] 157type=FUDesc 158children=opList0 opList1 159count=2 160opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 161 162[system.cpu.fuPool.FUList1.opList0] 163type=OpDesc 164issueLat=1 165opClass=IntMult 166opLat=3 167 168[system.cpu.fuPool.FUList1.opList1] 169type=OpDesc 170issueLat=19 171opClass=IntDiv 172opLat=20 173 174[system.cpu.fuPool.FUList2] 175type=FUDesc 176children=opList0 opList1 opList2 177count=4 178opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 179 180[system.cpu.fuPool.FUList2.opList0] 181type=OpDesc 182issueLat=1 183opClass=FloatAdd 184opLat=2 185 186[system.cpu.fuPool.FUList2.opList1] 187type=OpDesc 188issueLat=1 189opClass=FloatCmp 190opLat=2 191 192[system.cpu.fuPool.FUList2.opList2] 193type=OpDesc 194issueLat=1 195opClass=FloatCvt 196opLat=2 197 198[system.cpu.fuPool.FUList3] 199type=FUDesc 200children=opList0 opList1 opList2 201count=2 202opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 203 204[system.cpu.fuPool.FUList3.opList0] 205type=OpDesc 206issueLat=1 207opClass=FloatMult 208opLat=4 209 210[system.cpu.fuPool.FUList3.opList1] 211type=OpDesc 212issueLat=12 213opClass=FloatDiv 214opLat=12 215 216[system.cpu.fuPool.FUList3.opList2] 217type=OpDesc 218issueLat=24 219opClass=FloatSqrt 220opLat=24 221 222[system.cpu.fuPool.FUList4] 223type=FUDesc 224children=opList 225count=0 226opList=system.cpu.fuPool.FUList4.opList 227 228[system.cpu.fuPool.FUList4.opList] 229type=OpDesc 230issueLat=1 231opClass=MemRead 232opLat=1 233 234[system.cpu.fuPool.FUList5] 235type=FUDesc 236children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 237count=4 238opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 239 240[system.cpu.fuPool.FUList5.opList00] 241type=OpDesc 242issueLat=1 243opClass=SimdAdd 244opLat=1 245 246[system.cpu.fuPool.FUList5.opList01] 247type=OpDesc 248issueLat=1 249opClass=SimdAddAcc 250opLat=1 251 252[system.cpu.fuPool.FUList5.opList02] 253type=OpDesc 254issueLat=1 255opClass=SimdAlu 256opLat=1 257 258[system.cpu.fuPool.FUList5.opList03] 259type=OpDesc 260issueLat=1 261opClass=SimdCmp 262opLat=1 263 264[system.cpu.fuPool.FUList5.opList04] 265type=OpDesc 266issueLat=1 267opClass=SimdCvt 268opLat=1 269 270[system.cpu.fuPool.FUList5.opList05] 271type=OpDesc 272issueLat=1 273opClass=SimdMisc 274opLat=1 275 276[system.cpu.fuPool.FUList5.opList06] 277type=OpDesc 278issueLat=1 279opClass=SimdMult 280opLat=1 281 282[system.cpu.fuPool.FUList5.opList07] 283type=OpDesc 284issueLat=1 285opClass=SimdMultAcc 286opLat=1 287 288[system.cpu.fuPool.FUList5.opList08] 289type=OpDesc 290issueLat=1 291opClass=SimdShift 292opLat=1 293 294[system.cpu.fuPool.FUList5.opList09] 295type=OpDesc 296issueLat=1 297opClass=SimdShiftAcc 298opLat=1 299 300[system.cpu.fuPool.FUList5.opList10] 301type=OpDesc 302issueLat=1 303opClass=SimdSqrt 304opLat=1 305 306[system.cpu.fuPool.FUList5.opList11] 307type=OpDesc 308issueLat=1 309opClass=SimdFloatAdd 310opLat=1 311 312[system.cpu.fuPool.FUList5.opList12] 313type=OpDesc 314issueLat=1 315opClass=SimdFloatAlu 316opLat=1 317 318[system.cpu.fuPool.FUList5.opList13] 319type=OpDesc 320issueLat=1 321opClass=SimdFloatCmp 322opLat=1 323 324[system.cpu.fuPool.FUList5.opList14] 325type=OpDesc 326issueLat=1 327opClass=SimdFloatCvt 328opLat=1 329 330[system.cpu.fuPool.FUList5.opList15] 331type=OpDesc 332issueLat=1 333opClass=SimdFloatDiv 334opLat=1 335 336[system.cpu.fuPool.FUList5.opList16] 337type=OpDesc 338issueLat=1 339opClass=SimdFloatMisc 340opLat=1 341 342[system.cpu.fuPool.FUList5.opList17] 343type=OpDesc 344issueLat=1 345opClass=SimdFloatMult 346opLat=1 347 348[system.cpu.fuPool.FUList5.opList18] 349type=OpDesc 350issueLat=1 351opClass=SimdFloatMultAcc 352opLat=1 353 354[system.cpu.fuPool.FUList5.opList19] 355type=OpDesc 356issueLat=1 357opClass=SimdFloatSqrt 358opLat=1 359 360[system.cpu.fuPool.FUList6] 361type=FUDesc 362children=opList 363count=0 364opList=system.cpu.fuPool.FUList6.opList 365 366[system.cpu.fuPool.FUList6.opList] 367type=OpDesc 368issueLat=1 369opClass=MemWrite 370opLat=1 371 372[system.cpu.fuPool.FUList7] 373type=FUDesc 374children=opList0 opList1 375count=4 376opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 377 378[system.cpu.fuPool.FUList7.opList0] 379type=OpDesc 380issueLat=1 381opClass=MemRead 382opLat=1 383 384[system.cpu.fuPool.FUList7.opList1] 385type=OpDesc 386issueLat=1 387opClass=MemWrite 388opLat=1 389 390[system.cpu.fuPool.FUList8] 391type=FUDesc 392children=opList 393count=1 394opList=system.cpu.fuPool.FUList8.opList 395 396[system.cpu.fuPool.FUList8.opList] 397type=OpDesc 398issueLat=3 399opClass=IprAccess 400opLat=3 401 402[system.cpu.icache] 403type=BaseCache 404addr_range=0:18446744073709551615 405assoc=2 406block_size=64 407forward_snoops=true 408hash_delay=1 409latency=1000 410max_miss_count=0 411mshrs=10 412num_cpus=1 413prefetch_data_accesses_only=false 414prefetch_degree=1 415prefetch_latency=10000 416prefetch_on_access=false 417prefetch_past_page=false 418prefetch_policy=none 419prefetch_serial_squash=false 420prefetch_use_cpu_id=true 421prefetcher_size=100 422prioritizeRequests=false 423repl=Null 424size=131072 425subblock_size=0 426tgts_per_mshr=20 427trace_addr=0 428two_queue=false 429write_buffers=8 430cpu_side=system.cpu.icache_port 431mem_side=system.cpu.toL2Bus.port[0] 432 433[system.cpu.itb] 434type=X86TLB 435size=64 436 437[system.cpu.l2cache] 438type=BaseCache 439addr_range=0:18446744073709551615 440assoc=2 441block_size=64 442forward_snoops=true 443hash_delay=1 444latency=1000 445max_miss_count=0 446mshrs=10 447num_cpus=1 448prefetch_data_accesses_only=false 449prefetch_degree=1 450prefetch_latency=10000 451prefetch_on_access=false 452prefetch_past_page=false 453prefetch_policy=none 454prefetch_serial_squash=false 455prefetch_use_cpu_id=true 456prefetcher_size=100 457prioritizeRequests=false 458repl=Null 459size=2097152 460subblock_size=0 461tgts_per_mshr=5 462trace_addr=0 463two_queue=false 464write_buffers=8 465cpu_side=system.cpu.toL2Bus.port[2] 466mem_side=system.membus.port[1] 467 468[system.cpu.toL2Bus] 469type=Bus 470block_size=64 471bus_id=0 472clock=1000 473header_cycles=1 474use_default_range=false 475width=64 476port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side 477 478[system.cpu.tracer] 479type=ExeTracer 480 481[system.cpu.workload] 482type=LiveProcess 483cmd=parser 2.1.dict -batch 484cwd=build/X86_SE/tests/opt/long/20.parser/x86/linux/o3-timing 485egid=100 486env= 487errout=cerr 488euid=100 489executable=/dist/m5/cpu2000/binaries/x86/linux/parser 490gid=100 491input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in 492max_stack_size=67108864 493output=cout 494pid=100 495ppid=99 496simpoint=114600000000 497system=system 498uid=100 499 500[system.membus] 501type=Bus 502block_size=64 503bus_id=0 504clock=1000 505header_cycles=1 506use_default_range=false 507width=64 508port=system.physmem.port[0] system.cpu.l2cache.mem_side 509 510[system.physmem] 511type=PhysicalMemory 512file= 513latency=30000 514latency_var=0 515null=false 516range=0:134217727 517zero=false 518port=system.membus.port[0] 519 520