config.ini revision 10242
110515SAli.Saidi@ARM.com[root] 210515SAli.Saidi@ARM.comtype=Root 310515SAli.Saidi@ARM.comchildren=system 410515SAli.Saidi@ARM.comeventq_index=0 510515SAli.Saidi@ARM.comfull_system=false 610515SAli.Saidi@ARM.comsim_quantum=0 711014Sandreas.sandberg@arm.comtime_sync_enable=false 810515SAli.Saidi@ARM.comtime_sync_period=100000000000 910515SAli.Saidi@ARM.comtime_sync_spin_threshold=100000000 1011014Sandreas.sandberg@arm.com 1111014Sandreas.sandberg@arm.com[system] 1210515SAli.Saidi@ARM.comtype=System 1310515SAli.Saidi@ARM.comchildren=clk_domain cpu cpu_clk_domain membus physmem voltage_domain 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain 17eventq_index=0 18init_param=0 19kernel= 20load_addr_mask=1099511627775 21load_offset=0 22mem_mode=timing 23mem_ranges= 24memories=system.physmem 25num_work_ids=16 26readfile= 27symbolfile= 28work_begin_ckpt_count=0 29work_begin_cpu_id_exit=-1 30work_begin_exit_count=0 31work_cpus_ckpt_count=0 32work_end_ckpt_count=0 33work_end_exit_count=0 34work_item_id=-1 35system_port=system.membus.slave[0] 36 37[system.clk_domain] 38type=SrcClockDomain 39clock=1000 40eventq_index=0 41voltage_domain=system.voltage_domain 42 43[system.cpu] 44type=DerivO3CPU 45children=apic_clk_domain branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload 46LFSTSize=1024 47LQEntries=32 48LSQCheckLoads=true 49LSQDepCheckShift=4 50SQEntries=32 51SSITSize=1024 52activity=0 53backComSize=5 54branchPred=system.cpu.branchPred 55cachePorts=200 56checker=Null 57clk_domain=system.cpu_clk_domain 58commitToDecodeDelay=1 59commitToFetchDelay=1 60commitToIEWDelay=1 61commitToRenameDelay=1 62commitWidth=8 63cpu_id=0 64decodeToFetchDelay=1 65decodeToRenameDelay=1 66decodeWidth=8 67dispatchWidth=8 68do_checkpoint_insts=true 69do_quiesce=true 70do_statistics_insts=true 71dtb=system.cpu.dtb 72eventq_index=0 73fetchBufferSize=64 74fetchToDecodeDelay=1 75fetchTrapLatency=1 76fetchWidth=8 77forwardComSize=5 78fuPool=system.cpu.fuPool 79function_trace=false 80function_trace_start=0 81iewToCommitDelay=1 82iewToDecodeDelay=1 83iewToFetchDelay=1 84iewToRenameDelay=1 85interrupts=system.cpu.interrupts 86isa=system.cpu.isa 87issueToExecuteDelay=1 88issueWidth=8 89itb=system.cpu.itb 90max_insts_all_threads=0 91max_insts_any_thread=0 92max_loads_all_threads=0 93max_loads_any_thread=0 94needsTSO=true 95numIQEntries=64 96numPhysCCRegs=1280 97numPhysFloatRegs=256 98numPhysIntRegs=256 99numROBEntries=192 100numRobs=1 101numThreads=1 102profile=0 103progress_interval=0 104renameToDecodeDelay=1 105renameToFetchDelay=1 106renameToIEWDelay=2 107renameToROBDelay=1 108renameWidth=8 109simpoint_start_insts= 110smtCommitPolicy=RoundRobin 111smtFetchPolicy=SingleThread 112smtIQPolicy=Partitioned 113smtIQThreshold=100 114smtLSQPolicy=Partitioned 115smtLSQThreshold=100 116smtNumFetchingThreads=1 117smtROBPolicy=Partitioned 118smtROBThreshold=100 119socket_id=0 120squashWidth=8 121store_set_clear_period=250000 122switched_out=false 123system=system 124tracer=system.cpu.tracer 125trapLatency=13 126wbDepth=1 127wbWidth=8 128workload=system.cpu.workload 129dcache_port=system.cpu.dcache.cpu_side 130icache_port=system.cpu.icache.cpu_side 131 132[system.cpu.apic_clk_domain] 133type=DerivedClockDomain 134clk_divider=16 135clk_domain=system.cpu_clk_domain 136eventq_index=0 137 138[system.cpu.branchPred] 139type=BranchPredictor 140BTBEntries=4096 141BTBTagSize=16 142RASSize=16 143choiceCtrBits=2 144choicePredictorSize=8192 145eventq_index=0 146globalCtrBits=2 147globalPredictorSize=8192 148instShiftAmt=2 149localCtrBits=2 150localHistoryTableSize=2048 151localPredictorSize=2048 152numThreads=1 153predType=tournament 154 155[system.cpu.dcache] 156type=BaseCache 157children=tags 158addr_ranges=0:18446744073709551615 159assoc=2 160clk_domain=system.cpu_clk_domain 161eventq_index=0 162forward_snoops=true 163hit_latency=2 164is_top_level=true 165max_miss_count=0 166mshrs=4 167prefetch_on_access=false 168prefetcher=Null 169response_latency=2 170sequential_access=false 171size=262144 172system=system 173tags=system.cpu.dcache.tags 174tgts_per_mshr=20 175two_queue=false 176write_buffers=8 177cpu_side=system.cpu.dcache_port 178mem_side=system.cpu.toL2Bus.slave[1] 179 180[system.cpu.dcache.tags] 181type=LRU 182assoc=2 183block_size=64 184clk_domain=system.cpu_clk_domain 185eventq_index=0 186hit_latency=2 187sequential_access=false 188size=262144 189 190[system.cpu.dtb] 191type=X86TLB 192children=walker 193eventq_index=0 194size=64 195walker=system.cpu.dtb.walker 196 197[system.cpu.dtb.walker] 198type=X86PagetableWalker 199clk_domain=system.cpu_clk_domain 200eventq_index=0 201num_squash_per_cycle=4 202system=system 203port=system.cpu.toL2Bus.slave[3] 204 205[system.cpu.fuPool] 206type=FUPool 207children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 208FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 209eventq_index=0 210 211[system.cpu.fuPool.FUList0] 212type=FUDesc 213children=opList 214count=6 215eventq_index=0 216opList=system.cpu.fuPool.FUList0.opList 217 218[system.cpu.fuPool.FUList0.opList] 219type=OpDesc 220eventq_index=0 221issueLat=1 222opClass=IntAlu 223opLat=1 224 225[system.cpu.fuPool.FUList1] 226type=FUDesc 227children=opList0 opList1 228count=2 229eventq_index=0 230opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 231 232[system.cpu.fuPool.FUList1.opList0] 233type=OpDesc 234eventq_index=0 235issueLat=1 236opClass=IntMult 237opLat=3 238 239[system.cpu.fuPool.FUList1.opList1] 240type=OpDesc 241eventq_index=0 242issueLat=19 243opClass=IntDiv 244opLat=20 245 246[system.cpu.fuPool.FUList2] 247type=FUDesc 248children=opList0 opList1 opList2 249count=4 250eventq_index=0 251opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 252 253[system.cpu.fuPool.FUList2.opList0] 254type=OpDesc 255eventq_index=0 256issueLat=1 257opClass=FloatAdd 258opLat=2 259 260[system.cpu.fuPool.FUList2.opList1] 261type=OpDesc 262eventq_index=0 263issueLat=1 264opClass=FloatCmp 265opLat=2 266 267[system.cpu.fuPool.FUList2.opList2] 268type=OpDesc 269eventq_index=0 270issueLat=1 271opClass=FloatCvt 272opLat=2 273 274[system.cpu.fuPool.FUList3] 275type=FUDesc 276children=opList0 opList1 opList2 277count=2 278eventq_index=0 279opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 280 281[system.cpu.fuPool.FUList3.opList0] 282type=OpDesc 283eventq_index=0 284issueLat=1 285opClass=FloatMult 286opLat=4 287 288[system.cpu.fuPool.FUList3.opList1] 289type=OpDesc 290eventq_index=0 291issueLat=12 292opClass=FloatDiv 293opLat=12 294 295[system.cpu.fuPool.FUList3.opList2] 296type=OpDesc 297eventq_index=0 298issueLat=24 299opClass=FloatSqrt 300opLat=24 301 302[system.cpu.fuPool.FUList4] 303type=FUDesc 304children=opList 305count=0 306eventq_index=0 307opList=system.cpu.fuPool.FUList4.opList 308 309[system.cpu.fuPool.FUList4.opList] 310type=OpDesc 311eventq_index=0 312issueLat=1 313opClass=MemRead 314opLat=1 315 316[system.cpu.fuPool.FUList5] 317type=FUDesc 318children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 319count=4 320eventq_index=0 321opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 322 323[system.cpu.fuPool.FUList5.opList00] 324type=OpDesc 325eventq_index=0 326issueLat=1 327opClass=SimdAdd 328opLat=1 329 330[system.cpu.fuPool.FUList5.opList01] 331type=OpDesc 332eventq_index=0 333issueLat=1 334opClass=SimdAddAcc 335opLat=1 336 337[system.cpu.fuPool.FUList5.opList02] 338type=OpDesc 339eventq_index=0 340issueLat=1 341opClass=SimdAlu 342opLat=1 343 344[system.cpu.fuPool.FUList5.opList03] 345type=OpDesc 346eventq_index=0 347issueLat=1 348opClass=SimdCmp 349opLat=1 350 351[system.cpu.fuPool.FUList5.opList04] 352type=OpDesc 353eventq_index=0 354issueLat=1 355opClass=SimdCvt 356opLat=1 357 358[system.cpu.fuPool.FUList5.opList05] 359type=OpDesc 360eventq_index=0 361issueLat=1 362opClass=SimdMisc 363opLat=1 364 365[system.cpu.fuPool.FUList5.opList06] 366type=OpDesc 367eventq_index=0 368issueLat=1 369opClass=SimdMult 370opLat=1 371 372[system.cpu.fuPool.FUList5.opList07] 373type=OpDesc 374eventq_index=0 375issueLat=1 376opClass=SimdMultAcc 377opLat=1 378 379[system.cpu.fuPool.FUList5.opList08] 380type=OpDesc 381eventq_index=0 382issueLat=1 383opClass=SimdShift 384opLat=1 385 386[system.cpu.fuPool.FUList5.opList09] 387type=OpDesc 388eventq_index=0 389issueLat=1 390opClass=SimdShiftAcc 391opLat=1 392 393[system.cpu.fuPool.FUList5.opList10] 394type=OpDesc 395eventq_index=0 396issueLat=1 397opClass=SimdSqrt 398opLat=1 399 400[system.cpu.fuPool.FUList5.opList11] 401type=OpDesc 402eventq_index=0 403issueLat=1 404opClass=SimdFloatAdd 405opLat=1 406 407[system.cpu.fuPool.FUList5.opList12] 408type=OpDesc 409eventq_index=0 410issueLat=1 411opClass=SimdFloatAlu 412opLat=1 413 414[system.cpu.fuPool.FUList5.opList13] 415type=OpDesc 416eventq_index=0 417issueLat=1 418opClass=SimdFloatCmp 419opLat=1 420 421[system.cpu.fuPool.FUList5.opList14] 422type=OpDesc 423eventq_index=0 424issueLat=1 425opClass=SimdFloatCvt 426opLat=1 427 428[system.cpu.fuPool.FUList5.opList15] 429type=OpDesc 430eventq_index=0 431issueLat=1 432opClass=SimdFloatDiv 433opLat=1 434 435[system.cpu.fuPool.FUList5.opList16] 436type=OpDesc 437eventq_index=0 438issueLat=1 439opClass=SimdFloatMisc 440opLat=1 441 442[system.cpu.fuPool.FUList5.opList17] 443type=OpDesc 444eventq_index=0 445issueLat=1 446opClass=SimdFloatMult 447opLat=1 448 449[system.cpu.fuPool.FUList5.opList18] 450type=OpDesc 451eventq_index=0 452issueLat=1 453opClass=SimdFloatMultAcc 454opLat=1 455 456[system.cpu.fuPool.FUList5.opList19] 457type=OpDesc 458eventq_index=0 459issueLat=1 460opClass=SimdFloatSqrt 461opLat=1 462 463[system.cpu.fuPool.FUList6] 464type=FUDesc 465children=opList 466count=0 467eventq_index=0 468opList=system.cpu.fuPool.FUList6.opList 469 470[system.cpu.fuPool.FUList6.opList] 471type=OpDesc 472eventq_index=0 473issueLat=1 474opClass=MemWrite 475opLat=1 476 477[system.cpu.fuPool.FUList7] 478type=FUDesc 479children=opList0 opList1 480count=4 481eventq_index=0 482opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 483 484[system.cpu.fuPool.FUList7.opList0] 485type=OpDesc 486eventq_index=0 487issueLat=1 488opClass=MemRead 489opLat=1 490 491[system.cpu.fuPool.FUList7.opList1] 492type=OpDesc 493eventq_index=0 494issueLat=1 495opClass=MemWrite 496opLat=1 497 498[system.cpu.fuPool.FUList8] 499type=FUDesc 500children=opList 501count=1 502eventq_index=0 503opList=system.cpu.fuPool.FUList8.opList 504 505[system.cpu.fuPool.FUList8.opList] 506type=OpDesc 507eventq_index=0 508issueLat=3 509opClass=IprAccess 510opLat=3 511 512[system.cpu.icache] 513type=BaseCache 514children=tags 515addr_ranges=0:18446744073709551615 516assoc=2 517clk_domain=system.cpu_clk_domain 518eventq_index=0 519forward_snoops=true 520hit_latency=2 521is_top_level=true 522max_miss_count=0 523mshrs=4 524prefetch_on_access=false 525prefetcher=Null 526response_latency=2 527sequential_access=false 528size=131072 529system=system 530tags=system.cpu.icache.tags 531tgts_per_mshr=20 532two_queue=false 533write_buffers=8 534cpu_side=system.cpu.icache_port 535mem_side=system.cpu.toL2Bus.slave[0] 536 537[system.cpu.icache.tags] 538type=LRU 539assoc=2 540block_size=64 541clk_domain=system.cpu_clk_domain 542eventq_index=0 543hit_latency=2 544sequential_access=false 545size=131072 546 547[system.cpu.interrupts] 548type=X86LocalApic 549clk_domain=system.cpu.apic_clk_domain 550eventq_index=0 551int_latency=1000 552pio_addr=2305843009213693952 553pio_latency=100000 554system=system 555int_master=system.membus.slave[2] 556int_slave=system.membus.master[2] 557pio=system.membus.master[1] 558 559[system.cpu.isa] 560type=X86ISA 561eventq_index=0 562 563[system.cpu.itb] 564type=X86TLB 565children=walker 566eventq_index=0 567size=64 568walker=system.cpu.itb.walker 569 570[system.cpu.itb.walker] 571type=X86PagetableWalker 572clk_domain=system.cpu_clk_domain 573eventq_index=0 574num_squash_per_cycle=4 575system=system 576port=system.cpu.toL2Bus.slave[2] 577 578[system.cpu.l2cache] 579type=BaseCache 580children=tags 581addr_ranges=0:18446744073709551615 582assoc=8 583clk_domain=system.cpu_clk_domain 584eventq_index=0 585forward_snoops=true 586hit_latency=20 587is_top_level=false 588max_miss_count=0 589mshrs=20 590prefetch_on_access=false 591prefetcher=Null 592response_latency=20 593sequential_access=false 594size=2097152 595system=system 596tags=system.cpu.l2cache.tags 597tgts_per_mshr=12 598two_queue=false 599write_buffers=8 600cpu_side=system.cpu.toL2Bus.master[0] 601mem_side=system.membus.slave[1] 602 603[system.cpu.l2cache.tags] 604type=LRU 605assoc=8 606block_size=64 607clk_domain=system.cpu_clk_domain 608eventq_index=0 609hit_latency=20 610sequential_access=false 611size=2097152 612 613[system.cpu.toL2Bus] 614type=CoherentBus 615clk_domain=system.cpu_clk_domain 616eventq_index=0 617header_cycles=1 618system=system 619use_default_range=false 620width=32 621master=system.cpu.l2cache.cpu_side 622slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port 623 624[system.cpu.tracer] 625type=ExeTracer 626eventq_index=0 627 628[system.cpu.workload] 629type=LiveProcess 630cmd=parser 2.1.dict -batch 631cwd=build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing 632egid=100 633env= 634errout=cerr 635euid=100 636eventq_index=0 637executable=/home/stever/m5/dist/cpu2000/binaries/x86/linux/parser 638gid=100 639input=/home/stever/m5/dist/cpu2000/data/parser/mdred/input/parser.in 640max_stack_size=67108864 641output=cout 642pid=100 643ppid=99 644simpoint=114600000000 645system=system 646uid=100 647 648[system.cpu_clk_domain] 649type=SrcClockDomain 650clock=500 651eventq_index=0 652voltage_domain=system.voltage_domain 653 654[system.membus] 655type=CoherentBus 656clk_domain=system.clk_domain 657eventq_index=0 658header_cycles=1 659system=system 660use_default_range=false 661width=8 662master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave 663slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master 664 665[system.physmem] 666type=DRAMCtrl 667activation_limit=4 668addr_mapping=RoRaBaChCo 669banks_per_rank=8 670burst_length=8 671channels=1 672clk_domain=system.clk_domain 673conf_table_reported=true 674device_bus_width=8 675device_rowbuffer_size=1024 676devices_per_rank=8 677eventq_index=0 678in_addr_map=true 679max_accesses_per_row=16 680mem_sched_policy=frfcfs 681min_writes_per_switch=16 682null=false 683page_policy=open_adaptive 684range=0:134217727 685ranks_per_channel=2 686read_buffer_size=32 687static_backend_latency=10000 688static_frontend_latency=10000 689tBURST=5000 690tCK=1250 691tCL=13750 692tRAS=35000 693tRCD=13750 694tREFI=7800000 695tRFC=260000 696tRP=13750 697tRRD=6000 698tRTP=7500 699tRTW=2500 700tWR=15000 701tWTR=7500 702tXAW=30000 703write_buffer_size=64 704write_high_thresh_perc=85 705write_low_thresh_perc=50 706port=system.membus.master[0] 707 708[system.voltage_domain] 709type=VoltageDomain 710eventq_index=0 711voltage=1.000000 712 713