stats.txt revision 8893:e29c604a2582
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.722234 # Number of seconds simulated 4sim_ticks 722234364000 # Number of ticks simulated 5final_tick 722234364000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 1812748 # Simulator instruction rate (inst/s) 8host_op_rate 2042661 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2592600297 # Simulator tick rate (ticks/s) 10host_mem_usage 228776 # Number of bytes of host memory used 11host_seconds 278.58 # Real time elapsed on the host 12sim_insts 504986861 # Number of instructions simulated 13sim_ops 569034848 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read 14797056 # Number of bytes read from this memory 15system.physmem.bytes_inst_read 188608 # Number of instructions bytes read from this memory 16system.physmem.bytes_written 11027328 # Number of bytes written to this memory 17system.physmem.num_reads 231204 # Number of read requests responded to by this memory 18system.physmem.num_writes 172302 # Number of write requests responded to by this memory 19system.physmem.num_other 0 # Number of other requests responded to by this memory 20system.physmem.bw_read 20487887 # Total read bandwidth from this memory (bytes/s) 21system.physmem.bw_inst_read 261145 # Instruction read bandwidth from this memory (bytes/s) 22system.physmem.bw_write 15268351 # Write bandwidth from this memory (bytes/s) 23system.physmem.bw_total 35756238 # Total bandwidth to/from this memory (bytes/s) 24system.cpu.dtb.inst_hits 0 # ITB inst hits 25system.cpu.dtb.inst_misses 0 # ITB inst misses 26system.cpu.dtb.read_hits 0 # DTB read hits 27system.cpu.dtb.read_misses 0 # DTB read misses 28system.cpu.dtb.write_hits 0 # DTB write hits 29system.cpu.dtb.write_misses 0 # DTB write misses 30system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 31system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 32system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 33system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 34system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 35system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 36system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 37system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 38system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 39system.cpu.dtb.read_accesses 0 # DTB read accesses 40system.cpu.dtb.write_accesses 0 # DTB write accesses 41system.cpu.dtb.inst_accesses 0 # ITB inst accesses 42system.cpu.dtb.hits 0 # DTB hits 43system.cpu.dtb.misses 0 # DTB misses 44system.cpu.dtb.accesses 0 # DTB accesses 45system.cpu.itb.inst_hits 0 # ITB inst hits 46system.cpu.itb.inst_misses 0 # ITB inst misses 47system.cpu.itb.read_hits 0 # DTB read hits 48system.cpu.itb.read_misses 0 # DTB read misses 49system.cpu.itb.write_hits 0 # DTB write hits 50system.cpu.itb.write_misses 0 # DTB write misses 51system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 52system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 53system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 54system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 55system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 56system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 57system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 58system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 59system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 60system.cpu.itb.read_accesses 0 # DTB read accesses 61system.cpu.itb.write_accesses 0 # DTB write accesses 62system.cpu.itb.inst_accesses 0 # ITB inst accesses 63system.cpu.itb.hits 0 # DTB hits 64system.cpu.itb.misses 0 # DTB misses 65system.cpu.itb.accesses 0 # DTB accesses 66system.cpu.workload.num_syscalls 548 # Number of system calls 67system.cpu.numCycles 1444468728 # number of cpu cycles simulated 68system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 69system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 70system.cpu.committedInsts 504986861 # Number of instructions committed 71system.cpu.committedOps 569034848 # Number of ops (including micro ops) committed 72system.cpu.num_int_alu_accesses 470727703 # Number of integer alu accesses 73system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses 74system.cpu.num_func_calls 15725605 # number of times a function call or return occured 75system.cpu.num_conditional_control_insts 98480815 # number of instructions that are conditional controls 76system.cpu.num_int_insts 470727703 # number of integer instructions 77system.cpu.num_fp_insts 16 # number of float instructions 78system.cpu.num_int_register_reads 2844375220 # number of times the integer registers were read 79system.cpu.num_int_register_writes 646169365 # number of times the integer registers were written 80system.cpu.num_fp_register_reads 16 # number of times the floating registers were read 81system.cpu.num_fp_register_writes 0 # number of times the floating registers were written 82system.cpu.num_mem_refs 182890035 # number of memory refs 83system.cpu.num_load_insts 126029556 # Number of load instructions 84system.cpu.num_store_insts 56860479 # Number of store instructions 85system.cpu.num_idle_cycles 0 # Number of idle cycles 86system.cpu.num_busy_cycles 1444468728 # Number of busy cycles 87system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles 88system.cpu.idle_fraction 0 # Percentage of idle cycles 89system.cpu.icache.replacements 9788 # number of replacements 90system.cpu.icache.tagsinuse 984.426148 # Cycle average of tags in use 91system.cpu.icache.total_refs 516599864 # Total number of references to valid blocks. 92system.cpu.icache.sampled_refs 11521 # Sample count of references to valid blocks. 93system.cpu.icache.avg_refs 44839.845847 # Average number of references to valid blocks. 94system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 95system.cpu.icache.occ_blocks::cpu.inst 984.426148 # Average occupied blocks per requestor 96system.cpu.icache.occ_percent::cpu.inst 0.480677 # Average percentage of cache occupancy 97system.cpu.icache.occ_percent::total 0.480677 # Average percentage of cache occupancy 98system.cpu.icache.ReadReq_hits::cpu.inst 516599864 # number of ReadReq hits 99system.cpu.icache.ReadReq_hits::total 516599864 # number of ReadReq hits 100system.cpu.icache.demand_hits::cpu.inst 516599864 # number of demand (read+write) hits 101system.cpu.icache.demand_hits::total 516599864 # number of demand (read+write) hits 102system.cpu.icache.overall_hits::cpu.inst 516599864 # number of overall hits 103system.cpu.icache.overall_hits::total 516599864 # number of overall hits 104system.cpu.icache.ReadReq_misses::cpu.inst 11521 # number of ReadReq misses 105system.cpu.icache.ReadReq_misses::total 11521 # number of ReadReq misses 106system.cpu.icache.demand_misses::cpu.inst 11521 # number of demand (read+write) misses 107system.cpu.icache.demand_misses::total 11521 # number of demand (read+write) misses 108system.cpu.icache.overall_misses::cpu.inst 11521 # number of overall misses 109system.cpu.icache.overall_misses::total 11521 # number of overall misses 110system.cpu.icache.ReadReq_miss_latency::cpu.inst 285068000 # number of ReadReq miss cycles 111system.cpu.icache.ReadReq_miss_latency::total 285068000 # number of ReadReq miss cycles 112system.cpu.icache.demand_miss_latency::cpu.inst 285068000 # number of demand (read+write) miss cycles 113system.cpu.icache.demand_miss_latency::total 285068000 # number of demand (read+write) miss cycles 114system.cpu.icache.overall_miss_latency::cpu.inst 285068000 # number of overall miss cycles 115system.cpu.icache.overall_miss_latency::total 285068000 # number of overall miss cycles 116system.cpu.icache.ReadReq_accesses::cpu.inst 516611385 # number of ReadReq accesses(hits+misses) 117system.cpu.icache.ReadReq_accesses::total 516611385 # number of ReadReq accesses(hits+misses) 118system.cpu.icache.demand_accesses::cpu.inst 516611385 # number of demand (read+write) accesses 119system.cpu.icache.demand_accesses::total 516611385 # number of demand (read+write) accesses 120system.cpu.icache.overall_accesses::cpu.inst 516611385 # number of overall (read+write) accesses 121system.cpu.icache.overall_accesses::total 516611385 # number of overall (read+write) accesses 122system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000022 # miss rate for ReadReq accesses 123system.cpu.icache.demand_miss_rate::cpu.inst 0.000022 # miss rate for demand accesses 124system.cpu.icache.overall_miss_rate::cpu.inst 0.000022 # miss rate for overall accesses 125system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 24743.338252 # average ReadReq miss latency 126system.cpu.icache.demand_avg_miss_latency::cpu.inst 24743.338252 # average overall miss latency 127system.cpu.icache.overall_avg_miss_latency::cpu.inst 24743.338252 # average overall miss latency 128system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 129system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 130system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 131system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 132system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 133system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 134system.cpu.icache.fast_writes 0 # number of fast writes performed 135system.cpu.icache.cache_copies 0 # number of cache copies performed 136system.cpu.icache.ReadReq_mshr_misses::cpu.inst 11521 # number of ReadReq MSHR misses 137system.cpu.icache.ReadReq_mshr_misses::total 11521 # number of ReadReq MSHR misses 138system.cpu.icache.demand_mshr_misses::cpu.inst 11521 # number of demand (read+write) MSHR misses 139system.cpu.icache.demand_mshr_misses::total 11521 # number of demand (read+write) MSHR misses 140system.cpu.icache.overall_mshr_misses::cpu.inst 11521 # number of overall MSHR misses 141system.cpu.icache.overall_mshr_misses::total 11521 # number of overall MSHR misses 142system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 250505000 # number of ReadReq MSHR miss cycles 143system.cpu.icache.ReadReq_mshr_miss_latency::total 250505000 # number of ReadReq MSHR miss cycles 144system.cpu.icache.demand_mshr_miss_latency::cpu.inst 250505000 # number of demand (read+write) MSHR miss cycles 145system.cpu.icache.demand_mshr_miss_latency::total 250505000 # number of demand (read+write) MSHR miss cycles 146system.cpu.icache.overall_mshr_miss_latency::cpu.inst 250505000 # number of overall MSHR miss cycles 147system.cpu.icache.overall_mshr_miss_latency::total 250505000 # number of overall MSHR miss cycles 148system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for ReadReq accesses 149system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for demand accesses 150system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for overall accesses 151system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21743.338252 # average ReadReq mshr miss latency 152system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21743.338252 # average overall mshr miss latency 153system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21743.338252 # average overall mshr miss latency 154system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 155system.cpu.dcache.replacements 1134822 # number of replacements 156system.cpu.dcache.tagsinuse 4065.490059 # Cycle average of tags in use 157system.cpu.dcache.total_refs 179817787 # Total number of references to valid blocks. 158system.cpu.dcache.sampled_refs 1138918 # Sample count of references to valid blocks. 159system.cpu.dcache.avg_refs 157.884753 # Average number of references to valid blocks. 160system.cpu.dcache.warmup_cycle 11889987000 # Cycle when the warmup percentage was hit. 161system.cpu.dcache.occ_blocks::cpu.data 4065.490059 # Average occupied blocks per requestor 162system.cpu.dcache.occ_percent::cpu.data 0.992551 # Average percentage of cache occupancy 163system.cpu.dcache.occ_percent::total 0.992551 # Average percentage of cache occupancy 164system.cpu.dcache.ReadReq_hits::cpu.data 122957659 # number of ReadReq hits 165system.cpu.dcache.ReadReq_hits::total 122957659 # number of ReadReq hits 166system.cpu.dcache.WriteReq_hits::cpu.data 53883046 # number of WriteReq hits 167system.cpu.dcache.WriteReq_hits::total 53883046 # number of WriteReq hits 168system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488541 # number of LoadLockedReq hits 169system.cpu.dcache.LoadLockedReq_hits::total 1488541 # number of LoadLockedReq hits 170system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits 171system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits 172system.cpu.dcache.demand_hits::cpu.data 176840705 # number of demand (read+write) hits 173system.cpu.dcache.demand_hits::total 176840705 # number of demand (read+write) hits 174system.cpu.dcache.overall_hits::cpu.data 176840705 # number of overall hits 175system.cpu.dcache.overall_hits::total 176840705 # number of overall hits 176system.cpu.dcache.ReadReq_misses::cpu.data 782658 # number of ReadReq misses 177system.cpu.dcache.ReadReq_misses::total 782658 # number of ReadReq misses 178system.cpu.dcache.WriteReq_misses::cpu.data 356260 # number of WriteReq misses 179system.cpu.dcache.WriteReq_misses::total 356260 # number of WriteReq misses 180system.cpu.dcache.demand_misses::cpu.data 1138918 # number of demand (read+write) misses 181system.cpu.dcache.demand_misses::total 1138918 # number of demand (read+write) misses 182system.cpu.dcache.overall_misses::cpu.data 1138918 # number of overall misses 183system.cpu.dcache.overall_misses::total 1138918 # number of overall misses 184system.cpu.dcache.ReadReq_miss_latency::cpu.data 15502704000 # number of ReadReq miss cycles 185system.cpu.dcache.ReadReq_miss_latency::total 15502704000 # number of ReadReq miss cycles 186system.cpu.dcache.WriteReq_miss_latency::cpu.data 10028942000 # number of WriteReq miss cycles 187system.cpu.dcache.WriteReq_miss_latency::total 10028942000 # number of WriteReq miss cycles 188system.cpu.dcache.demand_miss_latency::cpu.data 25531646000 # number of demand (read+write) miss cycles 189system.cpu.dcache.demand_miss_latency::total 25531646000 # number of demand (read+write) miss cycles 190system.cpu.dcache.overall_miss_latency::cpu.data 25531646000 # number of overall miss cycles 191system.cpu.dcache.overall_miss_latency::total 25531646000 # number of overall miss cycles 192system.cpu.dcache.ReadReq_accesses::cpu.data 123740317 # number of ReadReq accesses(hits+misses) 193system.cpu.dcache.ReadReq_accesses::total 123740317 # number of ReadReq accesses(hits+misses) 194system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) 195system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) 196system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488541 # number of LoadLockedReq accesses(hits+misses) 197system.cpu.dcache.LoadLockedReq_accesses::total 1488541 # number of LoadLockedReq accesses(hits+misses) 198system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) 199system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) 200system.cpu.dcache.demand_accesses::cpu.data 177979623 # number of demand (read+write) accesses 201system.cpu.dcache.demand_accesses::total 177979623 # number of demand (read+write) accesses 202system.cpu.dcache.overall_accesses::cpu.data 177979623 # number of overall (read+write) accesses 203system.cpu.dcache.overall_accesses::total 177979623 # number of overall (read+write) accesses 204system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.006325 # miss rate for ReadReq accesses 205system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006568 # miss rate for WriteReq accesses 206system.cpu.dcache.demand_miss_rate::cpu.data 0.006399 # miss rate for demand accesses 207system.cpu.dcache.overall_miss_rate::cpu.data 0.006399 # miss rate for overall accesses 208system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19807.762778 # average ReadReq miss latency 209system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28150.625947 # average WriteReq miss latency 210system.cpu.dcache.demand_avg_miss_latency::cpu.data 22417.457622 # average overall miss latency 211system.cpu.dcache.overall_avg_miss_latency::cpu.data 22417.457622 # average overall miss latency 212system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 213system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 214system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 215system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 216system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 217system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 218system.cpu.dcache.fast_writes 0 # number of fast writes performed 219system.cpu.dcache.cache_copies 0 # number of cache copies performed 220system.cpu.dcache.writebacks::writebacks 1025440 # number of writebacks 221system.cpu.dcache.writebacks::total 1025440 # number of writebacks 222system.cpu.dcache.ReadReq_mshr_misses::cpu.data 782658 # number of ReadReq MSHR misses 223system.cpu.dcache.ReadReq_mshr_misses::total 782658 # number of ReadReq MSHR misses 224system.cpu.dcache.WriteReq_mshr_misses::cpu.data 356260 # number of WriteReq MSHR misses 225system.cpu.dcache.WriteReq_mshr_misses::total 356260 # number of WriteReq MSHR misses 226system.cpu.dcache.demand_mshr_misses::cpu.data 1138918 # number of demand (read+write) MSHR misses 227system.cpu.dcache.demand_mshr_misses::total 1138918 # number of demand (read+write) MSHR misses 228system.cpu.dcache.overall_mshr_misses::cpu.data 1138918 # number of overall MSHR misses 229system.cpu.dcache.overall_mshr_misses::total 1138918 # number of overall MSHR misses 230system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 13154730000 # number of ReadReq MSHR miss cycles 231system.cpu.dcache.ReadReq_mshr_miss_latency::total 13154730000 # number of ReadReq MSHR miss cycles 232system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8960162000 # number of WriteReq MSHR miss cycles 233system.cpu.dcache.WriteReq_mshr_miss_latency::total 8960162000 # number of WriteReq MSHR miss cycles 234system.cpu.dcache.demand_mshr_miss_latency::cpu.data 22114892000 # number of demand (read+write) MSHR miss cycles 235system.cpu.dcache.demand_mshr_miss_latency::total 22114892000 # number of demand (read+write) MSHR miss cycles 236system.cpu.dcache.overall_mshr_miss_latency::cpu.data 22114892000 # number of overall MSHR miss cycles 237system.cpu.dcache.overall_mshr_miss_latency::total 22114892000 # number of overall MSHR miss cycles 238system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006325 # mshr miss rate for ReadReq accesses 239system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006568 # mshr miss rate for WriteReq accesses 240system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006399 # mshr miss rate for demand accesses 241system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006399 # mshr miss rate for overall accesses 242system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16807.762778 # average ReadReq mshr miss latency 243system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25150.625947 # average WriteReq mshr miss latency 244system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19417.457622 # average overall mshr miss latency 245system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19417.457622 # average overall mshr miss latency 246system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 247system.cpu.l2cache.replacements 212089 # number of replacements 248system.cpu.l2cache.tagsinuse 20443.163614 # Cycle average of tags in use 249system.cpu.l2cache.total_refs 1426644 # Total number of references to valid blocks. 250system.cpu.l2cache.sampled_refs 232128 # Sample count of references to valid blocks. 251system.cpu.l2cache.avg_refs 6.145937 # Average number of references to valid blocks. 252system.cpu.l2cache.warmup_cycle 513135223000 # Cycle when the warmup percentage was hit. 253system.cpu.l2cache.occ_blocks::writebacks 14594.006011 # Average occupied blocks per requestor 254system.cpu.l2cache.occ_blocks::cpu.inst 132.842413 # Average occupied blocks per requestor 255system.cpu.l2cache.occ_blocks::cpu.data 5716.315189 # Average occupied blocks per requestor 256system.cpu.l2cache.occ_percent::writebacks 0.445374 # Average percentage of cache occupancy 257system.cpu.l2cache.occ_percent::cpu.inst 0.004054 # Average percentage of cache occupancy 258system.cpu.l2cache.occ_percent::cpu.data 0.174448 # Average percentage of cache occupancy 259system.cpu.l2cache.occ_percent::total 0.623876 # Average percentage of cache occupancy 260system.cpu.l2cache.ReadReq_hits::cpu.inst 8574 # number of ReadReq hits 261system.cpu.l2cache.ReadReq_hits::cpu.data 674432 # number of ReadReq hits 262system.cpu.l2cache.ReadReq_hits::total 683006 # number of ReadReq hits 263system.cpu.l2cache.Writeback_hits::writebacks 1025440 # number of Writeback hits 264system.cpu.l2cache.Writeback_hits::total 1025440 # number of Writeback hits 265system.cpu.l2cache.ReadExReq_hits::cpu.data 236229 # number of ReadExReq hits 266system.cpu.l2cache.ReadExReq_hits::total 236229 # number of ReadExReq hits 267system.cpu.l2cache.demand_hits::cpu.inst 8574 # number of demand (read+write) hits 268system.cpu.l2cache.demand_hits::cpu.data 910661 # number of demand (read+write) hits 269system.cpu.l2cache.demand_hits::total 919235 # number of demand (read+write) hits 270system.cpu.l2cache.overall_hits::cpu.inst 8574 # number of overall hits 271system.cpu.l2cache.overall_hits::cpu.data 910661 # number of overall hits 272system.cpu.l2cache.overall_hits::total 919235 # number of overall hits 273system.cpu.l2cache.ReadReq_misses::cpu.inst 2947 # number of ReadReq misses 274system.cpu.l2cache.ReadReq_misses::cpu.data 108226 # number of ReadReq misses 275system.cpu.l2cache.ReadReq_misses::total 111173 # number of ReadReq misses 276system.cpu.l2cache.ReadExReq_misses::cpu.data 120031 # number of ReadExReq misses 277system.cpu.l2cache.ReadExReq_misses::total 120031 # number of ReadExReq misses 278system.cpu.l2cache.demand_misses::cpu.inst 2947 # number of demand (read+write) misses 279system.cpu.l2cache.demand_misses::cpu.data 228257 # number of demand (read+write) misses 280system.cpu.l2cache.demand_misses::total 231204 # number of demand (read+write) misses 281system.cpu.l2cache.overall_misses::cpu.inst 2947 # number of overall misses 282system.cpu.l2cache.overall_misses::cpu.data 228257 # number of overall misses 283system.cpu.l2cache.overall_misses::total 231204 # number of overall misses 284system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 153244000 # number of ReadReq miss cycles 285system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5627752000 # number of ReadReq miss cycles 286system.cpu.l2cache.ReadReq_miss_latency::total 5780996000 # number of ReadReq miss cycles 287system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6241612000 # number of ReadExReq miss cycles 288system.cpu.l2cache.ReadExReq_miss_latency::total 6241612000 # number of ReadExReq miss cycles 289system.cpu.l2cache.demand_miss_latency::cpu.inst 153244000 # number of demand (read+write) miss cycles 290system.cpu.l2cache.demand_miss_latency::cpu.data 11869364000 # number of demand (read+write) miss cycles 291system.cpu.l2cache.demand_miss_latency::total 12022608000 # number of demand (read+write) miss cycles 292system.cpu.l2cache.overall_miss_latency::cpu.inst 153244000 # number of overall miss cycles 293system.cpu.l2cache.overall_miss_latency::cpu.data 11869364000 # number of overall miss cycles 294system.cpu.l2cache.overall_miss_latency::total 12022608000 # number of overall miss cycles 295system.cpu.l2cache.ReadReq_accesses::cpu.inst 11521 # number of ReadReq accesses(hits+misses) 296system.cpu.l2cache.ReadReq_accesses::cpu.data 782658 # number of ReadReq accesses(hits+misses) 297system.cpu.l2cache.ReadReq_accesses::total 794179 # number of ReadReq accesses(hits+misses) 298system.cpu.l2cache.Writeback_accesses::writebacks 1025440 # number of Writeback accesses(hits+misses) 299system.cpu.l2cache.Writeback_accesses::total 1025440 # number of Writeback accesses(hits+misses) 300system.cpu.l2cache.ReadExReq_accesses::cpu.data 356260 # number of ReadExReq accesses(hits+misses) 301system.cpu.l2cache.ReadExReq_accesses::total 356260 # number of ReadExReq accesses(hits+misses) 302system.cpu.l2cache.demand_accesses::cpu.inst 11521 # number of demand (read+write) accesses 303system.cpu.l2cache.demand_accesses::cpu.data 1138918 # number of demand (read+write) accesses 304system.cpu.l2cache.demand_accesses::total 1150439 # number of demand (read+write) accesses 305system.cpu.l2cache.overall_accesses::cpu.inst 11521 # number of overall (read+write) accesses 306system.cpu.l2cache.overall_accesses::cpu.data 1138918 # number of overall (read+write) accesses 307system.cpu.l2cache.overall_accesses::total 1150439 # number of overall (read+write) accesses 308system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.255794 # miss rate for ReadReq accesses 309system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.138280 # miss rate for ReadReq accesses 310system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.336920 # miss rate for ReadExReq accesses 311system.cpu.l2cache.demand_miss_rate::cpu.inst 0.255794 # miss rate for demand accesses 312system.cpu.l2cache.demand_miss_rate::cpu.data 0.200416 # miss rate for demand accesses 313system.cpu.l2cache.overall_miss_rate::cpu.inst 0.255794 # miss rate for overall accesses 314system.cpu.l2cache.overall_miss_rate::cpu.data 0.200416 # miss rate for overall accesses 315system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency 316system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency 317system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency 318system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency 319system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency 320system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency 321system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency 322system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 323system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 324system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 325system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 326system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 327system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 328system.cpu.l2cache.fast_writes 0 # number of fast writes performed 329system.cpu.l2cache.cache_copies 0 # number of cache copies performed 330system.cpu.l2cache.writebacks::writebacks 172302 # number of writebacks 331system.cpu.l2cache.writebacks::total 172302 # number of writebacks 332system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2947 # number of ReadReq MSHR misses 333system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 108226 # number of ReadReq MSHR misses 334system.cpu.l2cache.ReadReq_mshr_misses::total 111173 # number of ReadReq MSHR misses 335system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 120031 # number of ReadExReq MSHR misses 336system.cpu.l2cache.ReadExReq_mshr_misses::total 120031 # number of ReadExReq MSHR misses 337system.cpu.l2cache.demand_mshr_misses::cpu.inst 2947 # number of demand (read+write) MSHR misses 338system.cpu.l2cache.demand_mshr_misses::cpu.data 228257 # number of demand (read+write) MSHR misses 339system.cpu.l2cache.demand_mshr_misses::total 231204 # number of demand (read+write) MSHR misses 340system.cpu.l2cache.overall_mshr_misses::cpu.inst 2947 # number of overall MSHR misses 341system.cpu.l2cache.overall_mshr_misses::cpu.data 228257 # number of overall MSHR misses 342system.cpu.l2cache.overall_mshr_misses::total 231204 # number of overall MSHR misses 343system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 117880000 # number of ReadReq MSHR miss cycles 344system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4329040000 # number of ReadReq MSHR miss cycles 345system.cpu.l2cache.ReadReq_mshr_miss_latency::total 4446920000 # number of ReadReq MSHR miss cycles 346system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4801240000 # number of ReadExReq MSHR miss cycles 347system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4801240000 # number of ReadExReq MSHR miss cycles 348system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 117880000 # number of demand (read+write) MSHR miss cycles 349system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9130280000 # number of demand (read+write) MSHR miss cycles 350system.cpu.l2cache.demand_mshr_miss_latency::total 9248160000 # number of demand (read+write) MSHR miss cycles 351system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 117880000 # number of overall MSHR miss cycles 352system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9130280000 # number of overall MSHR miss cycles 353system.cpu.l2cache.overall_mshr_miss_latency::total 9248160000 # number of overall MSHR miss cycles 354system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.255794 # mshr miss rate for ReadReq accesses 355system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.138280 # mshr miss rate for ReadReq accesses 356system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.336920 # mshr miss rate for ReadExReq accesses 357system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.255794 # mshr miss rate for demand accesses 358system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.200416 # mshr miss rate for demand accesses 359system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.255794 # mshr miss rate for overall accesses 360system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.200416 # mshr miss rate for overall accesses 361system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency 362system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency 363system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency 364system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency 365system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency 366system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency 367system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency 368system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 369 370---------- End Simulation Statistics ---------- 371