stats.txt revision 11515:c48c7cc5a522
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.708539 # Number of seconds simulated 4sim_ticks 708539449500 # Number of ticks simulated 5final_tick 708539449500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 1440714 # Simulator instruction rate (inst/s) 8host_op_rate 1560229 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2021455048 # Simulator tick rate (ticks/s) 10host_mem_usage 314896 # Number of bytes of host memory used 11host_seconds 350.51 # Real time elapsed on the host 12sim_insts 504984064 # Number of instructions simulated 13sim_ops 546875315 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 147392 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 8963904 # Number of bytes read from this memory 18system.physmem.bytes_read::total 9111296 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 147392 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 147392 # Number of instructions bytes read from this memory 21system.physmem.bytes_written::writebacks 6165120 # Number of bytes written to this memory 22system.physmem.bytes_written::total 6165120 # Number of bytes written to this memory 23system.physmem.num_reads::cpu.inst 2303 # Number of read requests responded to by this memory 24system.physmem.num_reads::cpu.data 140061 # Number of read requests responded to by this memory 25system.physmem.num_reads::total 142364 # Number of read requests responded to by this memory 26system.physmem.num_writes::writebacks 96330 # Number of write requests responded to by this memory 27system.physmem.num_writes::total 96330 # Number of write requests responded to by this memory 28system.physmem.bw_read::cpu.inst 208022 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::cpu.data 12651242 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::total 12859264 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_inst_read::cpu.inst 208022 # Instruction read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::total 208022 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_write::writebacks 8701167 # Write bandwidth from this memory (bytes/s) 34system.physmem.bw_write::total 8701167 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_total::writebacks 8701167 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::cpu.inst 208022 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.data 12651242 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::total 21560431 # Total bandwidth to/from this memory (bytes/s) 39system.cpu_clk_domain.clock 500 # Clock period in ticks 40system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 41system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 42system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 43system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 44system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 45system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 46system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 47system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 48system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 49system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 50system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 51system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 52system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 53system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 54system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 55system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 56system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 57system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 58system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 59system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 60system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 61system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 62system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 63system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 64system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 65system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 66system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 67system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 68system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 69system.cpu.dtb.walker.walks 0 # Table walker walks requested 70system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 71system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 72system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 73system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 74system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 75system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 76system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 77system.cpu.dtb.inst_hits 0 # ITB inst hits 78system.cpu.dtb.inst_misses 0 # ITB inst misses 79system.cpu.dtb.read_hits 0 # DTB read hits 80system.cpu.dtb.read_misses 0 # DTB read misses 81system.cpu.dtb.write_hits 0 # DTB write hits 82system.cpu.dtb.write_misses 0 # DTB write misses 83system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 84system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 85system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 86system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 87system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 88system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 89system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 90system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 91system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 92system.cpu.dtb.read_accesses 0 # DTB read accesses 93system.cpu.dtb.write_accesses 0 # DTB write accesses 94system.cpu.dtb.inst_accesses 0 # ITB inst accesses 95system.cpu.dtb.hits 0 # DTB hits 96system.cpu.dtb.misses 0 # DTB misses 97system.cpu.dtb.accesses 0 # DTB accesses 98system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 99system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 100system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 101system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 102system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 103system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 104system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 105system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 106system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 107system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 108system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 109system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 110system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 111system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 112system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 113system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 114system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 115system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 116system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 117system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 118system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 119system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 120system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 121system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 122system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 123system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 124system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 125system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 126system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 127system.cpu.itb.walker.walks 0 # Table walker walks requested 128system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 129system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 130system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 131system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 132system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 133system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 134system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 135system.cpu.itb.inst_hits 0 # ITB inst hits 136system.cpu.itb.inst_misses 0 # ITB inst misses 137system.cpu.itb.read_hits 0 # DTB read hits 138system.cpu.itb.read_misses 0 # DTB read misses 139system.cpu.itb.write_hits 0 # DTB write hits 140system.cpu.itb.write_misses 0 # DTB write misses 141system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 142system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 143system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 144system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 145system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 146system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 147system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 148system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 149system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 150system.cpu.itb.read_accesses 0 # DTB read accesses 151system.cpu.itb.write_accesses 0 # DTB write accesses 152system.cpu.itb.inst_accesses 0 # ITB inst accesses 153system.cpu.itb.hits 0 # DTB hits 154system.cpu.itb.misses 0 # DTB misses 155system.cpu.itb.accesses 0 # DTB accesses 156system.cpu.workload.num_syscalls 548 # Number of system calls 157system.cpu.numCycles 1417078899 # number of cpu cycles simulated 158system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 159system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 160system.cpu.committedInsts 504984064 # Number of instructions committed 161system.cpu.committedOps 546875315 # Number of ops (including micro ops) committed 162system.cpu.num_int_alu_accesses 448447005 # Number of integer alu accesses 163system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses 164system.cpu.num_func_calls 19311615 # number of times a function call or return occured 165system.cpu.num_conditional_control_insts 90670594 # number of instructions that are conditional controls 166system.cpu.num_int_insts 448447005 # number of integer instructions 167system.cpu.num_fp_insts 16 # number of float instructions 168system.cpu.num_int_register_reads 748339627 # number of times the integer registers were read 169system.cpu.num_int_register_writes 289993515 # number of times the integer registers were written 170system.cpu.num_fp_register_reads 16 # number of times the floating registers were read 171system.cpu.num_fp_register_writes 0 # number of times the floating registers were written 172system.cpu.num_cc_register_reads 1984285070 # number of times the CC registers were read 173system.cpu.num_cc_register_writes 344062197 # number of times the CC registers were written 174system.cpu.num_mem_refs 172743505 # number of memory refs 175system.cpu.num_load_insts 115883283 # Number of load instructions 176system.cpu.num_store_insts 56860222 # Number of store instructions 177system.cpu.num_idle_cycles 0.002000 # Number of idle cycles 178system.cpu.num_busy_cycles 1417078898.998000 # Number of busy cycles 179system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles 180system.cpu.idle_fraction 0.000000 # Percentage of idle cycles 181system.cpu.Branches 121552863 # Number of branches fetched 182system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction 183system.cpu.op_class::IntAlu 375609862 68.46% 68.46% # Class of executed instruction 184system.cpu.op_class::IntMult 339219 0.06% 68.52% # Class of executed instruction 185system.cpu.op_class::IntDiv 0 0.00% 68.52% # Class of executed instruction 186system.cpu.op_class::FloatAdd 0 0.00% 68.52% # Class of executed instruction 187system.cpu.op_class::FloatCmp 0 0.00% 68.52% # Class of executed instruction 188system.cpu.op_class::FloatCvt 0 0.00% 68.52% # Class of executed instruction 189system.cpu.op_class::FloatMult 0 0.00% 68.52% # Class of executed instruction 190system.cpu.op_class::FloatDiv 0 0.00% 68.52% # Class of executed instruction 191system.cpu.op_class::FloatSqrt 0 0.00% 68.52% # Class of executed instruction 192system.cpu.op_class::SimdAdd 0 0.00% 68.52% # Class of executed instruction 193system.cpu.op_class::SimdAddAcc 0 0.00% 68.52% # Class of executed instruction 194system.cpu.op_class::SimdAlu 0 0.00% 68.52% # Class of executed instruction 195system.cpu.op_class::SimdCmp 0 0.00% 68.52% # Class of executed instruction 196system.cpu.op_class::SimdCvt 0 0.00% 68.52% # Class of executed instruction 197system.cpu.op_class::SimdMisc 0 0.00% 68.52% # Class of executed instruction 198system.cpu.op_class::SimdMult 0 0.00% 68.52% # Class of executed instruction 199system.cpu.op_class::SimdMultAcc 0 0.00% 68.52% # Class of executed instruction 200system.cpu.op_class::SimdShift 0 0.00% 68.52% # Class of executed instruction 201system.cpu.op_class::SimdShiftAcc 0 0.00% 68.52% # Class of executed instruction 202system.cpu.op_class::SimdSqrt 0 0.00% 68.52% # Class of executed instruction 203system.cpu.op_class::SimdFloatAdd 0 0.00% 68.52% # Class of executed instruction 204system.cpu.op_class::SimdFloatAlu 0 0.00% 68.52% # Class of executed instruction 205system.cpu.op_class::SimdFloatCmp 0 0.00% 68.52% # Class of executed instruction 206system.cpu.op_class::SimdFloatCvt 0 0.00% 68.52% # Class of executed instruction 207system.cpu.op_class::SimdFloatDiv 0 0.00% 68.52% # Class of executed instruction 208system.cpu.op_class::SimdFloatMisc 3 0.00% 68.52% # Class of executed instruction 209system.cpu.op_class::SimdFloatMult 0 0.00% 68.52% # Class of executed instruction 210system.cpu.op_class::SimdFloatMultAcc 0 0.00% 68.52% # Class of executed instruction 211system.cpu.op_class::SimdFloatSqrt 0 0.00% 68.52% # Class of executed instruction 212system.cpu.op_class::MemRead 115883283 21.12% 89.64% # Class of executed instruction 213system.cpu.op_class::MemWrite 56860222 10.36% 100.00% # Class of executed instruction 214system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 215system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 216system.cpu.op_class::total 548692589 # Class of executed instruction 217system.cpu.dcache.tags.replacements 1136276 # number of replacements 218system.cpu.dcache.tags.tagsinuse 4065.261181 # Cycle average of tags in use 219system.cpu.dcache.tags.total_refs 170177272 # Total number of references to valid blocks. 220system.cpu.dcache.tags.sampled_refs 1140372 # Sample count of references to valid blocks. 221system.cpu.dcache.tags.avg_refs 149.229613 # Average number of references to valid blocks. 222system.cpu.dcache.tags.warmup_cycle 11750119500 # Cycle when the warmup percentage was hit. 223system.cpu.dcache.tags.occ_blocks::cpu.data 4065.261181 # Average occupied blocks per requestor 224system.cpu.dcache.tags.occ_percent::cpu.data 0.992495 # Average percentage of cache occupancy 225system.cpu.dcache.tags.occ_percent::total 0.992495 # Average percentage of cache occupancy 226system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 227system.cpu.dcache.tags.age_task_id_blocks_1024::0 23 # Occupied blocks per task id 228system.cpu.dcache.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id 229system.cpu.dcache.tags.age_task_id_blocks_1024::2 343 # Occupied blocks per task id 230system.cpu.dcache.tags.age_task_id_blocks_1024::3 3546 # Occupied blocks per task id 231system.cpu.dcache.tags.age_task_id_blocks_1024::4 165 # Occupied blocks per task id 232system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 233system.cpu.dcache.tags.tag_accesses 343775660 # Number of tag accesses 234system.cpu.dcache.tags.data_accesses 343775660 # Number of data accesses 235system.cpu.dcache.ReadReq_hits::cpu.data 113315079 # number of ReadReq hits 236system.cpu.dcache.ReadReq_hits::total 113315079 # number of ReadReq hits 237system.cpu.dcache.WriteReq_hits::cpu.data 53882541 # number of WriteReq hits 238system.cpu.dcache.WriteReq_hits::total 53882541 # number of WriteReq hits 239system.cpu.dcache.SoftPFReq_hits::cpu.data 2570 # number of SoftPFReq hits 240system.cpu.dcache.SoftPFReq_hits::total 2570 # number of SoftPFReq hits 241system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488541 # number of LoadLockedReq hits 242system.cpu.dcache.LoadLockedReq_hits::total 1488541 # number of LoadLockedReq hits 243system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits 244system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits 245system.cpu.dcache.demand_hits::cpu.data 167197620 # number of demand (read+write) hits 246system.cpu.dcache.demand_hits::total 167197620 # number of demand (read+write) hits 247system.cpu.dcache.overall_hits::cpu.data 167200190 # number of overall hits 248system.cpu.dcache.overall_hits::total 167200190 # number of overall hits 249system.cpu.dcache.ReadReq_misses::cpu.data 783863 # number of ReadReq misses 250system.cpu.dcache.ReadReq_misses::total 783863 # number of ReadReq misses 251system.cpu.dcache.WriteReq_misses::cpu.data 356508 # number of WriteReq misses 252system.cpu.dcache.WriteReq_misses::total 356508 # number of WriteReq misses 253system.cpu.dcache.SoftPFReq_misses::cpu.data 1 # number of SoftPFReq misses 254system.cpu.dcache.SoftPFReq_misses::total 1 # number of SoftPFReq misses 255system.cpu.dcache.demand_misses::cpu.data 1140371 # number of demand (read+write) misses 256system.cpu.dcache.demand_misses::total 1140371 # number of demand (read+write) misses 257system.cpu.dcache.overall_misses::cpu.data 1140372 # number of overall misses 258system.cpu.dcache.overall_misses::total 1140372 # number of overall misses 259system.cpu.dcache.ReadReq_miss_latency::cpu.data 12120585500 # number of ReadReq miss cycles 260system.cpu.dcache.ReadReq_miss_latency::total 12120585500 # number of ReadReq miss cycles 261system.cpu.dcache.WriteReq_miss_latency::cpu.data 9577302500 # number of WriteReq miss cycles 262system.cpu.dcache.WriteReq_miss_latency::total 9577302500 # number of WriteReq miss cycles 263system.cpu.dcache.demand_miss_latency::cpu.data 21697888000 # number of demand (read+write) miss cycles 264system.cpu.dcache.demand_miss_latency::total 21697888000 # number of demand (read+write) miss cycles 265system.cpu.dcache.overall_miss_latency::cpu.data 21697888000 # number of overall miss cycles 266system.cpu.dcache.overall_miss_latency::total 21697888000 # number of overall miss cycles 267system.cpu.dcache.ReadReq_accesses::cpu.data 114098942 # number of ReadReq accesses(hits+misses) 268system.cpu.dcache.ReadReq_accesses::total 114098942 # number of ReadReq accesses(hits+misses) 269system.cpu.dcache.WriteReq_accesses::cpu.data 54239049 # number of WriteReq accesses(hits+misses) 270system.cpu.dcache.WriteReq_accesses::total 54239049 # number of WriteReq accesses(hits+misses) 271system.cpu.dcache.SoftPFReq_accesses::cpu.data 2571 # number of SoftPFReq accesses(hits+misses) 272system.cpu.dcache.SoftPFReq_accesses::total 2571 # number of SoftPFReq accesses(hits+misses) 273system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488541 # number of LoadLockedReq accesses(hits+misses) 274system.cpu.dcache.LoadLockedReq_accesses::total 1488541 # number of LoadLockedReq accesses(hits+misses) 275system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) 276system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) 277system.cpu.dcache.demand_accesses::cpu.data 168337991 # number of demand (read+write) accesses 278system.cpu.dcache.demand_accesses::total 168337991 # number of demand (read+write) accesses 279system.cpu.dcache.overall_accesses::cpu.data 168340562 # number of overall (read+write) accesses 280system.cpu.dcache.overall_accesses::total 168340562 # number of overall (read+write) accesses 281system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.006870 # miss rate for ReadReq accesses 282system.cpu.dcache.ReadReq_miss_rate::total 0.006870 # miss rate for ReadReq accesses 283system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006573 # miss rate for WriteReq accesses 284system.cpu.dcache.WriteReq_miss_rate::total 0.006573 # miss rate for WriteReq accesses 285system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000389 # miss rate for SoftPFReq accesses 286system.cpu.dcache.SoftPFReq_miss_rate::total 0.000389 # miss rate for SoftPFReq accesses 287system.cpu.dcache.demand_miss_rate::cpu.data 0.006774 # miss rate for demand accesses 288system.cpu.dcache.demand_miss_rate::total 0.006774 # miss rate for demand accesses 289system.cpu.dcache.overall_miss_rate::cpu.data 0.006774 # miss rate for overall accesses 290system.cpu.dcache.overall_miss_rate::total 0.006774 # miss rate for overall accesses 291system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15462.632501 # average ReadReq miss latency 292system.cpu.dcache.ReadReq_avg_miss_latency::total 15462.632501 # average ReadReq miss latency 293system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26864.200803 # average WriteReq miss latency 294system.cpu.dcache.WriteReq_avg_miss_latency::total 26864.200803 # average WriteReq miss latency 295system.cpu.dcache.demand_avg_miss_latency::cpu.data 19027.042954 # average overall miss latency 296system.cpu.dcache.demand_avg_miss_latency::total 19027.042954 # average overall miss latency 297system.cpu.dcache.overall_avg_miss_latency::cpu.data 19027.026269 # average overall miss latency 298system.cpu.dcache.overall_avg_miss_latency::total 19027.026269 # average overall miss latency 299system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 300system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 301system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 302system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 303system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 304system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 305system.cpu.dcache.writebacks::writebacks 1065708 # number of writebacks 306system.cpu.dcache.writebacks::total 1065708 # number of writebacks 307system.cpu.dcache.ReadReq_mshr_misses::cpu.data 783863 # number of ReadReq MSHR misses 308system.cpu.dcache.ReadReq_mshr_misses::total 783863 # number of ReadReq MSHR misses 309system.cpu.dcache.WriteReq_mshr_misses::cpu.data 356508 # number of WriteReq MSHR misses 310system.cpu.dcache.WriteReq_mshr_misses::total 356508 # number of WriteReq MSHR misses 311system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses 312system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses 313system.cpu.dcache.demand_mshr_misses::cpu.data 1140371 # number of demand (read+write) MSHR misses 314system.cpu.dcache.demand_mshr_misses::total 1140371 # number of demand (read+write) MSHR misses 315system.cpu.dcache.overall_mshr_misses::cpu.data 1140372 # number of overall MSHR misses 316system.cpu.dcache.overall_mshr_misses::total 1140372 # number of overall MSHR misses 317system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 11336722500 # number of ReadReq MSHR miss cycles 318system.cpu.dcache.ReadReq_mshr_miss_latency::total 11336722500 # number of ReadReq MSHR miss cycles 319system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9220794500 # number of WriteReq MSHR miss cycles 320system.cpu.dcache.WriteReq_mshr_miss_latency::total 9220794500 # number of WriteReq MSHR miss cycles 321system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 61000 # number of SoftPFReq MSHR miss cycles 322system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 61000 # number of SoftPFReq MSHR miss cycles 323system.cpu.dcache.demand_mshr_miss_latency::cpu.data 20557517000 # number of demand (read+write) MSHR miss cycles 324system.cpu.dcache.demand_mshr_miss_latency::total 20557517000 # number of demand (read+write) MSHR miss cycles 325system.cpu.dcache.overall_mshr_miss_latency::cpu.data 20557578000 # number of overall MSHR miss cycles 326system.cpu.dcache.overall_mshr_miss_latency::total 20557578000 # number of overall MSHR miss cycles 327system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006870 # mshr miss rate for ReadReq accesses 328system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006870 # mshr miss rate for ReadReq accesses 329system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006573 # mshr miss rate for WriteReq accesses 330system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006573 # mshr miss rate for WriteReq accesses 331system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.000389 # mshr miss rate for SoftPFReq accesses 332system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.000389 # mshr miss rate for SoftPFReq accesses 333system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006774 # mshr miss rate for demand accesses 334system.cpu.dcache.demand_mshr_miss_rate::total 0.006774 # mshr miss rate for demand accesses 335system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006774 # mshr miss rate for overall accesses 336system.cpu.dcache.overall_mshr_miss_rate::total 0.006774 # mshr miss rate for overall accesses 337system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14462.632501 # average ReadReq mshr miss latency 338system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14462.632501 # average ReadReq mshr miss latency 339system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25864.200803 # average WriteReq mshr miss latency 340system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25864.200803 # average WriteReq mshr miss latency 341system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 61000 # average SoftPFReq mshr miss latency 342system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 61000 # average SoftPFReq mshr miss latency 343system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18027.042954 # average overall mshr miss latency 344system.cpu.dcache.demand_avg_mshr_miss_latency::total 18027.042954 # average overall mshr miss latency 345system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18027.080637 # average overall mshr miss latency 346system.cpu.dcache.overall_avg_mshr_miss_latency::total 18027.080637 # average overall mshr miss latency 347system.cpu.icache.tags.replacements 9788 # number of replacements 348system.cpu.icache.tags.tagsinuse 983.198764 # Cycle average of tags in use 349system.cpu.icache.tags.total_refs 516597066 # Total number of references to valid blocks. 350system.cpu.icache.tags.sampled_refs 11521 # Sample count of references to valid blocks. 351system.cpu.icache.tags.avg_refs 44839.602986 # Average number of references to valid blocks. 352system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 353system.cpu.icache.tags.occ_blocks::cpu.inst 983.198764 # Average occupied blocks per requestor 354system.cpu.icache.tags.occ_percent::cpu.inst 0.480078 # Average percentage of cache occupancy 355system.cpu.icache.tags.occ_percent::total 0.480078 # Average percentage of cache occupancy 356system.cpu.icache.tags.occ_task_id_blocks::1024 1733 # Occupied blocks per task id 357system.cpu.icache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id 358system.cpu.icache.tags.age_task_id_blocks_1024::1 24 # Occupied blocks per task id 359system.cpu.icache.tags.age_task_id_blocks_1024::2 24 # Occupied blocks per task id 360system.cpu.icache.tags.age_task_id_blocks_1024::3 256 # Occupied blocks per task id 361system.cpu.icache.tags.age_task_id_blocks_1024::4 1402 # Occupied blocks per task id 362system.cpu.icache.tags.occ_task_id_percent::1024 0.846191 # Percentage of cache occupancy per task id 363system.cpu.icache.tags.tag_accesses 1033228695 # Number of tag accesses 364system.cpu.icache.tags.data_accesses 1033228695 # Number of data accesses 365system.cpu.icache.ReadReq_hits::cpu.inst 516597066 # number of ReadReq hits 366system.cpu.icache.ReadReq_hits::total 516597066 # number of ReadReq hits 367system.cpu.icache.demand_hits::cpu.inst 516597066 # number of demand (read+write) hits 368system.cpu.icache.demand_hits::total 516597066 # number of demand (read+write) hits 369system.cpu.icache.overall_hits::cpu.inst 516597066 # number of overall hits 370system.cpu.icache.overall_hits::total 516597066 # number of overall hits 371system.cpu.icache.ReadReq_misses::cpu.inst 11521 # number of ReadReq misses 372system.cpu.icache.ReadReq_misses::total 11521 # number of ReadReq misses 373system.cpu.icache.demand_misses::cpu.inst 11521 # number of demand (read+write) misses 374system.cpu.icache.demand_misses::total 11521 # number of demand (read+write) misses 375system.cpu.icache.overall_misses::cpu.inst 11521 # number of overall misses 376system.cpu.icache.overall_misses::total 11521 # number of overall misses 377system.cpu.icache.ReadReq_miss_latency::cpu.inst 263211000 # number of ReadReq miss cycles 378system.cpu.icache.ReadReq_miss_latency::total 263211000 # number of ReadReq miss cycles 379system.cpu.icache.demand_miss_latency::cpu.inst 263211000 # number of demand (read+write) miss cycles 380system.cpu.icache.demand_miss_latency::total 263211000 # number of demand (read+write) miss cycles 381system.cpu.icache.overall_miss_latency::cpu.inst 263211000 # number of overall miss cycles 382system.cpu.icache.overall_miss_latency::total 263211000 # number of overall miss cycles 383system.cpu.icache.ReadReq_accesses::cpu.inst 516608587 # number of ReadReq accesses(hits+misses) 384system.cpu.icache.ReadReq_accesses::total 516608587 # number of ReadReq accesses(hits+misses) 385system.cpu.icache.demand_accesses::cpu.inst 516608587 # number of demand (read+write) accesses 386system.cpu.icache.demand_accesses::total 516608587 # number of demand (read+write) accesses 387system.cpu.icache.overall_accesses::cpu.inst 516608587 # number of overall (read+write) accesses 388system.cpu.icache.overall_accesses::total 516608587 # number of overall (read+write) accesses 389system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000022 # miss rate for ReadReq accesses 390system.cpu.icache.ReadReq_miss_rate::total 0.000022 # miss rate for ReadReq accesses 391system.cpu.icache.demand_miss_rate::cpu.inst 0.000022 # miss rate for demand accesses 392system.cpu.icache.demand_miss_rate::total 0.000022 # miss rate for demand accesses 393system.cpu.icache.overall_miss_rate::cpu.inst 0.000022 # miss rate for overall accesses 394system.cpu.icache.overall_miss_rate::total 0.000022 # miss rate for overall accesses 395system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22846.193907 # average ReadReq miss latency 396system.cpu.icache.ReadReq_avg_miss_latency::total 22846.193907 # average ReadReq miss latency 397system.cpu.icache.demand_avg_miss_latency::cpu.inst 22846.193907 # average overall miss latency 398system.cpu.icache.demand_avg_miss_latency::total 22846.193907 # average overall miss latency 399system.cpu.icache.overall_avg_miss_latency::cpu.inst 22846.193907 # average overall miss latency 400system.cpu.icache.overall_avg_miss_latency::total 22846.193907 # average overall miss latency 401system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 402system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 403system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 404system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 405system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 406system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 407system.cpu.icache.writebacks::writebacks 9788 # number of writebacks 408system.cpu.icache.writebacks::total 9788 # number of writebacks 409system.cpu.icache.ReadReq_mshr_misses::cpu.inst 11521 # number of ReadReq MSHR misses 410system.cpu.icache.ReadReq_mshr_misses::total 11521 # number of ReadReq MSHR misses 411system.cpu.icache.demand_mshr_misses::cpu.inst 11521 # number of demand (read+write) MSHR misses 412system.cpu.icache.demand_mshr_misses::total 11521 # number of demand (read+write) MSHR misses 413system.cpu.icache.overall_mshr_misses::cpu.inst 11521 # number of overall MSHR misses 414system.cpu.icache.overall_mshr_misses::total 11521 # number of overall MSHR misses 415system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 251690000 # number of ReadReq MSHR miss cycles 416system.cpu.icache.ReadReq_mshr_miss_latency::total 251690000 # number of ReadReq MSHR miss cycles 417system.cpu.icache.demand_mshr_miss_latency::cpu.inst 251690000 # number of demand (read+write) MSHR miss cycles 418system.cpu.icache.demand_mshr_miss_latency::total 251690000 # number of demand (read+write) MSHR miss cycles 419system.cpu.icache.overall_mshr_miss_latency::cpu.inst 251690000 # number of overall MSHR miss cycles 420system.cpu.icache.overall_mshr_miss_latency::total 251690000 # number of overall MSHR miss cycles 421system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for ReadReq accesses 422system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000022 # mshr miss rate for ReadReq accesses 423system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for demand accesses 424system.cpu.icache.demand_mshr_miss_rate::total 0.000022 # mshr miss rate for demand accesses 425system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for overall accesses 426system.cpu.icache.overall_mshr_miss_rate::total 0.000022 # mshr miss rate for overall accesses 427system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21846.193907 # average ReadReq mshr miss latency 428system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21846.193907 # average ReadReq mshr miss latency 429system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21846.193907 # average overall mshr miss latency 430system.cpu.icache.demand_avg_mshr_miss_latency::total 21846.193907 # average overall mshr miss latency 431system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21846.193907 # average overall mshr miss latency 432system.cpu.icache.overall_avg_mshr_miss_latency::total 21846.193907 # average overall mshr miss latency 433system.cpu.l2cache.tags.replacements 110394 # number of replacements 434system.cpu.l2cache.tags.tagsinuse 27252.086651 # Cycle average of tags in use 435system.cpu.l2cache.tags.total_refs 1747015 # Total number of references to valid blocks. 436system.cpu.l2cache.tags.sampled_refs 141582 # Sample count of references to valid blocks. 437system.cpu.l2cache.tags.avg_refs 12.339245 # Average number of references to valid blocks. 438system.cpu.l2cache.tags.warmup_cycle 339115608000 # Cycle when the warmup percentage was hit. 439system.cpu.l2cache.tags.occ_blocks::writebacks 23375.830047 # Average occupied blocks per requestor 440system.cpu.l2cache.tags.occ_blocks::cpu.inst 240.203585 # Average occupied blocks per requestor 441system.cpu.l2cache.tags.occ_blocks::cpu.data 3636.053019 # Average occupied blocks per requestor 442system.cpu.l2cache.tags.occ_percent::writebacks 0.713374 # Average percentage of cache occupancy 443system.cpu.l2cache.tags.occ_percent::cpu.inst 0.007330 # Average percentage of cache occupancy 444system.cpu.l2cache.tags.occ_percent::cpu.data 0.110964 # Average percentage of cache occupancy 445system.cpu.l2cache.tags.occ_percent::total 0.831668 # Average percentage of cache occupancy 446system.cpu.l2cache.tags.occ_task_id_blocks::1024 31188 # Occupied blocks per task id 447system.cpu.l2cache.tags.age_task_id_blocks_1024::0 72 # Occupied blocks per task id 448system.cpu.l2cache.tags.age_task_id_blocks_1024::2 283 # Occupied blocks per task id 449system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3657 # Occupied blocks per task id 450system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27176 # Occupied blocks per task id 451system.cpu.l2cache.tags.occ_task_id_percent::1024 0.951782 # Percentage of cache occupancy per task id 452system.cpu.l2cache.tags.tag_accesses 18853226 # Number of tag accesses 453system.cpu.l2cache.tags.data_accesses 18853226 # Number of data accesses 454system.cpu.l2cache.WritebackDirty_hits::writebacks 1065708 # number of WritebackDirty hits 455system.cpu.l2cache.WritebackDirty_hits::total 1065708 # number of WritebackDirty hits 456system.cpu.l2cache.WritebackClean_hits::writebacks 9751 # number of WritebackClean hits 457system.cpu.l2cache.WritebackClean_hits::total 9751 # number of WritebackClean hits 458system.cpu.l2cache.ReadExReq_hits::cpu.data 255720 # number of ReadExReq hits 459system.cpu.l2cache.ReadExReq_hits::total 255720 # number of ReadExReq hits 460system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 9218 # number of ReadCleanReq hits 461system.cpu.l2cache.ReadCleanReq_hits::total 9218 # number of ReadCleanReq hits 462system.cpu.l2cache.ReadSharedReq_hits::cpu.data 744591 # number of ReadSharedReq hits 463system.cpu.l2cache.ReadSharedReq_hits::total 744591 # number of ReadSharedReq hits 464system.cpu.l2cache.demand_hits::cpu.inst 9218 # number of demand (read+write) hits 465system.cpu.l2cache.demand_hits::cpu.data 1000311 # number of demand (read+write) hits 466system.cpu.l2cache.demand_hits::total 1009529 # number of demand (read+write) hits 467system.cpu.l2cache.overall_hits::cpu.inst 9218 # number of overall hits 468system.cpu.l2cache.overall_hits::cpu.data 1000311 # number of overall hits 469system.cpu.l2cache.overall_hits::total 1009529 # number of overall hits 470system.cpu.l2cache.ReadExReq_misses::cpu.data 100788 # number of ReadExReq misses 471system.cpu.l2cache.ReadExReq_misses::total 100788 # number of ReadExReq misses 472system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2303 # number of ReadCleanReq misses 473system.cpu.l2cache.ReadCleanReq_misses::total 2303 # number of ReadCleanReq misses 474system.cpu.l2cache.ReadSharedReq_misses::cpu.data 39273 # number of ReadSharedReq misses 475system.cpu.l2cache.ReadSharedReq_misses::total 39273 # number of ReadSharedReq misses 476system.cpu.l2cache.demand_misses::cpu.inst 2303 # number of demand (read+write) misses 477system.cpu.l2cache.demand_misses::cpu.data 140061 # number of demand (read+write) misses 478system.cpu.l2cache.demand_misses::total 142364 # number of demand (read+write) misses 479system.cpu.l2cache.overall_misses::cpu.inst 2303 # number of overall misses 480system.cpu.l2cache.overall_misses::cpu.data 140061 # number of overall misses 481system.cpu.l2cache.overall_misses::total 142364 # number of overall misses 482system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6000939500 # number of ReadExReq miss cycles 483system.cpu.l2cache.ReadExReq_miss_latency::total 6000939500 # number of ReadExReq miss cycles 484system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 137232000 # number of ReadCleanReq miss cycles 485system.cpu.l2cache.ReadCleanReq_miss_latency::total 137232000 # number of ReadCleanReq miss cycles 486system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 2339459000 # number of ReadSharedReq miss cycles 487system.cpu.l2cache.ReadSharedReq_miss_latency::total 2339459000 # number of ReadSharedReq miss cycles 488system.cpu.l2cache.demand_miss_latency::cpu.inst 137232000 # number of demand (read+write) miss cycles 489system.cpu.l2cache.demand_miss_latency::cpu.data 8340398500 # number of demand (read+write) miss cycles 490system.cpu.l2cache.demand_miss_latency::total 8477630500 # number of demand (read+write) miss cycles 491system.cpu.l2cache.overall_miss_latency::cpu.inst 137232000 # number of overall miss cycles 492system.cpu.l2cache.overall_miss_latency::cpu.data 8340398500 # number of overall miss cycles 493system.cpu.l2cache.overall_miss_latency::total 8477630500 # number of overall miss cycles 494system.cpu.l2cache.WritebackDirty_accesses::writebacks 1065708 # number of WritebackDirty accesses(hits+misses) 495system.cpu.l2cache.WritebackDirty_accesses::total 1065708 # number of WritebackDirty accesses(hits+misses) 496system.cpu.l2cache.WritebackClean_accesses::writebacks 9751 # number of WritebackClean accesses(hits+misses) 497system.cpu.l2cache.WritebackClean_accesses::total 9751 # number of WritebackClean accesses(hits+misses) 498system.cpu.l2cache.ReadExReq_accesses::cpu.data 356508 # number of ReadExReq accesses(hits+misses) 499system.cpu.l2cache.ReadExReq_accesses::total 356508 # number of ReadExReq accesses(hits+misses) 500system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 11521 # number of ReadCleanReq accesses(hits+misses) 501system.cpu.l2cache.ReadCleanReq_accesses::total 11521 # number of ReadCleanReq accesses(hits+misses) 502system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 783864 # number of ReadSharedReq accesses(hits+misses) 503system.cpu.l2cache.ReadSharedReq_accesses::total 783864 # number of ReadSharedReq accesses(hits+misses) 504system.cpu.l2cache.demand_accesses::cpu.inst 11521 # number of demand (read+write) accesses 505system.cpu.l2cache.demand_accesses::cpu.data 1140372 # number of demand (read+write) accesses 506system.cpu.l2cache.demand_accesses::total 1151893 # number of demand (read+write) accesses 507system.cpu.l2cache.overall_accesses::cpu.inst 11521 # number of overall (read+write) accesses 508system.cpu.l2cache.overall_accesses::cpu.data 1140372 # number of overall (read+write) accesses 509system.cpu.l2cache.overall_accesses::total 1151893 # number of overall (read+write) accesses 510system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.282709 # miss rate for ReadExReq accesses 511system.cpu.l2cache.ReadExReq_miss_rate::total 0.282709 # miss rate for ReadExReq accesses 512system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.199896 # miss rate for ReadCleanReq accesses 513system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.199896 # miss rate for ReadCleanReq accesses 514system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.050102 # miss rate for ReadSharedReq accesses 515system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.050102 # miss rate for ReadSharedReq accesses 516system.cpu.l2cache.demand_miss_rate::cpu.inst 0.199896 # miss rate for demand accesses 517system.cpu.l2cache.demand_miss_rate::cpu.data 0.122820 # miss rate for demand accesses 518system.cpu.l2cache.demand_miss_rate::total 0.123591 # miss rate for demand accesses 519system.cpu.l2cache.overall_miss_rate::cpu.inst 0.199896 # miss rate for overall accesses 520system.cpu.l2cache.overall_miss_rate::cpu.data 0.122820 # miss rate for overall accesses 521system.cpu.l2cache.overall_miss_rate::total 0.123591 # miss rate for overall accesses 522system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59540.218082 # average ReadExReq miss latency 523system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59540.218082 # average ReadExReq miss latency 524system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59588.363005 # average ReadCleanReq miss latency 525system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59588.363005 # average ReadCleanReq miss latency 526system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59569.144196 # average ReadSharedReq miss latency 527system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59569.144196 # average ReadSharedReq miss latency 528system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59588.363005 # average overall miss latency 529system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59548.328942 # average overall miss latency 530system.cpu.l2cache.demand_avg_miss_latency::total 59548.976567 # average overall miss latency 531system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59588.363005 # average overall miss latency 532system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59548.328942 # average overall miss latency 533system.cpu.l2cache.overall_avg_miss_latency::total 59548.976567 # average overall miss latency 534system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 535system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 536system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 537system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 538system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 539system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 540system.cpu.l2cache.writebacks::writebacks 96330 # number of writebacks 541system.cpu.l2cache.writebacks::total 96330 # number of writebacks 542system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 2 # number of CleanEvict MSHR misses 543system.cpu.l2cache.CleanEvict_mshr_misses::total 2 # number of CleanEvict MSHR misses 544system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 100788 # number of ReadExReq MSHR misses 545system.cpu.l2cache.ReadExReq_mshr_misses::total 100788 # number of ReadExReq MSHR misses 546system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2303 # number of ReadCleanReq MSHR misses 547system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2303 # number of ReadCleanReq MSHR misses 548system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 39273 # number of ReadSharedReq MSHR misses 549system.cpu.l2cache.ReadSharedReq_mshr_misses::total 39273 # number of ReadSharedReq MSHR misses 550system.cpu.l2cache.demand_mshr_misses::cpu.inst 2303 # number of demand (read+write) MSHR misses 551system.cpu.l2cache.demand_mshr_misses::cpu.data 140061 # number of demand (read+write) MSHR misses 552system.cpu.l2cache.demand_mshr_misses::total 142364 # number of demand (read+write) MSHR misses 553system.cpu.l2cache.overall_mshr_misses::cpu.inst 2303 # number of overall MSHR misses 554system.cpu.l2cache.overall_mshr_misses::cpu.data 140061 # number of overall MSHR misses 555system.cpu.l2cache.overall_mshr_misses::total 142364 # number of overall MSHR misses 556system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4993059500 # number of ReadExReq MSHR miss cycles 557system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4993059500 # number of ReadExReq MSHR miss cycles 558system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 114202000 # number of ReadCleanReq MSHR miss cycles 559system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 114202000 # number of ReadCleanReq MSHR miss cycles 560system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1946729000 # number of ReadSharedReq MSHR miss cycles 561system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1946729000 # number of ReadSharedReq MSHR miss cycles 562system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 114202000 # number of demand (read+write) MSHR miss cycles 563system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6939788500 # number of demand (read+write) MSHR miss cycles 564system.cpu.l2cache.demand_mshr_miss_latency::total 7053990500 # number of demand (read+write) MSHR miss cycles 565system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 114202000 # number of overall MSHR miss cycles 566system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6939788500 # number of overall MSHR miss cycles 567system.cpu.l2cache.overall_mshr_miss_latency::total 7053990500 # number of overall MSHR miss cycles 568system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 569system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 570system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.282709 # mshr miss rate for ReadExReq accesses 571system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.282709 # mshr miss rate for ReadExReq accesses 572system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.199896 # mshr miss rate for ReadCleanReq accesses 573system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.199896 # mshr miss rate for ReadCleanReq accesses 574system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.050102 # mshr miss rate for ReadSharedReq accesses 575system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.050102 # mshr miss rate for ReadSharedReq accesses 576system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.199896 # mshr miss rate for demand accesses 577system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.122820 # mshr miss rate for demand accesses 578system.cpu.l2cache.demand_mshr_miss_rate::total 0.123591 # mshr miss rate for demand accesses 579system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.199896 # mshr miss rate for overall accesses 580system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.122820 # mshr miss rate for overall accesses 581system.cpu.l2cache.overall_mshr_miss_rate::total 0.123591 # mshr miss rate for overall accesses 582system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49540.218082 # average ReadExReq mshr miss latency 583system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49540.218082 # average ReadExReq mshr miss latency 584system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49588.363005 # average ReadCleanReq mshr miss latency 585system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49588.363005 # average ReadCleanReq mshr miss latency 586system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49569.144196 # average ReadSharedReq mshr miss latency 587system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49569.144196 # average ReadSharedReq mshr miss latency 588system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49588.363005 # average overall mshr miss latency 589system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49548.328942 # average overall mshr miss latency 590system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49548.976567 # average overall mshr miss latency 591system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49588.363005 # average overall mshr miss latency 592system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49548.328942 # average overall mshr miss latency 593system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49548.976567 # average overall mshr miss latency 594system.cpu.toL2Bus.snoop_filter.tot_requests 2297957 # Total number of requests made to the snoop filter. 595system.cpu.toL2Bus.snoop_filter.hit_single_requests 1146116 # Number of requests hitting in the snoop filter with a single holder of the requested data. 596system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3565 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 597system.cpu.toL2Bus.snoop_filter.tot_snoops 2146 # Total number of snoops made to the snoop filter. 598system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2145 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 599system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 600system.cpu.toL2Bus.trans_dist::ReadResp 795385 # Transaction distribution 601system.cpu.toL2Bus.trans_dist::WritebackDirty 1162038 # Transaction distribution 602system.cpu.toL2Bus.trans_dist::WritebackClean 9788 # Transaction distribution 603system.cpu.toL2Bus.trans_dist::CleanEvict 84632 # Transaction distribution 604system.cpu.toL2Bus.trans_dist::ReadExReq 356508 # Transaction distribution 605system.cpu.toL2Bus.trans_dist::ReadExResp 356508 # Transaction distribution 606system.cpu.toL2Bus.trans_dist::ReadCleanReq 11521 # Transaction distribution 607system.cpu.toL2Bus.trans_dist::ReadSharedReq 783864 # Transaction distribution 608system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 32830 # Packet count per connected master and slave (bytes) 609system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3417020 # Packet count per connected master and slave (bytes) 610system.cpu.toL2Bus.pkt_count::total 3449850 # Packet count per connected master and slave (bytes) 611system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1363776 # Cumulative packet size per connected master and slave (bytes) 612system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141189120 # Cumulative packet size per connected master and slave (bytes) 613system.cpu.toL2Bus.pkt_size::total 142552896 # Cumulative packet size per connected master and slave (bytes) 614system.cpu.toL2Bus.snoops 110394 # Total snoops (count) 615system.cpu.toL2Bus.snoop_fanout::samples 1262287 # Request fanout histogram 616system.cpu.toL2Bus.snoop_fanout::mean 0.004566 # Request fanout histogram 617system.cpu.toL2Bus.snoop_fanout::stdev 0.067432 # Request fanout histogram 618system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 619system.cpu.toL2Bus.snoop_fanout::0 1256524 99.54% 99.54% # Request fanout histogram 620system.cpu.toL2Bus.snoop_fanout::1 5762 0.46% 100.00% # Request fanout histogram 621system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% # Request fanout histogram 622system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 623system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 624system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 625system.cpu.toL2Bus.snoop_fanout::total 1262287 # Request fanout histogram 626system.cpu.toL2Bus.reqLayer0.occupancy 2224474500 # Layer occupancy (ticks) 627system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) 628system.cpu.toL2Bus.respLayer0.occupancy 17281500 # Layer occupancy (ticks) 629system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 630system.cpu.toL2Bus.respLayer1.occupancy 1710558000 # Layer occupancy (ticks) 631system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) 632system.membus.trans_dist::ReadResp 41576 # Transaction distribution 633system.membus.trans_dist::WritebackDirty 96330 # Transaction distribution 634system.membus.trans_dist::CleanEvict 11920 # Transaction distribution 635system.membus.trans_dist::ReadExReq 100788 # Transaction distribution 636system.membus.trans_dist::ReadExResp 100788 # Transaction distribution 637system.membus.trans_dist::ReadSharedReq 41576 # Transaction distribution 638system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 392978 # Packet count per connected master and slave (bytes) 639system.membus.pkt_count::total 392978 # Packet count per connected master and slave (bytes) 640system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15276416 # Cumulative packet size per connected master and slave (bytes) 641system.membus.pkt_size::total 15276416 # Cumulative packet size per connected master and slave (bytes) 642system.membus.snoops 0 # Total snoops (count) 643system.membus.snoop_fanout::samples 250615 # Request fanout histogram 644system.membus.snoop_fanout::mean 0 # Request fanout histogram 645system.membus.snoop_fanout::stdev 0 # Request fanout histogram 646system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 647system.membus.snoop_fanout::0 250615 100.00% 100.00% # Request fanout histogram 648system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 649system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 650system.membus.snoop_fanout::min_value 0 # Request fanout histogram 651system.membus.snoop_fanout::max_value 0 # Request fanout histogram 652system.membus.snoop_fanout::total 250615 # Request fanout histogram 653system.membus.reqLayer0.occupancy 644476328 # Layer occupancy (ticks) 654system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) 655system.membus.respLayer1.occupancy 711820000 # Layer occupancy (ticks) 656system.membus.respLayer1.utilization 0.1 # Layer utilization (%) 657 658---------- End Simulation Statistics ---------- 659