stats.txt revision 10063:9595c7a1d837
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.290499 # Number of seconds simulated 4sim_ticks 290498967000 # Number of ticks simulated 5final_tick 290498967000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 2103217 # Simulator instruction rate (inst/s) 8host_op_rate 2370536 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1206088561 # Simulator tick rate (ticks/s) 10host_mem_usage 262216 # Number of bytes of host memory used 11host_seconds 240.86 # Real time elapsed on the host 12sim_insts 506581607 # Number of instructions simulated 13sim_ops 570968167 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 2066445500 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 422852701 # Number of bytes read from this memory 18system.physmem.bytes_read::total 2489298201 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 2066445500 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 2066445500 # Number of instructions bytes read from this memory 21system.physmem.bytes_written::cpu.data 216067624 # Number of bytes written to this memory 22system.physmem.bytes_written::total 216067624 # Number of bytes written to this memory 23system.physmem.num_reads::cpu.inst 516611375 # Number of read requests responded to by this memory 24system.physmem.num_reads::cpu.data 125228857 # Number of read requests responded to by this memory 25system.physmem.num_reads::total 641840232 # Number of read requests responded to by this memory 26system.physmem.num_writes::cpu.data 55727847 # Number of write requests responded to by this memory 27system.physmem.num_writes::total 55727847 # Number of write requests responded to by this memory 28system.physmem.bw_read::cpu.inst 7113434933 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::cpu.data 1455608278 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::total 8569043211 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_inst_read::cpu.inst 7113434933 # Instruction read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::total 7113434933 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_write::cpu.data 743781041 # Write bandwidth from this memory (bytes/s) 34system.physmem.bw_write::total 743781041 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_total::cpu.inst 7113434933 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::cpu.data 2199389318 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::total 9312824252 # Total bandwidth to/from this memory (bytes/s) 38system.membus.throughput 9312824252 # Throughput (bytes/s) 39system.membus.data_through_bus 2705365825 # Total data (bytes) 40system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 41system.cpu_clk_domain.clock 500 # Clock period in ticks 42system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 43system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 44system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 45system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 46system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 47system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 48system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 49system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 50system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 51system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 52system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 53system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 54system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 55system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 56system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 57system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 58system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 59system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 60system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 61system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 62system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 63system.cpu.dtb.inst_hits 0 # ITB inst hits 64system.cpu.dtb.inst_misses 0 # ITB inst misses 65system.cpu.dtb.read_hits 0 # DTB read hits 66system.cpu.dtb.read_misses 0 # DTB read misses 67system.cpu.dtb.write_hits 0 # DTB write hits 68system.cpu.dtb.write_misses 0 # DTB write misses 69system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 70system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 71system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 72system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 73system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 74system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 75system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 76system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 77system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 78system.cpu.dtb.read_accesses 0 # DTB read accesses 79system.cpu.dtb.write_accesses 0 # DTB write accesses 80system.cpu.dtb.inst_accesses 0 # ITB inst accesses 81system.cpu.dtb.hits 0 # DTB hits 82system.cpu.dtb.misses 0 # DTB misses 83system.cpu.dtb.accesses 0 # DTB accesses 84system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 85system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 86system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 87system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 88system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 89system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 90system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 91system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 92system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 93system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 94system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 95system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 96system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 97system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 98system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 99system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 100system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 101system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 102system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 103system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 104system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 105system.cpu.itb.inst_hits 0 # ITB inst hits 106system.cpu.itb.inst_misses 0 # ITB inst misses 107system.cpu.itb.read_hits 0 # DTB read hits 108system.cpu.itb.read_misses 0 # DTB read misses 109system.cpu.itb.write_hits 0 # DTB write hits 110system.cpu.itb.write_misses 0 # DTB write misses 111system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 112system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 113system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 114system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 115system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 116system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 117system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 118system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 119system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 120system.cpu.itb.read_accesses 0 # DTB read accesses 121system.cpu.itb.write_accesses 0 # DTB write accesses 122system.cpu.itb.inst_accesses 0 # ITB inst accesses 123system.cpu.itb.hits 0 # DTB hits 124system.cpu.itb.misses 0 # DTB misses 125system.cpu.itb.accesses 0 # DTB accesses 126system.cpu.workload.num_syscalls 548 # Number of system calls 127system.cpu.numCycles 580997935 # number of cpu cycles simulated 128system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 129system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 130system.cpu.committedInsts 506581607 # Number of instructions committed 131system.cpu.committedOps 570968167 # Number of ops (including micro ops) committed 132system.cpu.num_int_alu_accesses 470727695 # Number of integer alu accesses 133system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses 134system.cpu.num_func_calls 19311615 # number of times a function call or return occured 135system.cpu.num_conditional_control_insts 94895872 # number of instructions that are conditional controls 136system.cpu.num_int_insts 470727695 # number of integer instructions 137system.cpu.num_fp_insts 16 # number of float instructions 138system.cpu.num_int_register_reads 2482508148 # number of times the integer registers were read 139system.cpu.num_int_register_writes 646169352 # number of times the integer registers were written 140system.cpu.num_fp_register_reads 16 # number of times the floating registers were read 141system.cpu.num_fp_register_writes 0 # number of times the floating registers were written 142system.cpu.num_mem_refs 182890034 # number of memory refs 143system.cpu.num_load_insts 126029555 # Number of load instructions 144system.cpu.num_store_insts 56860479 # Number of store instructions 145system.cpu.num_idle_cycles 0 # Number of idle cycles 146system.cpu.num_busy_cycles 580997935 # Number of busy cycles 147system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles 148system.cpu.idle_fraction 0 # Percentage of idle cycles 149system.cpu.Branches 121548301 # Number of branches fetched 150 151---------- End Simulation Statistics ---------- 152