stats.txt revision 9729:e2fafd224f43
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.202265 # Number of seconds simulated 4sim_ticks 202264702500 # Number of ticks simulated 5final_tick 202264702500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 152154 # Simulator instruction rate (inst/s) 8host_op_rate 171544 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 60912686 # Simulator tick rate (ticks/s) 10host_mem_usage 250588 # Number of bytes of host memory used 11host_seconds 3320.57 # Real time elapsed on the host 12sim_insts 505237723 # Number of instructions simulated 13sim_ops 569624283 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 216000 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 9260928 # Number of bytes read from this memory 16system.physmem.bytes_read::total 9476928 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 216000 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 216000 # Number of instructions bytes read from this memory 19system.physmem.bytes_written::writebacks 6246016 # Number of bytes written to this memory 20system.physmem.bytes_written::total 6246016 # Number of bytes written to this memory 21system.physmem.num_reads::cpu.inst 3375 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 144702 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 148077 # Number of read requests responded to by this memory 24system.physmem.num_writes::writebacks 97594 # Number of write requests responded to by this memory 25system.physmem.num_writes::total 97594 # Number of write requests responded to by this memory 26system.physmem.bw_read::cpu.inst 1067908 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::cpu.data 45786180 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_read::total 46854087 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::cpu.inst 1067908 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_inst_read::total 1067908 # Instruction read bandwidth from this memory (bytes/s) 31system.physmem.bw_write::writebacks 30880405 # Write bandwidth from this memory (bytes/s) 32system.physmem.bw_write::total 30880405 # Write bandwidth from this memory (bytes/s) 33system.physmem.bw_total::writebacks 30880405 # Total bandwidth to/from this memory (bytes/s) 34system.physmem.bw_total::cpu.inst 1067908 # Total bandwidth to/from this memory (bytes/s) 35system.physmem.bw_total::cpu.data 45786180 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::total 77734493 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.readReqs 148078 # Total number of read requests seen 38system.physmem.writeReqs 97594 # Total number of write requests seen 39system.physmem.cpureqs 245687 # Reqs generatd by CPU via cache - shady 40system.physmem.bytesRead 9476928 # Total number of bytes read from memory 41system.physmem.bytesWritten 6246016 # Total number of bytes written to memory 42system.physmem.bytesConsumedRd 9476928 # bytesRead derated as per pkt->getSize() 43system.physmem.bytesConsumedWr 6246016 # bytesWritten derated as per pkt->getSize() 44system.physmem.servicedByWrQ 65 # Number of read reqs serviced by write Q 45system.physmem.neitherReadNorWrite 9 # Reqs where no action is needed 46system.physmem.perBankRdReqs::0 9583 # Track reads on a per bank basis 47system.physmem.perBankRdReqs::1 9207 # Track reads on a per bank basis 48system.physmem.perBankRdReqs::2 9281 # Track reads on a per bank basis 49system.physmem.perBankRdReqs::3 8971 # Track reads on a per bank basis 50system.physmem.perBankRdReqs::4 9774 # Track reads on a per bank basis 51system.physmem.perBankRdReqs::5 9643 # Track reads on a per bank basis 52system.physmem.perBankRdReqs::6 9100 # Track reads on a per bank basis 53system.physmem.perBankRdReqs::7 8322 # Track reads on a per bank basis 54system.physmem.perBankRdReqs::8 8802 # Track reads on a per bank basis 55system.physmem.perBankRdReqs::9 8899 # Track reads on a per bank basis 56system.physmem.perBankRdReqs::10 8932 # Track reads on a per bank basis 57system.physmem.perBankRdReqs::11 9735 # Track reads on a per bank basis 58system.physmem.perBankRdReqs::12 9616 # Track reads on a per bank basis 59system.physmem.perBankRdReqs::13 9782 # Track reads on a per bank basis 60system.physmem.perBankRdReqs::14 8932 # Track reads on a per bank basis 61system.physmem.perBankRdReqs::15 9434 # Track reads on a per bank basis 62system.physmem.perBankWrReqs::0 6260 # Track writes on a per bank basis 63system.physmem.perBankWrReqs::1 6145 # Track writes on a per bank basis 64system.physmem.perBankWrReqs::2 6098 # Track writes on a per bank basis 65system.physmem.perBankWrReqs::3 5882 # Track writes on a per bank basis 66system.physmem.perBankWrReqs::4 6246 # Track writes on a per bank basis 67system.physmem.perBankWrReqs::5 6280 # Track writes on a per bank basis 68system.physmem.perBankWrReqs::6 6041 # Track writes on a per bank basis 69system.physmem.perBankWrReqs::7 5558 # Track writes on a per bank basis 70system.physmem.perBankWrReqs::8 5810 # Track writes on a per bank basis 71system.physmem.perBankWrReqs::9 5899 # Track writes on a per bank basis 72system.physmem.perBankWrReqs::10 5989 # Track writes on a per bank basis 73system.physmem.perBankWrReqs::11 6521 # Track writes on a per bank basis 74system.physmem.perBankWrReqs::12 6350 # Track writes on a per bank basis 75system.physmem.perBankWrReqs::13 6340 # Track writes on a per bank basis 76system.physmem.perBankWrReqs::14 6045 # Track writes on a per bank basis 77system.physmem.perBankWrReqs::15 6130 # Track writes on a per bank basis 78system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 79system.physmem.numWrRetry 6 # Number of times wr buffer was full causing retry 80system.physmem.totGap 202264683000 # Total gap between requests 81system.physmem.readPktSize::0 0 # Categorize read packet sizes 82system.physmem.readPktSize::1 0 # Categorize read packet sizes 83system.physmem.readPktSize::2 0 # Categorize read packet sizes 84system.physmem.readPktSize::3 0 # Categorize read packet sizes 85system.physmem.readPktSize::4 0 # Categorize read packet sizes 86system.physmem.readPktSize::5 0 # Categorize read packet sizes 87system.physmem.readPktSize::6 148078 # Categorize read packet sizes 88system.physmem.writePktSize::0 0 # Categorize write packet sizes 89system.physmem.writePktSize::1 0 # Categorize write packet sizes 90system.physmem.writePktSize::2 0 # Categorize write packet sizes 91system.physmem.writePktSize::3 0 # Categorize write packet sizes 92system.physmem.writePktSize::4 0 # Categorize write packet sizes 93system.physmem.writePktSize::5 0 # Categorize write packet sizes 94system.physmem.writePktSize::6 97594 # Categorize write packet sizes 95system.physmem.rdQLenPdf::0 138541 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::1 8888 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::2 522 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::3 55 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 127system.physmem.wrQLenPdf::0 4223 # What write queue length does an incoming req see 128system.physmem.wrQLenPdf::1 4234 # What write queue length does an incoming req see 129system.physmem.wrQLenPdf::2 4236 # What write queue length does an incoming req see 130system.physmem.wrQLenPdf::3 4236 # What write queue length does an incoming req see 131system.physmem.wrQLenPdf::4 4236 # What write queue length does an incoming req see 132system.physmem.wrQLenPdf::5 4235 # What write queue length does an incoming req see 133system.physmem.wrQLenPdf::6 4235 # What write queue length does an incoming req see 134system.physmem.wrQLenPdf::7 4237 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::8 4237 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::9 4243 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::10 4243 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::11 4243 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::12 4243 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::13 4243 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::14 4243 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::15 4243 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::16 4243 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::17 4243 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::18 4243 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::19 4243 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::20 4243 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::21 4243 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::22 4243 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::23 21 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::24 10 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::25 8 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::26 8 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::27 8 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::28 8 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::29 8 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::30 6 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::31 6 # What write queue length does an incoming req see 159system.physmem.bytesPerActivate::samples 55927 # Bytes accessed per row activation 160system.physmem.bytesPerActivate::mean 281.047508 # Bytes accessed per row activation 161system.physmem.bytesPerActivate::gmean 134.123063 # Bytes accessed per row activation 162system.physmem.bytesPerActivate::stdev 688.589570 # Bytes accessed per row activation 163system.physmem.bytesPerActivate::64-65 27857 49.81% 49.81% # Bytes accessed per row activation 164system.physmem.bytesPerActivate::128-129 10311 18.44% 68.25% # Bytes accessed per row activation 165system.physmem.bytesPerActivate::192-193 4742 8.48% 76.73% # Bytes accessed per row activation 166system.physmem.bytesPerActivate::256-257 2859 5.11% 81.84% # Bytes accessed per row activation 167system.physmem.bytesPerActivate::320-321 1799 3.22% 85.05% # Bytes accessed per row activation 168system.physmem.bytesPerActivate::384-385 1160 2.07% 87.13% # Bytes accessed per row activation 169system.physmem.bytesPerActivate::448-449 842 1.51% 88.63% # Bytes accessed per row activation 170system.physmem.bytesPerActivate::512-513 665 1.19% 89.82% # Bytes accessed per row activation 171system.physmem.bytesPerActivate::576-577 468 0.84% 90.66% # Bytes accessed per row activation 172system.physmem.bytesPerActivate::640-641 376 0.67% 91.33% # Bytes accessed per row activation 173system.physmem.bytesPerActivate::704-705 271 0.48% 91.82% # Bytes accessed per row activation 174system.physmem.bytesPerActivate::768-769 239 0.43% 92.24% # Bytes accessed per row activation 175system.physmem.bytesPerActivate::832-833 201 0.36% 92.60% # Bytes accessed per row activation 176system.physmem.bytesPerActivate::896-897 180 0.32% 92.92% # Bytes accessed per row activation 177system.physmem.bytesPerActivate::960-961 171 0.31% 93.23% # Bytes accessed per row activation 178system.physmem.bytesPerActivate::1024-1025 177 0.32% 93.55% # Bytes accessed per row activation 179system.physmem.bytesPerActivate::1088-1089 169 0.30% 93.85% # Bytes accessed per row activation 180system.physmem.bytesPerActivate::1152-1153 170 0.30% 94.15% # Bytes accessed per row activation 181system.physmem.bytesPerActivate::1216-1217 147 0.26% 94.42% # Bytes accessed per row activation 182system.physmem.bytesPerActivate::1280-1281 156 0.28% 94.69% # Bytes accessed per row activation 183system.physmem.bytesPerActivate::1344-1345 167 0.30% 94.99% # Bytes accessed per row activation 184system.physmem.bytesPerActivate::1408-1409 250 0.45% 95.44% # Bytes accessed per row activation 185system.physmem.bytesPerActivate::1472-1473 974 1.74% 97.18% # Bytes accessed per row activation 186system.physmem.bytesPerActivate::1536-1537 239 0.43% 97.61% # Bytes accessed per row activation 187system.physmem.bytesPerActivate::1600-1601 147 0.26% 97.87% # Bytes accessed per row activation 188system.physmem.bytesPerActivate::1664-1665 173 0.31% 98.18% # Bytes accessed per row activation 189system.physmem.bytesPerActivate::1728-1729 101 0.18% 98.36% # Bytes accessed per row activation 190system.physmem.bytesPerActivate::1792-1793 105 0.19% 98.55% # Bytes accessed per row activation 191system.physmem.bytesPerActivate::1856-1857 71 0.13% 98.68% # Bytes accessed per row activation 192system.physmem.bytesPerActivate::1920-1921 56 0.10% 98.78% # Bytes accessed per row activation 193system.physmem.bytesPerActivate::1984-1985 36 0.06% 98.84% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::2048-2049 46 0.08% 98.92% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::2112-2113 27 0.05% 98.97% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::2176-2177 25 0.04% 99.02% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::2240-2241 21 0.04% 99.05% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::2304-2305 22 0.04% 99.09% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::2368-2369 17 0.03% 99.12% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::2432-2433 12 0.02% 99.15% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::2496-2497 14 0.03% 99.17% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::2560-2561 11 0.02% 99.19% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::2624-2625 12 0.02% 99.21% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::2688-2689 9 0.02% 99.23% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::2752-2753 11 0.02% 99.25% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::2816-2817 10 0.02% 99.27% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::2880-2881 4 0.01% 99.27% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::2944-2945 5 0.01% 99.28% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::3008-3009 8 0.01% 99.30% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::3072-3073 7 0.01% 99.31% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::3136-3137 3 0.01% 99.31% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::3200-3201 5 0.01% 99.32% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::3264-3265 3 0.01% 99.33% # Bytes accessed per row activation 214system.physmem.bytesPerActivate::3328-3329 7 0.01% 99.34% # Bytes accessed per row activation 215system.physmem.bytesPerActivate::3392-3393 4 0.01% 99.35% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::3456-3457 3 0.01% 99.35% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::3520-3521 2 0.00% 99.36% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::3584-3585 9 0.02% 99.37% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::3648-3649 6 0.01% 99.38% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::3712-3713 4 0.01% 99.39% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::3776-3777 1 0.00% 99.39% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::3840-3841 2 0.00% 99.40% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::3904-3905 2 0.00% 99.40% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::3968-3969 1 0.00% 99.40% # Bytes accessed per row activation 225system.physmem.bytesPerActivate::4032-4033 4 0.01% 99.41% # Bytes accessed per row activation 226system.physmem.bytesPerActivate::4096-4097 3 0.01% 99.41% # Bytes accessed per row activation 227system.physmem.bytesPerActivate::4160-4161 2 0.00% 99.42% # Bytes accessed per row activation 228system.physmem.bytesPerActivate::4224-4225 1 0.00% 99.42% # Bytes accessed per row activation 229system.physmem.bytesPerActivate::4288-4289 2 0.00% 99.42% # Bytes accessed per row activation 230system.physmem.bytesPerActivate::4352-4353 3 0.01% 99.43% # Bytes accessed per row activation 231system.physmem.bytesPerActivate::4416-4417 2 0.00% 99.43% # Bytes accessed per row activation 232system.physmem.bytesPerActivate::4480-4481 2 0.00% 99.43% # Bytes accessed per row activation 233system.physmem.bytesPerActivate::4544-4545 1 0.00% 99.44% # Bytes accessed per row activation 234system.physmem.bytesPerActivate::4608-4609 2 0.00% 99.44% # Bytes accessed per row activation 235system.physmem.bytesPerActivate::4736-4737 1 0.00% 99.44% # Bytes accessed per row activation 236system.physmem.bytesPerActivate::4800-4801 1 0.00% 99.44% # Bytes accessed per row activation 237system.physmem.bytesPerActivate::4864-4865 1 0.00% 99.45% # Bytes accessed per row activation 238system.physmem.bytesPerActivate::4928-4929 1 0.00% 99.45% # Bytes accessed per row activation 239system.physmem.bytesPerActivate::4992-4993 1 0.00% 99.45% # Bytes accessed per row activation 240system.physmem.bytesPerActivate::5056-5057 4 0.01% 99.46% # Bytes accessed per row activation 241system.physmem.bytesPerActivate::5120-5121 4 0.01% 99.46% # Bytes accessed per row activation 242system.physmem.bytesPerActivate::5184-5185 1 0.00% 99.47% # Bytes accessed per row activation 243system.physmem.bytesPerActivate::5248-5249 1 0.00% 99.47% # Bytes accessed per row activation 244system.physmem.bytesPerActivate::5376-5377 4 0.01% 99.47% # Bytes accessed per row activation 245system.physmem.bytesPerActivate::5440-5441 3 0.01% 99.48% # Bytes accessed per row activation 246system.physmem.bytesPerActivate::5568-5569 2 0.00% 99.48% # Bytes accessed per row activation 247system.physmem.bytesPerActivate::5632-5633 1 0.00% 99.49% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::5696-5697 1 0.00% 99.49% # Bytes accessed per row activation 249system.physmem.bytesPerActivate::5760-5761 1 0.00% 99.49% # Bytes accessed per row activation 250system.physmem.bytesPerActivate::5888-5889 1 0.00% 99.49% # Bytes accessed per row activation 251system.physmem.bytesPerActivate::5952-5953 3 0.01% 99.50% # Bytes accessed per row activation 252system.physmem.bytesPerActivate::6144-6145 1 0.00% 99.50% # Bytes accessed per row activation 253system.physmem.bytesPerActivate::6208-6209 4 0.01% 99.50% # Bytes accessed per row activation 254system.physmem.bytesPerActivate::6272-6273 2 0.00% 99.51% # Bytes accessed per row activation 255system.physmem.bytesPerActivate::6336-6337 1 0.00% 99.51% # Bytes accessed per row activation 256system.physmem.bytesPerActivate::6464-6465 1 0.00% 99.51% # Bytes accessed per row activation 257system.physmem.bytesPerActivate::6720-6721 1 0.00% 99.51% # Bytes accessed per row activation 258system.physmem.bytesPerActivate::6784-6785 1 0.00% 99.52% # Bytes accessed per row activation 259system.physmem.bytesPerActivate::7040-7041 1 0.00% 99.52% # Bytes accessed per row activation 260system.physmem.bytesPerActivate::7104-7105 1 0.00% 99.52% # Bytes accessed per row activation 261system.physmem.bytesPerActivate::7168-7169 2 0.00% 99.52% # Bytes accessed per row activation 262system.physmem.bytesPerActivate::7360-7361 1 0.00% 99.52% # Bytes accessed per row activation 263system.physmem.bytesPerActivate::7552-7553 1 0.00% 99.53% # Bytes accessed per row activation 264system.physmem.bytesPerActivate::7616-7617 2 0.00% 99.53% # Bytes accessed per row activation 265system.physmem.bytesPerActivate::7680-7681 1 0.00% 99.53% # Bytes accessed per row activation 266system.physmem.bytesPerActivate::7744-7745 1 0.00% 99.53% # Bytes accessed per row activation 267system.physmem.bytesPerActivate::7808-7809 2 0.00% 99.54% # Bytes accessed per row activation 268system.physmem.bytesPerActivate::8128-8129 3 0.01% 99.54% # Bytes accessed per row activation 269system.physmem.bytesPerActivate::8192-8193 256 0.46% 100.00% # Bytes accessed per row activation 270system.physmem.bytesPerActivate::total 55927 # Bytes accessed per row activation 271system.physmem.totQLat 1510568250 # Total cycles spent in queuing delays 272system.physmem.totMemAccLat 4629837000 # Sum of mem lat for all requests 273system.physmem.totBusLat 740065000 # Total cycles spent in databus access 274system.physmem.totBankLat 2379203750 # Total cycles spent in bank access 275system.physmem.avgQLat 10205.65 # Average queueing delay per request 276system.physmem.avgBankLat 16074.29 # Average bank access latency per request 277system.physmem.avgBusLat 5000.00 # Average bus latency per request 278system.physmem.avgMemAccLat 31279.93 # Average memory access latency 279system.physmem.avgRdBW 46.85 # Average achieved read bandwidth in MB/s 280system.physmem.avgWrBW 30.88 # Average achieved write bandwidth in MB/s 281system.physmem.avgConsumedRdBW 46.85 # Average consumed read bandwidth in MB/s 282system.physmem.avgConsumedWrBW 30.88 # Average consumed write bandwidth in MB/s 283system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s 284system.physmem.busUtil 0.61 # Data bus utilization in percentage 285system.physmem.avgRdQLen 0.02 # Average read queue length over time 286system.physmem.avgWrQLen 8.55 # Average write queue length over time 287system.physmem.readRowHits 130620 # Number of row buffer hits during reads 288system.physmem.writeRowHits 59055 # Number of row buffer hits during writes 289system.physmem.readRowHitRate 88.25 # Row buffer hit rate for reads 290system.physmem.writeRowHitRate 60.51 # Row buffer hit rate for writes 291system.physmem.avgGap 823311.91 # Average gap between requests 292system.membus.throughput 77734493 # Throughput (bytes/s) 293system.membus.trans_dist::ReadReq 46795 # Transaction distribution 294system.membus.trans_dist::ReadResp 46794 # Transaction distribution 295system.membus.trans_dist::Writeback 97594 # Transaction distribution 296system.membus.trans_dist::UpgradeReq 9 # Transaction distribution 297system.membus.trans_dist::UpgradeResp 9 # Transaction distribution 298system.membus.trans_dist::ReadExReq 101283 # Transaction distribution 299system.membus.trans_dist::ReadExResp 101283 # Transaction distribution 300system.membus.pkt_count_system.cpu.l2cache.mem_side 393767 # Packet count per connected master and slave (bytes) 301system.membus.pkt_count 393767 # Packet count per connected master and slave (bytes) 302system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 15722944 # Cumulative packet size per connected master and slave (bytes) 303system.membus.tot_pkt_size 15722944 # Cumulative packet size per connected master and slave (bytes) 304system.membus.data_through_bus 15722944 # Total data (bytes) 305system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 306system.membus.reqLayer0.occupancy 1079125750 # Layer occupancy (ticks) 307system.membus.reqLayer0.utilization 0.5 # Layer utilization (%) 308system.membus.respLayer1.occupancy 1399666492 # Layer occupancy (ticks) 309system.membus.respLayer1.utilization 0.7 # Layer utilization (%) 310system.cpu.branchPred.lookups 182795351 # Number of BP lookups 311system.cpu.branchPred.condPredicted 143107535 # Number of conditional branches predicted 312system.cpu.branchPred.condIncorrect 7264975 # Number of conditional branches incorrect 313system.cpu.branchPred.BTBLookups 93466227 # Number of BTB lookups 314system.cpu.branchPred.BTBHits 87209092 # Number of BTB hits 315system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 316system.cpu.branchPred.BTBHitPct 93.305459 # BTB Hit Percentage 317system.cpu.branchPred.usedRAS 12678830 # Number of times the RAS was used to get a target. 318system.cpu.branchPred.RASInCorrect 116057 # Number of incorrect RAS predictions. 319system.cpu.dtb.inst_hits 0 # ITB inst hits 320system.cpu.dtb.inst_misses 0 # ITB inst misses 321system.cpu.dtb.read_hits 0 # DTB read hits 322system.cpu.dtb.read_misses 0 # DTB read misses 323system.cpu.dtb.write_hits 0 # DTB write hits 324system.cpu.dtb.write_misses 0 # DTB write misses 325system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 326system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 327system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 328system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 329system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 330system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 331system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 332system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 333system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 334system.cpu.dtb.read_accesses 0 # DTB read accesses 335system.cpu.dtb.write_accesses 0 # DTB write accesses 336system.cpu.dtb.inst_accesses 0 # ITB inst accesses 337system.cpu.dtb.hits 0 # DTB hits 338system.cpu.dtb.misses 0 # DTB misses 339system.cpu.dtb.accesses 0 # DTB accesses 340system.cpu.itb.inst_hits 0 # ITB inst hits 341system.cpu.itb.inst_misses 0 # ITB inst misses 342system.cpu.itb.read_hits 0 # DTB read hits 343system.cpu.itb.read_misses 0 # DTB read misses 344system.cpu.itb.write_hits 0 # DTB write hits 345system.cpu.itb.write_misses 0 # DTB write misses 346system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 347system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 348system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 349system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 350system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 351system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 352system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 353system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 354system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 355system.cpu.itb.read_accesses 0 # DTB read accesses 356system.cpu.itb.write_accesses 0 # DTB write accesses 357system.cpu.itb.inst_accesses 0 # ITB inst accesses 358system.cpu.itb.hits 0 # DTB hits 359system.cpu.itb.misses 0 # DTB misses 360system.cpu.itb.accesses 0 # DTB accesses 361system.cpu.workload.num_syscalls 548 # Number of system calls 362system.cpu.numCycles 404529406 # number of cpu cycles simulated 363system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 364system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 365system.cpu.fetch.icacheStallCycles 119370904 # Number of cycles fetch is stalled on an Icache miss 366system.cpu.fetch.Insts 761561247 # Number of instructions fetch has processed 367system.cpu.fetch.Branches 182795351 # Number of branches that fetch encountered 368system.cpu.fetch.predictedBranches 99887922 # Number of branches that fetch has predicted taken 369system.cpu.fetch.Cycles 170134463 # Number of cycles fetch has run and was not squashing or blocked 370system.cpu.fetch.SquashCycles 35678521 # Number of cycles fetch has spent squashing 371system.cpu.fetch.BlockedCycles 77150212 # Number of cycles fetch has spent blocked 372system.cpu.fetch.MiscStallCycles 98 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 373system.cpu.fetch.PendingTrapStallCycles 455 # Number of stall cycles due to pending traps 374system.cpu.fetch.IcacheWaitRetryStallCycles 48 # Number of stall cycles due to full MSHR 375system.cpu.fetch.CacheLines 114522843 # Number of cache lines fetched 376system.cpu.fetch.IcacheSquashes 2439505 # Number of outstanding Icache misses that were squashed 377system.cpu.fetch.rateDist::samples 394266586 # Number of instructions fetched each cycle (Total) 378system.cpu.fetch.rateDist::mean 2.166435 # Number of instructions fetched each cycle (Total) 379system.cpu.fetch.rateDist::stdev 2.987414 # Number of instructions fetched each cycle (Total) 380system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 381system.cpu.fetch.rateDist::0 224144737 56.85% 56.85% # Number of instructions fetched each cycle (Total) 382system.cpu.fetch.rateDist::1 14179887 3.60% 60.45% # Number of instructions fetched each cycle (Total) 383system.cpu.fetch.rateDist::2 22893161 5.81% 66.25% # Number of instructions fetched each cycle (Total) 384system.cpu.fetch.rateDist::3 22745024 5.77% 72.02% # Number of instructions fetched each cycle (Total) 385system.cpu.fetch.rateDist::4 20894474 5.30% 77.32% # Number of instructions fetched each cycle (Total) 386system.cpu.fetch.rateDist::5 11598135 2.94% 80.26% # Number of instructions fetched each cycle (Total) 387system.cpu.fetch.rateDist::6 13057002 3.31% 83.58% # Number of instructions fetched each cycle (Total) 388system.cpu.fetch.rateDist::7 11992402 3.04% 86.62% # Number of instructions fetched each cycle (Total) 389system.cpu.fetch.rateDist::8 52761764 13.38% 100.00% # Number of instructions fetched each cycle (Total) 390system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 391system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 392system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 393system.cpu.fetch.rateDist::total 394266586 # Number of instructions fetched each cycle (Total) 394system.cpu.fetch.branchRate 0.451872 # Number of branch fetches per cycle 395system.cpu.fetch.rate 1.882586 # Number of inst fetches per cycle 396system.cpu.decode.IdleCycles 129061208 # Number of cycles decode is idle 397system.cpu.decode.BlockedCycles 72641827 # Number of cycles decode is blocked 398system.cpu.decode.RunCycles 158799298 # Number of cycles decode is running 399system.cpu.decode.UnblockCycles 6227893 # Number of cycles decode is unblocking 400system.cpu.decode.SquashCycles 27536360 # Number of cycles decode is squashing 401system.cpu.decode.BranchResolved 26125699 # Number of times decode resolved a branch 402system.cpu.decode.BranchMispred 76608 # Number of times decode detected a branch misprediction 403system.cpu.decode.DecodedInsts 825532349 # Number of instructions handled by decode 404system.cpu.decode.SquashedInsts 291942 # Number of squashed instructions handled by decode 405system.cpu.rename.SquashCycles 27536360 # Number of cycles rename is squashing 406system.cpu.rename.IdleCycles 135656827 # Number of cycles rename is idle 407system.cpu.rename.BlockCycles 10155018 # Number of cycles rename is blocking 408system.cpu.rename.serializeStallCycles 47441534 # count of cycles rename stalled for serializing inst 409system.cpu.rename.RunCycles 158249633 # Number of cycles rename is running 410system.cpu.rename.UnblockCycles 15227214 # Number of cycles rename is unblocking 411system.cpu.rename.RenamedInsts 800580004 # Number of instructions processed by rename 412system.cpu.rename.ROBFullEvents 1401 # Number of times rename has blocked due to ROB full 413system.cpu.rename.IQFullEvents 3056484 # Number of times rename has blocked due to IQ full 414system.cpu.rename.LSQFullEvents 8970861 # Number of times rename has blocked due to LSQ full 415system.cpu.rename.FullRegisterEvents 208 # Number of times there has been no free registers 416system.cpu.rename.RenamedOperands 954230970 # Number of destination operands rename has renamed 417system.cpu.rename.RenameLookups 3500428728 # Number of register rename lookups that rename has made 418system.cpu.rename.int_rename_lookups 3500427418 # Number of integer rename lookups 419system.cpu.rename.fp_rename_lookups 1310 # Number of floating rename lookups 420system.cpu.rename.CommittedMaps 666252291 # Number of HB maps that are committed 421system.cpu.rename.UndoneMaps 287978679 # Number of HB maps that are undone due to squashing 422system.cpu.rename.serializingInsts 2292969 # count of serializing insts renamed 423system.cpu.rename.tempSerializingInsts 2292967 # count of temporary serializing insts renamed 424system.cpu.rename.skidInsts 41852604 # count of insts added to the skid buffer 425system.cpu.memDep0.insertedLoads 170255884 # Number of loads inserted to the mem dependence unit. 426system.cpu.memDep0.insertedStores 73472812 # Number of stores inserted to the mem dependence unit. 427system.cpu.memDep0.conflictingLoads 28582851 # Number of conflicting loads. 428system.cpu.memDep0.conflictingStores 15746500 # Number of conflicting stores. 429system.cpu.iq.iqInstsAdded 755022174 # Number of instructions added to the IQ (excludes non-spec) 430system.cpu.iq.iqNonSpecInstsAdded 3775311 # Number of non-speculative instructions added to the IQ 431system.cpu.iq.iqInstsIssued 665301102 # Number of instructions issued 432system.cpu.iq.iqSquashedInstsIssued 1380692 # Number of squashed instructions issued 433system.cpu.iq.iqSquashedInstsExamined 187339157 # Number of squashed instructions iterated over during squash; mainly for profiling 434system.cpu.iq.iqSquashedOperandsExamined 479760666 # Number of squashed operands that are examined and possibly removed from graph 435system.cpu.iq.iqSquashedNonSpecRemoved 797679 # Number of squashed non-spec instructions that were removed 436system.cpu.iq.issued_per_cycle::samples 394266586 # Number of insts issued each cycle 437system.cpu.iq.issued_per_cycle::mean 1.687440 # Number of insts issued each cycle 438system.cpu.iq.issued_per_cycle::stdev 1.735091 # Number of insts issued each cycle 439system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 440system.cpu.iq.issued_per_cycle::0 138747020 35.19% 35.19% # Number of insts issued each cycle 441system.cpu.iq.issued_per_cycle::1 69982581 17.75% 52.94% # Number of insts issued each cycle 442system.cpu.iq.issued_per_cycle::2 71470863 18.13% 71.07% # Number of insts issued each cycle 443system.cpu.iq.issued_per_cycle::3 53423224 13.55% 84.62% # Number of insts issued each cycle 444system.cpu.iq.issued_per_cycle::4 31142023 7.90% 92.52% # Number of insts issued each cycle 445system.cpu.iq.issued_per_cycle::5 16022250 4.06% 96.58% # Number of insts issued each cycle 446system.cpu.iq.issued_per_cycle::6 8747194 2.22% 98.80% # Number of insts issued each cycle 447system.cpu.iq.issued_per_cycle::7 2906831 0.74% 99.54% # Number of insts issued each cycle 448system.cpu.iq.issued_per_cycle::8 1824600 0.46% 100.00% # Number of insts issued each cycle 449system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 450system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 451system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 452system.cpu.iq.issued_per_cycle::total 394266586 # Number of insts issued each cycle 453system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 454system.cpu.iq.fu_full::IntAlu 480987 5.01% 5.01% # attempts to use FU when none available 455system.cpu.iq.fu_full::IntMult 0 0.00% 5.01% # attempts to use FU when none available 456system.cpu.iq.fu_full::IntDiv 0 0.00% 5.01% # attempts to use FU when none available 457system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.01% # attempts to use FU when none available 458system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.01% # attempts to use FU when none available 459system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.01% # attempts to use FU when none available 460system.cpu.iq.fu_full::FloatMult 0 0.00% 5.01% # attempts to use FU when none available 461system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.01% # attempts to use FU when none available 462system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.01% # attempts to use FU when none available 463system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.01% # attempts to use FU when none available 464system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.01% # attempts to use FU when none available 465system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.01% # attempts to use FU when none available 466system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.01% # attempts to use FU when none available 467system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.01% # attempts to use FU when none available 468system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.01% # attempts to use FU when none available 469system.cpu.iq.fu_full::SimdMult 0 0.00% 5.01% # attempts to use FU when none available 470system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.01% # attempts to use FU when none available 471system.cpu.iq.fu_full::SimdShift 0 0.00% 5.01% # attempts to use FU when none available 472system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.01% # attempts to use FU when none available 473system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.01% # attempts to use FU when none available 474system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.01% # attempts to use FU when none available 475system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.01% # attempts to use FU when none available 476system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.01% # attempts to use FU when none available 477system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.01% # attempts to use FU when none available 478system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.01% # attempts to use FU when none available 479system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.01% # attempts to use FU when none available 480system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.01% # attempts to use FU when none available 481system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.01% # attempts to use FU when none available 482system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.01% # attempts to use FU when none available 483system.cpu.iq.fu_full::MemRead 6546208 68.16% 73.16% # attempts to use FU when none available 484system.cpu.iq.fu_full::MemWrite 2577471 26.84% 100.00% # attempts to use FU when none available 485system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 486system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 487system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 488system.cpu.iq.FU_type_0::IntAlu 447771708 67.30% 67.30% # Type of FU issued 489system.cpu.iq.FU_type_0::IntMult 383310 0.06% 67.36% # Type of FU issued 490system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.36% # Type of FU issued 491system.cpu.iq.FU_type_0::FloatAdd 90 0.00% 67.36% # Type of FU issued 492system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.36% # Type of FU issued 493system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.36% # Type of FU issued 494system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.36% # Type of FU issued 495system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.36% # Type of FU issued 496system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.36% # Type of FU issued 497system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.36% # Type of FU issued 498system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.36% # Type of FU issued 499system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.36% # Type of FU issued 500system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.36% # Type of FU issued 501system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.36% # Type of FU issued 502system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.36% # Type of FU issued 503system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.36% # Type of FU issued 504system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.36% # Type of FU issued 505system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.36% # Type of FU issued 506system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.36% # Type of FU issued 507system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.36% # Type of FU issued 508system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.36% # Type of FU issued 509system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.36% # Type of FU issued 510system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.36% # Type of FU issued 511system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.36% # Type of FU issued 512system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.36% # Type of FU issued 513system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.36% # Type of FU issued 514system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.36% # Type of FU issued 515system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.36% # Type of FU issued 516system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.36% # Type of FU issued 517system.cpu.iq.FU_type_0::MemRead 153352638 23.05% 90.41% # Type of FU issued 518system.cpu.iq.FU_type_0::MemWrite 63793353 9.59% 100.00% # Type of FU issued 519system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 520system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 521system.cpu.iq.FU_type_0::total 665301102 # Type of FU issued 522system.cpu.iq.rate 1.644630 # Inst issue rate 523system.cpu.iq.fu_busy_cnt 9604666 # FU busy when requested 524system.cpu.iq.fu_busy_rate 0.014437 # FU busy rate (busy events/executed inst) 525system.cpu.iq.int_inst_queue_reads 1735853933 # Number of integer instruction queue reads 526system.cpu.iq.int_inst_queue_writes 946943275 # Number of integer instruction queue writes 527system.cpu.iq.int_inst_queue_wakeup_accesses 646028886 # Number of integer instruction queue wakeup accesses 528system.cpu.iq.fp_inst_queue_reads 215 # Number of floating instruction queue reads 529system.cpu.iq.fp_inst_queue_writes 292 # Number of floating instruction queue writes 530system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses 531system.cpu.iq.int_alu_accesses 674905659 # Number of integer alu accesses 532system.cpu.iq.fp_alu_accesses 109 # Number of floating point alu accesses 533system.cpu.iew.lsq.thread0.forwLoads 8552862 # Number of loads that had data forwarded from stores 534system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 535system.cpu.iew.lsq.thread0.squashedLoads 44226329 # Number of loads squashed 536system.cpu.iew.lsq.thread0.ignoredResponses 41059 # Number of memory responses ignored because the instruction is squashed 537system.cpu.iew.lsq.thread0.memOrderViolation 810522 # Number of memory ordering violations 538system.cpu.iew.lsq.thread0.squashedStores 16612335 # Number of stores squashed 539system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 540system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 541system.cpu.iew.lsq.thread0.rescheduledLoads 19495 # Number of loads that were rescheduled 542system.cpu.iew.lsq.thread0.cacheBlocked 7104 # Number of times an access to memory failed due to the cache being blocked 543system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 544system.cpu.iew.iewSquashCycles 27536360 # Number of cycles IEW is squashing 545system.cpu.iew.iewBlockCycles 5290664 # Number of cycles IEW is blocking 546system.cpu.iew.iewUnblockCycles 387489 # Number of cycles IEW is unblocking 547system.cpu.iew.iewDispatchedInsts 760356154 # Number of instructions dispatched to IQ 548system.cpu.iew.iewDispSquashedInsts 1118953 # Number of squashed instructions skipped by dispatch 549system.cpu.iew.iewDispLoadInsts 170255884 # Number of dispatched load instructions 550system.cpu.iew.iewDispStoreInsts 73472812 # Number of dispatched store instructions 551system.cpu.iew.iewDispNonSpecInsts 2286769 # Number of dispatched non-speculative instructions 552system.cpu.iew.iewIQFullEvents 219863 # Number of times the IQ has become full, causing a stall 553system.cpu.iew.iewLSQFullEvents 12400 # Number of times the LSQ has become full, causing a stall 554system.cpu.iew.memOrderViolationEvents 810522 # Number of memory order violations 555system.cpu.iew.predictedTakenIncorrect 4337912 # Number of branches that were predicted taken incorrectly 556system.cpu.iew.predictedNotTakenIncorrect 4002750 # Number of branches that were predicted not taken incorrectly 557system.cpu.iew.branchMispredicts 8340662 # Number of branch mispredicts detected at execute 558system.cpu.iew.iewExecutedInsts 655875003 # Number of executed instructions 559system.cpu.iew.iewExecLoadInsts 150077564 # Number of load instructions executed 560system.cpu.iew.iewExecSquashedInsts 9426099 # Number of squashed instructions skipped in execute 561system.cpu.iew.exec_swp 0 # number of swp insts executed 562system.cpu.iew.exec_nop 1558669 # number of nop insts executed 563system.cpu.iew.exec_refs 212570616 # number of memory reference insts executed 564system.cpu.iew.exec_branches 138493352 # Number of branches executed 565system.cpu.iew.exec_stores 62493052 # Number of stores executed 566system.cpu.iew.exec_rate 1.621328 # Inst execution rate 567system.cpu.iew.wb_sent 650999754 # cumulative count of insts sent to commit 568system.cpu.iew.wb_count 646028902 # cumulative count of insts written-back 569system.cpu.iew.wb_producers 374692861 # num instructions producing a value 570system.cpu.iew.wb_consumers 646290036 # num instructions consuming a value 571system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 572system.cpu.iew.wb_rate 1.596989 # insts written-back per cycle 573system.cpu.iew.wb_fanout 0.579760 # average fanout of values written-back 574system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 575system.cpu.commit.commitSquashedInsts 189414626 # The number of squashed insts skipped by commit 576system.cpu.commit.commitNonSpecStalls 2977632 # The number of times commit has been forced to stall to communicate backwards 577system.cpu.commit.branchMispredicts 7190929 # The number of times a branch was mispredicted 578system.cpu.commit.committed_per_cycle::samples 366730226 # Number of insts commited each cycle 579system.cpu.commit.committed_per_cycle::mean 1.556916 # Number of insts commited each cycle 580system.cpu.commit.committed_per_cycle::stdev 2.230567 # Number of insts commited each cycle 581system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 582system.cpu.commit.committed_per_cycle::0 159030510 43.36% 43.36% # Number of insts commited each cycle 583system.cpu.commit.committed_per_cycle::1 98471088 26.85% 70.22% # Number of insts commited each cycle 584system.cpu.commit.committed_per_cycle::2 33850160 9.23% 79.45% # Number of insts commited each cycle 585system.cpu.commit.committed_per_cycle::3 18801710 5.13% 84.57% # Number of insts commited each cycle 586system.cpu.commit.committed_per_cycle::4 16194042 4.42% 88.99% # Number of insts commited each cycle 587system.cpu.commit.committed_per_cycle::5 7449344 2.03% 91.02% # Number of insts commited each cycle 588system.cpu.commit.committed_per_cycle::6 6951093 1.90% 92.92% # Number of insts commited each cycle 589system.cpu.commit.committed_per_cycle::7 3196049 0.87% 93.79% # Number of insts commited each cycle 590system.cpu.commit.committed_per_cycle::8 22786230 6.21% 100.00% # Number of insts commited each cycle 591system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 592system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 593system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 594system.cpu.commit.committed_per_cycle::total 366730226 # Number of insts commited each cycle 595system.cpu.commit.committedInsts 506581607 # Number of instructions committed 596system.cpu.commit.committedOps 570968167 # Number of ops (including micro ops) committed 597system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 598system.cpu.commit.refs 182890032 # Number of memory references committed 599system.cpu.commit.loads 126029555 # Number of loads committed 600system.cpu.commit.membars 1488542 # Number of memory barriers committed 601system.cpu.commit.branches 121548301 # Number of branches committed 602system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. 603system.cpu.commit.int_insts 470727693 # Number of committed integer instructions. 604system.cpu.commit.function_calls 9757362 # Number of function calls committed. 605system.cpu.commit.bw_lim_events 22786230 # number cycles where commit BW limit reached 606system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 607system.cpu.rob.rob_reads 1104319651 # The number of ROB reads 608system.cpu.rob.rob_writes 1548423446 # The number of ROB writes 609system.cpu.timesIdled 327931 # Number of times that the entire CPU went into an idle state and unscheduled itself 610system.cpu.idleCycles 10262820 # Total number of cycles that the CPU has spent unscheduled due to idling 611system.cpu.committedInsts 505237723 # Number of Instructions Simulated 612system.cpu.committedOps 569624283 # Number of Ops (including micro ops) Simulated 613system.cpu.committedInsts_total 505237723 # Number of Instructions Simulated 614system.cpu.cpi 0.800671 # CPI: Cycles Per Instruction 615system.cpu.cpi_total 0.800671 # CPI: Total CPI of All Threads 616system.cpu.ipc 1.248952 # IPC: Instructions Per Cycle 617system.cpu.ipc_total 1.248952 # IPC: Total IPC of All Threads 618system.cpu.int_regfile_reads 3058568749 # number of integer regfile reads 619system.cpu.int_regfile_writes 751946172 # number of integer regfile writes 620system.cpu.fp_regfile_reads 16 # number of floating regfile reads 621system.cpu.misc_regfile_reads 210826056 # number of misc regfile reads 622system.cpu.misc_regfile_writes 2977084 # number of misc regfile writes 623system.cpu.toL2Bus.throughput 735267470 # Throughput (bytes/s) 624system.cpu.toL2Bus.trans_dist::ReadReq 864400 # Transaction distribution 625system.cpu.toL2Bus.trans_dist::ReadResp 864399 # Transaction distribution 626system.cpu.toL2Bus.trans_dist::Writeback 1110556 # Transaction distribution 627system.cpu.toL2Bus.trans_dist::UpgradeReq 92 # Transaction distribution 628system.cpu.toL2Bus.trans_dist::UpgradeResp 92 # Transaction distribution 629system.cpu.toL2Bus.trans_dist::ReadExReq 348774 # Transaction distribution 630system.cpu.toL2Bus.trans_dist::ReadExResp 348774 # Transaction distribution 631system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 33891 # Packet count per connected master and slave (bytes) 632system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 3503090 # Packet count per connected master and slave (bytes) 633system.cpu.toL2Bus.pkt_count 3536981 # Packet count per connected master and slave (bytes) 634system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 1081088 # Cumulative packet size per connected master and slave (bytes) 635system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 147630784 # Cumulative packet size per connected master and slave (bytes) 636system.cpu.toL2Bus.tot_pkt_size 148711872 # Cumulative packet size per connected master and slave (bytes) 637system.cpu.toL2Bus.data_through_bus 148711872 # Total data (bytes) 638system.cpu.toL2Bus.snoop_data_through_bus 6784 # Total snoop data (bytes) 639system.cpu.toL2Bus.reqLayer0.occupancy 2272470744 # Layer occupancy (ticks) 640system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) 641system.cpu.toL2Bus.respLayer0.occupancy 25507479 # Layer occupancy (ticks) 642system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 643system.cpu.toL2Bus.respLayer1.occupancy 1794320975 # Layer occupancy (ticks) 644system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) 645system.cpu.icache.replacements 15058 # number of replacements 646system.cpu.icache.tagsinuse 1102.051233 # Cycle average of tags in use 647system.cpu.icache.total_refs 114501571 # Total number of references to valid blocks. 648system.cpu.icache.sampled_refs 16910 # Sample count of references to valid blocks. 649system.cpu.icache.avg_refs 6771.234240 # Average number of references to valid blocks. 650system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 651system.cpu.icache.occ_blocks::cpu.inst 1102.051233 # Average occupied blocks per requestor 652system.cpu.icache.occ_percent::cpu.inst 0.538111 # Average percentage of cache occupancy 653system.cpu.icache.occ_percent::total 0.538111 # Average percentage of cache occupancy 654system.cpu.icache.ReadReq_hits::cpu.inst 114501582 # number of ReadReq hits 655system.cpu.icache.ReadReq_hits::total 114501582 # number of ReadReq hits 656system.cpu.icache.demand_hits::cpu.inst 114501582 # number of demand (read+write) hits 657system.cpu.icache.demand_hits::total 114501582 # number of demand (read+write) hits 658system.cpu.icache.overall_hits::cpu.inst 114501582 # number of overall hits 659system.cpu.icache.overall_hits::total 114501582 # number of overall hits 660system.cpu.icache.ReadReq_misses::cpu.inst 21259 # number of ReadReq misses 661system.cpu.icache.ReadReq_misses::total 21259 # number of ReadReq misses 662system.cpu.icache.demand_misses::cpu.inst 21259 # number of demand (read+write) misses 663system.cpu.icache.demand_misses::total 21259 # number of demand (read+write) misses 664system.cpu.icache.overall_misses::cpu.inst 21259 # number of overall misses 665system.cpu.icache.overall_misses::total 21259 # number of overall misses 666system.cpu.icache.ReadReq_miss_latency::cpu.inst 595415500 # number of ReadReq miss cycles 667system.cpu.icache.ReadReq_miss_latency::total 595415500 # number of ReadReq miss cycles 668system.cpu.icache.demand_miss_latency::cpu.inst 595415500 # number of demand (read+write) miss cycles 669system.cpu.icache.demand_miss_latency::total 595415500 # number of demand (read+write) miss cycles 670system.cpu.icache.overall_miss_latency::cpu.inst 595415500 # number of overall miss cycles 671system.cpu.icache.overall_miss_latency::total 595415500 # number of overall miss cycles 672system.cpu.icache.ReadReq_accesses::cpu.inst 114522841 # number of ReadReq accesses(hits+misses) 673system.cpu.icache.ReadReq_accesses::total 114522841 # number of ReadReq accesses(hits+misses) 674system.cpu.icache.demand_accesses::cpu.inst 114522841 # number of demand (read+write) accesses 675system.cpu.icache.demand_accesses::total 114522841 # number of demand (read+write) accesses 676system.cpu.icache.overall_accesses::cpu.inst 114522841 # number of overall (read+write) accesses 677system.cpu.icache.overall_accesses::total 114522841 # number of overall (read+write) accesses 678system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000186 # miss rate for ReadReq accesses 679system.cpu.icache.ReadReq_miss_rate::total 0.000186 # miss rate for ReadReq accesses 680system.cpu.icache.demand_miss_rate::cpu.inst 0.000186 # miss rate for demand accesses 681system.cpu.icache.demand_miss_rate::total 0.000186 # miss rate for demand accesses 682system.cpu.icache.overall_miss_rate::cpu.inst 0.000186 # miss rate for overall accesses 683system.cpu.icache.overall_miss_rate::total 0.000186 # miss rate for overall accesses 684system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28007.690860 # average ReadReq miss latency 685system.cpu.icache.ReadReq_avg_miss_latency::total 28007.690860 # average ReadReq miss latency 686system.cpu.icache.demand_avg_miss_latency::cpu.inst 28007.690860 # average overall miss latency 687system.cpu.icache.demand_avg_miss_latency::total 28007.690860 # average overall miss latency 688system.cpu.icache.overall_avg_miss_latency::cpu.inst 28007.690860 # average overall miss latency 689system.cpu.icache.overall_avg_miss_latency::total 28007.690860 # average overall miss latency 690system.cpu.icache.blocked_cycles::no_mshrs 2365 # number of cycles access was blocked 691system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 692system.cpu.icache.blocked::no_mshrs 13 # number of cycles access was blocked 693system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 694system.cpu.icache.avg_blocked_cycles::no_mshrs 181.923077 # average number of cycles each access was blocked 695system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 696system.cpu.icache.fast_writes 0 # number of fast writes performed 697system.cpu.icache.cache_copies 0 # number of cache copies performed 698system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4260 # number of ReadReq MSHR hits 699system.cpu.icache.ReadReq_mshr_hits::total 4260 # number of ReadReq MSHR hits 700system.cpu.icache.demand_mshr_hits::cpu.inst 4260 # number of demand (read+write) MSHR hits 701system.cpu.icache.demand_mshr_hits::total 4260 # number of demand (read+write) MSHR hits 702system.cpu.icache.overall_mshr_hits::cpu.inst 4260 # number of overall MSHR hits 703system.cpu.icache.overall_mshr_hits::total 4260 # number of overall MSHR hits 704system.cpu.icache.ReadReq_mshr_misses::cpu.inst 16999 # number of ReadReq MSHR misses 705system.cpu.icache.ReadReq_mshr_misses::total 16999 # number of ReadReq MSHR misses 706system.cpu.icache.demand_mshr_misses::cpu.inst 16999 # number of demand (read+write) MSHR misses 707system.cpu.icache.demand_mshr_misses::total 16999 # number of demand (read+write) MSHR misses 708system.cpu.icache.overall_mshr_misses::cpu.inst 16999 # number of overall MSHR misses 709system.cpu.icache.overall_mshr_misses::total 16999 # number of overall MSHR misses 710system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 426747521 # number of ReadReq MSHR miss cycles 711system.cpu.icache.ReadReq_mshr_miss_latency::total 426747521 # number of ReadReq MSHR miss cycles 712system.cpu.icache.demand_mshr_miss_latency::cpu.inst 426747521 # number of demand (read+write) MSHR miss cycles 713system.cpu.icache.demand_mshr_miss_latency::total 426747521 # number of demand (read+write) MSHR miss cycles 714system.cpu.icache.overall_mshr_miss_latency::cpu.inst 426747521 # number of overall MSHR miss cycles 715system.cpu.icache.overall_mshr_miss_latency::total 426747521 # number of overall MSHR miss cycles 716system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000148 # mshr miss rate for ReadReq accesses 717system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000148 # mshr miss rate for ReadReq accesses 718system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000148 # mshr miss rate for demand accesses 719system.cpu.icache.demand_mshr_miss_rate::total 0.000148 # mshr miss rate for demand accesses 720system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000148 # mshr miss rate for overall accesses 721system.cpu.icache.overall_mshr_miss_rate::total 0.000148 # mshr miss rate for overall accesses 722system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 25104.272075 # average ReadReq mshr miss latency 723system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 25104.272075 # average ReadReq mshr miss latency 724system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 25104.272075 # average overall mshr miss latency 725system.cpu.icache.demand_avg_mshr_miss_latency::total 25104.272075 # average overall mshr miss latency 726system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 25104.272075 # average overall mshr miss latency 727system.cpu.icache.overall_avg_mshr_miss_latency::total 25104.272075 # average overall mshr miss latency 728system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 729system.cpu.l2cache.replacements 115327 # number of replacements 730system.cpu.l2cache.tagsinuse 27103.990610 # Cycle average of tags in use 731system.cpu.l2cache.total_refs 1780423 # Total number of references to valid blocks. 732system.cpu.l2cache.sampled_refs 146587 # Sample count of references to valid blocks. 733system.cpu.l2cache.avg_refs 12.145845 # Average number of references to valid blocks. 734system.cpu.l2cache.warmup_cycle 89762160000 # Cycle when the warmup percentage was hit. 735system.cpu.l2cache.occ_blocks::writebacks 23023.222015 # Average occupied blocks per requestor 736system.cpu.l2cache.occ_blocks::cpu.inst 362.369972 # Average occupied blocks per requestor 737system.cpu.l2cache.occ_blocks::cpu.data 3718.398623 # Average occupied blocks per requestor 738system.cpu.l2cache.occ_percent::writebacks 0.702613 # Average percentage of cache occupancy 739system.cpu.l2cache.occ_percent::cpu.inst 0.011059 # Average percentage of cache occupancy 740system.cpu.l2cache.occ_percent::cpu.data 0.113477 # Average percentage of cache occupancy 741system.cpu.l2cache.occ_percent::total 0.827148 # Average percentage of cache occupancy 742system.cpu.l2cache.ReadReq_hits::cpu.inst 13513 # number of ReadReq hits 743system.cpu.l2cache.ReadReq_hits::cpu.data 803960 # number of ReadReq hits 744system.cpu.l2cache.ReadReq_hits::total 817473 # number of ReadReq hits 745system.cpu.l2cache.Writeback_hits::writebacks 1110556 # number of Writeback hits 746system.cpu.l2cache.Writeback_hits::total 1110556 # number of Writeback hits 747system.cpu.l2cache.UpgradeReq_hits::cpu.data 83 # number of UpgradeReq hits 748system.cpu.l2cache.UpgradeReq_hits::total 83 # number of UpgradeReq hits 749system.cpu.l2cache.ReadExReq_hits::cpu.data 247491 # number of ReadExReq hits 750system.cpu.l2cache.ReadExReq_hits::total 247491 # number of ReadExReq hits 751system.cpu.l2cache.demand_hits::cpu.inst 13513 # number of demand (read+write) hits 752system.cpu.l2cache.demand_hits::cpu.data 1051451 # number of demand (read+write) hits 753system.cpu.l2cache.demand_hits::total 1064964 # number of demand (read+write) hits 754system.cpu.l2cache.overall_hits::cpu.inst 13513 # number of overall hits 755system.cpu.l2cache.overall_hits::cpu.data 1051451 # number of overall hits 756system.cpu.l2cache.overall_hits::total 1064964 # number of overall hits 757system.cpu.l2cache.ReadReq_misses::cpu.inst 3380 # number of ReadReq misses 758system.cpu.l2cache.ReadReq_misses::cpu.data 43441 # number of ReadReq misses 759system.cpu.l2cache.ReadReq_misses::total 46821 # number of ReadReq misses 760system.cpu.l2cache.UpgradeReq_misses::cpu.data 9 # number of UpgradeReq misses 761system.cpu.l2cache.UpgradeReq_misses::total 9 # number of UpgradeReq misses 762system.cpu.l2cache.ReadExReq_misses::cpu.data 101283 # number of ReadExReq misses 763system.cpu.l2cache.ReadExReq_misses::total 101283 # number of ReadExReq misses 764system.cpu.l2cache.demand_misses::cpu.inst 3380 # number of demand (read+write) misses 765system.cpu.l2cache.demand_misses::cpu.data 144724 # number of demand (read+write) misses 766system.cpu.l2cache.demand_misses::total 148104 # number of demand (read+write) misses 767system.cpu.l2cache.overall_misses::cpu.inst 3380 # number of overall misses 768system.cpu.l2cache.overall_misses::cpu.data 144724 # number of overall misses 769system.cpu.l2cache.overall_misses::total 148104 # number of overall misses 770system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 274234000 # number of ReadReq miss cycles 771system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3645115500 # number of ReadReq miss cycles 772system.cpu.l2cache.ReadReq_miss_latency::total 3919349500 # number of ReadReq miss cycles 773system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 22500 # number of UpgradeReq miss cycles 774system.cpu.l2cache.UpgradeReq_miss_latency::total 22500 # number of UpgradeReq miss cycles 775system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7042551500 # number of ReadExReq miss cycles 776system.cpu.l2cache.ReadExReq_miss_latency::total 7042551500 # number of ReadExReq miss cycles 777system.cpu.l2cache.demand_miss_latency::cpu.inst 274234000 # number of demand (read+write) miss cycles 778system.cpu.l2cache.demand_miss_latency::cpu.data 10687667000 # number of demand (read+write) miss cycles 779system.cpu.l2cache.demand_miss_latency::total 10961901000 # number of demand (read+write) miss cycles 780system.cpu.l2cache.overall_miss_latency::cpu.inst 274234000 # number of overall miss cycles 781system.cpu.l2cache.overall_miss_latency::cpu.data 10687667000 # number of overall miss cycles 782system.cpu.l2cache.overall_miss_latency::total 10961901000 # number of overall miss cycles 783system.cpu.l2cache.ReadReq_accesses::cpu.inst 16893 # number of ReadReq accesses(hits+misses) 784system.cpu.l2cache.ReadReq_accesses::cpu.data 847401 # number of ReadReq accesses(hits+misses) 785system.cpu.l2cache.ReadReq_accesses::total 864294 # number of ReadReq accesses(hits+misses) 786system.cpu.l2cache.Writeback_accesses::writebacks 1110556 # number of Writeback accesses(hits+misses) 787system.cpu.l2cache.Writeback_accesses::total 1110556 # number of Writeback accesses(hits+misses) 788system.cpu.l2cache.UpgradeReq_accesses::cpu.data 92 # number of UpgradeReq accesses(hits+misses) 789system.cpu.l2cache.UpgradeReq_accesses::total 92 # number of UpgradeReq accesses(hits+misses) 790system.cpu.l2cache.ReadExReq_accesses::cpu.data 348774 # number of ReadExReq accesses(hits+misses) 791system.cpu.l2cache.ReadExReq_accesses::total 348774 # number of ReadExReq accesses(hits+misses) 792system.cpu.l2cache.demand_accesses::cpu.inst 16893 # number of demand (read+write) accesses 793system.cpu.l2cache.demand_accesses::cpu.data 1196175 # number of demand (read+write) accesses 794system.cpu.l2cache.demand_accesses::total 1213068 # number of demand (read+write) accesses 795system.cpu.l2cache.overall_accesses::cpu.inst 16893 # number of overall (read+write) accesses 796system.cpu.l2cache.overall_accesses::cpu.data 1196175 # number of overall (read+write) accesses 797system.cpu.l2cache.overall_accesses::total 1213068 # number of overall (read+write) accesses 798system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.200083 # miss rate for ReadReq accesses 799system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.051264 # miss rate for ReadReq accesses 800system.cpu.l2cache.ReadReq_miss_rate::total 0.054173 # miss rate for ReadReq accesses 801system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.097826 # miss rate for UpgradeReq accesses 802system.cpu.l2cache.UpgradeReq_miss_rate::total 0.097826 # miss rate for UpgradeReq accesses 803system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.290397 # miss rate for ReadExReq accesses 804system.cpu.l2cache.ReadExReq_miss_rate::total 0.290397 # miss rate for ReadExReq accesses 805system.cpu.l2cache.demand_miss_rate::cpu.inst 0.200083 # miss rate for demand accesses 806system.cpu.l2cache.demand_miss_rate::cpu.data 0.120989 # miss rate for demand accesses 807system.cpu.l2cache.demand_miss_rate::total 0.122090 # miss rate for demand accesses 808system.cpu.l2cache.overall_miss_rate::cpu.inst 0.200083 # miss rate for overall accesses 809system.cpu.l2cache.overall_miss_rate::cpu.data 0.120989 # miss rate for overall accesses 810system.cpu.l2cache.overall_miss_rate::total 0.122090 # miss rate for overall accesses 811system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 81134.319527 # average ReadReq miss latency 812system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 83909.566999 # average ReadReq miss latency 813system.cpu.l2cache.ReadReq_avg_miss_latency::total 83709.222357 # average ReadReq miss latency 814system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 2500 # average UpgradeReq miss latency 815system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 2500 # average UpgradeReq miss latency 816system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69533.401459 # average ReadExReq miss latency 817system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69533.401459 # average ReadExReq miss latency 818system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 81134.319527 # average overall miss latency 819system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73848.615295 # average overall miss latency 820system.cpu.l2cache.demand_avg_miss_latency::total 74014.888187 # average overall miss latency 821system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 81134.319527 # average overall miss latency 822system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73848.615295 # average overall miss latency 823system.cpu.l2cache.overall_avg_miss_latency::total 74014.888187 # average overall miss latency 824system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 825system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 826system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 827system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 828system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 829system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 830system.cpu.l2cache.fast_writes 0 # number of fast writes performed 831system.cpu.l2cache.cache_copies 0 # number of cache copies performed 832system.cpu.l2cache.writebacks::writebacks 97594 # number of writebacks 833system.cpu.l2cache.writebacks::total 97594 # number of writebacks 834system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 4 # number of ReadReq MSHR hits 835system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 22 # number of ReadReq MSHR hits 836system.cpu.l2cache.ReadReq_mshr_hits::total 26 # number of ReadReq MSHR hits 837system.cpu.l2cache.demand_mshr_hits::cpu.inst 4 # number of demand (read+write) MSHR hits 838system.cpu.l2cache.demand_mshr_hits::cpu.data 22 # number of demand (read+write) MSHR hits 839system.cpu.l2cache.demand_mshr_hits::total 26 # number of demand (read+write) MSHR hits 840system.cpu.l2cache.overall_mshr_hits::cpu.inst 4 # number of overall MSHR hits 841system.cpu.l2cache.overall_mshr_hits::cpu.data 22 # number of overall MSHR hits 842system.cpu.l2cache.overall_mshr_hits::total 26 # number of overall MSHR hits 843system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3376 # number of ReadReq MSHR misses 844system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 43419 # number of ReadReq MSHR misses 845system.cpu.l2cache.ReadReq_mshr_misses::total 46795 # number of ReadReq MSHR misses 846system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 9 # number of UpgradeReq MSHR misses 847system.cpu.l2cache.UpgradeReq_mshr_misses::total 9 # number of UpgradeReq MSHR misses 848system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 101283 # number of ReadExReq MSHR misses 849system.cpu.l2cache.ReadExReq_mshr_misses::total 101283 # number of ReadExReq MSHR misses 850system.cpu.l2cache.demand_mshr_misses::cpu.inst 3376 # number of demand (read+write) MSHR misses 851system.cpu.l2cache.demand_mshr_misses::cpu.data 144702 # number of demand (read+write) MSHR misses 852system.cpu.l2cache.demand_mshr_misses::total 148078 # number of demand (read+write) MSHR misses 853system.cpu.l2cache.overall_mshr_misses::cpu.inst 3376 # number of overall MSHR misses 854system.cpu.l2cache.overall_mshr_misses::cpu.data 144702 # number of overall MSHR misses 855system.cpu.l2cache.overall_mshr_misses::total 148078 # number of overall MSHR misses 856system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 231774000 # number of ReadReq MSHR miss cycles 857system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3104828000 # number of ReadReq MSHR miss cycles 858system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3336602000 # number of ReadReq MSHR miss cycles 859system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 94508 # number of UpgradeReq MSHR miss cycles 860system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 94508 # number of UpgradeReq MSHR miss cycles 861system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5779215000 # number of ReadExReq MSHR miss cycles 862system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5779215000 # number of ReadExReq MSHR miss cycles 863system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 231774000 # number of demand (read+write) MSHR miss cycles 864system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8884043000 # number of demand (read+write) MSHR miss cycles 865system.cpu.l2cache.demand_mshr_miss_latency::total 9115817000 # number of demand (read+write) MSHR miss cycles 866system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 231774000 # number of overall MSHR miss cycles 867system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8884043000 # number of overall MSHR miss cycles 868system.cpu.l2cache.overall_mshr_miss_latency::total 9115817000 # number of overall MSHR miss cycles 869system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.199846 # mshr miss rate for ReadReq accesses 870system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.051238 # mshr miss rate for ReadReq accesses 871system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.054142 # mshr miss rate for ReadReq accesses 872system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.097826 # mshr miss rate for UpgradeReq accesses 873system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.097826 # mshr miss rate for UpgradeReq accesses 874system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.290397 # mshr miss rate for ReadExReq accesses 875system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.290397 # mshr miss rate for ReadExReq accesses 876system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.199846 # mshr miss rate for demand accesses 877system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.120971 # mshr miss rate for demand accesses 878system.cpu.l2cache.demand_mshr_miss_rate::total 0.122069 # mshr miss rate for demand accesses 879system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.199846 # mshr miss rate for overall accesses 880system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.120971 # mshr miss rate for overall accesses 881system.cpu.l2cache.overall_mshr_miss_rate::total 0.122069 # mshr miss rate for overall accesses 882system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 68653.436019 # average ReadReq mshr miss latency 883system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 71508.510099 # average ReadReq mshr miss latency 884system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 71302.532322 # average ReadReq mshr miss latency 885system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10500.888889 # average UpgradeReq mshr miss latency 886system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10500.888889 # average UpgradeReq mshr miss latency 887system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57060.069311 # average ReadExReq mshr miss latency 888system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57060.069311 # average ReadExReq mshr miss latency 889system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68653.436019 # average overall mshr miss latency 890system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61395.440284 # average overall mshr miss latency 891system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61560.913843 # average overall mshr miss latency 892system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68653.436019 # average overall mshr miss latency 893system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61395.440284 # average overall mshr miss latency 894system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61560.913843 # average overall mshr miss latency 895system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 896system.cpu.dcache.replacements 1192079 # number of replacements 897system.cpu.dcache.tagsinuse 4057.787384 # Cycle average of tags in use 898system.cpu.dcache.total_refs 190170418 # Total number of references to valid blocks. 899system.cpu.dcache.sampled_refs 1196175 # Sample count of references to valid blocks. 900system.cpu.dcache.avg_refs 158.982104 # Average number of references to valid blocks. 901system.cpu.dcache.warmup_cycle 4220492000 # Cycle when the warmup percentage was hit. 902system.cpu.dcache.occ_blocks::cpu.data 4057.787384 # Average occupied blocks per requestor 903system.cpu.dcache.occ_percent::cpu.data 0.990671 # Average percentage of cache occupancy 904system.cpu.dcache.occ_percent::total 0.990671 # Average percentage of cache occupancy 905system.cpu.dcache.ReadReq_hits::cpu.data 136204469 # number of ReadReq hits 906system.cpu.dcache.ReadReq_hits::total 136204469 # number of ReadReq hits 907system.cpu.dcache.WriteReq_hits::cpu.data 50988281 # number of WriteReq hits 908system.cpu.dcache.WriteReq_hits::total 50988281 # number of WriteReq hits 909system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488831 # number of LoadLockedReq hits 910system.cpu.dcache.LoadLockedReq_hits::total 1488831 # number of LoadLockedReq hits 911system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits 912system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits 913system.cpu.dcache.demand_hits::cpu.data 187192750 # number of demand (read+write) hits 914system.cpu.dcache.demand_hits::total 187192750 # number of demand (read+write) hits 915system.cpu.dcache.overall_hits::cpu.data 187192750 # number of overall hits 916system.cpu.dcache.overall_hits::total 187192750 # number of overall hits 917system.cpu.dcache.ReadReq_misses::cpu.data 1701442 # number of ReadReq misses 918system.cpu.dcache.ReadReq_misses::total 1701442 # number of ReadReq misses 919system.cpu.dcache.WriteReq_misses::cpu.data 3251025 # number of WriteReq misses 920system.cpu.dcache.WriteReq_misses::total 3251025 # number of WriteReq misses 921system.cpu.dcache.LoadLockedReq_misses::cpu.data 38 # number of LoadLockedReq misses 922system.cpu.dcache.LoadLockedReq_misses::total 38 # number of LoadLockedReq misses 923system.cpu.dcache.demand_misses::cpu.data 4952467 # number of demand (read+write) misses 924system.cpu.dcache.demand_misses::total 4952467 # number of demand (read+write) misses 925system.cpu.dcache.overall_misses::cpu.data 4952467 # number of overall misses 926system.cpu.dcache.overall_misses::total 4952467 # number of overall misses 927system.cpu.dcache.ReadReq_miss_latency::cpu.data 29643398500 # number of ReadReq miss cycles 928system.cpu.dcache.ReadReq_miss_latency::total 29643398500 # number of ReadReq miss cycles 929system.cpu.dcache.WriteReq_miss_latency::cpu.data 68982804444 # number of WriteReq miss cycles 930system.cpu.dcache.WriteReq_miss_latency::total 68982804444 # number of WriteReq miss cycles 931system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 639500 # number of LoadLockedReq miss cycles 932system.cpu.dcache.LoadLockedReq_miss_latency::total 639500 # number of LoadLockedReq miss cycles 933system.cpu.dcache.demand_miss_latency::cpu.data 98626202944 # number of demand (read+write) miss cycles 934system.cpu.dcache.demand_miss_latency::total 98626202944 # number of demand (read+write) miss cycles 935system.cpu.dcache.overall_miss_latency::cpu.data 98626202944 # number of overall miss cycles 936system.cpu.dcache.overall_miss_latency::total 98626202944 # number of overall miss cycles 937system.cpu.dcache.ReadReq_accesses::cpu.data 137905911 # number of ReadReq accesses(hits+misses) 938system.cpu.dcache.ReadReq_accesses::total 137905911 # number of ReadReq accesses(hits+misses) 939system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) 940system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) 941system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488869 # number of LoadLockedReq accesses(hits+misses) 942system.cpu.dcache.LoadLockedReq_accesses::total 1488869 # number of LoadLockedReq accesses(hits+misses) 943system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) 944system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) 945system.cpu.dcache.demand_accesses::cpu.data 192145217 # number of demand (read+write) accesses 946system.cpu.dcache.demand_accesses::total 192145217 # number of demand (read+write) accesses 947system.cpu.dcache.overall_accesses::cpu.data 192145217 # number of overall (read+write) accesses 948system.cpu.dcache.overall_accesses::total 192145217 # number of overall (read+write) accesses 949system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012338 # miss rate for ReadReq accesses 950system.cpu.dcache.ReadReq_miss_rate::total 0.012338 # miss rate for ReadReq accesses 951system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.059939 # miss rate for WriteReq accesses 952system.cpu.dcache.WriteReq_miss_rate::total 0.059939 # miss rate for WriteReq accesses 953system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000026 # miss rate for LoadLockedReq accesses 954system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000026 # miss rate for LoadLockedReq accesses 955system.cpu.dcache.demand_miss_rate::cpu.data 0.025775 # miss rate for demand accesses 956system.cpu.dcache.demand_miss_rate::total 0.025775 # miss rate for demand accesses 957system.cpu.dcache.overall_miss_rate::cpu.data 0.025775 # miss rate for overall accesses 958system.cpu.dcache.overall_miss_rate::total 0.025775 # miss rate for overall accesses 959system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17422.514843 # average ReadReq miss latency 960system.cpu.dcache.ReadReq_avg_miss_latency::total 17422.514843 # average ReadReq miss latency 961system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 21218.786212 # average WriteReq miss latency 962system.cpu.dcache.WriteReq_avg_miss_latency::total 21218.786212 # average WriteReq miss latency 963system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16828.947368 # average LoadLockedReq miss latency 964system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16828.947368 # average LoadLockedReq miss latency 965system.cpu.dcache.demand_avg_miss_latency::cpu.data 19914.560348 # average overall miss latency 966system.cpu.dcache.demand_avg_miss_latency::total 19914.560348 # average overall miss latency 967system.cpu.dcache.overall_avg_miss_latency::cpu.data 19914.560348 # average overall miss latency 968system.cpu.dcache.overall_avg_miss_latency::total 19914.560348 # average overall miss latency 969system.cpu.dcache.blocked_cycles::no_mshrs 17857 # number of cycles access was blocked 970system.cpu.dcache.blocked_cycles::no_targets 40598 # number of cycles access was blocked 971system.cpu.dcache.blocked::no_mshrs 1694 # number of cycles access was blocked 972system.cpu.dcache.blocked::no_targets 662 # number of cycles access was blocked 973system.cpu.dcache.avg_blocked_cycles::no_mshrs 10.541322 # average number of cycles each access was blocked 974system.cpu.dcache.avg_blocked_cycles::no_targets 61.326284 # average number of cycles each access was blocked 975system.cpu.dcache.fast_writes 0 # number of fast writes performed 976system.cpu.dcache.cache_copies 0 # number of cache copies performed 977system.cpu.dcache.writebacks::writebacks 1110556 # number of writebacks 978system.cpu.dcache.writebacks::total 1110556 # number of writebacks 979system.cpu.dcache.ReadReq_mshr_hits::cpu.data 853509 # number of ReadReq MSHR hits 980system.cpu.dcache.ReadReq_mshr_hits::total 853509 # number of ReadReq MSHR hits 981system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2902691 # number of WriteReq MSHR hits 982system.cpu.dcache.WriteReq_mshr_hits::total 2902691 # number of WriteReq MSHR hits 983system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 38 # number of LoadLockedReq MSHR hits 984system.cpu.dcache.LoadLockedReq_mshr_hits::total 38 # number of LoadLockedReq MSHR hits 985system.cpu.dcache.demand_mshr_hits::cpu.data 3756200 # number of demand (read+write) MSHR hits 986system.cpu.dcache.demand_mshr_hits::total 3756200 # number of demand (read+write) MSHR hits 987system.cpu.dcache.overall_mshr_hits::cpu.data 3756200 # number of overall MSHR hits 988system.cpu.dcache.overall_mshr_hits::total 3756200 # number of overall MSHR hits 989system.cpu.dcache.ReadReq_mshr_misses::cpu.data 847933 # number of ReadReq MSHR misses 990system.cpu.dcache.ReadReq_mshr_misses::total 847933 # number of ReadReq MSHR misses 991system.cpu.dcache.WriteReq_mshr_misses::cpu.data 348334 # number of WriteReq MSHR misses 992system.cpu.dcache.WriteReq_mshr_misses::total 348334 # number of WriteReq MSHR misses 993system.cpu.dcache.demand_mshr_misses::cpu.data 1196267 # number of demand (read+write) MSHR misses 994system.cpu.dcache.demand_mshr_misses::total 1196267 # number of demand (read+write) MSHR misses 995system.cpu.dcache.overall_mshr_misses::cpu.data 1196267 # number of overall MSHR misses 996system.cpu.dcache.overall_mshr_misses::total 1196267 # number of overall MSHR misses 997system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12570935024 # number of ReadReq MSHR miss cycles 998system.cpu.dcache.ReadReq_mshr_miss_latency::total 12570935024 # number of ReadReq MSHR miss cycles 999system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9915738995 # number of WriteReq MSHR miss cycles 1000system.cpu.dcache.WriteReq_mshr_miss_latency::total 9915738995 # number of WriteReq MSHR miss cycles 1001system.cpu.dcache.demand_mshr_miss_latency::cpu.data 22486674019 # number of demand (read+write) MSHR miss cycles 1002system.cpu.dcache.demand_mshr_miss_latency::total 22486674019 # number of demand (read+write) MSHR miss cycles 1003system.cpu.dcache.overall_mshr_miss_latency::cpu.data 22486674019 # number of overall MSHR miss cycles 1004system.cpu.dcache.overall_mshr_miss_latency::total 22486674019 # number of overall MSHR miss cycles 1005system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006149 # mshr miss rate for ReadReq accesses 1006system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006149 # mshr miss rate for ReadReq accesses 1007system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006422 # mshr miss rate for WriteReq accesses 1008system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006422 # mshr miss rate for WriteReq accesses 1009system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006226 # mshr miss rate for demand accesses 1010system.cpu.dcache.demand_mshr_miss_rate::total 0.006226 # mshr miss rate for demand accesses 1011system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006226 # mshr miss rate for overall accesses 1012system.cpu.dcache.overall_mshr_miss_rate::total 0.006226 # mshr miss rate for overall accesses 1013system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14825.387176 # average ReadReq mshr miss latency 1014system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14825.387176 # average ReadReq mshr miss latency 1015system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28466.181869 # average WriteReq mshr miss latency 1016system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28466.181869 # average WriteReq mshr miss latency 1017system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18797.370503 # average overall mshr miss latency 1018system.cpu.dcache.demand_avg_mshr_miss_latency::total 18797.370503 # average overall mshr miss latency 1019system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18797.370503 # average overall mshr miss latency 1020system.cpu.dcache.overall_avg_mshr_miss_latency::total 18797.370503 # average overall mshr miss latency 1021system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1022 1023---------- End Simulation Statistics ---------- 1024