stats.txt revision 9285:9901180cd573
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.201852 # Number of seconds simulated 4sim_ticks 201852280500 # Number of ticks simulated 5final_tick 201852280500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 114620 # Simulator instruction rate (inst/s) 8host_op_rate 129121 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 45458575 # Simulator tick rate (ticks/s) 10host_mem_usage 239092 # Number of bytes of host memory used 11host_seconds 4440.36 # Real time elapsed on the host 12sim_insts 508955133 # Number of instructions simulated 13sim_ops 573341693 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 218816 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 10015872 # Number of bytes read from this memory 16system.physmem.bytes_read::total 10234688 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 218816 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 218816 # Number of instructions bytes read from this memory 19system.physmem.bytes_written::writebacks 6679360 # Number of bytes written to this memory 20system.physmem.bytes_written::total 6679360 # Number of bytes written to this memory 21system.physmem.num_reads::cpu.inst 3419 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 156498 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 159917 # Number of read requests responded to by this memory 24system.physmem.num_writes::writebacks 104365 # Number of write requests responded to by this memory 25system.physmem.num_writes::total 104365 # Number of write requests responded to by this memory 26system.physmem.bw_read::cpu.inst 1084040 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::cpu.data 49619811 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_read::total 50703851 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::cpu.inst 1084040 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_inst_read::total 1084040 # Instruction read bandwidth from this memory (bytes/s) 31system.physmem.bw_write::writebacks 33090337 # Write bandwidth from this memory (bytes/s) 32system.physmem.bw_write::total 33090337 # Write bandwidth from this memory (bytes/s) 33system.physmem.bw_total::writebacks 33090337 # Total bandwidth to/from this memory (bytes/s) 34system.physmem.bw_total::cpu.inst 1084040 # Total bandwidth to/from this memory (bytes/s) 35system.physmem.bw_total::cpu.data 49619811 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::total 83794188 # Total bandwidth to/from this memory (bytes/s) 37system.cpu.dtb.inst_hits 0 # ITB inst hits 38system.cpu.dtb.inst_misses 0 # ITB inst misses 39system.cpu.dtb.read_hits 0 # DTB read hits 40system.cpu.dtb.read_misses 0 # DTB read misses 41system.cpu.dtb.write_hits 0 # DTB write hits 42system.cpu.dtb.write_misses 0 # DTB write misses 43system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 44system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 45system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 46system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 47system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 48system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 49system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 50system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 51system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 52system.cpu.dtb.read_accesses 0 # DTB read accesses 53system.cpu.dtb.write_accesses 0 # DTB write accesses 54system.cpu.dtb.inst_accesses 0 # ITB inst accesses 55system.cpu.dtb.hits 0 # DTB hits 56system.cpu.dtb.misses 0 # DTB misses 57system.cpu.dtb.accesses 0 # DTB accesses 58system.cpu.itb.inst_hits 0 # ITB inst hits 59system.cpu.itb.inst_misses 0 # ITB inst misses 60system.cpu.itb.read_hits 0 # DTB read hits 61system.cpu.itb.read_misses 0 # DTB read misses 62system.cpu.itb.write_hits 0 # DTB write hits 63system.cpu.itb.write_misses 0 # DTB write misses 64system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 65system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 66system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 67system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 68system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 69system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 70system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 71system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 72system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 73system.cpu.itb.read_accesses 0 # DTB read accesses 74system.cpu.itb.write_accesses 0 # DTB write accesses 75system.cpu.itb.inst_accesses 0 # ITB inst accesses 76system.cpu.itb.hits 0 # DTB hits 77system.cpu.itb.misses 0 # DTB misses 78system.cpu.itb.accesses 0 # DTB accesses 79system.cpu.workload.num_syscalls 548 # Number of system calls 80system.cpu.numCycles 403704562 # number of cpu cycles simulated 81system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 82system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 83system.cpu.BPredUnit.lookups 183613146 # Number of BP lookups 84system.cpu.BPredUnit.condPredicted 143294212 # Number of conditional branches predicted 85system.cpu.BPredUnit.condIncorrect 7789120 # Number of conditional branches incorrect 86system.cpu.BPredUnit.BTBLookups 98042390 # Number of BTB lookups 87system.cpu.BPredUnit.BTBHits 90143773 # Number of BTB hits 88system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 89system.cpu.BPredUnit.usedRAS 12795154 # Number of times the RAS was used to get a target. 90system.cpu.BPredUnit.RASInCorrect 116199 # Number of incorrect RAS predictions. 91system.cpu.fetch.icacheStallCycles 119018383 # Number of cycles fetch is stalled on an Icache miss 92system.cpu.fetch.Insts 771038085 # Number of instructions fetch has processed 93system.cpu.fetch.Branches 183613146 # Number of branches that fetch encountered 94system.cpu.fetch.predictedBranches 102938927 # Number of branches that fetch has predicted taken 95system.cpu.fetch.Cycles 173093371 # Number of cycles fetch has run and was not squashing or blocked 96system.cpu.fetch.SquashCycles 37034444 # Number of cycles fetch has spent squashing 97system.cpu.fetch.BlockedCycles 81728576 # Number of cycles fetch has spent blocked 98system.cpu.fetch.MiscStallCycles 14 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 99system.cpu.fetch.PendingTrapStallCycles 370 # Number of stall cycles due to pending traps 100system.cpu.fetch.CacheLines 114776707 # Number of cache lines fetched 101system.cpu.fetch.IcacheSquashes 2639607 # Number of outstanding Icache misses that were squashed 102system.cpu.fetch.rateDist::samples 402291353 # Number of instructions fetched each cycle (Total) 103system.cpu.fetch.rateDist::mean 2.154621 # Number of instructions fetched each cycle (Total) 104system.cpu.fetch.rateDist::stdev 2.975773 # Number of instructions fetched each cycle (Total) 105system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 106system.cpu.fetch.rateDist::0 229210831 56.98% 56.98% # Number of instructions fetched each cycle (Total) 107system.cpu.fetch.rateDist::1 14330362 3.56% 60.54% # Number of instructions fetched each cycle (Total) 108system.cpu.fetch.rateDist::2 23398991 5.82% 66.35% # Number of instructions fetched each cycle (Total) 109system.cpu.fetch.rateDist::3 22962860 5.71% 72.06% # Number of instructions fetched each cycle (Total) 110system.cpu.fetch.rateDist::4 20943651 5.21% 77.27% # Number of instructions fetched each cycle (Total) 111system.cpu.fetch.rateDist::5 13279878 3.30% 80.57% # Number of instructions fetched each cycle (Total) 112system.cpu.fetch.rateDist::6 13299573 3.31% 83.88% # Number of instructions fetched each cycle (Total) 113system.cpu.fetch.rateDist::7 12124758 3.01% 86.89% # Number of instructions fetched each cycle (Total) 114system.cpu.fetch.rateDist::8 52740449 13.11% 100.00% # Number of instructions fetched each cycle (Total) 115system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 116system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 117system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 118system.cpu.fetch.rateDist::total 402291353 # Number of instructions fetched each cycle (Total) 119system.cpu.fetch.branchRate 0.454821 # Number of branch fetches per cycle 120system.cpu.fetch.rate 1.909907 # Number of inst fetches per cycle 121system.cpu.decode.IdleCycles 129139991 # Number of cycles decode is idle 122system.cpu.decode.BlockedCycles 76355942 # Number of cycles decode is blocked 123system.cpu.decode.RunCycles 163648868 # Number of cycles decode is running 124system.cpu.decode.UnblockCycles 4771100 # Number of cycles decode is unblocking 125system.cpu.decode.SquashCycles 28375452 # Number of cycles decode is squashing 126system.cpu.decode.BranchResolved 26593121 # Number of times decode resolved a branch 127system.cpu.decode.BranchMispred 78321 # Number of times decode detected a branch misprediction 128system.cpu.decode.DecodedInsts 842377409 # Number of instructions handled by decode 129system.cpu.decode.SquashedInsts 313716 # Number of squashed instructions handled by decode 130system.cpu.rename.SquashCycles 28375452 # Number of cycles rename is squashing 131system.cpu.rename.IdleCycles 137010485 # Number of cycles rename is idle 132system.cpu.rename.BlockCycles 5387793 # Number of cycles rename is blocking 133system.cpu.rename.serializeStallCycles 57527480 # count of cycles rename stalled for serializing inst 134system.cpu.rename.RunCycles 160406240 # Number of cycles rename is running 135system.cpu.rename.UnblockCycles 13583903 # Number of cycles rename is unblocking 136system.cpu.rename.RenamedInsts 812203916 # Number of instructions processed by rename 137system.cpu.rename.ROBFullEvents 883 # Number of times rename has blocked due to ROB full 138system.cpu.rename.IQFullEvents 2847047 # Number of times rename has blocked due to IQ full 139system.cpu.rename.LSQFullEvents 7163226 # Number of times rename has blocked due to LSQ full 140system.cpu.rename.FullRegisterEvents 116 # Number of times there has been no free registers 141system.cpu.rename.RenamedOperands 967528997 # Number of destination operands rename has renamed 142system.cpu.rename.RenameLookups 3555884446 # Number of register rename lookups that rename has made 143system.cpu.rename.int_rename_lookups 3555882861 # Number of integer rename lookups 144system.cpu.rename.fp_rename_lookups 1585 # Number of floating rename lookups 145system.cpu.rename.CommittedMaps 672200147 # Number of HB maps that are committed 146system.cpu.rename.UndoneMaps 295328850 # Number of HB maps that are undone due to squashing 147system.cpu.rename.serializingInsts 3042535 # count of serializing insts renamed 148system.cpu.rename.tempSerializingInsts 3042531 # count of temporary serializing insts renamed 149system.cpu.rename.skidInsts 44411709 # count of insts added to the skid buffer 150system.cpu.memDep0.insertedLoads 172477044 # Number of loads inserted to the mem dependence unit. 151system.cpu.memDep0.insertedStores 75019988 # Number of stores inserted to the mem dependence unit. 152system.cpu.memDep0.conflictingLoads 27139166 # Number of conflicting loads. 153system.cpu.memDep0.conflictingStores 14058077 # Number of conflicting stores. 154system.cpu.iq.iqInstsAdded 762853534 # Number of instructions added to the IQ (excludes non-spec) 155system.cpu.iq.iqNonSpecInstsAdded 4467400 # Number of non-speculative instructions added to the IQ 156system.cpu.iq.iqInstsIssued 672309193 # Number of instructions issued 157system.cpu.iq.iqSquashedInstsIssued 1597303 # Number of squashed instructions issued 158system.cpu.iq.iqSquashedInstsExamined 191893802 # Number of squashed instructions iterated over during squash; mainly for profiling 159system.cpu.iq.iqSquashedOperandsExamined 493277148 # Number of squashed operands that are examined and possibly removed from graph 160system.cpu.iq.iqSquashedNonSpecRemoved 746286 # Number of squashed non-spec instructions that were removed 161system.cpu.iq.issued_per_cycle::samples 402291353 # Number of insts issued each cycle 162system.cpu.iq.issued_per_cycle::mean 1.671200 # Number of insts issued each cycle 163system.cpu.iq.issued_per_cycle::stdev 1.739620 # Number of insts issued each cycle 164system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 165system.cpu.iq.issued_per_cycle::0 143645817 35.71% 35.71% # Number of insts issued each cycle 166system.cpu.iq.issued_per_cycle::1 74204584 18.45% 54.15% # Number of insts issued each cycle 167system.cpu.iq.issued_per_cycle::2 68520883 17.03% 71.19% # Number of insts issued each cycle 168system.cpu.iq.issued_per_cycle::3 53274856 13.24% 84.43% # Number of insts issued each cycle 169system.cpu.iq.issued_per_cycle::4 32167138 8.00% 92.42% # Number of insts issued each cycle 170system.cpu.iq.issued_per_cycle::5 16325737 4.06% 96.48% # Number of insts issued each cycle 171system.cpu.iq.issued_per_cycle::6 9421817 2.34% 98.82% # Number of insts issued each cycle 172system.cpu.iq.issued_per_cycle::7 3434032 0.85% 99.68% # Number of insts issued each cycle 173system.cpu.iq.issued_per_cycle::8 1296489 0.32% 100.00% # Number of insts issued each cycle 174system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 175system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 176system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 177system.cpu.iq.issued_per_cycle::total 402291353 # Number of insts issued each cycle 178system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 179system.cpu.iq.fu_full::IntAlu 436530 4.38% 4.38% # attempts to use FU when none available 180system.cpu.iq.fu_full::IntMult 0 0.00% 4.38% # attempts to use FU when none available 181system.cpu.iq.fu_full::IntDiv 0 0.00% 4.38% # attempts to use FU when none available 182system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.38% # attempts to use FU when none available 183system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.38% # attempts to use FU when none available 184system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.38% # attempts to use FU when none available 185system.cpu.iq.fu_full::FloatMult 0 0.00% 4.38% # attempts to use FU when none available 186system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.38% # attempts to use FU when none available 187system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.38% # attempts to use FU when none available 188system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.38% # attempts to use FU when none available 189system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.38% # attempts to use FU when none available 190system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.38% # attempts to use FU when none available 191system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.38% # attempts to use FU when none available 192system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.38% # attempts to use FU when none available 193system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.38% # attempts to use FU when none available 194system.cpu.iq.fu_full::SimdMult 0 0.00% 4.38% # attempts to use FU when none available 195system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.38% # attempts to use FU when none available 196system.cpu.iq.fu_full::SimdShift 0 0.00% 4.38% # attempts to use FU when none available 197system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.38% # attempts to use FU when none available 198system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.38% # attempts to use FU when none available 199system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.38% # attempts to use FU when none available 200system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.38% # attempts to use FU when none available 201system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.38% # attempts to use FU when none available 202system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.38% # attempts to use FU when none available 203system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.38% # attempts to use FU when none available 204system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.38% # attempts to use FU when none available 205system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.38% # attempts to use FU when none available 206system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.38% # attempts to use FU when none available 207system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.38% # attempts to use FU when none available 208system.cpu.iq.fu_full::MemRead 6785214 68.04% 72.42% # attempts to use FU when none available 209system.cpu.iq.fu_full::MemWrite 2750735 27.58% 100.00% # attempts to use FU when none available 210system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 211system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 212system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 213system.cpu.iq.FU_type_0::IntAlu 451600936 67.17% 67.17% # Type of FU issued 214system.cpu.iq.FU_type_0::IntMult 386071 0.06% 67.23% # Type of FU issued 215system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.23% # Type of FU issued 216system.cpu.iq.FU_type_0::FloatAdd 116 0.00% 67.23% # Type of FU issued 217system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.23% # Type of FU issued 218system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.23% # Type of FU issued 219system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.23% # Type of FU issued 220system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.23% # Type of FU issued 221system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.23% # Type of FU issued 222system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.23% # Type of FU issued 223system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.23% # Type of FU issued 224system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.23% # Type of FU issued 225system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.23% # Type of FU issued 226system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.23% # Type of FU issued 227system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.23% # Type of FU issued 228system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.23% # Type of FU issued 229system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.23% # Type of FU issued 230system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.23% # Type of FU issued 231system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.23% # Type of FU issued 232system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.23% # Type of FU issued 233system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.23% # Type of FU issued 234system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.23% # Type of FU issued 235system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.23% # Type of FU issued 236system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.23% # Type of FU issued 237system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.23% # Type of FU issued 238system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.23% # Type of FU issued 239system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.23% # Type of FU issued 240system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.23% # Type of FU issued 241system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.23% # Type of FU issued 242system.cpu.iq.FU_type_0::MemRead 155208445 23.09% 90.31% # Type of FU issued 243system.cpu.iq.FU_type_0::MemWrite 65113622 9.69% 100.00% # Type of FU issued 244system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 245system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 246system.cpu.iq.FU_type_0::total 672309193 # Type of FU issued 247system.cpu.iq.rate 1.665350 # Inst issue rate 248system.cpu.iq.fu_busy_cnt 9972479 # FU busy when requested 249system.cpu.iq.fu_busy_rate 0.014833 # FU busy rate (busy events/executed inst) 250system.cpu.iq.int_inst_queue_reads 1758479254 # Number of integer instruction queue reads 251system.cpu.iq.int_inst_queue_writes 960016621 # Number of integer instruction queue writes 252system.cpu.iq.int_inst_queue_wakeup_accesses 651381097 # Number of integer instruction queue wakeup accesses 253system.cpu.iq.fp_inst_queue_reads 267 # Number of floating instruction queue reads 254system.cpu.iq.fp_inst_queue_writes 364 # Number of floating instruction queue writes 255system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses 256system.cpu.iq.int_alu_accesses 682281537 # Number of integer alu accesses 257system.cpu.iq.fp_alu_accesses 135 # Number of floating point alu accesses 258system.cpu.iew.lsq.thread0.forwLoads 8428766 # Number of loads that had data forwarded from stores 259system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 260system.cpu.iew.lsq.thread0.squashedLoads 45704007 # Number of loads squashed 261system.cpu.iew.lsq.thread0.ignoredResponses 43585 # Number of memory responses ignored because the instruction is squashed 262system.cpu.iew.lsq.thread0.memOrderViolation 806080 # Number of memory ordering violations 263system.cpu.iew.lsq.thread0.squashedStores 17416029 # Number of stores squashed 264system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 265system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 266system.cpu.iew.lsq.thread0.rescheduledLoads 19464 # Number of loads that were rescheduled 267system.cpu.iew.lsq.thread0.cacheBlocked 1080 # Number of times an access to memory failed due to the cache being blocked 268system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 269system.cpu.iew.iewSquashCycles 28375452 # Number of cycles IEW is squashing 270system.cpu.iew.iewBlockCycles 1989251 # Number of cycles IEW is blocking 271system.cpu.iew.iewUnblockCycles 96453 # Number of cycles IEW is unblocking 272system.cpu.iew.iewDispatchedInsts 768887058 # Number of instructions dispatched to IQ 273system.cpu.iew.iewDispSquashedInsts 1243291 # Number of squashed instructions skipped by dispatch 274system.cpu.iew.iewDispLoadInsts 172477044 # Number of dispatched load instructions 275system.cpu.iew.iewDispStoreInsts 75019988 # Number of dispatched store instructions 276system.cpu.iew.iewDispNonSpecInsts 2978672 # Number of dispatched non-speculative instructions 277system.cpu.iew.iewIQFullEvents 38122 # Number of times the IQ has become full, causing a stall 278system.cpu.iew.iewLSQFullEvents 5312 # Number of times the LSQ has become full, causing a stall 279system.cpu.iew.memOrderViolationEvents 806080 # Number of memory order violations 280system.cpu.iew.predictedTakenIncorrect 4756345 # Number of branches that were predicted taken incorrectly 281system.cpu.iew.predictedNotTakenIncorrect 4163931 # Number of branches that were predicted not taken incorrectly 282system.cpu.iew.branchMispredicts 8920276 # Number of branch mispredicts detected at execute 283system.cpu.iew.iewExecutedInsts 661932492 # Number of executed instructions 284system.cpu.iew.iewExecLoadInsts 151574229 # Number of load instructions executed 285system.cpu.iew.iewExecSquashedInsts 10376701 # Number of squashed instructions skipped in execute 286system.cpu.iew.exec_swp 0 # number of swp insts executed 287system.cpu.iew.exec_nop 1566124 # number of nop insts executed 288system.cpu.iew.exec_refs 215230219 # number of memory reference insts executed 289system.cpu.iew.exec_branches 139385144 # Number of branches executed 290system.cpu.iew.exec_stores 63655990 # Number of stores executed 291system.cpu.iew.exec_rate 1.639646 # Inst execution rate 292system.cpu.iew.wb_sent 656632887 # cumulative count of insts sent to commit 293system.cpu.iew.wb_count 651381113 # cumulative count of insts written-back 294system.cpu.iew.wb_producers 375930281 # num instructions producing a value 295system.cpu.iew.wb_consumers 649035735 # num instructions consuming a value 296system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 297system.cpu.iew.wb_rate 1.613509 # insts written-back per cycle 298system.cpu.iew.wb_fanout 0.579214 # average fanout of values written-back 299system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 300system.cpu.commit.commitSquashedInsts 194215600 # The number of squashed insts skipped by commit 301system.cpu.commit.commitNonSpecStalls 3721114 # The number of times commit has been forced to stall to communicate backwards 302system.cpu.commit.branchMispredicts 7713933 # The number of times a branch was mispredicted 303system.cpu.commit.committed_per_cycle::samples 373915902 # Number of insts commited each cycle 304system.cpu.commit.committed_per_cycle::mean 1.536938 # Number of insts commited each cycle 305system.cpu.commit.committed_per_cycle::stdev 2.196487 # Number of insts commited each cycle 306system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 307system.cpu.commit.committed_per_cycle::0 161102013 43.09% 43.09% # Number of insts commited each cycle 308system.cpu.commit.committed_per_cycle::1 102670077 27.46% 70.54% # Number of insts commited each cycle 309system.cpu.commit.committed_per_cycle::2 34449601 9.21% 79.76% # Number of insts commited each cycle 310system.cpu.commit.committed_per_cycle::3 18433917 4.93% 84.69% # Number of insts commited each cycle 311system.cpu.commit.committed_per_cycle::4 17480337 4.67% 89.36% # Number of insts commited each cycle 312system.cpu.commit.committed_per_cycle::5 7750601 2.07% 91.43% # Number of insts commited each cycle 313system.cpu.commit.committed_per_cycle::6 6975147 1.87% 93.30% # Number of insts commited each cycle 314system.cpu.commit.committed_per_cycle::7 3144360 0.84% 94.14% # Number of insts commited each cycle 315system.cpu.commit.committed_per_cycle::8 21909849 5.86% 100.00% # Number of insts commited each cycle 316system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 317system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 318system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 319system.cpu.commit.committed_per_cycle::total 373915902 # Number of insts commited each cycle 320system.cpu.commit.committedInsts 510299017 # Number of instructions committed 321system.cpu.commit.committedOps 574685577 # Number of ops (including micro ops) committed 322system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 323system.cpu.commit.refs 184376996 # Number of memory references committed 324system.cpu.commit.loads 126773037 # Number of loads committed 325system.cpu.commit.membars 1488542 # Number of memory barriers committed 326system.cpu.commit.branches 122291783 # Number of branches committed 327system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. 328system.cpu.commit.int_insts 473701621 # Number of committed integer instructions. 329system.cpu.commit.function_calls 9757362 # Number of function calls committed. 330system.cpu.commit.bw_lim_events 21909849 # number cycles where commit BW limit reached 331system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 332system.cpu.rob.rob_reads 1120900092 # The number of ROB reads 333system.cpu.rob.rob_writes 1566319482 # The number of ROB writes 334system.cpu.timesIdled 51224 # Number of times that the entire CPU went into an idle state and unscheduled itself 335system.cpu.idleCycles 1413209 # Total number of cycles that the CPU has spent unscheduled due to idling 336system.cpu.committedInsts 508955133 # Number of Instructions Simulated 337system.cpu.committedOps 573341693 # Number of Ops (including micro ops) Simulated 338system.cpu.committedInsts_total 508955133 # Number of Instructions Simulated 339system.cpu.cpi 0.793203 # CPI: Cycles Per Instruction 340system.cpu.cpi_total 0.793203 # CPI: Total CPI of All Threads 341system.cpu.ipc 1.260712 # IPC: Instructions Per Cycle 342system.cpu.ipc_total 1.260712 # IPC: Total IPC of All Threads 343system.cpu.int_regfile_reads 3088645957 # number of integer regfile reads 344system.cpu.int_regfile_writes 759574381 # number of integer regfile writes 345system.cpu.fp_regfile_reads 16 # number of floating regfile reads 346system.cpu.misc_regfile_reads 999041226 # number of misc regfile reads 347system.cpu.misc_regfile_writes 4464048 # number of misc regfile writes 348system.cpu.icache.replacements 15551 # number of replacements 349system.cpu.icache.tagsinuse 1091.493459 # Cycle average of tags in use 350system.cpu.icache.total_refs 114757583 # Total number of references to valid blocks. 351system.cpu.icache.sampled_refs 17412 # Sample count of references to valid blocks. 352system.cpu.icache.avg_refs 6590.718068 # Average number of references to valid blocks. 353system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 354system.cpu.icache.occ_blocks::cpu.inst 1091.493459 # Average occupied blocks per requestor 355system.cpu.icache.occ_percent::cpu.inst 0.532956 # Average percentage of cache occupancy 356system.cpu.icache.occ_percent::total 0.532956 # Average percentage of cache occupancy 357system.cpu.icache.ReadReq_hits::cpu.inst 114757583 # number of ReadReq hits 358system.cpu.icache.ReadReq_hits::total 114757583 # number of ReadReq hits 359system.cpu.icache.demand_hits::cpu.inst 114757583 # number of demand (read+write) hits 360system.cpu.icache.demand_hits::total 114757583 # number of demand (read+write) hits 361system.cpu.icache.overall_hits::cpu.inst 114757583 # number of overall hits 362system.cpu.icache.overall_hits::total 114757583 # number of overall hits 363system.cpu.icache.ReadReq_misses::cpu.inst 19124 # number of ReadReq misses 364system.cpu.icache.ReadReq_misses::total 19124 # number of ReadReq misses 365system.cpu.icache.demand_misses::cpu.inst 19124 # number of demand (read+write) misses 366system.cpu.icache.demand_misses::total 19124 # number of demand (read+write) misses 367system.cpu.icache.overall_misses::cpu.inst 19124 # number of overall misses 368system.cpu.icache.overall_misses::total 19124 # number of overall misses 369system.cpu.icache.ReadReq_miss_latency::cpu.inst 228709500 # number of ReadReq miss cycles 370system.cpu.icache.ReadReq_miss_latency::total 228709500 # number of ReadReq miss cycles 371system.cpu.icache.demand_miss_latency::cpu.inst 228709500 # number of demand (read+write) miss cycles 372system.cpu.icache.demand_miss_latency::total 228709500 # number of demand (read+write) miss cycles 373system.cpu.icache.overall_miss_latency::cpu.inst 228709500 # number of overall miss cycles 374system.cpu.icache.overall_miss_latency::total 228709500 # number of overall miss cycles 375system.cpu.icache.ReadReq_accesses::cpu.inst 114776707 # number of ReadReq accesses(hits+misses) 376system.cpu.icache.ReadReq_accesses::total 114776707 # number of ReadReq accesses(hits+misses) 377system.cpu.icache.demand_accesses::cpu.inst 114776707 # number of demand (read+write) accesses 378system.cpu.icache.demand_accesses::total 114776707 # number of demand (read+write) accesses 379system.cpu.icache.overall_accesses::cpu.inst 114776707 # number of overall (read+write) accesses 380system.cpu.icache.overall_accesses::total 114776707 # number of overall (read+write) accesses 381system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000167 # miss rate for ReadReq accesses 382system.cpu.icache.ReadReq_miss_rate::total 0.000167 # miss rate for ReadReq accesses 383system.cpu.icache.demand_miss_rate::cpu.inst 0.000167 # miss rate for demand accesses 384system.cpu.icache.demand_miss_rate::total 0.000167 # miss rate for demand accesses 385system.cpu.icache.overall_miss_rate::cpu.inst 0.000167 # miss rate for overall accesses 386system.cpu.icache.overall_miss_rate::total 0.000167 # miss rate for overall accesses 387system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 11959.291989 # average ReadReq miss latency 388system.cpu.icache.ReadReq_avg_miss_latency::total 11959.291989 # average ReadReq miss latency 389system.cpu.icache.demand_avg_miss_latency::cpu.inst 11959.291989 # average overall miss latency 390system.cpu.icache.demand_avg_miss_latency::total 11959.291989 # average overall miss latency 391system.cpu.icache.overall_avg_miss_latency::cpu.inst 11959.291989 # average overall miss latency 392system.cpu.icache.overall_avg_miss_latency::total 11959.291989 # average overall miss latency 393system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 394system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 395system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 396system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 397system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 398system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 399system.cpu.icache.fast_writes 0 # number of fast writes performed 400system.cpu.icache.cache_copies 0 # number of cache copies performed 401system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1676 # number of ReadReq MSHR hits 402system.cpu.icache.ReadReq_mshr_hits::total 1676 # number of ReadReq MSHR hits 403system.cpu.icache.demand_mshr_hits::cpu.inst 1676 # number of demand (read+write) MSHR hits 404system.cpu.icache.demand_mshr_hits::total 1676 # number of demand (read+write) MSHR hits 405system.cpu.icache.overall_mshr_hits::cpu.inst 1676 # number of overall MSHR hits 406system.cpu.icache.overall_mshr_hits::total 1676 # number of overall MSHR hits 407system.cpu.icache.ReadReq_mshr_misses::cpu.inst 17448 # number of ReadReq MSHR misses 408system.cpu.icache.ReadReq_mshr_misses::total 17448 # number of ReadReq MSHR misses 409system.cpu.icache.demand_mshr_misses::cpu.inst 17448 # number of demand (read+write) MSHR misses 410system.cpu.icache.demand_mshr_misses::total 17448 # number of demand (read+write) MSHR misses 411system.cpu.icache.overall_mshr_misses::cpu.inst 17448 # number of overall MSHR misses 412system.cpu.icache.overall_mshr_misses::total 17448 # number of overall MSHR misses 413system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 154473000 # number of ReadReq MSHR miss cycles 414system.cpu.icache.ReadReq_mshr_miss_latency::total 154473000 # number of ReadReq MSHR miss cycles 415system.cpu.icache.demand_mshr_miss_latency::cpu.inst 154473000 # number of demand (read+write) MSHR miss cycles 416system.cpu.icache.demand_mshr_miss_latency::total 154473000 # number of demand (read+write) MSHR miss cycles 417system.cpu.icache.overall_mshr_miss_latency::cpu.inst 154473000 # number of overall MSHR miss cycles 418system.cpu.icache.overall_mshr_miss_latency::total 154473000 # number of overall MSHR miss cycles 419system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000152 # mshr miss rate for ReadReq accesses 420system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000152 # mshr miss rate for ReadReq accesses 421system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000152 # mshr miss rate for demand accesses 422system.cpu.icache.demand_mshr_miss_rate::total 0.000152 # mshr miss rate for demand accesses 423system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000152 # mshr miss rate for overall accesses 424system.cpu.icache.overall_mshr_miss_rate::total 0.000152 # mshr miss rate for overall accesses 425system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 8853.335626 # average ReadReq mshr miss latency 426system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 8853.335626 # average ReadReq mshr miss latency 427system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 8853.335626 # average overall mshr miss latency 428system.cpu.icache.demand_avg_mshr_miss_latency::total 8853.335626 # average overall mshr miss latency 429system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 8853.335626 # average overall mshr miss latency 430system.cpu.icache.overall_avg_mshr_miss_latency::total 8853.335626 # average overall mshr miss latency 431system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 432system.cpu.dcache.replacements 1187048 # number of replacements 433system.cpu.dcache.tagsinuse 4054.257449 # Cycle average of tags in use 434system.cpu.dcache.total_refs 194842504 # Total number of references to valid blocks. 435system.cpu.dcache.sampled_refs 1191144 # Sample count of references to valid blocks. 436system.cpu.dcache.avg_refs 163.575944 # Average number of references to valid blocks. 437system.cpu.dcache.warmup_cycle 4633717000 # Cycle when the warmup percentage was hit. 438system.cpu.dcache.occ_blocks::cpu.data 4054.257449 # Average occupied blocks per requestor 439system.cpu.dcache.occ_percent::cpu.data 0.989809 # Average percentage of cache occupancy 440system.cpu.dcache.occ_percent::total 0.989809 # Average percentage of cache occupancy 441system.cpu.dcache.ReadReq_hits::cpu.data 137485453 # number of ReadReq hits 442system.cpu.dcache.ReadReq_hits::total 137485453 # number of ReadReq hits 443system.cpu.dcache.WriteReq_hits::cpu.data 52891890 # number of WriteReq hits 444system.cpu.dcache.WriteReq_hits::total 52891890 # number of WriteReq hits 445system.cpu.dcache.LoadLockedReq_hits::cpu.data 2233029 # number of LoadLockedReq hits 446system.cpu.dcache.LoadLockedReq_hits::total 2233029 # number of LoadLockedReq hits 447system.cpu.dcache.StoreCondReq_hits::cpu.data 2232023 # number of StoreCondReq hits 448system.cpu.dcache.StoreCondReq_hits::total 2232023 # number of StoreCondReq hits 449system.cpu.dcache.demand_hits::cpu.data 190377343 # number of demand (read+write) hits 450system.cpu.dcache.demand_hits::total 190377343 # number of demand (read+write) hits 451system.cpu.dcache.overall_hits::cpu.data 190377343 # number of overall hits 452system.cpu.dcache.overall_hits::total 190377343 # number of overall hits 453system.cpu.dcache.ReadReq_misses::cpu.data 1221436 # number of ReadReq misses 454system.cpu.dcache.ReadReq_misses::total 1221436 # number of ReadReq misses 455system.cpu.dcache.WriteReq_misses::cpu.data 1347416 # number of WriteReq misses 456system.cpu.dcache.WriteReq_misses::total 1347416 # number of WriteReq misses 457system.cpu.dcache.LoadLockedReq_misses::cpu.data 47 # number of LoadLockedReq misses 458system.cpu.dcache.LoadLockedReq_misses::total 47 # number of LoadLockedReq misses 459system.cpu.dcache.demand_misses::cpu.data 2568852 # number of demand (read+write) misses 460system.cpu.dcache.demand_misses::total 2568852 # number of demand (read+write) misses 461system.cpu.dcache.overall_misses::cpu.data 2568852 # number of overall misses 462system.cpu.dcache.overall_misses::total 2568852 # number of overall misses 463system.cpu.dcache.ReadReq_miss_latency::cpu.data 9648379000 # number of ReadReq miss cycles 464system.cpu.dcache.ReadReq_miss_latency::total 9648379000 # number of ReadReq miss cycles 465system.cpu.dcache.WriteReq_miss_latency::cpu.data 23124597500 # number of WriteReq miss cycles 466system.cpu.dcache.WriteReq_miss_latency::total 23124597500 # number of WriteReq miss cycles 467system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 412500 # number of LoadLockedReq miss cycles 468system.cpu.dcache.LoadLockedReq_miss_latency::total 412500 # number of LoadLockedReq miss cycles 469system.cpu.dcache.demand_miss_latency::cpu.data 32772976500 # number of demand (read+write) miss cycles 470system.cpu.dcache.demand_miss_latency::total 32772976500 # number of demand (read+write) miss cycles 471system.cpu.dcache.overall_miss_latency::cpu.data 32772976500 # number of overall miss cycles 472system.cpu.dcache.overall_miss_latency::total 32772976500 # number of overall miss cycles 473system.cpu.dcache.ReadReq_accesses::cpu.data 138706889 # number of ReadReq accesses(hits+misses) 474system.cpu.dcache.ReadReq_accesses::total 138706889 # number of ReadReq accesses(hits+misses) 475system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) 476system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) 477system.cpu.dcache.LoadLockedReq_accesses::cpu.data 2233076 # number of LoadLockedReq accesses(hits+misses) 478system.cpu.dcache.LoadLockedReq_accesses::total 2233076 # number of LoadLockedReq accesses(hits+misses) 479system.cpu.dcache.StoreCondReq_accesses::cpu.data 2232023 # number of StoreCondReq accesses(hits+misses) 480system.cpu.dcache.StoreCondReq_accesses::total 2232023 # number of StoreCondReq accesses(hits+misses) 481system.cpu.dcache.demand_accesses::cpu.data 192946195 # number of demand (read+write) accesses 482system.cpu.dcache.demand_accesses::total 192946195 # number of demand (read+write) accesses 483system.cpu.dcache.overall_accesses::cpu.data 192946195 # number of overall (read+write) accesses 484system.cpu.dcache.overall_accesses::total 192946195 # number of overall (read+write) accesses 485system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.008806 # miss rate for ReadReq accesses 486system.cpu.dcache.ReadReq_miss_rate::total 0.008806 # miss rate for ReadReq accesses 487system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024842 # miss rate for WriteReq accesses 488system.cpu.dcache.WriteReq_miss_rate::total 0.024842 # miss rate for WriteReq accesses 489system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000021 # miss rate for LoadLockedReq accesses 490system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000021 # miss rate for LoadLockedReq accesses 491system.cpu.dcache.demand_miss_rate::cpu.data 0.013314 # miss rate for demand accesses 492system.cpu.dcache.demand_miss_rate::total 0.013314 # miss rate for demand accesses 493system.cpu.dcache.overall_miss_rate::cpu.data 0.013314 # miss rate for overall accesses 494system.cpu.dcache.overall_miss_rate::total 0.013314 # miss rate for overall accesses 495system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 7899.209619 # average ReadReq miss latency 496system.cpu.dcache.ReadReq_avg_miss_latency::total 7899.209619 # average ReadReq miss latency 497system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17162.181168 # average WriteReq miss latency 498system.cpu.dcache.WriteReq_avg_miss_latency::total 17162.181168 # average WriteReq miss latency 499system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 8776.595745 # average LoadLockedReq miss latency 500system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 8776.595745 # average LoadLockedReq miss latency 501system.cpu.dcache.demand_avg_miss_latency::cpu.data 12757.829762 # average overall miss latency 502system.cpu.dcache.demand_avg_miss_latency::total 12757.829762 # average overall miss latency 503system.cpu.dcache.overall_avg_miss_latency::cpu.data 12757.829762 # average overall miss latency 504system.cpu.dcache.overall_avg_miss_latency::total 12757.829762 # average overall miss latency 505system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 506system.cpu.dcache.blocked_cycles::no_targets 3322000 # number of cycles access was blocked 507system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 508system.cpu.dcache.blocked::no_targets 557 # number of cycles access was blocked 509system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 510system.cpu.dcache.avg_blocked_cycles::no_targets 5964.093357 # average number of cycles each access was blocked 511system.cpu.dcache.fast_writes 0 # number of fast writes performed 512system.cpu.dcache.cache_copies 0 # number of cache copies performed 513system.cpu.dcache.writebacks::writebacks 1101507 # number of writebacks 514system.cpu.dcache.writebacks::total 1101507 # number of writebacks 515system.cpu.dcache.ReadReq_mshr_hits::cpu.data 378352 # number of ReadReq MSHR hits 516system.cpu.dcache.ReadReq_mshr_hits::total 378352 # number of ReadReq MSHR hits 517system.cpu.dcache.WriteReq_mshr_hits::cpu.data 999317 # number of WriteReq MSHR hits 518system.cpu.dcache.WriteReq_mshr_hits::total 999317 # number of WriteReq MSHR hits 519system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 47 # number of LoadLockedReq MSHR hits 520system.cpu.dcache.LoadLockedReq_mshr_hits::total 47 # number of LoadLockedReq MSHR hits 521system.cpu.dcache.demand_mshr_hits::cpu.data 1377669 # number of demand (read+write) MSHR hits 522system.cpu.dcache.demand_mshr_hits::total 1377669 # number of demand (read+write) MSHR hits 523system.cpu.dcache.overall_mshr_hits::cpu.data 1377669 # number of overall MSHR hits 524system.cpu.dcache.overall_mshr_hits::total 1377669 # number of overall MSHR hits 525system.cpu.dcache.ReadReq_mshr_misses::cpu.data 843084 # number of ReadReq MSHR misses 526system.cpu.dcache.ReadReq_mshr_misses::total 843084 # number of ReadReq MSHR misses 527system.cpu.dcache.WriteReq_mshr_misses::cpu.data 348099 # number of WriteReq MSHR misses 528system.cpu.dcache.WriteReq_mshr_misses::total 348099 # number of WriteReq MSHR misses 529system.cpu.dcache.demand_mshr_misses::cpu.data 1191183 # number of demand (read+write) MSHR misses 530system.cpu.dcache.demand_mshr_misses::total 1191183 # number of demand (read+write) MSHR misses 531system.cpu.dcache.overall_mshr_misses::cpu.data 1191183 # number of overall MSHR misses 532system.cpu.dcache.overall_mshr_misses::total 1191183 # number of overall MSHR misses 533system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3511124500 # number of ReadReq MSHR miss cycles 534system.cpu.dcache.ReadReq_mshr_miss_latency::total 3511124500 # number of ReadReq MSHR miss cycles 535system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4141906500 # number of WriteReq MSHR miss cycles 536system.cpu.dcache.WriteReq_mshr_miss_latency::total 4141906500 # number of WriteReq MSHR miss cycles 537system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7653031000 # number of demand (read+write) MSHR miss cycles 538system.cpu.dcache.demand_mshr_miss_latency::total 7653031000 # number of demand (read+write) MSHR miss cycles 539system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7653031000 # number of overall MSHR miss cycles 540system.cpu.dcache.overall_mshr_miss_latency::total 7653031000 # number of overall MSHR miss cycles 541system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006078 # mshr miss rate for ReadReq accesses 542system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006078 # mshr miss rate for ReadReq accesses 543system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006418 # mshr miss rate for WriteReq accesses 544system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006418 # mshr miss rate for WriteReq accesses 545system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006174 # mshr miss rate for demand accesses 546system.cpu.dcache.demand_mshr_miss_rate::total 0.006174 # mshr miss rate for demand accesses 547system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006174 # mshr miss rate for overall accesses 548system.cpu.dcache.overall_mshr_miss_rate::total 0.006174 # mshr miss rate for overall accesses 549system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 4164.620014 # average ReadReq mshr miss latency 550system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 4164.620014 # average ReadReq mshr miss latency 551system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 11898.645213 # average WriteReq mshr miss latency 552system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 11898.645213 # average WriteReq mshr miss latency 553system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 6424.731548 # average overall mshr miss latency 554system.cpu.dcache.demand_avg_mshr_miss_latency::total 6424.731548 # average overall mshr miss latency 555system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 6424.731548 # average overall mshr miss latency 556system.cpu.dcache.overall_avg_mshr_miss_latency::total 6424.731548 # average overall mshr miss latency 557system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 558system.cpu.l2cache.replacements 128736 # number of replacements 559system.cpu.l2cache.tagsinuse 26456.309379 # Cycle average of tags in use 560system.cpu.l2cache.total_refs 1725132 # Total number of references to valid blocks. 561system.cpu.l2cache.sampled_refs 159966 # Sample count of references to valid blocks. 562system.cpu.l2cache.avg_refs 10.784367 # Average number of references to valid blocks. 563system.cpu.l2cache.warmup_cycle 105169103500 # Cycle when the warmup percentage was hit. 564system.cpu.l2cache.occ_blocks::writebacks 22633.637803 # Average occupied blocks per requestor 565system.cpu.l2cache.occ_blocks::cpu.inst 309.674133 # Average occupied blocks per requestor 566system.cpu.l2cache.occ_blocks::cpu.data 3512.997443 # Average occupied blocks per requestor 567system.cpu.l2cache.occ_percent::writebacks 0.690724 # Average percentage of cache occupancy 568system.cpu.l2cache.occ_percent::cpu.inst 0.009451 # Average percentage of cache occupancy 569system.cpu.l2cache.occ_percent::cpu.data 0.107208 # Average percentage of cache occupancy 570system.cpu.l2cache.occ_percent::total 0.807382 # Average percentage of cache occupancy 571system.cpu.l2cache.ReadReq_hits::cpu.inst 13983 # number of ReadReq hits 572system.cpu.l2cache.ReadReq_hits::cpu.data 789454 # number of ReadReq hits 573system.cpu.l2cache.ReadReq_hits::total 803437 # number of ReadReq hits 574system.cpu.l2cache.Writeback_hits::writebacks 1101507 # number of Writeback hits 575system.cpu.l2cache.Writeback_hits::total 1101507 # number of Writeback hits 576system.cpu.l2cache.UpgradeReq_hits::cpu.data 35 # number of UpgradeReq hits 577system.cpu.l2cache.UpgradeReq_hits::total 35 # number of UpgradeReq hits 578system.cpu.l2cache.ReadExReq_hits::cpu.data 245171 # number of ReadExReq hits 579system.cpu.l2cache.ReadExReq_hits::total 245171 # number of ReadExReq hits 580system.cpu.l2cache.demand_hits::cpu.inst 13983 # number of demand (read+write) hits 581system.cpu.l2cache.demand_hits::cpu.data 1034625 # number of demand (read+write) hits 582system.cpu.l2cache.demand_hits::total 1048608 # number of demand (read+write) hits 583system.cpu.l2cache.overall_hits::cpu.inst 13983 # number of overall hits 584system.cpu.l2cache.overall_hits::cpu.data 1034625 # number of overall hits 585system.cpu.l2cache.overall_hits::total 1048608 # number of overall hits 586system.cpu.l2cache.ReadReq_misses::cpu.inst 3427 # number of ReadReq misses 587system.cpu.l2cache.ReadReq_misses::cpu.data 53077 # number of ReadReq misses 588system.cpu.l2cache.ReadReq_misses::total 56504 # number of ReadReq misses 589system.cpu.l2cache.UpgradeReq_misses::cpu.data 4 # number of UpgradeReq misses 590system.cpu.l2cache.UpgradeReq_misses::total 4 # number of UpgradeReq misses 591system.cpu.l2cache.ReadExReq_misses::cpu.data 103442 # number of ReadExReq misses 592system.cpu.l2cache.ReadExReq_misses::total 103442 # number of ReadExReq misses 593system.cpu.l2cache.demand_misses::cpu.inst 3427 # number of demand (read+write) misses 594system.cpu.l2cache.demand_misses::cpu.data 156519 # number of demand (read+write) misses 595system.cpu.l2cache.demand_misses::total 159946 # number of demand (read+write) misses 596system.cpu.l2cache.overall_misses::cpu.inst 3427 # number of overall misses 597system.cpu.l2cache.overall_misses::cpu.data 156519 # number of overall misses 598system.cpu.l2cache.overall_misses::total 159946 # number of overall misses 599system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 122356000 # number of ReadReq miss cycles 600system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1846533500 # number of ReadReq miss cycles 601system.cpu.l2cache.ReadReq_miss_latency::total 1968889500 # number of ReadReq miss cycles 602system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3549540000 # number of ReadExReq miss cycles 603system.cpu.l2cache.ReadExReq_miss_latency::total 3549540000 # number of ReadExReq miss cycles 604system.cpu.l2cache.demand_miss_latency::cpu.inst 122356000 # number of demand (read+write) miss cycles 605system.cpu.l2cache.demand_miss_latency::cpu.data 5396073500 # number of demand (read+write) miss cycles 606system.cpu.l2cache.demand_miss_latency::total 5518429500 # number of demand (read+write) miss cycles 607system.cpu.l2cache.overall_miss_latency::cpu.inst 122356000 # number of overall miss cycles 608system.cpu.l2cache.overall_miss_latency::cpu.data 5396073500 # number of overall miss cycles 609system.cpu.l2cache.overall_miss_latency::total 5518429500 # number of overall miss cycles 610system.cpu.l2cache.ReadReq_accesses::cpu.inst 17410 # number of ReadReq accesses(hits+misses) 611system.cpu.l2cache.ReadReq_accesses::cpu.data 842531 # number of ReadReq accesses(hits+misses) 612system.cpu.l2cache.ReadReq_accesses::total 859941 # number of ReadReq accesses(hits+misses) 613system.cpu.l2cache.Writeback_accesses::writebacks 1101507 # number of Writeback accesses(hits+misses) 614system.cpu.l2cache.Writeback_accesses::total 1101507 # number of Writeback accesses(hits+misses) 615system.cpu.l2cache.UpgradeReq_accesses::cpu.data 39 # number of UpgradeReq accesses(hits+misses) 616system.cpu.l2cache.UpgradeReq_accesses::total 39 # number of UpgradeReq accesses(hits+misses) 617system.cpu.l2cache.ReadExReq_accesses::cpu.data 348613 # number of ReadExReq accesses(hits+misses) 618system.cpu.l2cache.ReadExReq_accesses::total 348613 # number of ReadExReq accesses(hits+misses) 619system.cpu.l2cache.demand_accesses::cpu.inst 17410 # number of demand (read+write) accesses 620system.cpu.l2cache.demand_accesses::cpu.data 1191144 # number of demand (read+write) accesses 621system.cpu.l2cache.demand_accesses::total 1208554 # number of demand (read+write) accesses 622system.cpu.l2cache.overall_accesses::cpu.inst 17410 # number of overall (read+write) accesses 623system.cpu.l2cache.overall_accesses::cpu.data 1191144 # number of overall (read+write) accesses 624system.cpu.l2cache.overall_accesses::total 1208554 # number of overall (read+write) accesses 625system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.196841 # miss rate for ReadReq accesses 626system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.062997 # miss rate for ReadReq accesses 627system.cpu.l2cache.ReadReq_miss_rate::total 0.065707 # miss rate for ReadReq accesses 628system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.102564 # miss rate for UpgradeReq accesses 629system.cpu.l2cache.UpgradeReq_miss_rate::total 0.102564 # miss rate for UpgradeReq accesses 630system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.296724 # miss rate for ReadExReq accesses 631system.cpu.l2cache.ReadExReq_miss_rate::total 0.296724 # miss rate for ReadExReq accesses 632system.cpu.l2cache.demand_miss_rate::cpu.inst 0.196841 # miss rate for demand accesses 633system.cpu.l2cache.demand_miss_rate::cpu.data 0.131402 # miss rate for demand accesses 634system.cpu.l2cache.demand_miss_rate::total 0.132345 # miss rate for demand accesses 635system.cpu.l2cache.overall_miss_rate::cpu.inst 0.196841 # miss rate for overall accesses 636system.cpu.l2cache.overall_miss_rate::cpu.data 0.131402 # miss rate for overall accesses 637system.cpu.l2cache.overall_miss_rate::total 0.132345 # miss rate for overall accesses 638system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35703.530785 # average ReadReq miss latency 639system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34789.711174 # average ReadReq miss latency 640system.cpu.l2cache.ReadReq_avg_miss_latency::total 34845.134858 # average ReadReq miss latency 641system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34314.301734 # average ReadExReq miss latency 642system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34314.301734 # average ReadExReq miss latency 643system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35703.530785 # average overall miss latency 644system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34475.517349 # average overall miss latency 645system.cpu.l2cache.demand_avg_miss_latency::total 34501.828742 # average overall miss latency 646system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35703.530785 # average overall miss latency 647system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34475.517349 # average overall miss latency 648system.cpu.l2cache.overall_avg_miss_latency::total 34501.828742 # average overall miss latency 649system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 650system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 651system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 652system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 653system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 654system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 655system.cpu.l2cache.fast_writes 0 # number of fast writes performed 656system.cpu.l2cache.cache_copies 0 # number of cache copies performed 657system.cpu.l2cache.writebacks::writebacks 104365 # number of writebacks 658system.cpu.l2cache.writebacks::total 104365 # number of writebacks 659system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 8 # number of ReadReq MSHR hits 660system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 21 # number of ReadReq MSHR hits 661system.cpu.l2cache.ReadReq_mshr_hits::total 29 # number of ReadReq MSHR hits 662system.cpu.l2cache.demand_mshr_hits::cpu.inst 8 # number of demand (read+write) MSHR hits 663system.cpu.l2cache.demand_mshr_hits::cpu.data 21 # number of demand (read+write) MSHR hits 664system.cpu.l2cache.demand_mshr_hits::total 29 # number of demand (read+write) MSHR hits 665system.cpu.l2cache.overall_mshr_hits::cpu.inst 8 # number of overall MSHR hits 666system.cpu.l2cache.overall_mshr_hits::cpu.data 21 # number of overall MSHR hits 667system.cpu.l2cache.overall_mshr_hits::total 29 # number of overall MSHR hits 668system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3419 # number of ReadReq MSHR misses 669system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 53056 # number of ReadReq MSHR misses 670system.cpu.l2cache.ReadReq_mshr_misses::total 56475 # number of ReadReq MSHR misses 671system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 4 # number of UpgradeReq MSHR misses 672system.cpu.l2cache.UpgradeReq_mshr_misses::total 4 # number of UpgradeReq MSHR misses 673system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 103442 # number of ReadExReq MSHR misses 674system.cpu.l2cache.ReadExReq_mshr_misses::total 103442 # number of ReadExReq MSHR misses 675system.cpu.l2cache.demand_mshr_misses::cpu.inst 3419 # number of demand (read+write) MSHR misses 676system.cpu.l2cache.demand_mshr_misses::cpu.data 156498 # number of demand (read+write) MSHR misses 677system.cpu.l2cache.demand_mshr_misses::total 159917 # number of demand (read+write) MSHR misses 678system.cpu.l2cache.overall_mshr_misses::cpu.inst 3419 # number of overall MSHR misses 679system.cpu.l2cache.overall_mshr_misses::cpu.data 156498 # number of overall MSHR misses 680system.cpu.l2cache.overall_mshr_misses::total 159917 # number of overall MSHR misses 681system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 111443000 # number of ReadReq MSHR miss cycles 682system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1678392000 # number of ReadReq MSHR miss cycles 683system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1789835000 # number of ReadReq MSHR miss cycles 684system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 124000 # number of UpgradeReq MSHR miss cycles 685system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 124000 # number of UpgradeReq MSHR miss cycles 686system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3216081000 # number of ReadExReq MSHR miss cycles 687system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3216081000 # number of ReadExReq MSHR miss cycles 688system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 111443000 # number of demand (read+write) MSHR miss cycles 689system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4894473000 # number of demand (read+write) MSHR miss cycles 690system.cpu.l2cache.demand_mshr_miss_latency::total 5005916000 # number of demand (read+write) MSHR miss cycles 691system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 111443000 # number of overall MSHR miss cycles 692system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4894473000 # number of overall MSHR miss cycles 693system.cpu.l2cache.overall_mshr_miss_latency::total 5005916000 # number of overall MSHR miss cycles 694system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.196381 # mshr miss rate for ReadReq accesses 695system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.062972 # mshr miss rate for ReadReq accesses 696system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.065673 # mshr miss rate for ReadReq accesses 697system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.102564 # mshr miss rate for UpgradeReq accesses 698system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.102564 # mshr miss rate for UpgradeReq accesses 699system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.296724 # mshr miss rate for ReadExReq accesses 700system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.296724 # mshr miss rate for ReadExReq accesses 701system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.196381 # mshr miss rate for demand accesses 702system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.131385 # mshr miss rate for demand accesses 703system.cpu.l2cache.demand_mshr_miss_rate::total 0.132321 # mshr miss rate for demand accesses 704system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.196381 # mshr miss rate for overall accesses 705system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.131385 # mshr miss rate for overall accesses 706system.cpu.l2cache.overall_mshr_miss_rate::total 0.132321 # mshr miss rate for overall accesses 707system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32595.203276 # average ReadReq mshr miss latency 708system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31634.348613 # average ReadReq mshr miss latency 709system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31692.518814 # average ReadReq mshr miss latency 710system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31000 # average UpgradeReq mshr miss latency 711system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31000 # average UpgradeReq mshr miss latency 712system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31090.669167 # average ReadExReq mshr miss latency 713system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31090.669167 # average ReadExReq mshr miss latency 714system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32595.203276 # average overall mshr miss latency 715system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31274.987540 # average overall mshr miss latency 716system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31303.213542 # average overall mshr miss latency 717system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32595.203276 # average overall mshr miss latency 718system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31274.987540 # average overall mshr miss latency 719system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31303.213542 # average overall mshr miss latency 720system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 721 722---------- End Simulation Statistics ---------- 723