stats.txt revision 9096:8971a998190a
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.213266 # Number of seconds simulated 4sim_ticks 213265939500 # Number of ticks simulated 5final_tick 213265939500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 150954 # Simulator instruction rate (inst/s) 8host_op_rate 170051 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 63253971 # Simulator tick rate (ticks/s) 10host_mem_usage 238980 # Number of bytes of host memory used 11host_seconds 3371.58 # Real time elapsed on the host 12sim_insts 508955143 # Number of instructions simulated 13sim_ops 573341703 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 218944 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 10016576 # Number of bytes read from this memory 16system.physmem.bytes_read::total 10235520 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 218944 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 218944 # Number of instructions bytes read from this memory 19system.physmem.bytes_written::writebacks 6679616 # Number of bytes written to this memory 20system.physmem.bytes_written::total 6679616 # Number of bytes written to this memory 21system.physmem.num_reads::cpu.inst 3421 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 156509 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 159930 # Number of read requests responded to by this memory 24system.physmem.num_writes::writebacks 104369 # Number of write requests responded to by this memory 25system.physmem.num_writes::total 104369 # Number of write requests responded to by this memory 26system.physmem.bw_read::cpu.inst 1026624 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::cpu.data 46967537 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_read::total 47994162 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::cpu.inst 1026624 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_inst_read::total 1026624 # Instruction read bandwidth from this memory (bytes/s) 31system.physmem.bw_write::writebacks 31320594 # Write bandwidth from this memory (bytes/s) 32system.physmem.bw_write::total 31320594 # Write bandwidth from this memory (bytes/s) 33system.physmem.bw_total::writebacks 31320594 # Total bandwidth to/from this memory (bytes/s) 34system.physmem.bw_total::cpu.inst 1026624 # Total bandwidth to/from this memory (bytes/s) 35system.physmem.bw_total::cpu.data 46967537 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::total 79314756 # Total bandwidth to/from this memory (bytes/s) 37system.cpu.dtb.inst_hits 0 # ITB inst hits 38system.cpu.dtb.inst_misses 0 # ITB inst misses 39system.cpu.dtb.read_hits 0 # DTB read hits 40system.cpu.dtb.read_misses 0 # DTB read misses 41system.cpu.dtb.write_hits 0 # DTB write hits 42system.cpu.dtb.write_misses 0 # DTB write misses 43system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 44system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 45system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 46system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 47system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 48system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 49system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 50system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 51system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 52system.cpu.dtb.read_accesses 0 # DTB read accesses 53system.cpu.dtb.write_accesses 0 # DTB write accesses 54system.cpu.dtb.inst_accesses 0 # ITB inst accesses 55system.cpu.dtb.hits 0 # DTB hits 56system.cpu.dtb.misses 0 # DTB misses 57system.cpu.dtb.accesses 0 # DTB accesses 58system.cpu.itb.inst_hits 0 # ITB inst hits 59system.cpu.itb.inst_misses 0 # ITB inst misses 60system.cpu.itb.read_hits 0 # DTB read hits 61system.cpu.itb.read_misses 0 # DTB read misses 62system.cpu.itb.write_hits 0 # DTB write hits 63system.cpu.itb.write_misses 0 # DTB write misses 64system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 65system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 66system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 67system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 68system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 69system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 70system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 71system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 72system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 73system.cpu.itb.read_accesses 0 # DTB read accesses 74system.cpu.itb.write_accesses 0 # DTB write accesses 75system.cpu.itb.inst_accesses 0 # ITB inst accesses 76system.cpu.itb.hits 0 # DTB hits 77system.cpu.itb.misses 0 # DTB misses 78system.cpu.itb.accesses 0 # DTB accesses 79system.cpu.workload.num_syscalls 548 # Number of system calls 80system.cpu.numCycles 426531880 # number of cpu cycles simulated 81system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 82system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 83system.cpu.BPredUnit.lookups 180717428 # Number of BP lookups 84system.cpu.BPredUnit.condPredicted 143299693 # Number of conditional branches predicted 85system.cpu.BPredUnit.condIncorrect 7745708 # Number of conditional branches incorrect 86system.cpu.BPredUnit.BTBLookups 94822680 # Number of BTB lookups 87system.cpu.BPredUnit.BTBHits 87599174 # Number of BTB hits 88system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 89system.cpu.BPredUnit.usedRAS 12446842 # Number of times the RAS was used to get a target. 90system.cpu.BPredUnit.RASInCorrect 117258 # Number of incorrect RAS predictions. 91system.cpu.fetch.icacheStallCycles 120998369 # Number of cycles fetch is stalled on an Icache miss 92system.cpu.fetch.Insts 797263404 # Number of instructions fetch has processed 93system.cpu.fetch.Branches 180717428 # Number of branches that fetch encountered 94system.cpu.fetch.predictedBranches 100046016 # Number of branches that fetch has predicted taken 95system.cpu.fetch.Cycles 177300353 # Number of cycles fetch has run and was not squashing or blocked 96system.cpu.fetch.SquashCycles 41685655 # Number of cycles fetch has spent squashing 97system.cpu.fetch.BlockedCycles 95764916 # Number of cycles fetch has spent blocked 98system.cpu.fetch.MiscStallCycles 19 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 99system.cpu.fetch.PendingTrapStallCycles 750 # Number of stall cycles due to pending traps 100system.cpu.fetch.CacheLines 114346660 # Number of cache lines fetched 101system.cpu.fetch.IcacheSquashes 2503858 # Number of outstanding Icache misses that were squashed 102system.cpu.fetch.rateDist::samples 424958022 # Number of instructions fetched each cycle (Total) 103system.cpu.fetch.rateDist::mean 2.156047 # Number of instructions fetched each cycle (Total) 104system.cpu.fetch.rateDist::stdev 3.022518 # Number of instructions fetched each cycle (Total) 105system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 106system.cpu.fetch.rateDist::0 247670464 58.28% 58.28% # Number of instructions fetched each cycle (Total) 107system.cpu.fetch.rateDist::1 14397332 3.39% 61.67% # Number of instructions fetched each cycle (Total) 108system.cpu.fetch.rateDist::2 20689751 4.87% 66.54% # Number of instructions fetched each cycle (Total) 109system.cpu.fetch.rateDist::3 22947722 5.40% 71.94% # Number of instructions fetched each cycle (Total) 110system.cpu.fetch.rateDist::4 21025298 4.95% 76.89% # Number of instructions fetched each cycle (Total) 111system.cpu.fetch.rateDist::5 13188609 3.10% 79.99% # Number of instructions fetched each cycle (Total) 112system.cpu.fetch.rateDist::6 13288793 3.13% 83.12% # Number of instructions fetched each cycle (Total) 113system.cpu.fetch.rateDist::7 12167829 2.86% 85.98% # Number of instructions fetched each cycle (Total) 114system.cpu.fetch.rateDist::8 59582224 14.02% 100.00% # Number of instructions fetched each cycle (Total) 115system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 116system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 117system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 118system.cpu.fetch.rateDist::total 424958022 # Number of instructions fetched each cycle (Total) 119system.cpu.fetch.branchRate 0.423690 # Number of branch fetches per cycle 120system.cpu.fetch.rate 1.869177 # Number of inst fetches per cycle 121system.cpu.decode.IdleCycles 133827033 # Number of cycles decode is idle 122system.cpu.decode.BlockedCycles 89884158 # Number of cycles decode is blocked 123system.cpu.decode.RunCycles 165222726 # Number of cycles decode is running 124system.cpu.decode.UnblockCycles 5205901 # Number of cycles decode is unblocking 125system.cpu.decode.SquashCycles 30818204 # Number of cycles decode is squashing 126system.cpu.decode.BranchResolved 26548087 # Number of times decode resolved a branch 127system.cpu.decode.BranchMispred 78411 # Number of times decode detected a branch misprediction 128system.cpu.decode.DecodedInsts 873467434 # Number of instructions handled by decode 129system.cpu.decode.SquashedInsts 311843 # Number of squashed instructions handled by decode 130system.cpu.rename.SquashCycles 30818204 # Number of cycles rename is squashing 131system.cpu.rename.IdleCycles 144286364 # Number of cycles rename is idle 132system.cpu.rename.BlockCycles 8884116 # Number of cycles rename is blocking 133system.cpu.rename.serializeStallCycles 66224882 # count of cycles rename stalled for serializing inst 134system.cpu.rename.RunCycles 159795223 # Number of cycles rename is running 135system.cpu.rename.UnblockCycles 14949233 # Number of cycles rename is unblocking 136system.cpu.rename.RenamedInsts 818684887 # Number of instructions processed by rename 137system.cpu.rename.ROBFullEvents 1541 # Number of times rename has blocked due to ROB full 138system.cpu.rename.IQFullEvents 2838925 # Number of times rename has blocked due to IQ full 139system.cpu.rename.LSQFullEvents 8204276 # Number of times rename has blocked due to LSQ full 140system.cpu.rename.FullRegisterEvents 192 # Number of times there has been no free registers 141system.cpu.rename.RenamedOperands 966602186 # Number of destination operands rename has renamed 142system.cpu.rename.RenameLookups 3574693177 # Number of register rename lookups that rename has made 143system.cpu.rename.int_rename_lookups 3574688542 # Number of integer rename lookups 144system.cpu.rename.fp_rename_lookups 4635 # Number of floating rename lookups 145system.cpu.rename.CommittedMaps 672200163 # Number of HB maps that are committed 146system.cpu.rename.UndoneMaps 294402023 # Number of HB maps that are undone due to squashing 147system.cpu.rename.serializingInsts 5323897 # count of serializing insts renamed 148system.cpu.rename.tempSerializingInsts 5323528 # count of temporary serializing insts renamed 149system.cpu.rename.skidInsts 70458787 # count of insts added to the skid buffer 150system.cpu.memDep0.insertedLoads 172688867 # Number of loads inserted to the mem dependence unit. 151system.cpu.memDep0.insertedStores 75177672 # Number of stores inserted to the mem dependence unit. 152system.cpu.memDep0.conflictingLoads 27536611 # Number of conflicting loads. 153system.cpu.memDep0.conflictingStores 15452316 # Number of conflicting stores. 154system.cpu.iq.iqInstsAdded 763600148 # Number of instructions added to the IQ (excludes non-spec) 155system.cpu.iq.iqNonSpecInstsAdded 6775253 # Number of non-speculative instructions added to the IQ 156system.cpu.iq.iqInstsIssued 672568642 # Number of instructions issued 157system.cpu.iq.iqSquashedInstsIssued 1541380 # Number of squashed instructions issued 158system.cpu.iq.iqSquashedInstsExamined 194741611 # Number of squashed instructions iterated over during squash; mainly for profiling 159system.cpu.iq.iqSquashedOperandsExamined 494202077 # Number of squashed operands that are examined and possibly removed from graph 160system.cpu.iq.iqSquashedNonSpecRemoved 3054137 # Number of squashed non-spec instructions that were removed 161system.cpu.iq.issued_per_cycle::samples 424958022 # Number of insts issued each cycle 162system.cpu.iq.issued_per_cycle::mean 1.582671 # Number of insts issued each cycle 163system.cpu.iq.issued_per_cycle::stdev 1.715070 # Number of insts issued each cycle 164system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 165system.cpu.iq.issued_per_cycle::0 161198015 37.93% 37.93% # Number of insts issued each cycle 166system.cpu.iq.issued_per_cycle::1 79163376 18.63% 56.56% # Number of insts issued each cycle 167system.cpu.iq.issued_per_cycle::2 71154341 16.74% 73.31% # Number of insts issued each cycle 168system.cpu.iq.issued_per_cycle::3 52720722 12.41% 85.71% # Number of insts issued each cycle 169system.cpu.iq.issued_per_cycle::4 30628875 7.21% 92.92% # Number of insts issued each cycle 170system.cpu.iq.issued_per_cycle::5 16032619 3.77% 96.69% # Number of insts issued each cycle 171system.cpu.iq.issued_per_cycle::6 9417662 2.22% 98.91% # Number of insts issued each cycle 172system.cpu.iq.issued_per_cycle::7 3389445 0.80% 99.71% # Number of insts issued each cycle 173system.cpu.iq.issued_per_cycle::8 1252967 0.29% 100.00% # Number of insts issued each cycle 174system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 175system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 176system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 177system.cpu.iq.issued_per_cycle::total 424958022 # Number of insts issued each cycle 178system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 179system.cpu.iq.fu_full::IntAlu 469414 4.82% 4.82% # attempts to use FU when none available 180system.cpu.iq.fu_full::IntMult 0 0.00% 4.82% # attempts to use FU when none available 181system.cpu.iq.fu_full::IntDiv 0 0.00% 4.82% # attempts to use FU when none available 182system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.82% # attempts to use FU when none available 183system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.82% # attempts to use FU when none available 184system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.82% # attempts to use FU when none available 185system.cpu.iq.fu_full::FloatMult 0 0.00% 4.82% # attempts to use FU when none available 186system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.82% # attempts to use FU when none available 187system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.82% # attempts to use FU when none available 188system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.82% # attempts to use FU when none available 189system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.82% # attempts to use FU when none available 190system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.82% # attempts to use FU when none available 191system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.82% # attempts to use FU when none available 192system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.82% # attempts to use FU when none available 193system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.82% # attempts to use FU when none available 194system.cpu.iq.fu_full::SimdMult 0 0.00% 4.82% # attempts to use FU when none available 195system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.82% # attempts to use FU when none available 196system.cpu.iq.fu_full::SimdShift 0 0.00% 4.82% # attempts to use FU when none available 197system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.82% # attempts to use FU when none available 198system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.82% # attempts to use FU when none available 199system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.82% # attempts to use FU when none available 200system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.82% # attempts to use FU when none available 201system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.82% # attempts to use FU when none available 202system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.82% # attempts to use FU when none available 203system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.82% # attempts to use FU when none available 204system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.82% # attempts to use FU when none available 205system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.82% # attempts to use FU when none available 206system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.82% # attempts to use FU when none available 207system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.82% # attempts to use FU when none available 208system.cpu.iq.fu_full::MemRead 6674941 68.55% 73.37% # attempts to use FU when none available 209system.cpu.iq.fu_full::MemWrite 2592845 26.63% 100.00% # attempts to use FU when none available 210system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 211system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 212system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 213system.cpu.iq.FU_type_0::IntAlu 451773589 67.17% 67.17% # Type of FU issued 214system.cpu.iq.FU_type_0::IntMult 385931 0.06% 67.23% # Type of FU issued 215system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.23% # Type of FU issued 216system.cpu.iq.FU_type_0::FloatAdd 236 0.00% 67.23% # Type of FU issued 217system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.23% # Type of FU issued 218system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.23% # Type of FU issued 219system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.23% # Type of FU issued 220system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.23% # Type of FU issued 221system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.23% # Type of FU issued 222system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.23% # Type of FU issued 223system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.23% # Type of FU issued 224system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.23% # Type of FU issued 225system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.23% # Type of FU issued 226system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.23% # Type of FU issued 227system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.23% # Type of FU issued 228system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.23% # Type of FU issued 229system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.23% # Type of FU issued 230system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.23% # Type of FU issued 231system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.23% # Type of FU issued 232system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.23% # Type of FU issued 233system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.23% # Type of FU issued 234system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.23% # Type of FU issued 235system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.23% # Type of FU issued 236system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.23% # Type of FU issued 237system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.23% # Type of FU issued 238system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.23% # Type of FU issued 239system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.23% # Type of FU issued 240system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.23% # Type of FU issued 241system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.23% # Type of FU issued 242system.cpu.iq.FU_type_0::MemRead 155280491 23.09% 90.32% # Type of FU issued 243system.cpu.iq.FU_type_0::MemWrite 65128392 9.68% 100.00% # Type of FU issued 244system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 245system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 246system.cpu.iq.FU_type_0::total 672568642 # Type of FU issued 247system.cpu.iq.rate 1.576831 # Inst issue rate 248system.cpu.iq.fu_busy_cnt 9737200 # FU busy when requested 249system.cpu.iq.fu_busy_rate 0.014478 # FU busy rate (busy events/executed inst) 250system.cpu.iq.int_inst_queue_reads 1781373379 # Number of integer instruction queue reads 251system.cpu.iq.int_inst_queue_writes 965920498 # Number of integer instruction queue writes 252system.cpu.iq.int_inst_queue_wakeup_accesses 652179695 # Number of integer instruction queue wakeup accesses 253system.cpu.iq.fp_inst_queue_reads 507 # Number of floating instruction queue reads 254system.cpu.iq.fp_inst_queue_writes 988 # Number of floating instruction queue writes 255system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses 256system.cpu.iq.int_alu_accesses 682305587 # Number of integer alu accesses 257system.cpu.iq.fp_alu_accesses 255 # Number of floating point alu accesses 258system.cpu.iew.lsq.thread0.forwLoads 8455481 # Number of loads that had data forwarded from stores 259system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 260system.cpu.iew.lsq.thread0.squashedLoads 45915828 # Number of loads squashed 261system.cpu.iew.lsq.thread0.ignoredResponses 43410 # Number of memory responses ignored because the instruction is squashed 262system.cpu.iew.lsq.thread0.memOrderViolation 808399 # Number of memory ordering violations 263system.cpu.iew.lsq.thread0.squashedStores 17573711 # Number of stores squashed 264system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 265system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 266system.cpu.iew.lsq.thread0.rescheduledLoads 19491 # Number of loads that were rescheduled 267system.cpu.iew.lsq.thread0.cacheBlocked 1190 # Number of times an access to memory failed due to the cache being blocked 268system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 269system.cpu.iew.iewSquashCycles 30818204 # Number of cycles IEW is squashing 270system.cpu.iew.iewBlockCycles 4164130 # Number of cycles IEW is blocking 271system.cpu.iew.iewUnblockCycles 269264 # Number of cycles IEW is unblocking 272system.cpu.iew.iewDispatchedInsts 776544403 # Number of instructions dispatched to IQ 273system.cpu.iew.iewDispSquashedInsts 1215899 # Number of squashed instructions skipped by dispatch 274system.cpu.iew.iewDispLoadInsts 172688867 # Number of dispatched load instructions 275system.cpu.iew.iewDispStoreInsts 75177672 # Number of dispatched store instructions 276system.cpu.iew.iewDispNonSpecInsts 5286544 # Number of dispatched non-speculative instructions 277system.cpu.iew.iewIQFullEvents 138154 # Number of times the IQ has become full, causing a stall 278system.cpu.iew.iewLSQFullEvents 7994 # Number of times the LSQ has become full, causing a stall 279system.cpu.iew.memOrderViolationEvents 808399 # Number of memory order violations 280system.cpu.iew.predictedTakenIncorrect 4709852 # Number of branches that were predicted taken incorrectly 281system.cpu.iew.predictedNotTakenIncorrect 6436476 # Number of branches that were predicted not taken incorrectly 282system.cpu.iew.branchMispredicts 11146328 # Number of branch mispredicts detected at execute 283system.cpu.iew.iewExecutedInsts 662608710 # Number of executed instructions 284system.cpu.iew.iewExecLoadInsts 151741633 # Number of load instructions executed 285system.cpu.iew.iewExecSquashedInsts 9959932 # Number of squashed instructions skipped in execute 286system.cpu.iew.exec_swp 0 # number of swp insts executed 287system.cpu.iew.exec_nop 6169002 # number of nop insts executed 288system.cpu.iew.exec_refs 215464084 # number of memory reference insts executed 289system.cpu.iew.exec_branches 137322673 # Number of branches executed 290system.cpu.iew.exec_stores 63722451 # Number of stores executed 291system.cpu.iew.exec_rate 1.553480 # Inst execution rate 292system.cpu.iew.wb_sent 657371500 # cumulative count of insts sent to commit 293system.cpu.iew.wb_count 652179711 # cumulative count of insts written-back 294system.cpu.iew.wb_producers 375708324 # num instructions producing a value 295system.cpu.iew.wb_consumers 644520569 # num instructions consuming a value 296system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 297system.cpu.iew.wb_rate 1.529029 # insts written-back per cycle 298system.cpu.iew.wb_fanout 0.582927 # average fanout of values written-back 299system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 300system.cpu.commit.commitCommittedInsts 510299027 # The number of committed instructions 301system.cpu.commit.commitCommittedOps 574685587 # The number of committed instructions 302system.cpu.commit.commitSquashedInsts 201878689 # The number of squashed insts skipped by commit 303system.cpu.commit.commitNonSpecStalls 3721116 # The number of times commit has been forced to stall to communicate backwards 304system.cpu.commit.branchMispredicts 9919991 # The number of times a branch was mispredicted 305system.cpu.commit.committed_per_cycle::samples 394139819 # Number of insts commited each cycle 306system.cpu.commit.committed_per_cycle::mean 1.458075 # Number of insts commited each cycle 307system.cpu.commit.committed_per_cycle::stdev 2.151494 # Number of insts commited each cycle 308system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 309system.cpu.commit.committed_per_cycle::0 179649221 45.58% 45.58% # Number of insts commited each cycle 310system.cpu.commit.committed_per_cycle::1 103014328 26.14% 71.72% # Number of insts commited each cycle 311system.cpu.commit.committed_per_cycle::2 36282541 9.21% 80.92% # Number of insts commited each cycle 312system.cpu.commit.committed_per_cycle::3 18903013 4.80% 85.72% # Number of insts commited each cycle 313system.cpu.commit.committed_per_cycle::4 16466891 4.18% 89.90% # Number of insts commited each cycle 314system.cpu.commit.committed_per_cycle::5 8169845 2.07% 91.97% # Number of insts commited each cycle 315system.cpu.commit.committed_per_cycle::6 6904317 1.75% 93.72% # Number of insts commited each cycle 316system.cpu.commit.committed_per_cycle::7 3742857 0.95% 94.67% # Number of insts commited each cycle 317system.cpu.commit.committed_per_cycle::8 21006806 5.33% 100.00% # Number of insts commited each cycle 318system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 319system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 320system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 321system.cpu.commit.committed_per_cycle::total 394139819 # Number of insts commited each cycle 322system.cpu.commit.committedInsts 510299027 # Number of instructions committed 323system.cpu.commit.committedOps 574685587 # Number of ops (including micro ops) committed 324system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 325system.cpu.commit.refs 184377000 # Number of memory references committed 326system.cpu.commit.loads 126773039 # Number of loads committed 327system.cpu.commit.membars 1488542 # Number of memory barriers committed 328system.cpu.commit.branches 120192224 # Number of branches committed 329system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. 330system.cpu.commit.int_insts 473701629 # Number of committed integer instructions. 331system.cpu.commit.function_calls 9757362 # Number of function calls committed. 332system.cpu.commit.bw_lim_events 21006806 # number cycles where commit BW limit reached 333system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 334system.cpu.rob.rob_reads 1149690151 # The number of ROB reads 335system.cpu.rob.rob_writes 1584089992 # The number of ROB writes 336system.cpu.timesIdled 76999 # Number of times that the entire CPU went into an idle state and unscheduled itself 337system.cpu.idleCycles 1573858 # Total number of cycles that the CPU has spent unscheduled due to idling 338system.cpu.committedInsts 508955143 # Number of Instructions Simulated 339system.cpu.committedOps 573341703 # Number of Ops (including micro ops) Simulated 340system.cpu.committedInsts_total 508955143 # Number of Instructions Simulated 341system.cpu.cpi 0.838054 # CPI: Cycles Per Instruction 342system.cpu.cpi_total 0.838054 # CPI: Total CPI of All Threads 343system.cpu.ipc 1.193241 # IPC: Instructions Per Cycle 344system.cpu.ipc_total 1.193241 # IPC: Total IPC of All Threads 345system.cpu.int_regfile_reads 3092178369 # number of integer regfile reads 346system.cpu.int_regfile_writes 760489659 # number of integer regfile writes 347system.cpu.fp_regfile_reads 16 # number of floating regfile reads 348system.cpu.misc_regfile_reads 1025175182 # number of misc regfile reads 349system.cpu.misc_regfile_writes 4464052 # number of misc regfile writes 350system.cpu.icache.replacements 15943 # number of replacements 351system.cpu.icache.tagsinuse 1097.454054 # Cycle average of tags in use 352system.cpu.icache.total_refs 114326971 # Total number of references to valid blocks. 353system.cpu.icache.sampled_refs 17802 # Sample count of references to valid blocks. 354system.cpu.icache.avg_refs 6422.141950 # Average number of references to valid blocks. 355system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 356system.cpu.icache.occ_blocks::cpu.inst 1097.454054 # Average occupied blocks per requestor 357system.cpu.icache.occ_percent::cpu.inst 0.535866 # Average percentage of cache occupancy 358system.cpu.icache.occ_percent::total 0.535866 # Average percentage of cache occupancy 359system.cpu.icache.ReadReq_hits::cpu.inst 114326971 # number of ReadReq hits 360system.cpu.icache.ReadReq_hits::total 114326971 # number of ReadReq hits 361system.cpu.icache.demand_hits::cpu.inst 114326971 # number of demand (read+write) hits 362system.cpu.icache.demand_hits::total 114326971 # number of demand (read+write) hits 363system.cpu.icache.overall_hits::cpu.inst 114326971 # number of overall hits 364system.cpu.icache.overall_hits::total 114326971 # number of overall hits 365system.cpu.icache.ReadReq_misses::cpu.inst 19689 # number of ReadReq misses 366system.cpu.icache.ReadReq_misses::total 19689 # number of ReadReq misses 367system.cpu.icache.demand_misses::cpu.inst 19689 # number of demand (read+write) misses 368system.cpu.icache.demand_misses::total 19689 # number of demand (read+write) misses 369system.cpu.icache.overall_misses::cpu.inst 19689 # number of overall misses 370system.cpu.icache.overall_misses::total 19689 # number of overall misses 371system.cpu.icache.ReadReq_miss_latency::cpu.inst 281738500 # number of ReadReq miss cycles 372system.cpu.icache.ReadReq_miss_latency::total 281738500 # number of ReadReq miss cycles 373system.cpu.icache.demand_miss_latency::cpu.inst 281738500 # number of demand (read+write) miss cycles 374system.cpu.icache.demand_miss_latency::total 281738500 # number of demand (read+write) miss cycles 375system.cpu.icache.overall_miss_latency::cpu.inst 281738500 # number of overall miss cycles 376system.cpu.icache.overall_miss_latency::total 281738500 # number of overall miss cycles 377system.cpu.icache.ReadReq_accesses::cpu.inst 114346660 # number of ReadReq accesses(hits+misses) 378system.cpu.icache.ReadReq_accesses::total 114346660 # number of ReadReq accesses(hits+misses) 379system.cpu.icache.demand_accesses::cpu.inst 114346660 # number of demand (read+write) accesses 380system.cpu.icache.demand_accesses::total 114346660 # number of demand (read+write) accesses 381system.cpu.icache.overall_accesses::cpu.inst 114346660 # number of overall (read+write) accesses 382system.cpu.icache.overall_accesses::total 114346660 # number of overall (read+write) accesses 383system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000172 # miss rate for ReadReq accesses 384system.cpu.icache.ReadReq_miss_rate::total 0.000172 # miss rate for ReadReq accesses 385system.cpu.icache.demand_miss_rate::cpu.inst 0.000172 # miss rate for demand accesses 386system.cpu.icache.demand_miss_rate::total 0.000172 # miss rate for demand accesses 387system.cpu.icache.overall_miss_rate::cpu.inst 0.000172 # miss rate for overall accesses 388system.cpu.icache.overall_miss_rate::total 0.000172 # miss rate for overall accesses 389system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14309.436741 # average ReadReq miss latency 390system.cpu.icache.ReadReq_avg_miss_latency::total 14309.436741 # average ReadReq miss latency 391system.cpu.icache.demand_avg_miss_latency::cpu.inst 14309.436741 # average overall miss latency 392system.cpu.icache.demand_avg_miss_latency::total 14309.436741 # average overall miss latency 393system.cpu.icache.overall_avg_miss_latency::cpu.inst 14309.436741 # average overall miss latency 394system.cpu.icache.overall_avg_miss_latency::total 14309.436741 # average overall miss latency 395system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 396system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 397system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 398system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 399system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 400system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 401system.cpu.icache.fast_writes 0 # number of fast writes performed 402system.cpu.icache.cache_copies 0 # number of cache copies performed 403system.cpu.icache.writebacks::writebacks 1 # number of writebacks 404system.cpu.icache.writebacks::total 1 # number of writebacks 405system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1829 # number of ReadReq MSHR hits 406system.cpu.icache.ReadReq_mshr_hits::total 1829 # number of ReadReq MSHR hits 407system.cpu.icache.demand_mshr_hits::cpu.inst 1829 # number of demand (read+write) MSHR hits 408system.cpu.icache.demand_mshr_hits::total 1829 # number of demand (read+write) MSHR hits 409system.cpu.icache.overall_mshr_hits::cpu.inst 1829 # number of overall MSHR hits 410system.cpu.icache.overall_mshr_hits::total 1829 # number of overall MSHR hits 411system.cpu.icache.ReadReq_mshr_misses::cpu.inst 17860 # number of ReadReq MSHR misses 412system.cpu.icache.ReadReq_mshr_misses::total 17860 # number of ReadReq MSHR misses 413system.cpu.icache.demand_mshr_misses::cpu.inst 17860 # number of demand (read+write) MSHR misses 414system.cpu.icache.demand_mshr_misses::total 17860 # number of demand (read+write) MSHR misses 415system.cpu.icache.overall_mshr_misses::cpu.inst 17860 # number of overall MSHR misses 416system.cpu.icache.overall_mshr_misses::total 17860 # number of overall MSHR misses 417system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 184743000 # number of ReadReq MSHR miss cycles 418system.cpu.icache.ReadReq_mshr_miss_latency::total 184743000 # number of ReadReq MSHR miss cycles 419system.cpu.icache.demand_mshr_miss_latency::cpu.inst 184743000 # number of demand (read+write) MSHR miss cycles 420system.cpu.icache.demand_mshr_miss_latency::total 184743000 # number of demand (read+write) MSHR miss cycles 421system.cpu.icache.overall_mshr_miss_latency::cpu.inst 184743000 # number of overall MSHR miss cycles 422system.cpu.icache.overall_mshr_miss_latency::total 184743000 # number of overall MSHR miss cycles 423system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000156 # mshr miss rate for ReadReq accesses 424system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000156 # mshr miss rate for ReadReq accesses 425system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000156 # mshr miss rate for demand accesses 426system.cpu.icache.demand_mshr_miss_rate::total 0.000156 # mshr miss rate for demand accesses 427system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000156 # mshr miss rate for overall accesses 428system.cpu.icache.overall_mshr_miss_rate::total 0.000156 # mshr miss rate for overall accesses 429system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 10343.952968 # average ReadReq mshr miss latency 430system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 10343.952968 # average ReadReq mshr miss latency 431system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 10343.952968 # average overall mshr miss latency 432system.cpu.icache.demand_avg_mshr_miss_latency::total 10343.952968 # average overall mshr miss latency 433system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 10343.952968 # average overall mshr miss latency 434system.cpu.icache.overall_avg_mshr_miss_latency::total 10343.952968 # average overall mshr miss latency 435system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 436system.cpu.dcache.replacements 1188340 # number of replacements 437system.cpu.dcache.tagsinuse 4054.521086 # Cycle average of tags in use 438system.cpu.dcache.total_refs 194732293 # Total number of references to valid blocks. 439system.cpu.dcache.sampled_refs 1192436 # Sample count of references to valid blocks. 440system.cpu.dcache.avg_refs 163.306285 # Average number of references to valid blocks. 441system.cpu.dcache.warmup_cycle 4858281000 # Cycle when the warmup percentage was hit. 442system.cpu.dcache.occ_blocks::cpu.data 4054.521086 # Average occupied blocks per requestor 443system.cpu.dcache.occ_percent::cpu.data 0.989873 # Average percentage of cache occupancy 444system.cpu.dcache.occ_percent::total 0.989873 # Average percentage of cache occupancy 445system.cpu.dcache.ReadReq_hits::cpu.data 137583731 # number of ReadReq hits 446system.cpu.dcache.ReadReq_hits::total 137583731 # number of ReadReq hits 447system.cpu.dcache.WriteReq_hits::cpu.data 52683552 # number of WriteReq hits 448system.cpu.dcache.WriteReq_hits::total 52683552 # number of WriteReq hits 449system.cpu.dcache.LoadLockedReq_hits::cpu.data 2232862 # number of LoadLockedReq hits 450system.cpu.dcache.LoadLockedReq_hits::total 2232862 # number of LoadLockedReq hits 451system.cpu.dcache.StoreCondReq_hits::cpu.data 2232025 # number of StoreCondReq hits 452system.cpu.dcache.StoreCondReq_hits::total 2232025 # number of StoreCondReq hits 453system.cpu.dcache.demand_hits::cpu.data 190267283 # number of demand (read+write) hits 454system.cpu.dcache.demand_hits::total 190267283 # number of demand (read+write) hits 455system.cpu.dcache.overall_hits::cpu.data 190267283 # number of overall hits 456system.cpu.dcache.overall_hits::total 190267283 # number of overall hits 457system.cpu.dcache.ReadReq_misses::cpu.data 1266916 # number of ReadReq misses 458system.cpu.dcache.ReadReq_misses::total 1266916 # number of ReadReq misses 459system.cpu.dcache.WriteReq_misses::cpu.data 1555754 # number of WriteReq misses 460system.cpu.dcache.WriteReq_misses::total 1555754 # number of WriteReq misses 461system.cpu.dcache.LoadLockedReq_misses::cpu.data 41 # number of LoadLockedReq misses 462system.cpu.dcache.LoadLockedReq_misses::total 41 # number of LoadLockedReq misses 463system.cpu.dcache.demand_misses::cpu.data 2822670 # number of demand (read+write) misses 464system.cpu.dcache.demand_misses::total 2822670 # number of demand (read+write) misses 465system.cpu.dcache.overall_misses::cpu.data 2822670 # number of overall misses 466system.cpu.dcache.overall_misses::total 2822670 # number of overall misses 467system.cpu.dcache.ReadReq_miss_latency::cpu.data 15542571000 # number of ReadReq miss cycles 468system.cpu.dcache.ReadReq_miss_latency::total 15542571000 # number of ReadReq miss cycles 469system.cpu.dcache.WriteReq_miss_latency::cpu.data 33103572500 # number of WriteReq miss cycles 470system.cpu.dcache.WriteReq_miss_latency::total 33103572500 # number of WriteReq miss cycles 471system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 516500 # number of LoadLockedReq miss cycles 472system.cpu.dcache.LoadLockedReq_miss_latency::total 516500 # number of LoadLockedReq miss cycles 473system.cpu.dcache.demand_miss_latency::cpu.data 48646143500 # number of demand (read+write) miss cycles 474system.cpu.dcache.demand_miss_latency::total 48646143500 # number of demand (read+write) miss cycles 475system.cpu.dcache.overall_miss_latency::cpu.data 48646143500 # number of overall miss cycles 476system.cpu.dcache.overall_miss_latency::total 48646143500 # number of overall miss cycles 477system.cpu.dcache.ReadReq_accesses::cpu.data 138850647 # number of ReadReq accesses(hits+misses) 478system.cpu.dcache.ReadReq_accesses::total 138850647 # number of ReadReq accesses(hits+misses) 479system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) 480system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) 481system.cpu.dcache.LoadLockedReq_accesses::cpu.data 2232903 # number of LoadLockedReq accesses(hits+misses) 482system.cpu.dcache.LoadLockedReq_accesses::total 2232903 # number of LoadLockedReq accesses(hits+misses) 483system.cpu.dcache.StoreCondReq_accesses::cpu.data 2232025 # number of StoreCondReq accesses(hits+misses) 484system.cpu.dcache.StoreCondReq_accesses::total 2232025 # number of StoreCondReq accesses(hits+misses) 485system.cpu.dcache.demand_accesses::cpu.data 193089953 # number of demand (read+write) accesses 486system.cpu.dcache.demand_accesses::total 193089953 # number of demand (read+write) accesses 487system.cpu.dcache.overall_accesses::cpu.data 193089953 # number of overall (read+write) accesses 488system.cpu.dcache.overall_accesses::total 193089953 # number of overall (read+write) accesses 489system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009124 # miss rate for ReadReq accesses 490system.cpu.dcache.ReadReq_miss_rate::total 0.009124 # miss rate for ReadReq accesses 491system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.028683 # miss rate for WriteReq accesses 492system.cpu.dcache.WriteReq_miss_rate::total 0.028683 # miss rate for WriteReq accesses 493system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000018 # miss rate for LoadLockedReq accesses 494system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000018 # miss rate for LoadLockedReq accesses 495system.cpu.dcache.demand_miss_rate::cpu.data 0.014618 # miss rate for demand accesses 496system.cpu.dcache.demand_miss_rate::total 0.014618 # miss rate for demand accesses 497system.cpu.dcache.overall_miss_rate::cpu.data 0.014618 # miss rate for overall accesses 498system.cpu.dcache.overall_miss_rate::total 0.014618 # miss rate for overall accesses 499system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12268.035923 # average ReadReq miss latency 500system.cpu.dcache.ReadReq_avg_miss_latency::total 12268.035923 # average ReadReq miss latency 501system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 21278.153551 # average WriteReq miss latency 502system.cpu.dcache.WriteReq_avg_miss_latency::total 21278.153551 # average WriteReq miss latency 503system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 12597.560976 # average LoadLockedReq miss latency 504system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 12597.560976 # average LoadLockedReq miss latency 505system.cpu.dcache.demand_avg_miss_latency::cpu.data 17234.088115 # average overall miss latency 506system.cpu.dcache.demand_avg_miss_latency::total 17234.088115 # average overall miss latency 507system.cpu.dcache.overall_avg_miss_latency::cpu.data 17234.088115 # average overall miss latency 508system.cpu.dcache.overall_avg_miss_latency::total 17234.088115 # average overall miss latency 509system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 510system.cpu.dcache.blocked_cycles::no_targets 3299000 # number of cycles access was blocked 511system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 512system.cpu.dcache.blocked::no_targets 559 # number of cycles access was blocked 513system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 514system.cpu.dcache.avg_blocked_cycles::no_targets 5901.610018 # average number of cycles each access was blocked 515system.cpu.dcache.fast_writes 0 # number of fast writes performed 516system.cpu.dcache.cache_copies 0 # number of cache copies performed 517system.cpu.dcache.writebacks::writebacks 1102764 # number of writebacks 518system.cpu.dcache.writebacks::total 1102764 # number of writebacks 519system.cpu.dcache.ReadReq_mshr_hits::cpu.data 422570 # number of ReadReq MSHR hits 520system.cpu.dcache.ReadReq_mshr_hits::total 422570 # number of ReadReq MSHR hits 521system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1207611 # number of WriteReq MSHR hits 522system.cpu.dcache.WriteReq_mshr_hits::total 1207611 # number of WriteReq MSHR hits 523system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 41 # number of LoadLockedReq MSHR hits 524system.cpu.dcache.LoadLockedReq_mshr_hits::total 41 # number of LoadLockedReq MSHR hits 525system.cpu.dcache.demand_mshr_hits::cpu.data 1630181 # number of demand (read+write) MSHR hits 526system.cpu.dcache.demand_mshr_hits::total 1630181 # number of demand (read+write) MSHR hits 527system.cpu.dcache.overall_mshr_hits::cpu.data 1630181 # number of overall MSHR hits 528system.cpu.dcache.overall_mshr_hits::total 1630181 # number of overall MSHR hits 529system.cpu.dcache.ReadReq_mshr_misses::cpu.data 844346 # number of ReadReq MSHR misses 530system.cpu.dcache.ReadReq_mshr_misses::total 844346 # number of ReadReq MSHR misses 531system.cpu.dcache.WriteReq_mshr_misses::cpu.data 348143 # number of WriteReq MSHR misses 532system.cpu.dcache.WriteReq_mshr_misses::total 348143 # number of WriteReq MSHR misses 533system.cpu.dcache.demand_mshr_misses::cpu.data 1192489 # number of demand (read+write) MSHR misses 534system.cpu.dcache.demand_mshr_misses::total 1192489 # number of demand (read+write) MSHR misses 535system.cpu.dcache.overall_mshr_misses::cpu.data 1192489 # number of overall MSHR misses 536system.cpu.dcache.overall_mshr_misses::total 1192489 # number of overall MSHR misses 537system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4793812500 # number of ReadReq MSHR miss cycles 538system.cpu.dcache.ReadReq_mshr_miss_latency::total 4793812500 # number of ReadReq MSHR miss cycles 539system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4284005501 # number of WriteReq MSHR miss cycles 540system.cpu.dcache.WriteReq_mshr_miss_latency::total 4284005501 # number of WriteReq MSHR miss cycles 541system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9077818001 # number of demand (read+write) MSHR miss cycles 542system.cpu.dcache.demand_mshr_miss_latency::total 9077818001 # number of demand (read+write) MSHR miss cycles 543system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9077818001 # number of overall MSHR miss cycles 544system.cpu.dcache.overall_mshr_miss_latency::total 9077818001 # number of overall MSHR miss cycles 545system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006081 # mshr miss rate for ReadReq accesses 546system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006081 # mshr miss rate for ReadReq accesses 547system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006419 # mshr miss rate for WriteReq accesses 548system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006419 # mshr miss rate for WriteReq accesses 549system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006176 # mshr miss rate for demand accesses 550system.cpu.dcache.demand_mshr_miss_rate::total 0.006176 # mshr miss rate for demand accesses 551system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006176 # mshr miss rate for overall accesses 552system.cpu.dcache.overall_mshr_miss_rate::total 0.006176 # mshr miss rate for overall accesses 553system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 5677.545106 # average ReadReq mshr miss latency 554system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 5677.545106 # average ReadReq mshr miss latency 555system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 12305.304145 # average WriteReq mshr miss latency 556system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 12305.304145 # average WriteReq mshr miss latency 557system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 7612.496217 # average overall mshr miss latency 558system.cpu.dcache.demand_avg_mshr_miss_latency::total 7612.496217 # average overall mshr miss latency 559system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 7612.496217 # average overall mshr miss latency 560system.cpu.dcache.overall_avg_mshr_miss_latency::total 7612.496217 # average overall mshr miss latency 561system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 562system.cpu.l2cache.replacements 128738 # number of replacements 563system.cpu.l2cache.tagsinuse 26549.866286 # Cycle average of tags in use 564system.cpu.l2cache.total_refs 1724393 # Total number of references to valid blocks. 565system.cpu.l2cache.sampled_refs 159968 # Sample count of references to valid blocks. 566system.cpu.l2cache.avg_refs 10.779612 # Average number of references to valid blocks. 567system.cpu.l2cache.warmup_cycle 109550112000 # Cycle when the warmup percentage was hit. 568system.cpu.l2cache.occ_blocks::writebacks 22721.325025 # Average occupied blocks per requestor 569system.cpu.l2cache.occ_blocks::cpu.inst 308.211644 # Average occupied blocks per requestor 570system.cpu.l2cache.occ_blocks::cpu.data 3520.329617 # Average occupied blocks per requestor 571system.cpu.l2cache.occ_percent::writebacks 0.693400 # Average percentage of cache occupancy 572system.cpu.l2cache.occ_percent::cpu.inst 0.009406 # Average percentage of cache occupancy 573system.cpu.l2cache.occ_percent::cpu.data 0.107432 # Average percentage of cache occupancy 574system.cpu.l2cache.occ_percent::total 0.810238 # Average percentage of cache occupancy 575system.cpu.l2cache.ReadReq_hits::cpu.inst 14375 # number of ReadReq hits 576system.cpu.l2cache.ReadReq_hits::cpu.data 787281 # number of ReadReq hits 577system.cpu.l2cache.ReadReq_hits::total 801656 # number of ReadReq hits 578system.cpu.l2cache.Writeback_hits::writebacks 1102765 # number of Writeback hits 579system.cpu.l2cache.Writeback_hits::total 1102765 # number of Writeback hits 580system.cpu.l2cache.UpgradeReq_hits::cpu.data 44 # number of UpgradeReq hits 581system.cpu.l2cache.UpgradeReq_hits::total 44 # number of UpgradeReq hits 582system.cpu.l2cache.ReadExReq_hits::cpu.data 248622 # number of ReadExReq hits 583system.cpu.l2cache.ReadExReq_hits::total 248622 # number of ReadExReq hits 584system.cpu.l2cache.demand_hits::cpu.inst 14375 # number of demand (read+write) hits 585system.cpu.l2cache.demand_hits::cpu.data 1035903 # number of demand (read+write) hits 586system.cpu.l2cache.demand_hits::total 1050278 # number of demand (read+write) hits 587system.cpu.l2cache.overall_hits::cpu.inst 14375 # number of overall hits 588system.cpu.l2cache.overall_hits::cpu.data 1035903 # number of overall hits 589system.cpu.l2cache.overall_hits::total 1050278 # number of overall hits 590system.cpu.l2cache.ReadReq_misses::cpu.inst 3428 # number of ReadReq misses 591system.cpu.l2cache.ReadReq_misses::cpu.data 53041 # number of ReadReq misses 592system.cpu.l2cache.ReadReq_misses::total 56469 # number of ReadReq misses 593system.cpu.l2cache.UpgradeReq_misses::cpu.data 6 # number of UpgradeReq misses 594system.cpu.l2cache.UpgradeReq_misses::total 6 # number of UpgradeReq misses 595system.cpu.l2cache.ReadExReq_misses::cpu.data 103489 # number of ReadExReq misses 596system.cpu.l2cache.ReadExReq_misses::total 103489 # number of ReadExReq misses 597system.cpu.l2cache.demand_misses::cpu.inst 3428 # number of demand (read+write) misses 598system.cpu.l2cache.demand_misses::cpu.data 156530 # number of demand (read+write) misses 599system.cpu.l2cache.demand_misses::total 159958 # number of demand (read+write) misses 600system.cpu.l2cache.overall_misses::cpu.inst 3428 # number of overall misses 601system.cpu.l2cache.overall_misses::cpu.data 156530 # number of overall misses 602system.cpu.l2cache.overall_misses::total 159958 # number of overall misses 603system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 121134500 # number of ReadReq miss cycles 604system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1832266000 # number of ReadReq miss cycles 605system.cpu.l2cache.ReadReq_miss_latency::total 1953400500 # number of ReadReq miss cycles 606system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3547601500 # number of ReadExReq miss cycles 607system.cpu.l2cache.ReadExReq_miss_latency::total 3547601500 # number of ReadExReq miss cycles 608system.cpu.l2cache.demand_miss_latency::cpu.inst 121134500 # number of demand (read+write) miss cycles 609system.cpu.l2cache.demand_miss_latency::cpu.data 5379867500 # number of demand (read+write) miss cycles 610system.cpu.l2cache.demand_miss_latency::total 5501002000 # number of demand (read+write) miss cycles 611system.cpu.l2cache.overall_miss_latency::cpu.inst 121134500 # number of overall miss cycles 612system.cpu.l2cache.overall_miss_latency::cpu.data 5379867500 # number of overall miss cycles 613system.cpu.l2cache.overall_miss_latency::total 5501002000 # number of overall miss cycles 614system.cpu.l2cache.ReadReq_accesses::cpu.inst 17803 # number of ReadReq accesses(hits+misses) 615system.cpu.l2cache.ReadReq_accesses::cpu.data 840322 # number of ReadReq accesses(hits+misses) 616system.cpu.l2cache.ReadReq_accesses::total 858125 # number of ReadReq accesses(hits+misses) 617system.cpu.l2cache.Writeback_accesses::writebacks 1102765 # number of Writeback accesses(hits+misses) 618system.cpu.l2cache.Writeback_accesses::total 1102765 # number of Writeback accesses(hits+misses) 619system.cpu.l2cache.UpgradeReq_accesses::cpu.data 50 # number of UpgradeReq accesses(hits+misses) 620system.cpu.l2cache.UpgradeReq_accesses::total 50 # number of UpgradeReq accesses(hits+misses) 621system.cpu.l2cache.ReadExReq_accesses::cpu.data 352111 # number of ReadExReq accesses(hits+misses) 622system.cpu.l2cache.ReadExReq_accesses::total 352111 # number of ReadExReq accesses(hits+misses) 623system.cpu.l2cache.demand_accesses::cpu.inst 17803 # number of demand (read+write) accesses 624system.cpu.l2cache.demand_accesses::cpu.data 1192433 # number of demand (read+write) accesses 625system.cpu.l2cache.demand_accesses::total 1210236 # number of demand (read+write) accesses 626system.cpu.l2cache.overall_accesses::cpu.inst 17803 # number of overall (read+write) accesses 627system.cpu.l2cache.overall_accesses::cpu.data 1192433 # number of overall (read+write) accesses 628system.cpu.l2cache.overall_accesses::total 1210236 # number of overall (read+write) accesses 629system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.192552 # miss rate for ReadReq accesses 630system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.063120 # miss rate for ReadReq accesses 631system.cpu.l2cache.ReadReq_miss_rate::total 0.065805 # miss rate for ReadReq accesses 632system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.120000 # miss rate for UpgradeReq accesses 633system.cpu.l2cache.UpgradeReq_miss_rate::total 0.120000 # miss rate for UpgradeReq accesses 634system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.293910 # miss rate for ReadExReq accesses 635system.cpu.l2cache.ReadExReq_miss_rate::total 0.293910 # miss rate for ReadExReq accesses 636system.cpu.l2cache.demand_miss_rate::cpu.inst 0.192552 # miss rate for demand accesses 637system.cpu.l2cache.demand_miss_rate::cpu.data 0.131269 # miss rate for demand accesses 638system.cpu.l2cache.demand_miss_rate::total 0.132171 # miss rate for demand accesses 639system.cpu.l2cache.overall_miss_rate::cpu.inst 0.192552 # miss rate for overall accesses 640system.cpu.l2cache.overall_miss_rate::cpu.data 0.131269 # miss rate for overall accesses 641system.cpu.l2cache.overall_miss_rate::total 0.132171 # miss rate for overall accesses 642system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35336.785298 # average ReadReq miss latency 643system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34544.333629 # average ReadReq miss latency 644system.cpu.l2cache.ReadReq_avg_miss_latency::total 34592.440100 # average ReadReq miss latency 645system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34279.986279 # average ReadExReq miss latency 646system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34279.986279 # average ReadExReq miss latency 647system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35336.785298 # average overall miss latency 648system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34369.561745 # average overall miss latency 649system.cpu.l2cache.demand_avg_miss_latency::total 34390.289951 # average overall miss latency 650system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35336.785298 # average overall miss latency 651system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34369.561745 # average overall miss latency 652system.cpu.l2cache.overall_avg_miss_latency::total 34390.289951 # average overall miss latency 653system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 654system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 655system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 656system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 657system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 658system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 659system.cpu.l2cache.fast_writes 0 # number of fast writes performed 660system.cpu.l2cache.cache_copies 0 # number of cache copies performed 661system.cpu.l2cache.writebacks::writebacks 104369 # number of writebacks 662system.cpu.l2cache.writebacks::total 104369 # number of writebacks 663system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 7 # number of ReadReq MSHR hits 664system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 20 # number of ReadReq MSHR hits 665system.cpu.l2cache.ReadReq_mshr_hits::total 27 # number of ReadReq MSHR hits 666system.cpu.l2cache.demand_mshr_hits::cpu.inst 7 # number of demand (read+write) MSHR hits 667system.cpu.l2cache.demand_mshr_hits::cpu.data 20 # number of demand (read+write) MSHR hits 668system.cpu.l2cache.demand_mshr_hits::total 27 # number of demand (read+write) MSHR hits 669system.cpu.l2cache.overall_mshr_hits::cpu.inst 7 # number of overall MSHR hits 670system.cpu.l2cache.overall_mshr_hits::cpu.data 20 # number of overall MSHR hits 671system.cpu.l2cache.overall_mshr_hits::total 27 # number of overall MSHR hits 672system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3421 # number of ReadReq MSHR misses 673system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 53021 # number of ReadReq MSHR misses 674system.cpu.l2cache.ReadReq_mshr_misses::total 56442 # number of ReadReq MSHR misses 675system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 6 # number of UpgradeReq MSHR misses 676system.cpu.l2cache.UpgradeReq_mshr_misses::total 6 # number of UpgradeReq MSHR misses 677system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 103489 # number of ReadExReq MSHR misses 678system.cpu.l2cache.ReadExReq_mshr_misses::total 103489 # number of ReadExReq MSHR misses 679system.cpu.l2cache.demand_mshr_misses::cpu.inst 3421 # number of demand (read+write) MSHR misses 680system.cpu.l2cache.demand_mshr_misses::cpu.data 156510 # number of demand (read+write) MSHR misses 681system.cpu.l2cache.demand_mshr_misses::total 159931 # number of demand (read+write) MSHR misses 682system.cpu.l2cache.overall_mshr_misses::cpu.inst 3421 # number of overall MSHR misses 683system.cpu.l2cache.overall_mshr_misses::cpu.data 156510 # number of overall MSHR misses 684system.cpu.l2cache.overall_mshr_misses::total 159931 # number of overall MSHR misses 685system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 110230000 # number of ReadReq MSHR miss cycles 686system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1664605500 # number of ReadReq MSHR miss cycles 687system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1774835500 # number of ReadReq MSHR miss cycles 688system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 186000 # number of UpgradeReq MSHR miss cycles 689system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 186000 # number of UpgradeReq MSHR miss cycles 690system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3213112500 # number of ReadExReq MSHR miss cycles 691system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3213112500 # number of ReadExReq MSHR miss cycles 692system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 110230000 # number of demand (read+write) MSHR miss cycles 693system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4877718000 # number of demand (read+write) MSHR miss cycles 694system.cpu.l2cache.demand_mshr_miss_latency::total 4987948000 # number of demand (read+write) MSHR miss cycles 695system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 110230000 # number of overall MSHR miss cycles 696system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4877718000 # number of overall MSHR miss cycles 697system.cpu.l2cache.overall_mshr_miss_latency::total 4987948000 # number of overall MSHR miss cycles 698system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.192159 # mshr miss rate for ReadReq accesses 699system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.063096 # mshr miss rate for ReadReq accesses 700system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.065774 # mshr miss rate for ReadReq accesses 701system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.120000 # mshr miss rate for UpgradeReq accesses 702system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.120000 # mshr miss rate for UpgradeReq accesses 703system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.293910 # mshr miss rate for ReadExReq accesses 704system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.293910 # mshr miss rate for ReadExReq accesses 705system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.192159 # mshr miss rate for demand accesses 706system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.131253 # mshr miss rate for demand accesses 707system.cpu.l2cache.demand_mshr_miss_rate::total 0.132149 # mshr miss rate for demand accesses 708system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.192159 # mshr miss rate for overall accesses 709system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.131253 # mshr miss rate for overall accesses 710system.cpu.l2cache.overall_mshr_miss_rate::total 0.132149 # mshr miss rate for overall accesses 711system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32221.572640 # average ReadReq mshr miss latency 712system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31395.211331 # average ReadReq mshr miss latency 713system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31445.297828 # average ReadReq mshr miss latency 714system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31000 # average UpgradeReq mshr miss latency 715system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31000 # average UpgradeReq mshr miss latency 716system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31047.864990 # average ReadExReq mshr miss latency 717system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31047.864990 # average ReadExReq mshr miss latency 718system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32221.572640 # average overall mshr miss latency 719system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31165.535749 # average overall mshr miss latency 720system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31188.124879 # average overall mshr miss latency 721system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32221.572640 # average overall mshr miss latency 722system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31165.535749 # average overall mshr miss latency 723system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31188.124879 # average overall mshr miss latency 724system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 725 726---------- End Simulation Statistics ---------- 727