stats.txt revision 11754:c209cb86278a
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.236024 # Number of seconds simulated 4sim_ticks 236023688000 # Number of ticks simulated 5final_tick 236023688000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 256452 # Simulator instruction rate (inst/s) 8host_op_rate 277829 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 119803336 # Simulator tick rate (ticks/s) 10host_mem_usage 301968 # Number of bytes of host memory used 11host_seconds 1970.09 # Real time elapsed on the host 12sim_insts 505234934 # Number of instructions simulated 13sim_ops 547348155 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.pwrStateResidencyTicks::UNDEFINED 236023688000 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.inst 640832 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 10509760 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.l2cache.prefetcher 16394496 # Number of bytes read from this memory 20system.physmem.bytes_read::total 27545088 # Number of bytes read from this memory 21system.physmem.bytes_inst_read::cpu.inst 640832 # Number of instructions bytes read from this memory 22system.physmem.bytes_inst_read::total 640832 # Number of instructions bytes read from this memory 23system.physmem.bytes_written::writebacks 18630208 # Number of bytes written to this memory 24system.physmem.bytes_written::total 18630208 # Number of bytes written to this memory 25system.physmem.num_reads::cpu.inst 10013 # Number of read requests responded to by this memory 26system.physmem.num_reads::cpu.data 164215 # Number of read requests responded to by this memory 27system.physmem.num_reads::cpu.l2cache.prefetcher 256164 # Number of read requests responded to by this memory 28system.physmem.num_reads::total 430392 # Number of read requests responded to by this memory 29system.physmem.num_writes::writebacks 291097 # Number of write requests responded to by this memory 30system.physmem.num_writes::total 291097 # Number of write requests responded to by this memory 31system.physmem.bw_read::cpu.inst 2715117 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_read::cpu.data 44528412 # Total read bandwidth from this memory (bytes/s) 33system.physmem.bw_read::cpu.l2cache.prefetcher 69461231 # Total read bandwidth from this memory (bytes/s) 34system.physmem.bw_read::total 116704761 # Total read bandwidth from this memory (bytes/s) 35system.physmem.bw_inst_read::cpu.inst 2715117 # Instruction read bandwidth from this memory (bytes/s) 36system.physmem.bw_inst_read::total 2715117 # Instruction read bandwidth from this memory (bytes/s) 37system.physmem.bw_write::writebacks 78933637 # Write bandwidth from this memory (bytes/s) 38system.physmem.bw_write::total 78933637 # Write bandwidth from this memory (bytes/s) 39system.physmem.bw_total::writebacks 78933637 # Total bandwidth to/from this memory (bytes/s) 40system.physmem.bw_total::cpu.inst 2715117 # Total bandwidth to/from this memory (bytes/s) 41system.physmem.bw_total::cpu.data 44528412 # Total bandwidth to/from this memory (bytes/s) 42system.physmem.bw_total::cpu.l2cache.prefetcher 69461231 # Total bandwidth to/from this memory (bytes/s) 43system.physmem.bw_total::total 195638397 # Total bandwidth to/from this memory (bytes/s) 44system.physmem.readReqs 430392 # Number of read requests accepted 45system.physmem.writeReqs 291097 # Number of write requests accepted 46system.physmem.readBursts 430392 # Number of DRAM read bursts, including those serviced by the write queue 47system.physmem.writeBursts 291097 # Number of DRAM write bursts, including those merged in the write queue 48system.physmem.bytesReadDRAM 27379648 # Total number of bytes read from DRAM 49system.physmem.bytesReadWrQ 165440 # Total number of bytes read from write queue 50system.physmem.bytesWritten 18628032 # Total number of bytes written to DRAM 51system.physmem.bytesReadSys 27545088 # Total read bytes from the system interface side 52system.physmem.bytesWrittenSys 18630208 # Total written bytes from the system interface side 53system.physmem.servicedByWrQ 2585 # Number of DRAM read bursts serviced by the write queue 54system.physmem.mergedWrBursts 6 # Number of DRAM write bursts merged with an existing one 55system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 56system.physmem.perBankRdBursts::0 27300 # Per bank write bursts 57system.physmem.perBankRdBursts::1 26589 # Per bank write bursts 58system.physmem.perBankRdBursts::2 25489 # Per bank write bursts 59system.physmem.perBankRdBursts::3 32817 # Per bank write bursts 60system.physmem.perBankRdBursts::4 28238 # Per bank write bursts 61system.physmem.perBankRdBursts::5 30052 # Per bank write bursts 62system.physmem.perBankRdBursts::6 25322 # Per bank write bursts 63system.physmem.perBankRdBursts::7 24428 # Per bank write bursts 64system.physmem.perBankRdBursts::8 25638 # Per bank write bursts 65system.physmem.perBankRdBursts::9 25508 # Per bank write bursts 66system.physmem.perBankRdBursts::10 25695 # Per bank write bursts 67system.physmem.perBankRdBursts::11 26146 # Per bank write bursts 68system.physmem.perBankRdBursts::12 27543 # Per bank write bursts 69system.physmem.perBankRdBursts::13 26122 # Per bank write bursts 70system.physmem.perBankRdBursts::14 24924 # Per bank write bursts 71system.physmem.perBankRdBursts::15 25996 # Per bank write bursts 72system.physmem.perBankWrBursts::0 18688 # Per bank write bursts 73system.physmem.perBankWrBursts::1 18252 # Per bank write bursts 74system.physmem.perBankWrBursts::2 17892 # Per bank write bursts 75system.physmem.perBankWrBursts::3 17877 # Per bank write bursts 76system.physmem.perBankWrBursts::4 18635 # Per bank write bursts 77system.physmem.perBankWrBursts::5 18189 # Per bank write bursts 78system.physmem.perBankWrBursts::6 17877 # Per bank write bursts 79system.physmem.perBankWrBursts::7 17743 # Per bank write bursts 80system.physmem.perBankWrBursts::8 17943 # Per bank write bursts 81system.physmem.perBankWrBursts::9 17697 # Per bank write bursts 82system.physmem.perBankWrBursts::10 18014 # Per bank write bursts 83system.physmem.perBankWrBursts::11 18785 # Per bank write bursts 84system.physmem.perBankWrBursts::12 18684 # Per bank write bursts 85system.physmem.perBankWrBursts::13 18184 # Per bank write bursts 86system.physmem.perBankWrBursts::14 18324 # Per bank write bursts 87system.physmem.perBankWrBursts::15 18279 # Per bank write bursts 88system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 89system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 90system.physmem.totGap 236023635500 # Total gap between requests 91system.physmem.readPktSize::0 0 # Read request sizes (log2) 92system.physmem.readPktSize::1 0 # Read request sizes (log2) 93system.physmem.readPktSize::2 0 # Read request sizes (log2) 94system.physmem.readPktSize::3 0 # Read request sizes (log2) 95system.physmem.readPktSize::4 0 # Read request sizes (log2) 96system.physmem.readPktSize::5 0 # Read request sizes (log2) 97system.physmem.readPktSize::6 430392 # Read request sizes (log2) 98system.physmem.writePktSize::0 0 # Write request sizes (log2) 99system.physmem.writePktSize::1 0 # Write request sizes (log2) 100system.physmem.writePktSize::2 0 # Write request sizes (log2) 101system.physmem.writePktSize::3 0 # Write request sizes (log2) 102system.physmem.writePktSize::4 0 # Write request sizes (log2) 103system.physmem.writePktSize::5 0 # Write request sizes (log2) 104system.physmem.writePktSize::6 291097 # Write request sizes (log2) 105system.physmem.rdQLenPdf::0 318668 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::1 60537 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::2 13344 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::3 8917 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::4 7275 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::5 6198 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::6 5201 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::7 4287 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::8 3249 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::9 78 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::10 32 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::11 10 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::12 8 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::13 3 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 137system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::15 6733 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::16 7233 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::17 12073 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::18 14859 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::19 16212 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::20 16884 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::21 17281 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::22 17602 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::23 17833 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::24 18085 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::25 18311 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::26 18465 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::27 18518 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::28 18609 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::29 18833 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::30 18532 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::31 17483 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::32 17245 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::33 140 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::34 75 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::35 31 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::36 17 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::37 7 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::38 3 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::39 2 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::40 2 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::41 3 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::42 1 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::43 2 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::44 1 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::45 1 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 201system.physmem.bytesPerActivate::samples 328591 # Bytes accessed per row activation 202system.physmem.bytesPerActivate::mean 140.009775 # Bytes accessed per row activation 203system.physmem.bytesPerActivate::gmean 98.675291 # Bytes accessed per row activation 204system.physmem.bytesPerActivate::stdev 178.430270 # Bytes accessed per row activation 205system.physmem.bytesPerActivate::0-127 209431 63.74% 63.74% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::128-255 79588 24.22% 87.96% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::256-383 14900 4.53% 92.49% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::384-511 7308 2.22% 94.72% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::512-639 4939 1.50% 96.22% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::640-767 2586 0.79% 97.01% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::768-895 1820 0.55% 97.56% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::896-1023 1543 0.47% 98.03% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::1024-1151 6476 1.97% 100.00% # Bytes accessed per row activation 214system.physmem.bytesPerActivate::total 328591 # Bytes accessed per row activation 215system.physmem.rdPerTurnAround::samples 17028 # Reads before turning the bus around for writes 216system.physmem.rdPerTurnAround::mean 25.118628 # Reads before turning the bus around for writes 217system.physmem.rdPerTurnAround::stdev 145.022717 # Reads before turning the bus around for writes 218system.physmem.rdPerTurnAround::0-1023 17026 99.99% 99.99% # Reads before turning the bus around for writes 219system.physmem.rdPerTurnAround::1024-2047 1 0.01% 99.99% # Reads before turning the bus around for writes 220system.physmem.rdPerTurnAround::18432-19455 1 0.01% 100.00% # Reads before turning the bus around for writes 221system.physmem.rdPerTurnAround::total 17028 # Reads before turning the bus around for writes 222system.physmem.wrPerTurnAround::samples 17028 # Writes before turning the bus around for reads 223system.physmem.wrPerTurnAround::mean 17.093199 # Writes before turning the bus around for reads 224system.physmem.wrPerTurnAround::gmean 17.022957 # Writes before turning the bus around for reads 225system.physmem.wrPerTurnAround::stdev 1.821852 # Writes before turning the bus around for reads 226system.physmem.wrPerTurnAround::16-17 10045 58.99% 58.99% # Writes before turning the bus around for reads 227system.physmem.wrPerTurnAround::18-19 6192 36.36% 95.35% # Writes before turning the bus around for reads 228system.physmem.wrPerTurnAround::20-21 538 3.16% 98.51% # Writes before turning the bus around for reads 229system.physmem.wrPerTurnAround::22-23 158 0.93% 99.44% # Writes before turning the bus around for reads 230system.physmem.wrPerTurnAround::24-25 50 0.29% 99.74% # Writes before turning the bus around for reads 231system.physmem.wrPerTurnAround::26-27 18 0.11% 99.84% # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::28-29 8 0.05% 99.89% # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::30-31 3 0.02% 99.91% # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::32-33 4 0.02% 99.93% # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::34-35 3 0.02% 99.95% # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::36-37 1 0.01% 99.95% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::38-39 1 0.01% 99.96% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::42-43 1 0.01% 99.96% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::44-45 1 0.01% 99.97% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::50-51 1 0.01% 99.98% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::52-53 1 0.01% 99.98% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::70-71 1 0.01% 99.99% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::90-91 1 0.01% 99.99% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::92-93 1 0.01% 100.00% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::total 17028 # Writes before turning the bus around for reads 246system.physmem.totQLat 14230918095 # Total ticks spent queuing 247system.physmem.totMemAccLat 22252299345 # Total ticks spent from burst creation until serviced by the DRAM 248system.physmem.totBusLat 2139035000 # Total ticks spent in databus transfers 249system.physmem.avgQLat 33264.81 # Average queueing delay per DRAM burst 250system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 251system.physmem.avgMemAccLat 52014.81 # Average memory access latency per DRAM burst 252system.physmem.avgRdBW 116.00 # Average DRAM read bandwidth in MiByte/s 253system.physmem.avgWrBW 78.92 # Average achieved write bandwidth in MiByte/s 254system.physmem.avgRdBWSys 116.70 # Average system read bandwidth in MiByte/s 255system.physmem.avgWrBWSys 78.93 # Average system write bandwidth in MiByte/s 256system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 257system.physmem.busUtil 1.52 # Data bus utilization in percentage 258system.physmem.busUtilRead 0.91 # Data bus utilization in percentage for reads 259system.physmem.busUtilWrite 0.62 # Data bus utilization in percentage for writes 260system.physmem.avgRdQLen 1.13 # Average read queue length when enqueuing 261system.physmem.avgWrQLen 21.76 # Average write queue length when enqueuing 262system.physmem.readRowHits 308090 # Number of row buffer hits during reads 263system.physmem.writeRowHits 82180 # Number of row buffer hits during writes 264system.physmem.readRowHitRate 72.02 # Row buffer hit rate for reads 265system.physmem.writeRowHitRate 28.23 # Row buffer hit rate for writes 266system.physmem.avgGap 327134.07 # Average gap between requests 267system.physmem.pageHitRate 54.29 # Row buffer hit rate, read and write combined 268system.physmem_0.actEnergy 1195143180 # Energy for activate commands per rank (pJ) 269system.physmem_0.preEnergy 635214690 # Energy for precharge commands per rank (pJ) 270system.physmem_0.readEnergy 1572477900 # Energy for read commands per rank (pJ) 271system.physmem_0.writeEnergy 757698660 # Energy for write commands per rank (pJ) 272system.physmem_0.refreshEnergy 15717574080.000004 # Energy for refresh commands per rank (pJ) 273system.physmem_0.actBackEnergy 13455213090 # Energy for active background per rank (pJ) 274system.physmem_0.preBackEnergy 610838880 # Energy for precharge background per rank (pJ) 275system.physmem_0.actPowerDownEnergy 46153778370 # Energy for active power-down per rank (pJ) 276system.physmem_0.prePowerDownEnergy 17481507840 # Energy for precharge power-down per rank (pJ) 277system.physmem_0.selfRefreshEnergy 15586959435 # Energy for self refresh per rank (pJ) 278system.physmem_0.totalEnergy 113172096165 # Total energy per rank (pJ) 279system.physmem_0.averagePower 479.494648 # Core power per rank (mW) 280system.physmem_0.totalIdleTime 204913310074 # Total Idle time Per DRAM Rank 281system.physmem_0.memoryStateTime::IDLE 902504711 # Time in different power states 282system.physmem_0.memoryStateTime::REF 6666906000 # Time in different power states 283system.physmem_0.memoryStateTime::SREF 58174043250 # Time in different power states 284system.physmem_0.memoryStateTime::PRE_PDN 45524259021 # Time in different power states 285system.physmem_0.memoryStateTime::ACT 23540851965 # Time in different power states 286system.physmem_0.memoryStateTime::ACT_PDN 101215123053 # Time in different power states 287system.physmem_1.actEnergy 1151060820 # Energy for activate commands per rank (pJ) 288system.physmem_1.preEnergy 611788155 # Energy for precharge commands per rank (pJ) 289system.physmem_1.readEnergy 1482064080 # Energy for read commands per rank (pJ) 290system.physmem_1.writeEnergy 761650200 # Energy for write commands per rank (pJ) 291system.physmem_1.refreshEnergy 15007050240.000004 # Energy for refresh commands per rank (pJ) 292system.physmem_1.actBackEnergy 13420176330 # Energy for active background per rank (pJ) 293system.physmem_1.preBackEnergy 597461760 # Energy for precharge background per rank (pJ) 294system.physmem_1.actPowerDownEnergy 42655727700 # Energy for active power-down per rank (pJ) 295system.physmem_1.prePowerDownEnergy 16961144160 # Energy for precharge power-down per rank (pJ) 296system.physmem_1.selfRefreshEnergy 17790500985 # Energy for self refresh per rank (pJ) 297system.physmem_1.totalEnergy 110444200560 # Total energy per rank (pJ) 298system.physmem_1.averagePower 467.936931 # Core power per rank (mW) 299system.physmem_1.totalIdleTime 205025277615 # Total Idle time Per DRAM Rank 300system.physmem_1.memoryStateTime::IDLE 898721445 # Time in different power states 301system.physmem_1.memoryStateTime::REF 6366412000 # Time in different power states 302system.physmem_1.memoryStateTime::SREF 67312288506 # Time in different power states 303system.physmem_1.memoryStateTime::PRE_PDN 44168958563 # Time in different power states 304system.physmem_1.memoryStateTime::ACT 23733276940 # Time in different power states 305system.physmem_1.memoryStateTime::ACT_PDN 93544030546 # Time in different power states 306system.pwrStateResidencyTicks::UNDEFINED 236023688000 # Cumulative time (in ticks) in various power states 307system.cpu.branchPred.lookups 174594111 # Number of BP lookups 308system.cpu.branchPred.condPredicted 131059017 # Number of conditional branches predicted 309system.cpu.branchPred.condIncorrect 7233933 # Number of conditional branches incorrect 310system.cpu.branchPred.BTBLookups 90232346 # Number of BTB lookups 311system.cpu.branchPred.BTBHits 78999638 # Number of BTB hits 312system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 313system.cpu.branchPred.BTBHitPct 87.551351 # BTB Hit Percentage 314system.cpu.branchPred.usedRAS 12106114 # Number of times the RAS was used to get a target. 315system.cpu.branchPred.RASInCorrect 104453 # Number of incorrect RAS predictions. 316system.cpu.branchPred.indirectLookups 4688512 # Number of indirect predictor lookups. 317system.cpu.branchPred.indirectHits 4673325 # Number of indirect target hits. 318system.cpu.branchPred.indirectMisses 15187 # Number of indirect misses. 319system.cpu.branchPredindirectMispredicted 53879 # Number of mispredicted indirect branches. 320system.cpu_clk_domain.clock 500 # Clock period in ticks 321system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 236023688000 # Cumulative time (in ticks) in various power states 322system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 323system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 324system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 325system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 326system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 327system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 328system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 329system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 330system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 331system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 332system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 333system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 334system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 335system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 336system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 337system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 338system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 339system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 340system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 341system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 342system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 343system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 344system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 345system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 346system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 347system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 348system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 349system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 350system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 351system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 236023688000 # Cumulative time (in ticks) in various power states 352system.cpu.dtb.walker.walks 0 # Table walker walks requested 353system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 354system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 355system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 356system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 357system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 358system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 359system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 360system.cpu.dtb.inst_hits 0 # ITB inst hits 361system.cpu.dtb.inst_misses 0 # ITB inst misses 362system.cpu.dtb.read_hits 0 # DTB read hits 363system.cpu.dtb.read_misses 0 # DTB read misses 364system.cpu.dtb.write_hits 0 # DTB write hits 365system.cpu.dtb.write_misses 0 # DTB write misses 366system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 367system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 368system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 369system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 370system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 371system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 372system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 373system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 374system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 375system.cpu.dtb.read_accesses 0 # DTB read accesses 376system.cpu.dtb.write_accesses 0 # DTB write accesses 377system.cpu.dtb.inst_accesses 0 # ITB inst accesses 378system.cpu.dtb.hits 0 # DTB hits 379system.cpu.dtb.misses 0 # DTB misses 380system.cpu.dtb.accesses 0 # DTB accesses 381system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 236023688000 # Cumulative time (in ticks) in various power states 382system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 383system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 384system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 385system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 386system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 387system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 388system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 389system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 390system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 391system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 392system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 393system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 394system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 395system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 396system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 397system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 398system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 399system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 400system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 401system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 402system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 403system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 404system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 405system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 406system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 407system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 408system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 409system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 410system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 411system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 236023688000 # Cumulative time (in ticks) in various power states 412system.cpu.itb.walker.walks 0 # Table walker walks requested 413system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 414system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 415system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 416system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 417system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 418system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 419system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 420system.cpu.itb.inst_hits 0 # ITB inst hits 421system.cpu.itb.inst_misses 0 # ITB inst misses 422system.cpu.itb.read_hits 0 # DTB read hits 423system.cpu.itb.read_misses 0 # DTB read misses 424system.cpu.itb.write_hits 0 # DTB write hits 425system.cpu.itb.write_misses 0 # DTB write misses 426system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 427system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 428system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 429system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 430system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 431system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 432system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 433system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 434system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 435system.cpu.itb.read_accesses 0 # DTB read accesses 436system.cpu.itb.write_accesses 0 # DTB write accesses 437system.cpu.itb.inst_accesses 0 # ITB inst accesses 438system.cpu.itb.hits 0 # DTB hits 439system.cpu.itb.misses 0 # DTB misses 440system.cpu.itb.accesses 0 # DTB accesses 441system.cpu.workload.num_syscalls 548 # Number of system calls 442system.cpu.pwrStateResidencyTicks::ON 236023688000 # Cumulative time (in ticks) in various power states 443system.cpu.numCycles 472047377 # number of cpu cycles simulated 444system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 445system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 446system.cpu.fetch.icacheStallCycles 7665841 # Number of cycles fetch is stalled on an Icache miss 447system.cpu.fetch.Insts 727531021 # Number of instructions fetch has processed 448system.cpu.fetch.Branches 174594111 # Number of branches that fetch encountered 449system.cpu.fetch.predictedBranches 95779077 # Number of branches that fetch has predicted taken 450system.cpu.fetch.Cycles 455980909 # Number of cycles fetch has run and was not squashing or blocked 451system.cpu.fetch.SquashCycles 14521279 # Number of cycles fetch has spent squashing 452system.cpu.fetch.MiscStallCycles 6370 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 453system.cpu.fetch.PendingTrapStallCycles 74 # Number of stall cycles due to pending traps 454system.cpu.fetch.IcacheWaitRetryStallCycles 14846 # Number of stall cycles due to full MSHR 455system.cpu.fetch.CacheLines 235277273 # Number of cache lines fetched 456system.cpu.fetch.IcacheSquashes 36996 # Number of outstanding Icache misses that were squashed 457system.cpu.fetch.rateDist::samples 470928679 # Number of instructions fetched each cycle (Total) 458system.cpu.fetch.rateDist::mean 1.672614 # Number of instructions fetched each cycle (Total) 459system.cpu.fetch.rateDist::stdev 1.189870 # Number of instructions fetched each cycle (Total) 460system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 461system.cpu.fetch.rateDist::0 101212688 21.49% 21.49% # Number of instructions fetched each cycle (Total) 462system.cpu.fetch.rateDist::1 132055507 28.04% 49.53% # Number of instructions fetched each cycle (Total) 463system.cpu.fetch.rateDist::2 57355152 12.18% 61.71% # Number of instructions fetched each cycle (Total) 464system.cpu.fetch.rateDist::3 180305332 38.29% 100.00% # Number of instructions fetched each cycle (Total) 465system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 466system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 467system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) 468system.cpu.fetch.rateDist::total 470928679 # Number of instructions fetched each cycle (Total) 469system.cpu.fetch.branchRate 0.369866 # Number of branch fetches per cycle 470system.cpu.fetch.rate 1.541225 # Number of inst fetches per cycle 471system.cpu.decode.IdleCycles 32549304 # Number of cycles decode is idle 472system.cpu.decode.BlockedCycles 125870927 # Number of cycles decode is blocked 473system.cpu.decode.RunCycles 282926168 # Number of cycles decode is running 474system.cpu.decode.UnblockCycles 22809881 # Number of cycles decode is unblocking 475system.cpu.decode.SquashCycles 6772399 # Number of cycles decode is squashing 476system.cpu.decode.BranchResolved 23857268 # Number of times decode resolved a branch 477system.cpu.decode.BranchMispred 495900 # Number of times decode detected a branch misprediction 478system.cpu.decode.DecodedInsts 710989368 # Number of instructions handled by decode 479system.cpu.decode.SquashedInsts 29087460 # Number of squashed instructions handled by decode 480system.cpu.rename.SquashCycles 6772399 # Number of cycles rename is squashing 481system.cpu.rename.IdleCycles 63357486 # Number of cycles rename is idle 482system.cpu.rename.BlockCycles 61253040 # Number of cycles rename is blocking 483system.cpu.rename.serializeStallCycles 40466365 # count of cycles rename stalled for serializing inst 484system.cpu.rename.RunCycles 273530421 # Number of cycles rename is running 485system.cpu.rename.UnblockCycles 25548968 # Number of cycles rename is unblocking 486system.cpu.rename.RenamedInsts 682720764 # Number of instructions processed by rename 487system.cpu.rename.SquashedInsts 12849971 # Number of squashed instructions processed by rename 488system.cpu.rename.ROBFullEvents 10025216 # Number of times rename has blocked due to ROB full 489system.cpu.rename.IQFullEvents 2519363 # Number of times rename has blocked due to IQ full 490system.cpu.rename.LQFullEvents 1823930 # Number of times rename has blocked due to LQ full 491system.cpu.rename.SQFullEvents 2318589 # Number of times rename has blocked due to SQ full 492system.cpu.rename.RenamedOperands 827514324 # Number of destination operands rename has renamed 493system.cpu.rename.RenameLookups 3000521547 # Number of register rename lookups that rename has made 494system.cpu.rename.int_rename_lookups 718647704 # Number of integer rename lookups 495system.cpu.rename.fp_rename_lookups 128 # Number of floating rename lookups 496system.cpu.rename.CommittedMaps 654095674 # Number of HB maps that are committed 497system.cpu.rename.UndoneMaps 173418650 # Number of HB maps that are undone due to squashing 498system.cpu.rename.serializingInsts 1545803 # count of serializing insts renamed 499system.cpu.rename.tempSerializingInsts 1536177 # count of temporary serializing insts renamed 500system.cpu.rename.skidInsts 43812625 # count of insts added to the skid buffer 501system.cpu.memDep0.insertedLoads 142363196 # Number of loads inserted to the mem dependence unit. 502system.cpu.memDep0.insertedStores 67528532 # Number of stores inserted to the mem dependence unit. 503system.cpu.memDep0.conflictingLoads 12884136 # Number of conflicting loads. 504system.cpu.memDep0.conflictingStores 11268568 # Number of conflicting stores. 505system.cpu.iq.iqInstsAdded 664776091 # Number of instructions added to the IQ (excludes non-spec) 506system.cpu.iq.iqNonSpecInstsAdded 2979332 # Number of non-speculative instructions added to the IQ 507system.cpu.iq.iqInstsIssued 608934070 # Number of instructions issued 508system.cpu.iq.iqSquashedInstsIssued 5749195 # Number of squashed instructions issued 509system.cpu.iq.iqSquashedInstsExamined 120407268 # Number of squashed instructions iterated over during squash; mainly for profiling 510system.cpu.iq.iqSquashedOperandsExamined 306545068 # Number of squashed operands that are examined and possibly removed from graph 511system.cpu.iq.iqSquashedNonSpecRemoved 1700 # Number of squashed non-spec instructions that were removed 512system.cpu.iq.issued_per_cycle::samples 470928679 # Number of insts issued each cycle 513system.cpu.iq.issued_per_cycle::mean 1.293049 # Number of insts issued each cycle 514system.cpu.iq.issued_per_cycle::stdev 1.104484 # Number of insts issued each cycle 515system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 516system.cpu.iq.issued_per_cycle::0 154505965 32.81% 32.81% # Number of insts issued each cycle 517system.cpu.iq.issued_per_cycle::1 100895056 21.42% 54.23% # Number of insts issued each cycle 518system.cpu.iq.issued_per_cycle::2 145511490 30.90% 85.13% # Number of insts issued each cycle 519system.cpu.iq.issued_per_cycle::3 63049261 13.39% 98.52% # Number of insts issued each cycle 520system.cpu.iq.issued_per_cycle::4 6966284 1.48% 100.00% # Number of insts issued each cycle 521system.cpu.iq.issued_per_cycle::5 623 0.00% 100.00% # Number of insts issued each cycle 522system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 523system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 524system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 525system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 526system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 527system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle 528system.cpu.iq.issued_per_cycle::total 470928679 # Number of insts issued each cycle 529system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 530system.cpu.iq.fu_full::IntAlu 71893204 53.11% 53.11% # attempts to use FU when none available 531system.cpu.iq.fu_full::IntMult 30 0.00% 53.11% # attempts to use FU when none available 532system.cpu.iq.fu_full::IntDiv 0 0.00% 53.11% # attempts to use FU when none available 533system.cpu.iq.fu_full::FloatAdd 0 0.00% 53.11% # attempts to use FU when none available 534system.cpu.iq.fu_full::FloatCmp 0 0.00% 53.11% # attempts to use FU when none available 535system.cpu.iq.fu_full::FloatCvt 0 0.00% 53.11% # attempts to use FU when none available 536system.cpu.iq.fu_full::FloatMult 0 0.00% 53.11% # attempts to use FU when none available 537system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 53.11% # attempts to use FU when none available 538system.cpu.iq.fu_full::FloatDiv 0 0.00% 53.11% # attempts to use FU when none available 539system.cpu.iq.fu_full::FloatMisc 0 0.00% 53.11% # attempts to use FU when none available 540system.cpu.iq.fu_full::FloatSqrt 0 0.00% 53.11% # attempts to use FU when none available 541system.cpu.iq.fu_full::SimdAdd 0 0.00% 53.11% # attempts to use FU when none available 542system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 53.11% # attempts to use FU when none available 543system.cpu.iq.fu_full::SimdAlu 0 0.00% 53.11% # attempts to use FU when none available 544system.cpu.iq.fu_full::SimdCmp 0 0.00% 53.11% # attempts to use FU when none available 545system.cpu.iq.fu_full::SimdCvt 0 0.00% 53.11% # attempts to use FU when none available 546system.cpu.iq.fu_full::SimdMisc 0 0.00% 53.11% # attempts to use FU when none available 547system.cpu.iq.fu_full::SimdMult 0 0.00% 53.11% # attempts to use FU when none available 548system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 53.11% # attempts to use FU when none available 549system.cpu.iq.fu_full::SimdShift 0 0.00% 53.11% # attempts to use FU when none available 550system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 53.11% # attempts to use FU when none available 551system.cpu.iq.fu_full::SimdSqrt 0 0.00% 53.11% # attempts to use FU when none available 552system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 53.11% # attempts to use FU when none available 553system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 53.11% # attempts to use FU when none available 554system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 53.11% # attempts to use FU when none available 555system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 53.11% # attempts to use FU when none available 556system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 53.11% # attempts to use FU when none available 557system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 53.11% # attempts to use FU when none available 558system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 53.11% # attempts to use FU when none available 559system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 53.11% # attempts to use FU when none available 560system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 53.11% # attempts to use FU when none available 561system.cpu.iq.fu_full::MemRead 44308845 32.73% 85.84% # attempts to use FU when none available 562system.cpu.iq.fu_full::MemWrite 19163928 14.16% 100.00% # attempts to use FU when none available 563system.cpu.iq.fu_full::FloatMemRead 14 0.00% 100.00% # attempts to use FU when none available 564system.cpu.iq.fu_full::FloatMemWrite 22 0.00% 100.00% # attempts to use FU when none available 565system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 566system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 567system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 568system.cpu.iq.FU_type_0::IntAlu 412595854 67.76% 67.76% # Type of FU issued 569system.cpu.iq.FU_type_0::IntMult 352107 0.06% 67.81% # Type of FU issued 570system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.81% # Type of FU issued 571system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.81% # Type of FU issued 572system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.81% # Type of FU issued 573system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.81% # Type of FU issued 574system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.81% # Type of FU issued 575system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 67.81% # Type of FU issued 576system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.81% # Type of FU issued 577system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 67.81% # Type of FU issued 578system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.81% # Type of FU issued 579system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.81% # Type of FU issued 580system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.81% # Type of FU issued 581system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.81% # Type of FU issued 582system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.81% # Type of FU issued 583system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.81% # Type of FU issued 584system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.81% # Type of FU issued 585system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.81% # Type of FU issued 586system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.81% # Type of FU issued 587system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.81% # Type of FU issued 588system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.81% # Type of FU issued 589system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.81% # Type of FU issued 590system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.81% # Type of FU issued 591system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.81% # Type of FU issued 592system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.81% # Type of FU issued 593system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.81% # Type of FU issued 594system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.81% # Type of FU issued 595system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.81% # Type of FU issued 596system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.81% # Type of FU issued 597system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.81% # Type of FU issued 598system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.81% # Type of FU issued 599system.cpu.iq.FU_type_0::MemRead 133581364 21.94% 89.75% # Type of FU issued 600system.cpu.iq.FU_type_0::MemWrite 62404700 10.25% 100.00% # Type of FU issued 601system.cpu.iq.FU_type_0::FloatMemRead 26 0.00% 100.00% # Type of FU issued 602system.cpu.iq.FU_type_0::FloatMemWrite 16 0.00% 100.00% # Type of FU issued 603system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 604system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 605system.cpu.iq.FU_type_0::total 608934070 # Type of FU issued 606system.cpu.iq.rate 1.289985 # Inst issue rate 607system.cpu.iq.fu_busy_cnt 135366043 # FU busy when requested 608system.cpu.iq.fu_busy_rate 0.222300 # FU busy rate (busy events/executed inst) 609system.cpu.iq.int_inst_queue_reads 1829911935 # Number of integer instruction queue reads 610system.cpu.iq.int_inst_queue_writes 788191546 # Number of integer instruction queue writes 611system.cpu.iq.int_inst_queue_wakeup_accesses 594211471 # Number of integer instruction queue wakeup accesses 612system.cpu.iq.fp_inst_queue_reads 122 # Number of floating instruction queue reads 613system.cpu.iq.fp_inst_queue_writes 100 # Number of floating instruction queue writes 614system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses 615system.cpu.iq.int_alu_accesses 744300035 # Number of integer alu accesses 616system.cpu.iq.fp_alu_accesses 78 # Number of floating point alu accesses 617system.cpu.iew.lsq.thread0.forwLoads 7286788 # Number of loads that had data forwarded from stores 618system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 619system.cpu.iew.lsq.thread0.squashedLoads 26479913 # Number of loads squashed 620system.cpu.iew.lsq.thread0.ignoredResponses 24891 # Number of memory responses ignored because the instruction is squashed 621system.cpu.iew.lsq.thread0.memOrderViolation 29414 # Number of memory ordering violations 622system.cpu.iew.lsq.thread0.squashedStores 10668312 # Number of stores squashed 623system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 624system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 625system.cpu.iew.lsq.thread0.rescheduledLoads 225406 # Number of loads that were rescheduled 626system.cpu.iew.lsq.thread0.cacheBlocked 23080 # Number of times an access to memory failed due to the cache being blocked 627system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 628system.cpu.iew.iewSquashCycles 6772399 # Number of cycles IEW is squashing 629system.cpu.iew.iewBlockCycles 23806628 # Number of cycles IEW is blocking 630system.cpu.iew.iewUnblockCycles 967662 # Number of cycles IEW is unblocking 631system.cpu.iew.iewDispatchedInsts 669248404 # Number of instructions dispatched to IQ 632system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch 633system.cpu.iew.iewDispLoadInsts 142363196 # Number of dispatched load instructions 634system.cpu.iew.iewDispStoreInsts 67528532 # Number of dispatched store instructions 635system.cpu.iew.iewDispNonSpecInsts 1490790 # Number of dispatched non-speculative instructions 636system.cpu.iew.iewIQFullEvents 256473 # Number of times the IQ has become full, causing a stall 637system.cpu.iew.iewLSQFullEvents 573815 # Number of times the LSQ has become full, causing a stall 638system.cpu.iew.memOrderViolationEvents 29414 # Number of memory order violations 639system.cpu.iew.predictedTakenIncorrect 3591193 # Number of branches that were predicted taken incorrectly 640system.cpu.iew.predictedNotTakenIncorrect 3742987 # Number of branches that were predicted not taken incorrectly 641system.cpu.iew.branchMispredicts 7334180 # Number of branch mispredicts detected at execute 642system.cpu.iew.iewExecutedInsts 598436406 # Number of executed instructions 643system.cpu.iew.iewExecLoadInsts 129089013 # Number of load instructions executed 644system.cpu.iew.iewExecSquashedInsts 10497664 # Number of squashed instructions skipped in execute 645system.cpu.iew.exec_swp 0 # number of swp insts executed 646system.cpu.iew.exec_nop 1492981 # number of nop insts executed 647system.cpu.iew.exec_refs 190011710 # number of memory reference insts executed 648system.cpu.iew.exec_branches 131264327 # Number of branches executed 649system.cpu.iew.exec_stores 60922697 # Number of stores executed 650system.cpu.iew.exec_rate 1.267746 # Inst execution rate 651system.cpu.iew.wb_sent 595457934 # cumulative count of insts sent to commit 652system.cpu.iew.wb_count 594211487 # cumulative count of insts written-back 653system.cpu.iew.wb_producers 349573647 # num instructions producing a value 654system.cpu.iew.wb_consumers 571370339 # num instructions consuming a value 655system.cpu.iew.wb_rate 1.258796 # insts written-back per cycle 656system.cpu.iew.wb_fanout 0.611816 # average fanout of values written-back 657system.cpu.commit.commitSquashedInsts 107140247 # The number of squashed insts skipped by commit 658system.cpu.commit.commitNonSpecStalls 2977632 # The number of times commit has been forced to stall to communicate backwards 659system.cpu.commit.branchMispredicts 6745693 # The number of times a branch was mispredicted 660system.cpu.commit.committed_per_cycle::samples 454265599 # Number of insts commited each cycle 661system.cpu.commit.committed_per_cycle::mean 1.207866 # Number of insts commited each cycle 662system.cpu.commit.committed_per_cycle::stdev 1.884244 # Number of insts commited each cycle 663system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 664system.cpu.commit.committed_per_cycle::0 225450125 49.63% 49.63% # Number of insts commited each cycle 665system.cpu.commit.committed_per_cycle::1 116407668 25.63% 75.26% # Number of insts commited each cycle 666system.cpu.commit.committed_per_cycle::2 43488632 9.57% 84.83% # Number of insts commited each cycle 667system.cpu.commit.committed_per_cycle::3 23202465 5.11% 89.94% # Number of insts commited each cycle 668system.cpu.commit.committed_per_cycle::4 11495162 2.53% 92.47% # Number of insts commited each cycle 669system.cpu.commit.committed_per_cycle::5 7755603 1.71% 94.17% # Number of insts commited each cycle 670system.cpu.commit.committed_per_cycle::6 8270201 1.82% 95.99% # Number of insts commited each cycle 671system.cpu.commit.committed_per_cycle::7 4246101 0.93% 96.93% # Number of insts commited each cycle 672system.cpu.commit.committed_per_cycle::8 13949642 3.07% 100.00% # Number of insts commited each cycle 673system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 674system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 675system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 676system.cpu.commit.committed_per_cycle::total 454265599 # Number of insts commited each cycle 677system.cpu.commit.committedInsts 506578818 # Number of instructions committed 678system.cpu.commit.committedOps 548692039 # Number of ops (including micro ops) committed 679system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 680system.cpu.commit.refs 172743503 # Number of memory references committed 681system.cpu.commit.loads 115883283 # Number of loads committed 682system.cpu.commit.membars 1488542 # Number of memory barriers committed 683system.cpu.commit.branches 121552863 # Number of branches committed 684system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. 685system.cpu.commit.int_insts 448447003 # Number of committed integer instructions. 686system.cpu.commit.function_calls 9757362 # Number of function calls committed. 687system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 688system.cpu.commit.op_class_0::IntAlu 375609314 68.46% 68.46% # Class of committed instruction 689system.cpu.commit.op_class_0::IntMult 339219 0.06% 68.52% # Class of committed instruction 690system.cpu.commit.op_class_0::IntDiv 0 0.00% 68.52% # Class of committed instruction 691system.cpu.commit.op_class_0::FloatAdd 0 0.00% 68.52% # Class of committed instruction 692system.cpu.commit.op_class_0::FloatCmp 0 0.00% 68.52% # Class of committed instruction 693system.cpu.commit.op_class_0::FloatCvt 0 0.00% 68.52% # Class of committed instruction 694system.cpu.commit.op_class_0::FloatMult 0 0.00% 68.52% # Class of committed instruction 695system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 68.52% # Class of committed instruction 696system.cpu.commit.op_class_0::FloatDiv 0 0.00% 68.52% # Class of committed instruction 697system.cpu.commit.op_class_0::FloatMisc 0 0.00% 68.52% # Class of committed instruction 698system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 68.52% # Class of committed instruction 699system.cpu.commit.op_class_0::SimdAdd 0 0.00% 68.52% # Class of committed instruction 700system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 68.52% # Class of committed instruction 701system.cpu.commit.op_class_0::SimdAlu 0 0.00% 68.52% # Class of committed instruction 702system.cpu.commit.op_class_0::SimdCmp 0 0.00% 68.52% # Class of committed instruction 703system.cpu.commit.op_class_0::SimdCvt 0 0.00% 68.52% # Class of committed instruction 704system.cpu.commit.op_class_0::SimdMisc 0 0.00% 68.52% # Class of committed instruction 705system.cpu.commit.op_class_0::SimdMult 0 0.00% 68.52% # Class of committed instruction 706system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 68.52% # Class of committed instruction 707system.cpu.commit.op_class_0::SimdShift 0 0.00% 68.52% # Class of committed instruction 708system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 68.52% # Class of committed instruction 709system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 68.52% # Class of committed instruction 710system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 68.52% # Class of committed instruction 711system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 68.52% # Class of committed instruction 712system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 68.52% # Class of committed instruction 713system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 68.52% # Class of committed instruction 714system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 68.52% # Class of committed instruction 715system.cpu.commit.op_class_0::SimdFloatMisc 3 0.00% 68.52% # Class of committed instruction 716system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 68.52% # Class of committed instruction 717system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 68.52% # Class of committed instruction 718system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 68.52% # Class of committed instruction 719system.cpu.commit.op_class_0::MemRead 115883283 21.12% 89.64% # Class of committed instruction 720system.cpu.commit.op_class_0::MemWrite 56860204 10.36% 100.00% # Class of committed instruction 721system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction 722system.cpu.commit.op_class_0::FloatMemWrite 16 0.00% 100.00% # Class of committed instruction 723system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 724system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 725system.cpu.commit.op_class_0::total 548692039 # Class of committed instruction 726system.cpu.commit.bw_lim_events 13949642 # number cycles where commit BW limit reached 727system.cpu.rob.rob_reads 1096141105 # The number of ROB reads 728system.cpu.rob.rob_writes 1328357052 # The number of ROB writes 729system.cpu.timesIdled 14656 # Number of times that the entire CPU went into an idle state and unscheduled itself 730system.cpu.idleCycles 1118698 # Total number of cycles that the CPU has spent unscheduled due to idling 731system.cpu.committedInsts 505234934 # Number of Instructions Simulated 732system.cpu.committedOps 547348155 # Number of Ops (including micro ops) Simulated 733system.cpu.cpi 0.934313 # CPI: Cycles Per Instruction 734system.cpu.cpi_total 0.934313 # CPI: Total CPI of All Threads 735system.cpu.ipc 1.070306 # IPC: Instructions Per Cycle 736system.cpu.ipc_total 1.070306 # IPC: Total IPC of All Threads 737system.cpu.int_regfile_reads 610147261 # number of integer regfile reads 738system.cpu.int_regfile_writes 327343686 # number of integer regfile writes 739system.cpu.fp_regfile_reads 16 # number of floating regfile reads 740system.cpu.cc_regfile_reads 2166295309 # number of cc regfile reads 741system.cpu.cc_regfile_writes 376541599 # number of cc regfile writes 742system.cpu.misc_regfile_reads 217608578 # number of misc regfile reads 743system.cpu.misc_regfile_writes 2977084 # number of misc regfile writes 744system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 236023688000 # Cumulative time (in ticks) in various power states 745system.cpu.dcache.tags.replacements 2817163 # number of replacements 746system.cpu.dcache.tags.tagsinuse 511.628180 # Cycle average of tags in use 747system.cpu.dcache.tags.total_refs 168869146 # Total number of references to valid blocks. 748system.cpu.dcache.tags.sampled_refs 2817675 # Sample count of references to valid blocks. 749system.cpu.dcache.tags.avg_refs 59.932088 # Average number of references to valid blocks. 750system.cpu.dcache.tags.warmup_cycle 504794000 # Cycle when the warmup percentage was hit. 751system.cpu.dcache.tags.occ_blocks::cpu.data 511.628180 # Average occupied blocks per requestor 752system.cpu.dcache.tags.occ_percent::cpu.data 0.999274 # Average percentage of cache occupancy 753system.cpu.dcache.tags.occ_percent::total 0.999274 # Average percentage of cache occupancy 754system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 755system.cpu.dcache.tags.age_task_id_blocks_1024::0 155 # Occupied blocks per task id 756system.cpu.dcache.tags.age_task_id_blocks_1024::1 290 # Occupied blocks per task id 757system.cpu.dcache.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id 758system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 759system.cpu.dcache.tags.tag_accesses 355269881 # Number of tag accesses 760system.cpu.dcache.tags.data_accesses 355269881 # Number of data accesses 761system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 236023688000 # Cumulative time (in ticks) in various power states 762system.cpu.dcache.ReadReq_hits::cpu.data 114167630 # number of ReadReq hits 763system.cpu.dcache.ReadReq_hits::total 114167630 # number of ReadReq hits 764system.cpu.dcache.WriteReq_hits::cpu.data 51721570 # number of WriteReq hits 765system.cpu.dcache.WriteReq_hits::total 51721570 # number of WriteReq hits 766system.cpu.dcache.SoftPFReq_hits::cpu.data 2787 # number of SoftPFReq hits 767system.cpu.dcache.SoftPFReq_hits::total 2787 # number of SoftPFReq hits 768system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488559 # number of LoadLockedReq hits 769system.cpu.dcache.LoadLockedReq_hits::total 1488559 # number of LoadLockedReq hits 770system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits 771system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits 772system.cpu.dcache.demand_hits::cpu.data 165889200 # number of demand (read+write) hits 773system.cpu.dcache.demand_hits::total 165889200 # number of demand (read+write) hits 774system.cpu.dcache.overall_hits::cpu.data 165891987 # number of overall hits 775system.cpu.dcache.overall_hits::total 165891987 # number of overall hits 776system.cpu.dcache.ReadReq_misses::cpu.data 4839460 # number of ReadReq misses 777system.cpu.dcache.ReadReq_misses::total 4839460 # number of ReadReq misses 778system.cpu.dcache.WriteReq_misses::cpu.data 2517479 # number of WriteReq misses 779system.cpu.dcache.WriteReq_misses::total 2517479 # number of WriteReq misses 780system.cpu.dcache.SoftPFReq_misses::cpu.data 11 # number of SoftPFReq misses 781system.cpu.dcache.SoftPFReq_misses::total 11 # number of SoftPFReq misses 782system.cpu.dcache.LoadLockedReq_misses::cpu.data 66 # number of LoadLockedReq misses 783system.cpu.dcache.LoadLockedReq_misses::total 66 # number of LoadLockedReq misses 784system.cpu.dcache.demand_misses::cpu.data 7356939 # number of demand (read+write) misses 785system.cpu.dcache.demand_misses::total 7356939 # number of demand (read+write) misses 786system.cpu.dcache.overall_misses::cpu.data 7356950 # number of overall misses 787system.cpu.dcache.overall_misses::total 7356950 # number of overall misses 788system.cpu.dcache.ReadReq_miss_latency::cpu.data 63959252000 # number of ReadReq miss cycles 789system.cpu.dcache.ReadReq_miss_latency::total 63959252000 # number of ReadReq miss cycles 790system.cpu.dcache.WriteReq_miss_latency::cpu.data 19900951428 # number of WriteReq miss cycles 791system.cpu.dcache.WriteReq_miss_latency::total 19900951428 # number of WriteReq miss cycles 792system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 1024000 # number of LoadLockedReq miss cycles 793system.cpu.dcache.LoadLockedReq_miss_latency::total 1024000 # number of LoadLockedReq miss cycles 794system.cpu.dcache.demand_miss_latency::cpu.data 83860203428 # number of demand (read+write) miss cycles 795system.cpu.dcache.demand_miss_latency::total 83860203428 # number of demand (read+write) miss cycles 796system.cpu.dcache.overall_miss_latency::cpu.data 83860203428 # number of overall miss cycles 797system.cpu.dcache.overall_miss_latency::total 83860203428 # number of overall miss cycles 798system.cpu.dcache.ReadReq_accesses::cpu.data 119007090 # number of ReadReq accesses(hits+misses) 799system.cpu.dcache.ReadReq_accesses::total 119007090 # number of ReadReq accesses(hits+misses) 800system.cpu.dcache.WriteReq_accesses::cpu.data 54239049 # number of WriteReq accesses(hits+misses) 801system.cpu.dcache.WriteReq_accesses::total 54239049 # number of WriteReq accesses(hits+misses) 802system.cpu.dcache.SoftPFReq_accesses::cpu.data 2798 # number of SoftPFReq accesses(hits+misses) 803system.cpu.dcache.SoftPFReq_accesses::total 2798 # number of SoftPFReq accesses(hits+misses) 804system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488625 # number of LoadLockedReq accesses(hits+misses) 805system.cpu.dcache.LoadLockedReq_accesses::total 1488625 # number of LoadLockedReq accesses(hits+misses) 806system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) 807system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) 808system.cpu.dcache.demand_accesses::cpu.data 173246139 # number of demand (read+write) accesses 809system.cpu.dcache.demand_accesses::total 173246139 # number of demand (read+write) accesses 810system.cpu.dcache.overall_accesses::cpu.data 173248937 # number of overall (read+write) accesses 811system.cpu.dcache.overall_accesses::total 173248937 # number of overall (read+write) accesses 812system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040665 # miss rate for ReadReq accesses 813system.cpu.dcache.ReadReq_miss_rate::total 0.040665 # miss rate for ReadReq accesses 814system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.046415 # miss rate for WriteReq accesses 815system.cpu.dcache.WriteReq_miss_rate::total 0.046415 # miss rate for WriteReq accesses 816system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.003931 # miss rate for SoftPFReq accesses 817system.cpu.dcache.SoftPFReq_miss_rate::total 0.003931 # miss rate for SoftPFReq accesses 818system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000044 # miss rate for LoadLockedReq accesses 819system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000044 # miss rate for LoadLockedReq accesses 820system.cpu.dcache.demand_miss_rate::cpu.data 0.042465 # miss rate for demand accesses 821system.cpu.dcache.demand_miss_rate::total 0.042465 # miss rate for demand accesses 822system.cpu.dcache.overall_miss_rate::cpu.data 0.042465 # miss rate for overall accesses 823system.cpu.dcache.overall_miss_rate::total 0.042465 # miss rate for overall accesses 824system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13216.196022 # average ReadReq miss latency 825system.cpu.dcache.ReadReq_avg_miss_latency::total 13216.196022 # average ReadReq miss latency 826system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 7905.111196 # average WriteReq miss latency 827system.cpu.dcache.WriteReq_avg_miss_latency::total 7905.111196 # average WriteReq miss latency 828system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15515.151515 # average LoadLockedReq miss latency 829system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15515.151515 # average LoadLockedReq miss latency 830system.cpu.dcache.demand_avg_miss_latency::cpu.data 11398.790098 # average overall miss latency 831system.cpu.dcache.demand_avg_miss_latency::total 11398.790098 # average overall miss latency 832system.cpu.dcache.overall_avg_miss_latency::cpu.data 11398.773055 # average overall miss latency 833system.cpu.dcache.overall_avg_miss_latency::total 11398.773055 # average overall miss latency 834system.cpu.dcache.blocked_cycles::no_mshrs 21 # number of cycles access was blocked 835system.cpu.dcache.blocked_cycles::no_targets 1096029 # number of cycles access was blocked 836system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked 837system.cpu.dcache.blocked::no_targets 221098 # number of cycles access was blocked 838system.cpu.dcache.avg_blocked_cycles::no_mshrs 7 # average number of cycles each access was blocked 839system.cpu.dcache.avg_blocked_cycles::no_targets 4.957209 # average number of cycles each access was blocked 840system.cpu.dcache.writebacks::writebacks 2817163 # number of writebacks 841system.cpu.dcache.writebacks::total 2817163 # number of writebacks 842system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2541567 # number of ReadReq MSHR hits 843system.cpu.dcache.ReadReq_mshr_hits::total 2541567 # number of ReadReq MSHR hits 844system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1997678 # number of WriteReq MSHR hits 845system.cpu.dcache.WriteReq_mshr_hits::total 1997678 # number of WriteReq MSHR hits 846system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 66 # number of LoadLockedReq MSHR hits 847system.cpu.dcache.LoadLockedReq_mshr_hits::total 66 # number of LoadLockedReq MSHR hits 848system.cpu.dcache.demand_mshr_hits::cpu.data 4539245 # number of demand (read+write) MSHR hits 849system.cpu.dcache.demand_mshr_hits::total 4539245 # number of demand (read+write) MSHR hits 850system.cpu.dcache.overall_mshr_hits::cpu.data 4539245 # number of overall MSHR hits 851system.cpu.dcache.overall_mshr_hits::total 4539245 # number of overall MSHR hits 852system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2297893 # number of ReadReq MSHR misses 853system.cpu.dcache.ReadReq_mshr_misses::total 2297893 # number of ReadReq MSHR misses 854system.cpu.dcache.WriteReq_mshr_misses::cpu.data 519801 # number of WriteReq MSHR misses 855system.cpu.dcache.WriteReq_mshr_misses::total 519801 # number of WriteReq MSHR misses 856system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 10 # number of SoftPFReq MSHR misses 857system.cpu.dcache.SoftPFReq_mshr_misses::total 10 # number of SoftPFReq MSHR misses 858system.cpu.dcache.demand_mshr_misses::cpu.data 2817694 # number of demand (read+write) MSHR misses 859system.cpu.dcache.demand_mshr_misses::total 2817694 # number of demand (read+write) MSHR misses 860system.cpu.dcache.overall_mshr_misses::cpu.data 2817704 # number of overall MSHR misses 861system.cpu.dcache.overall_mshr_misses::total 2817704 # number of overall MSHR misses 862system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 32776399000 # number of ReadReq MSHR miss cycles 863system.cpu.dcache.ReadReq_mshr_miss_latency::total 32776399000 # number of ReadReq MSHR miss cycles 864system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4786328496 # number of WriteReq MSHR miss cycles 865system.cpu.dcache.WriteReq_mshr_miss_latency::total 4786328496 # number of WriteReq MSHR miss cycles 866system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1261500 # number of SoftPFReq MSHR miss cycles 867system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1261500 # number of SoftPFReq MSHR miss cycles 868system.cpu.dcache.demand_mshr_miss_latency::cpu.data 37562727496 # number of demand (read+write) MSHR miss cycles 869system.cpu.dcache.demand_mshr_miss_latency::total 37562727496 # number of demand (read+write) MSHR miss cycles 870system.cpu.dcache.overall_mshr_miss_latency::cpu.data 37563988996 # number of overall MSHR miss cycles 871system.cpu.dcache.overall_mshr_miss_latency::total 37563988996 # number of overall MSHR miss cycles 872system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.019309 # mshr miss rate for ReadReq accesses 873system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.019309 # mshr miss rate for ReadReq accesses 874system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009584 # mshr miss rate for WriteReq accesses 875system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009584 # mshr miss rate for WriteReq accesses 876system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.003574 # mshr miss rate for SoftPFReq accesses 877system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.003574 # mshr miss rate for SoftPFReq accesses 878system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016264 # mshr miss rate for demand accesses 879system.cpu.dcache.demand_mshr_miss_rate::total 0.016264 # mshr miss rate for demand accesses 880system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.016264 # mshr miss rate for overall accesses 881system.cpu.dcache.overall_mshr_miss_rate::total 0.016264 # mshr miss rate for overall accesses 882system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14263.675028 # average ReadReq mshr miss latency 883system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14263.675028 # average ReadReq mshr miss latency 884system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 9208.001708 # average WriteReq mshr miss latency 885system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 9208.001708 # average WriteReq mshr miss latency 886system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 126150 # average SoftPFReq mshr miss latency 887system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 126150 # average SoftPFReq mshr miss latency 888system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13331.017313 # average overall mshr miss latency 889system.cpu.dcache.demand_avg_mshr_miss_latency::total 13331.017313 # average overall mshr miss latency 890system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13331.417706 # average overall mshr miss latency 891system.cpu.dcache.overall_avg_mshr_miss_latency::total 13331.417706 # average overall mshr miss latency 892system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 236023688000 # Cumulative time (in ticks) in various power states 893system.cpu.icache.tags.replacements 76621 # number of replacements 894system.cpu.icache.tags.tagsinuse 466.068009 # Cycle average of tags in use 895system.cpu.icache.tags.total_refs 235191085 # Total number of references to valid blocks. 896system.cpu.icache.tags.sampled_refs 77133 # Sample count of references to valid blocks. 897system.cpu.icache.tags.avg_refs 3049.162939 # Average number of references to valid blocks. 898system.cpu.icache.tags.warmup_cycle 116620130500 # Cycle when the warmup percentage was hit. 899system.cpu.icache.tags.occ_blocks::cpu.inst 466.068009 # Average occupied blocks per requestor 900system.cpu.icache.tags.occ_percent::cpu.inst 0.910289 # Average percentage of cache occupancy 901system.cpu.icache.tags.occ_percent::total 0.910289 # Average percentage of cache occupancy 902system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 903system.cpu.icache.tags.age_task_id_blocks_1024::0 97 # Occupied blocks per task id 904system.cpu.icache.tags.age_task_id_blocks_1024::1 262 # Occupied blocks per task id 905system.cpu.icache.tags.age_task_id_blocks_1024::2 118 # Occupied blocks per task id 906system.cpu.icache.tags.age_task_id_blocks_1024::3 18 # Occupied blocks per task id 907system.cpu.icache.tags.age_task_id_blocks_1024::4 17 # Occupied blocks per task id 908system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 909system.cpu.icache.tags.tag_accesses 470631453 # Number of tag accesses 910system.cpu.icache.tags.data_accesses 470631453 # Number of data accesses 911system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 236023688000 # Cumulative time (in ticks) in various power states 912system.cpu.icache.ReadReq_hits::cpu.inst 235191085 # number of ReadReq hits 913system.cpu.icache.ReadReq_hits::total 235191085 # number of ReadReq hits 914system.cpu.icache.demand_hits::cpu.inst 235191085 # number of demand (read+write) hits 915system.cpu.icache.demand_hits::total 235191085 # number of demand (read+write) hits 916system.cpu.icache.overall_hits::cpu.inst 235191085 # number of overall hits 917system.cpu.icache.overall_hits::total 235191085 # number of overall hits 918system.cpu.icache.ReadReq_misses::cpu.inst 86061 # number of ReadReq misses 919system.cpu.icache.ReadReq_misses::total 86061 # number of ReadReq misses 920system.cpu.icache.demand_misses::cpu.inst 86061 # number of demand (read+write) misses 921system.cpu.icache.demand_misses::total 86061 # number of demand (read+write) misses 922system.cpu.icache.overall_misses::cpu.inst 86061 # number of overall misses 923system.cpu.icache.overall_misses::total 86061 # number of overall misses 924system.cpu.icache.ReadReq_miss_latency::cpu.inst 1945774184 # number of ReadReq miss cycles 925system.cpu.icache.ReadReq_miss_latency::total 1945774184 # number of ReadReq miss cycles 926system.cpu.icache.demand_miss_latency::cpu.inst 1945774184 # number of demand (read+write) miss cycles 927system.cpu.icache.demand_miss_latency::total 1945774184 # number of demand (read+write) miss cycles 928system.cpu.icache.overall_miss_latency::cpu.inst 1945774184 # number of overall miss cycles 929system.cpu.icache.overall_miss_latency::total 1945774184 # number of overall miss cycles 930system.cpu.icache.ReadReq_accesses::cpu.inst 235277146 # number of ReadReq accesses(hits+misses) 931system.cpu.icache.ReadReq_accesses::total 235277146 # number of ReadReq accesses(hits+misses) 932system.cpu.icache.demand_accesses::cpu.inst 235277146 # number of demand (read+write) accesses 933system.cpu.icache.demand_accesses::total 235277146 # number of demand (read+write) accesses 934system.cpu.icache.overall_accesses::cpu.inst 235277146 # number of overall (read+write) accesses 935system.cpu.icache.overall_accesses::total 235277146 # number of overall (read+write) accesses 936system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000366 # miss rate for ReadReq accesses 937system.cpu.icache.ReadReq_miss_rate::total 0.000366 # miss rate for ReadReq accesses 938system.cpu.icache.demand_miss_rate::cpu.inst 0.000366 # miss rate for demand accesses 939system.cpu.icache.demand_miss_rate::total 0.000366 # miss rate for demand accesses 940system.cpu.icache.overall_miss_rate::cpu.inst 0.000366 # miss rate for overall accesses 941system.cpu.icache.overall_miss_rate::total 0.000366 # miss rate for overall accesses 942system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22609.244420 # average ReadReq miss latency 943system.cpu.icache.ReadReq_avg_miss_latency::total 22609.244420 # average ReadReq miss latency 944system.cpu.icache.demand_avg_miss_latency::cpu.inst 22609.244420 # average overall miss latency 945system.cpu.icache.demand_avg_miss_latency::total 22609.244420 # average overall miss latency 946system.cpu.icache.overall_avg_miss_latency::cpu.inst 22609.244420 # average overall miss latency 947system.cpu.icache.overall_avg_miss_latency::total 22609.244420 # average overall miss latency 948system.cpu.icache.blocked_cycles::no_mshrs 200857 # number of cycles access was blocked 949system.cpu.icache.blocked_cycles::no_targets 1531 # number of cycles access was blocked 950system.cpu.icache.blocked::no_mshrs 7099 # number of cycles access was blocked 951system.cpu.icache.blocked::no_targets 8 # number of cycles access was blocked 952system.cpu.icache.avg_blocked_cycles::no_mshrs 28.293703 # average number of cycles each access was blocked 953system.cpu.icache.avg_blocked_cycles::no_targets 191.375000 # average number of cycles each access was blocked 954system.cpu.icache.writebacks::writebacks 76621 # number of writebacks 955system.cpu.icache.writebacks::total 76621 # number of writebacks 956system.cpu.icache.ReadReq_mshr_hits::cpu.inst 8898 # number of ReadReq MSHR hits 957system.cpu.icache.ReadReq_mshr_hits::total 8898 # number of ReadReq MSHR hits 958system.cpu.icache.demand_mshr_hits::cpu.inst 8898 # number of demand (read+write) MSHR hits 959system.cpu.icache.demand_mshr_hits::total 8898 # number of demand (read+write) MSHR hits 960system.cpu.icache.overall_mshr_hits::cpu.inst 8898 # number of overall MSHR hits 961system.cpu.icache.overall_mshr_hits::total 8898 # number of overall MSHR hits 962system.cpu.icache.ReadReq_mshr_misses::cpu.inst 77163 # number of ReadReq MSHR misses 963system.cpu.icache.ReadReq_mshr_misses::total 77163 # number of ReadReq MSHR misses 964system.cpu.icache.demand_mshr_misses::cpu.inst 77163 # number of demand (read+write) MSHR misses 965system.cpu.icache.demand_mshr_misses::total 77163 # number of demand (read+write) MSHR misses 966system.cpu.icache.overall_mshr_misses::cpu.inst 77163 # number of overall MSHR misses 967system.cpu.icache.overall_mshr_misses::total 77163 # number of overall MSHR misses 968system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1533201777 # number of ReadReq MSHR miss cycles 969system.cpu.icache.ReadReq_mshr_miss_latency::total 1533201777 # number of ReadReq MSHR miss cycles 970system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1533201777 # number of demand (read+write) MSHR miss cycles 971system.cpu.icache.demand_mshr_miss_latency::total 1533201777 # number of demand (read+write) MSHR miss cycles 972system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1533201777 # number of overall MSHR miss cycles 973system.cpu.icache.overall_mshr_miss_latency::total 1533201777 # number of overall MSHR miss cycles 974system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000328 # mshr miss rate for ReadReq accesses 975system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000328 # mshr miss rate for ReadReq accesses 976system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000328 # mshr miss rate for demand accesses 977system.cpu.icache.demand_mshr_miss_rate::total 0.000328 # mshr miss rate for demand accesses 978system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000328 # mshr miss rate for overall accesses 979system.cpu.icache.overall_mshr_miss_rate::total 0.000328 # mshr miss rate for overall accesses 980system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19869.649664 # average ReadReq mshr miss latency 981system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19869.649664 # average ReadReq mshr miss latency 982system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19869.649664 # average overall mshr miss latency 983system.cpu.icache.demand_avg_mshr_miss_latency::total 19869.649664 # average overall mshr miss latency 984system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19869.649664 # average overall mshr miss latency 985system.cpu.icache.overall_avg_mshr_miss_latency::total 19869.649664 # average overall mshr miss latency 986system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 236023688000 # Cumulative time (in ticks) in various power states 987system.cpu.l2cache.prefetcher.num_hwpf_issued 8513489 # number of hwpf issued 988system.cpu.l2cache.prefetcher.pfIdentified 8514918 # number of prefetch candidates identified 989system.cpu.l2cache.prefetcher.pfBufferHit 429 # number of redundant prefetches already in prefetch queue 990system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 991system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 992system.cpu.l2cache.prefetcher.pfSpanPage 744218 # number of prefetches not generated due to page crossing 993system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 236023688000 # Cumulative time (in ticks) in various power states 994system.cpu.l2cache.tags.replacements 389920 # number of replacements 995system.cpu.l2cache.tags.tagsinuse 15006.987953 # Cycle average of tags in use 996system.cpu.l2cache.tags.total_refs 2697445 # Total number of references to valid blocks. 997system.cpu.l2cache.tags.sampled_refs 405523 # Sample count of references to valid blocks. 998system.cpu.l2cache.tags.avg_refs 6.651768 # Average number of references to valid blocks. 999system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1000system.cpu.l2cache.tags.occ_blocks::writebacks 14934.817227 # Average occupied blocks per requestor 1001system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 72.170726 # Average occupied blocks per requestor 1002system.cpu.l2cache.tags.occ_percent::writebacks 0.911549 # Average percentage of cache occupancy 1003system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.004405 # Average percentage of cache occupancy 1004system.cpu.l2cache.tags.occ_percent::total 0.915954 # Average percentage of cache occupancy 1005system.cpu.l2cache.tags.occ_task_id_blocks::1022 103 # Occupied blocks per task id 1006system.cpu.l2cache.tags.occ_task_id_blocks::1024 15500 # Occupied blocks per task id 1007system.cpu.l2cache.tags.age_task_id_blocks_1022::0 2 # Occupied blocks per task id 1008system.cpu.l2cache.tags.age_task_id_blocks_1022::1 2 # Occupied blocks per task id 1009system.cpu.l2cache.tags.age_task_id_blocks_1022::2 15 # Occupied blocks per task id 1010system.cpu.l2cache.tags.age_task_id_blocks_1022::3 49 # Occupied blocks per task id 1011system.cpu.l2cache.tags.age_task_id_blocks_1022::4 35 # Occupied blocks per task id 1012system.cpu.l2cache.tags.age_task_id_blocks_1024::0 249 # Occupied blocks per task id 1013system.cpu.l2cache.tags.age_task_id_blocks_1024::1 665 # Occupied blocks per task id 1014system.cpu.l2cache.tags.age_task_id_blocks_1024::2 5454 # Occupied blocks per task id 1015system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6553 # Occupied blocks per task id 1016system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2579 # Occupied blocks per task id 1017system.cpu.l2cache.tags.occ_task_id_percent::1022 0.006287 # Percentage of cache occupancy per task id 1018system.cpu.l2cache.tags.occ_task_id_percent::1024 0.946045 # Percentage of cache occupancy per task id 1019system.cpu.l2cache.tags.tag_accesses 95362177 # Number of tag accesses 1020system.cpu.l2cache.tags.data_accesses 95362177 # Number of data accesses 1021system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 236023688000 # Cumulative time (in ticks) in various power states 1022system.cpu.l2cache.WritebackDirty_hits::writebacks 2356317 # number of WritebackDirty hits 1023system.cpu.l2cache.WritebackDirty_hits::total 2356317 # number of WritebackDirty hits 1024system.cpu.l2cache.WritebackClean_hits::writebacks 513605 # number of WritebackClean hits 1025system.cpu.l2cache.WritebackClean_hits::total 513605 # number of WritebackClean hits 1026system.cpu.l2cache.ReadExReq_hits::cpu.data 516771 # number of ReadExReq hits 1027system.cpu.l2cache.ReadExReq_hits::total 516771 # number of ReadExReq hits 1028system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 67113 # number of ReadCleanReq hits 1029system.cpu.l2cache.ReadCleanReq_hits::total 67113 # number of ReadCleanReq hits 1030system.cpu.l2cache.ReadSharedReq_hits::cpu.data 2130678 # number of ReadSharedReq hits 1031system.cpu.l2cache.ReadSharedReq_hits::total 2130678 # number of ReadSharedReq hits 1032system.cpu.l2cache.demand_hits::cpu.inst 67113 # number of demand (read+write) hits 1033system.cpu.l2cache.demand_hits::cpu.data 2647449 # number of demand (read+write) hits 1034system.cpu.l2cache.demand_hits::total 2714562 # number of demand (read+write) hits 1035system.cpu.l2cache.overall_hits::cpu.inst 67113 # number of overall hits 1036system.cpu.l2cache.overall_hits::cpu.data 2647449 # number of overall hits 1037system.cpu.l2cache.overall_hits::total 2714562 # number of overall hits 1038system.cpu.l2cache.UpgradeReq_misses::cpu.data 29 # number of UpgradeReq misses 1039system.cpu.l2cache.UpgradeReq_misses::total 29 # number of UpgradeReq misses 1040system.cpu.l2cache.ReadExReq_misses::cpu.data 5213 # number of ReadExReq misses 1041system.cpu.l2cache.ReadExReq_misses::total 5213 # number of ReadExReq misses 1042system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 10017 # number of ReadCleanReq misses 1043system.cpu.l2cache.ReadCleanReq_misses::total 10017 # number of ReadCleanReq misses 1044system.cpu.l2cache.ReadSharedReq_misses::cpu.data 165013 # number of ReadSharedReq misses 1045system.cpu.l2cache.ReadSharedReq_misses::total 165013 # number of ReadSharedReq misses 1046system.cpu.l2cache.demand_misses::cpu.inst 10017 # number of demand (read+write) misses 1047system.cpu.l2cache.demand_misses::cpu.data 170226 # number of demand (read+write) misses 1048system.cpu.l2cache.demand_misses::total 180243 # number of demand (read+write) misses 1049system.cpu.l2cache.overall_misses::cpu.inst 10017 # number of overall misses 1050system.cpu.l2cache.overall_misses::cpu.data 170226 # number of overall misses 1051system.cpu.l2cache.overall_misses::total 180243 # number of overall misses 1052system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 21500 # number of UpgradeReq miss cycles 1053system.cpu.l2cache.UpgradeReq_miss_latency::total 21500 # number of UpgradeReq miss cycles 1054system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 669742000 # number of ReadExReq miss cycles 1055system.cpu.l2cache.ReadExReq_miss_latency::total 669742000 # number of ReadExReq miss cycles 1056system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 1015207000 # number of ReadCleanReq miss cycles 1057system.cpu.l2cache.ReadCleanReq_miss_latency::total 1015207000 # number of ReadCleanReq miss cycles 1058system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 15371129000 # number of ReadSharedReq miss cycles 1059system.cpu.l2cache.ReadSharedReq_miss_latency::total 15371129000 # number of ReadSharedReq miss cycles 1060system.cpu.l2cache.demand_miss_latency::cpu.inst 1015207000 # number of demand (read+write) miss cycles 1061system.cpu.l2cache.demand_miss_latency::cpu.data 16040871000 # number of demand (read+write) miss cycles 1062system.cpu.l2cache.demand_miss_latency::total 17056078000 # number of demand (read+write) miss cycles 1063system.cpu.l2cache.overall_miss_latency::cpu.inst 1015207000 # number of overall miss cycles 1064system.cpu.l2cache.overall_miss_latency::cpu.data 16040871000 # number of overall miss cycles 1065system.cpu.l2cache.overall_miss_latency::total 17056078000 # number of overall miss cycles 1066system.cpu.l2cache.WritebackDirty_accesses::writebacks 2356317 # number of WritebackDirty accesses(hits+misses) 1067system.cpu.l2cache.WritebackDirty_accesses::total 2356317 # number of WritebackDirty accesses(hits+misses) 1068system.cpu.l2cache.WritebackClean_accesses::writebacks 513605 # number of WritebackClean accesses(hits+misses) 1069system.cpu.l2cache.WritebackClean_accesses::total 513605 # number of WritebackClean accesses(hits+misses) 1070system.cpu.l2cache.UpgradeReq_accesses::cpu.data 29 # number of UpgradeReq accesses(hits+misses) 1071system.cpu.l2cache.UpgradeReq_accesses::total 29 # number of UpgradeReq accesses(hits+misses) 1072system.cpu.l2cache.ReadExReq_accesses::cpu.data 521984 # number of ReadExReq accesses(hits+misses) 1073system.cpu.l2cache.ReadExReq_accesses::total 521984 # number of ReadExReq accesses(hits+misses) 1074system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 77130 # number of ReadCleanReq accesses(hits+misses) 1075system.cpu.l2cache.ReadCleanReq_accesses::total 77130 # number of ReadCleanReq accesses(hits+misses) 1076system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 2295691 # number of ReadSharedReq accesses(hits+misses) 1077system.cpu.l2cache.ReadSharedReq_accesses::total 2295691 # number of ReadSharedReq accesses(hits+misses) 1078system.cpu.l2cache.demand_accesses::cpu.inst 77130 # number of demand (read+write) accesses 1079system.cpu.l2cache.demand_accesses::cpu.data 2817675 # number of demand (read+write) accesses 1080system.cpu.l2cache.demand_accesses::total 2894805 # number of demand (read+write) accesses 1081system.cpu.l2cache.overall_accesses::cpu.inst 77130 # number of overall (read+write) accesses 1082system.cpu.l2cache.overall_accesses::cpu.data 2817675 # number of overall (read+write) accesses 1083system.cpu.l2cache.overall_accesses::total 2894805 # number of overall (read+write) accesses 1084system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses 1085system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses 1086system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.009987 # miss rate for ReadExReq accesses 1087system.cpu.l2cache.ReadExReq_miss_rate::total 0.009987 # miss rate for ReadExReq accesses 1088system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.129872 # miss rate for ReadCleanReq accesses 1089system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.129872 # miss rate for ReadCleanReq accesses 1090system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.071879 # miss rate for ReadSharedReq accesses 1091system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.071879 # miss rate for ReadSharedReq accesses 1092system.cpu.l2cache.demand_miss_rate::cpu.inst 0.129872 # miss rate for demand accesses 1093system.cpu.l2cache.demand_miss_rate::cpu.data 0.060414 # miss rate for demand accesses 1094system.cpu.l2cache.demand_miss_rate::total 0.062264 # miss rate for demand accesses 1095system.cpu.l2cache.overall_miss_rate::cpu.inst 0.129872 # miss rate for overall accesses 1096system.cpu.l2cache.overall_miss_rate::cpu.data 0.060414 # miss rate for overall accesses 1097system.cpu.l2cache.overall_miss_rate::total 0.062264 # miss rate for overall accesses 1098system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 741.379310 # average UpgradeReq miss latency 1099system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 741.379310 # average UpgradeReq miss latency 1100system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 128475.350086 # average ReadExReq miss latency 1101system.cpu.l2cache.ReadExReq_avg_miss_latency::total 128475.350086 # average ReadExReq miss latency 1102system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 101348.407707 # average ReadCleanReq miss latency 1103system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 101348.407707 # average ReadCleanReq miss latency 1104system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 93151.018405 # average ReadSharedReq miss latency 1105system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 93151.018405 # average ReadSharedReq miss latency 1106system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 101348.407707 # average overall miss latency 1107system.cpu.l2cache.demand_avg_miss_latency::cpu.data 94232.790526 # average overall miss latency 1108system.cpu.l2cache.demand_avg_miss_latency::total 94628.240764 # average overall miss latency 1109system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 101348.407707 # average overall miss latency 1110system.cpu.l2cache.overall_avg_miss_latency::cpu.data 94232.790526 # average overall miss latency 1111system.cpu.l2cache.overall_avg_miss_latency::total 94628.240764 # average overall miss latency 1112system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1113system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1114system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1115system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1116system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1117system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1118system.cpu.l2cache.unused_prefetches 2009 # number of HardPF blocks evicted w/o reference 1119system.cpu.l2cache.writebacks::writebacks 291097 # number of writebacks 1120system.cpu.l2cache.writebacks::total 291097 # number of writebacks 1121system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 1528 # number of ReadExReq MSHR hits 1122system.cpu.l2cache.ReadExReq_mshr_hits::total 1528 # number of ReadExReq MSHR hits 1123system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 4 # number of ReadCleanReq MSHR hits 1124system.cpu.l2cache.ReadCleanReq_mshr_hits::total 4 # number of ReadCleanReq MSHR hits 1125system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 4483 # number of ReadSharedReq MSHR hits 1126system.cpu.l2cache.ReadSharedReq_mshr_hits::total 4483 # number of ReadSharedReq MSHR hits 1127system.cpu.l2cache.demand_mshr_hits::cpu.inst 4 # number of demand (read+write) MSHR hits 1128system.cpu.l2cache.demand_mshr_hits::cpu.data 6011 # number of demand (read+write) MSHR hits 1129system.cpu.l2cache.demand_mshr_hits::total 6015 # number of demand (read+write) MSHR hits 1130system.cpu.l2cache.overall_mshr_hits::cpu.inst 4 # number of overall MSHR hits 1131system.cpu.l2cache.overall_mshr_hits::cpu.data 6011 # number of overall MSHR hits 1132system.cpu.l2cache.overall_mshr_hits::total 6015 # number of overall MSHR hits 1133system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 355832 # number of HardPFReq MSHR misses 1134system.cpu.l2cache.HardPFReq_mshr_misses::total 355832 # number of HardPFReq MSHR misses 1135system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 29 # number of UpgradeReq MSHR misses 1136system.cpu.l2cache.UpgradeReq_mshr_misses::total 29 # number of UpgradeReq MSHR misses 1137system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3685 # number of ReadExReq MSHR misses 1138system.cpu.l2cache.ReadExReq_mshr_misses::total 3685 # number of ReadExReq MSHR misses 1139system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 10013 # number of ReadCleanReq MSHR misses 1140system.cpu.l2cache.ReadCleanReq_mshr_misses::total 10013 # number of ReadCleanReq MSHR misses 1141system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 160530 # number of ReadSharedReq MSHR misses 1142system.cpu.l2cache.ReadSharedReq_mshr_misses::total 160530 # number of ReadSharedReq MSHR misses 1143system.cpu.l2cache.demand_mshr_misses::cpu.inst 10013 # number of demand (read+write) MSHR misses 1144system.cpu.l2cache.demand_mshr_misses::cpu.data 164215 # number of demand (read+write) MSHR misses 1145system.cpu.l2cache.demand_mshr_misses::total 174228 # number of demand (read+write) MSHR misses 1146system.cpu.l2cache.overall_mshr_misses::cpu.inst 10013 # number of overall MSHR misses 1147system.cpu.l2cache.overall_mshr_misses::cpu.data 164215 # number of overall MSHR misses 1148system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 355832 # number of overall MSHR misses 1149system.cpu.l2cache.overall_mshr_misses::total 530060 # number of overall MSHR misses 1150system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 21330424894 # number of HardPFReq MSHR miss cycles 1151system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 21330424894 # number of HardPFReq MSHR miss cycles 1152system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 451500 # number of UpgradeReq MSHR miss cycles 1153system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 451500 # number of UpgradeReq MSHR miss cycles 1154system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 469308000 # number of ReadExReq MSHR miss cycles 1155system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 469308000 # number of ReadExReq MSHR miss cycles 1156system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 954360500 # number of ReadCleanReq MSHR miss cycles 1157system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 954360500 # number of ReadCleanReq MSHR miss cycles 1158system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 13996060500 # number of ReadSharedReq MSHR miss cycles 1159system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 13996060500 # number of ReadSharedReq MSHR miss cycles 1160system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 954360500 # number of demand (read+write) MSHR miss cycles 1161system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 14465368500 # number of demand (read+write) MSHR miss cycles 1162system.cpu.l2cache.demand_mshr_miss_latency::total 15419729000 # number of demand (read+write) MSHR miss cycles 1163system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 954360500 # number of overall MSHR miss cycles 1164system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 14465368500 # number of overall MSHR miss cycles 1165system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 21330424894 # number of overall MSHR miss cycles 1166system.cpu.l2cache.overall_mshr_miss_latency::total 36750153894 # number of overall MSHR miss cycles 1167system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1168system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 1169system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses 1170system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses 1171system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.007060 # mshr miss rate for ReadExReq accesses 1172system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.007060 # mshr miss rate for ReadExReq accesses 1173system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.129820 # mshr miss rate for ReadCleanReq accesses 1174system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.129820 # mshr miss rate for ReadCleanReq accesses 1175system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.069927 # mshr miss rate for ReadSharedReq accesses 1176system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.069927 # mshr miss rate for ReadSharedReq accesses 1177system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.129820 # mshr miss rate for demand accesses 1178system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.058280 # mshr miss rate for demand accesses 1179system.cpu.l2cache.demand_mshr_miss_rate::total 0.060186 # mshr miss rate for demand accesses 1180system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.129820 # mshr miss rate for overall accesses 1181system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.058280 # mshr miss rate for overall accesses 1182system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses 1183system.cpu.l2cache.overall_mshr_miss_rate::total 0.183107 # mshr miss rate for overall accesses 1184system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 59945.212612 # average HardPFReq mshr miss latency 1185system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 59945.212612 # average HardPFReq mshr miss latency 1186system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15568.965517 # average UpgradeReq mshr miss latency 1187system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15568.965517 # average UpgradeReq mshr miss latency 1188system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 127356.309362 # average ReadExReq mshr miss latency 1189system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 127356.309362 # average ReadExReq mshr miss latency 1190system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 95312.144213 # average ReadCleanReq mshr miss latency 1191system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 95312.144213 # average ReadCleanReq mshr miss latency 1192system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 87186.572603 # average ReadSharedReq mshr miss latency 1193system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 87186.572603 # average ReadSharedReq mshr miss latency 1194system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 95312.144213 # average overall mshr miss latency 1195system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 88087.985263 # average overall mshr miss latency 1196system.cpu.l2cache.demand_avg_mshr_miss_latency::total 88503.162523 # average overall mshr miss latency 1197system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 95312.144213 # average overall mshr miss latency 1198system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 88087.985263 # average overall mshr miss latency 1199system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 59945.212612 # average overall mshr miss latency 1200system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69332.064095 # average overall mshr miss latency 1201system.cpu.toL2Bus.snoop_filter.tot_requests 5788651 # Total number of requests made to the snoop filter. 1202system.cpu.toL2Bus.snoop_filter.hit_single_requests 2893810 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1203system.cpu.toL2Bus.snoop_filter.hit_multi_requests 26608 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1204system.cpu.toL2Bus.snoop_filter.tot_snoops 99788 # Total number of snoops made to the snoop filter. 1205system.cpu.toL2Bus.snoop_filter.hit_single_snoops 99240 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1206system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 548 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1207system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 236023688000 # Cumulative time (in ticks) in various power states 1208system.cpu.toL2Bus.trans_dist::ReadResp 2372852 # Transaction distribution 1209system.cpu.toL2Bus.trans_dist::WritebackDirty 2647414 # Transaction distribution 1210system.cpu.toL2Bus.trans_dist::WritebackClean 537467 # Transaction distribution 1211system.cpu.toL2Bus.trans_dist::CleanEvict 98823 # Transaction distribution 1212system.cpu.toL2Bus.trans_dist::HardPFReq 402669 # Transaction distribution 1213system.cpu.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution 1214system.cpu.toL2Bus.trans_dist::UpgradeReq 29 # Transaction distribution 1215system.cpu.toL2Bus.trans_dist::UpgradeResp 29 # Transaction distribution 1216system.cpu.toL2Bus.trans_dist::ReadExReq 521984 # Transaction distribution 1217system.cpu.toL2Bus.trans_dist::ReadExResp 521984 # Transaction distribution 1218system.cpu.toL2Bus.trans_dist::ReadCleanReq 77163 # Transaction distribution 1219system.cpu.toL2Bus.trans_dist::ReadSharedReq 2295691 # Transaction distribution 1220system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 230912 # Packet count per connected master and slave (bytes) 1221system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8452572 # Packet count per connected master and slave (bytes) 1222system.cpu.toL2Bus.pkt_count::total 8683484 # Packet count per connected master and slave (bytes) 1223system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9839936 # Cumulative packet size per connected master and slave (bytes) 1224system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 360629696 # Cumulative packet size per connected master and slave (bytes) 1225system.cpu.toL2Bus.pkt_size::total 370469632 # Cumulative packet size per connected master and slave (bytes) 1226system.cpu.toL2Bus.snoops 792623 # Total snoops (count) 1227system.cpu.toL2Bus.snoopTraffic 18632384 # Total snoop traffic (bytes) 1228system.cpu.toL2Bus.snoop_fanout::samples 3687456 # Request fanout histogram 1229system.cpu.toL2Bus.snoop_fanout::mean 0.034433 # Request fanout histogram 1230system.cpu.toL2Bus.snoop_fanout::stdev 0.183151 # Request fanout histogram 1231system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1232system.cpu.toL2Bus.snoop_fanout::0 3561035 96.57% 96.57% # Request fanout histogram 1233system.cpu.toL2Bus.snoop_fanout::1 125873 3.41% 99.99% # Request fanout histogram 1234system.cpu.toL2Bus.snoop_fanout::2 548 0.01% 100.00% # Request fanout histogram 1235system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1236system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1237system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 1238system.cpu.toL2Bus.snoop_fanout::total 3687456 # Request fanout histogram 1239system.cpu.toL2Bus.reqLayer0.occupancy 5788109505 # Layer occupancy (ticks) 1240system.cpu.toL2Bus.reqLayer0.utilization 2.5 # Layer utilization (%) 1241system.cpu.toL2Bus.snoopLayer0.occupancy 1506 # Layer occupancy (ticks) 1242system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1243system.cpu.toL2Bus.respLayer0.occupancy 115773436 # Layer occupancy (ticks) 1244system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 1245system.cpu.toL2Bus.respLayer1.occupancy 4226542968 # Layer occupancy (ticks) 1246system.cpu.toL2Bus.respLayer1.utilization 1.8 # Layer utilization (%) 1247system.membus.snoop_filter.tot_requests 820344 # Total number of requests made to the snoop filter. 1248system.membus.snoop_filter.hit_single_requests 413808 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1249system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1250system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 1251system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1252system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1253system.membus.pwrStateResidencyTicks::UNDEFINED 236023688000 # Cumulative time (in ticks) in various power states 1254system.membus.trans_dist::ReadResp 426709 # Transaction distribution 1255system.membus.trans_dist::WritebackDirty 291097 # Transaction distribution 1256system.membus.trans_dist::CleanEvict 98823 # Transaction distribution 1257system.membus.trans_dist::UpgradeReq 32 # Transaction distribution 1258system.membus.trans_dist::ReadExReq 3682 # Transaction distribution 1259system.membus.trans_dist::ReadExResp 3682 # Transaction distribution 1260system.membus.trans_dist::ReadSharedReq 426710 # Transaction distribution 1261system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1250735 # Packet count per connected master and slave (bytes) 1262system.membus.pkt_count::total 1250735 # Packet count per connected master and slave (bytes) 1263system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 46175232 # Cumulative packet size per connected master and slave (bytes) 1264system.membus.pkt_size::total 46175232 # Cumulative packet size per connected master and slave (bytes) 1265system.membus.snoops 0 # Total snoops (count) 1266system.membus.snoopTraffic 0 # Total snoop traffic (bytes) 1267system.membus.snoop_fanout::samples 430424 # Request fanout histogram 1268system.membus.snoop_fanout::mean 0 # Request fanout histogram 1269system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1270system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1271system.membus.snoop_fanout::0 430424 100.00% 100.00% # Request fanout histogram 1272system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 1273system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1274system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1275system.membus.snoop_fanout::max_value 0 # Request fanout histogram 1276system.membus.snoop_fanout::total 430424 # Request fanout histogram 1277system.membus.reqLayer0.occupancy 2210945378 # Layer occupancy (ticks) 1278system.membus.reqLayer0.utilization 0.9 # Layer utilization (%) 1279system.membus.respLayer1.occupancy 2277916539 # Layer occupancy (ticks) 1280system.membus.respLayer1.utilization 1.0 # Layer utilization (%) 1281 1282---------- End Simulation Statistics ---------- 1283